A dynamic parameter test circuit and test method for wafer

Abstract

The present disclosure provides a dynamic parameter test circuit and test method for a wafer, wherein the test circuit may include a power supply module, a router, an energy storage module, a companion test device, a wafer stage, a test module, a main test device and at least one auxiliary test device, wherein the power supply module is used to provide a current signal; the energy storage module is used to store the current signal; the router is used to transmit the current signal to the main test device and / or the auxiliary test device via the energy storage module and the wafer stage, or to transmit the current signal to the main test device via the auxiliary test device and the energy storage module; the companion test device is connected between the auxiliary test device and the power supply module; the wafer stage is used to fix the main test device and transmit the current signal provided by the power supply module; the test module is used to obtain the voltage and current of the main test device to determine the test result based on the voltage and current.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor characteristic testing, and in particular to a dynamic parameter testing circuit and testing method for a wafer. Background Art

[0002] At present, power semiconductor devices mainly include Metal Oxide Semiconductor Field Effect Transistor (MOSFET), bipolar transistor (BJT), diode (DIODE), SiC field effect transistor, GaN field effect transistor, insulated gate bipolar transistor (IGBT). In order to ensure the effective use of power semiconductor devices in power electronic systems, it is necessary to pre-test the intermediate products of the power semiconductor devices, that is, wafers, to eliminate failed devices so that qualified devices can proceed to subsequent packaging processes.

[0003] With the development of technological requirements, a large number of bare chips are used for the assembly of power switch modules, which requires that the DC parameters and AC parameters of the bare chip itself must meet the requirements of the power switch module. In order to improve the overall switching performance of the power switch module, it is necessary to perform matching tests on the DC parameters and AC parameters of the bare chip. However, there is a lack of corresponding testing means for wafer-level AC parameters, that is, dynamic parameter testing of the power semiconductor device, because the dynamic parameter testing of the power semiconductor device requires that the stray inductance in the test main circuit is extremely small, generally required to be at least less than 50nH, otherwise the stray inductance will cause a large current, resulting in a high voltage spike generated by the high-speed switch, and the voltage spike will destroy the accuracy of the dynamic parameter test data and also pose a threat to the safety of the power semiconductor device. Summary of the Invention

[0004] In view of this, the present disclosure hopes to provide a dynamic parameter test circuit and test method for a wafer, which can reduce the influence of stray inductance in the test circuit, improve the accuracy and reliability of the dynamic parameter test of the main test device, and ensure the safety of the main test device.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, the present disclosure provides a dynamic parameter test circuit for a wafer, the test circuit comprising: a power supply module, a path selector, an energy storage module, a companion test device, a wafer stage, a test module, a main test device, and at least one auxiliary test device, wherein:

[0007] The power supply module is used to provide a current signal to the test circuit;

[0008] The energy storage module is used to store the current signal;

[0009] The router is configured to transmit the current signal to the main test device and / or the auxiliary test device via the energy storage module and the wafer stage, or transmit the current signal to the main test device via the auxiliary test device and the energy storage module;

[0010] The accompanying test device is connected between the auxiliary test device and the power module;

[0011] The wafer stage is used to fix the main test device and transmit the current signal provided by the power module;

[0012] The test module is used to obtain the voltage and current of the main test device to determine the test result according to the voltage and current.

[0013] In a second aspect, the present disclosure provides a method for testing dynamic parameters of a wafer, the method being applied to the test circuit described in the first aspect, the method comprising:

[0014] Determine the driving signal according to the parameters to be tested;

[0015] Controlling the states of the main test device, the companion test device, and the auxiliary test device in the test circuit of the first aspect according to the drive signal, and obtaining the voltage and current of the main test device corresponding to the parameter to be tested;

[0016] The parameters to be tested are determined according to the voltage and current of the main test device, wherein the parameters to be tested include switching parameters of the wafer and parameters of the reverse recovery process.

[0017] The present disclosure provides a dynamic parameter test circuit and test method for a wafer. When testing the dynamic parameters of a wafer, the different states of the selector and the accompanying test device provide more test configuration options, can accurately control the flow direction of the current signal, so that the test circuit can adapt to different types of main test devices and test requirements, and can quickly switch test conditions, thereby improving the repeatability and test efficiency of the test. The setting of the energy storage module allows for rapid release and recovery of energy, so that the test circuit can support complex tests, and improves the efficiency of the test in test scenarios where the main test device needs to be frequently switched on and off. By controlling the precise path of the current signal, the error in the test process is reduced and the accuracy of the test results is improved. In addition, by accurately controlling the voltage and current, the circuit is connected between the wafer stage of the main test device and the energy storage module, which can also realize the testing of the dynamic parameters of the wafer, significantly reducing the influence of stray inductance in the test circuit, and effectively avoiding excessive voltage or current shocks to the main test device, thereby protecting the main test device from damage and ensuring the safety of the main test device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a standard double-pulse test circuit for dynamic parameter testing of a wafer;

[0019] Figure 2 This is a working principle diagram of a double-pulse dynamic parameter test;

[0020] Figure 3 This is a typical waveform diagram of a switch parameter test;

[0021] Figure 4 A schematic diagram of the module composition of a dynamic parameter test circuit for a wafer provided by the present disclosure;

[0022] Figure 5 A schematic diagram of the composition of a main test device and an auxiliary test device provided by the present disclosure;

[0023] Figure 6 A schematic diagram of an integration method of a main test device and an auxiliary test device provided by the present disclosure;

[0024] Figure 7 A schematic diagram of another main test device and auxiliary test device provided by the present disclosure;

[0025] Figure 8 A schematic diagram of another integration method of a main test device and an auxiliary test device provided by the present disclosure;

[0026] Figure 9 A schematic diagram of the composition of another main test device and auxiliary test device provided by the present disclosure;

[0027] Figure 10A schematic diagram of another integration method of a main test device and an auxiliary test device provided by the present disclosure;

[0028] Figure 11 A schematic diagram of the composition of a companion test device provided by the present disclosure;

[0029] Figure 12 A schematic diagram of another test device provided by the present disclosure;

[0030] Figure 13 A schematic diagram of the components of a power supply module, energy storage module, test module, controller, and router provided by the present disclosure;

[0031] Figure 14 A schematic diagram of current signal flow for a switch parameter test in which both the main test device and the accompanying test device are MOS tubes provided by the present disclosure;

[0032] Figure 15 A schematic diagram of current signal flow for another switch parameter test in which both the main test device and the accompanying test device are MOS tubes provided by the present disclosure;

[0033] Figure 16 A switch parameter test waveform diagram provided by the present disclosure;

[0034] Figure 17 A schematic diagram of current signal flow for a parameter test of a reverse recovery process in which both the main test device and the accompanying test device are MOS tubes provided by the present disclosure;

[0035] Figure 18 A schematic diagram of current signal flow for a parameter test of a reverse recovery process of a MOS tube in which both the main test device and the accompanying test device provided by the present invention are MOS tubes;

[0036] Figure 19 A parameter test waveform diagram of a reverse recovery process provided by the present disclosure;

[0037] Figure 20 A schematic diagram of the current signal flow direction for a parameter test during a reverse recovery process in which a main test device is a diode and a companion test device is a MOS transistor, provided by the present disclosure;

[0038] Figure 21 A schematic diagram of current signal flow for parameter testing during a reverse recovery process in which a diode is the primary test device and a MOS transistor is the secondary test device provided by the present disclosure;

[0039] Figure 22 A schematic diagram of current signal flow for parameter testing of a reverse recovery process of a constant current device, wherein the main test device is a diode, the accompanying test device is a MOS tube, and the constant current device is provided in the present disclosure;

[0040] Figure 23 A schematic diagram of current signal flow for parameter testing of a reverse recovery process in which a main test device is a diode, a companion test device is a MOS tube, and a second power supply module is provided in the present disclosure;

[0041] Figure 24 Another current signal flow diagram provided by the present disclosure for a parameter test of a reverse recovery process in which a main test device is a diode, a companion test device is a MOS transistor, and a second power supply module is included;

[0042] Figure 25 A schematic diagram of current signal flow for a switch parameter test in which the main test device is an insulated gate bipolar transistor and the accompanying test device is a diode, provided by the present disclosure;

[0043] Figure 26 Another current signal flow diagram for a switch parameter test in which the main test device is an insulated gate bipolar transistor and the accompanying test device is a diode is provided in the present disclosure;

[0044] Figure 27 A connection diagram of a sampling resistor provided by the present disclosure. DETAILED DESCRIPTION

[0045] To more clearly illustrate the technical solutions in the present disclosure or the prior art, the technical solutions in the present disclosure will be clearly and completely described below in conjunction with the drawings in the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0046] The terms "first" and "second" in this disclosure are used for descriptive purposes only, and are used solely to distinguish one entity or operation from another. They do not necessarily require or imply any actual relationship or order between these entities or operations, nor should they be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of such features.

[0047] See also Figure 1, which shows a schematic diagram of a standard double-pulse test circuit for dynamic parameter testing of a wafer, wherein K1 is the first switch, K2 is the second switch, C1 is a capacitor array arranged in parallel, L1 is a freewheeling inductor, RS is a sampling resistor, the first transistor Q1 is the main test device, and the switching transistor Q3 is the accompanying test device. The gate (Gate) of the first transistor Q1 controls the first transistor Q1 to be in different states, i.e., on state or off state, by responding to a pulse signal from an external controller. The drain (Drain) of the first transistor Q1 constitutes a semiconductor substrate and is connected to the source (Source) of the switching transistor Q3 through a wafer carrier and a cable. The source of the first transistor Q1 is connected to the second end of the capacitor array C1 through the sampling resistor RS. A special probe can be designed for this connection to minimize the distance from the probe to the second end of the capacitor array C1 to reduce stray inductance. The freewheeling inductor L1 and the switching transistor Q3 are arranged in parallel. The first end of the switching transistor Q3 and the first end of the freewheeling inductor L1 are connected to the first end of the capacitor array C1 through the first switch K1. The second end of the freewheeling inductor L1 and the second end of the switching transistor Q3 are connected to the wafer stage. The sampling resistor RS is connected to the source of the first transistor Q1 through a probe.

[0048] Combine Figure 1 The test circuit shown is shown in Figure 2 , which shows a working principle diagram of a dual-pulse dynamic parameter test. Specifically, the dynamic parameter test of the wafer includes at least a switch parameter test, a diode reverse recovery process parameter test, and a short-circuit parameter test. This disclosure takes the test of the switch parameter and the diode reverse recovery process parameter as an example. It can be understood that the dynamic parameter test of the wafer is the dynamic parameter test of the main test device. Figure 1 In the test circuit shown in FIG1 , the switching parameter test is performed by applying two short pulse signals to the first transistor Q1 to simulate the fast switching process of the main test device in the actual circuit, and at the same time using a high-speed oscilloscope G2 to monitor and record the key dynamic parameters of the main test device during the switching process, such as Figure 3 The turn-on delay time Ton, turn-off delay time Toff, rise time Tr, fall time Tf, turn-on time Tdon and turn-off time Tdoff are shown to evaluate the switching performance and transient behavior dynamic performance of the main test device.

[0049] This disclosure takes MOS transistor as the main test device as an example. The MOS transistor can be Si-MOS or SiC-MOS. Its state includes on state and off state. Applying two short pulse signals is the gate voltage pulse. Figure 2In the test circuit shown, the first switch K1 is closed and the second switch K2 is open. Switching transistor Q3 is typically the same MOS transistor as the first transistor Q1, both with built-in body diodes. In this test circuit, switching transistor Q3 is always in the off state, utilizing only its internal parasitic anti-parallel body diode as a freewheeling diode. The Power-IGBT acts as a protection switch, promptly shutting off the entire main current loop if an abnormal condition such as a short circuit occurs in the first transistor Q1, preventing accidents such as transistor explosion. A high-speed oscilloscope G2 with at least three channels monitors the gate-source voltage (VGS), drain-source voltage (VDS), and drain-source current (IDS) of the first transistor Q1 during the test.

[0050] Before testing the switching parameters of the wafer, charge the capacitor array C1 to the rated voltage. Figure 2 The test circuit shown in the figure provides energy. A high-level pulse, the first pulse, which can also be called a turn-on pulse, is applied to the gate of the MOS tube through an external power supply, causing it to turn on quickly from the cut-off state. The conduction duration is T1, as shown in the figure. Figure 3 As shown, a conductive channel is formed between the drain and source of the MOS transistor, and current begins to flow through the first transistor Q1. After the first transistor Q1 is turned on, the gate voltage is maintained, allowing current to flow between the drain and source, simulating the behavior of the first transistor Q1 in the on state. After a certain period of time, the gate voltage is reduced, that is, a second pulse, also called an off pulse, is applied. The off-state duration is T2, which quickly turns the first transistor Q1 off from the on state, and current flows through the body diode or other freewheeling path built into the first transistor Q1. The gate voltage is suddenly increased, and the first transistor Q1 is turned on for a duration of T3. At the end of periods T1 and T3, the first transistor Q1's turn-off transient process and its dynamic parameters can be tested. At the end of period T2, the first transistor Q1's turn-on transient process and its dynamic parameters can be tested.

[0051] During the entire test process, a high-speed oscilloscope G2 was used to monitor the Figure 3 The gate-source voltage (VGS) and drain-source current (IDS) shown in Figure 1 are used to measure the switching parameters of the first transistor Q1. By analyzing the waveforms captured by the high-speed oscilloscope G2, the transient behavior of the first transistor Q1 during the switching process can be obtained, including the rate of change of voltage and current, as well as voltage spikes and oscillations.

[0052] In some examples, the parameters of the diode reverse recovery process are tested by first conducting the body diode built into the first transistor Q1 in the forward direction, then suddenly cutting off the current and applying a reverse voltage within a specified time, and measuring the reverse recovery time Trr, reverse recovery current Irr, and reverse recovery charge Qrr required for the body diode to recover from the forward conduction state to the reverse blocking state. These parameters characterize the dynamic characteristics and efficiency of the body diode in fast switching applications. Specifically, combined with Figure 2 The test schematic shown and Figure 3 As shown in the switching parameter test waveform diagram, during the test process, the first transistor Q1 is always in the cut-off state, and the test process is controlled by the switching pulse of the switching transistor Q3.

[0053] For the above example, in detail, the test process of the parameters of the diode reverse recovery process is as follows: energy is stored on the capacitor array C1 to the rated voltage, the gate-source voltage (VGS) of the switching transistor Q3 suddenly increases, the switching transistor Q3 is turned on for a duration of T1, and the current signal in the test circuit flows through the switching transistor Q3, the freewheeling inductor L1, and the second switch K2. The current slope rises to ID At point ID1, the reverse drain-source voltage (VDS) is applied to the body diode of the first transistor Q1. The gate-source voltage (VGS) of the switching transistor Q3 suddenly drops, causing it to abruptly turn off. At this point, the current signal in the test circuit flows through the body diode of the first transistor Q1, the freewheeling inductor L1, and the second switch K2 for a duration of T2. The gate-source voltage (VGS) of the switching transistor Q3 suddenly increases, causing the switching transistor Q3 to be on for a duration of T3. The current signal in the test circuit flows through the switching transistor Q3, the freewheeling inductor L1, and the second switch K2, with the current slope rising from slightly below ID1 to ID2. Then, the gate-source voltage (VGS) of the switching transistor Q3 drops, causing the current signal in the test circuit to flow through the first transistor Q1, the freewheeling inductor L1, and the second switch K2, with the current slope gradually decreasing to 0. Finally, the Power-IGBT is turned off, completing the test. At the end of the T2 phase, the parameters of the reverse recovery process of the built-in body diode of the first transistor Q1, such as the reverse recovery time Trr, the reverse recovery current Irr and the reverse recovery charge Qrr, can be tested. The rate of current change can be controlled by controlling the turn-off speed of the switching transistor Q3.

[0054] In the present disclosure, for wafer testing equipment, a wafer stage refers to a mechanical component used to fix and move wafers. It usually refers to a part that can clamp the wafer, and may include a vacuum suction cup or other types of clamping structures to ensure that the wafer is stably fixed on the wafer stage during the test. In some examples, the wafer stage is movable, for example, translational or rotational, so that different positions on the wafer can be sent to the test area in sequence. This design enables the test equipment to test multiple chip units (Die) on the wafer within one test cycle. Therefore, if Figure 1 The wafer stage in the test circuit shown in the figure is a moving component, so the cable cannot be directly shortened. Consequently, the test circuit between the wafer stage and the cable is difficult to optimize, and the stray inductance in this test circuit far exceeds the test requirements. This is because the large parasitic inductance in this test circuit generates voltage spikes, causing severe oscillation in the drive waveform, further affecting the performance of the power semiconductor device, resulting in inaccurate waveform data and making dynamic parameter testing of the wafer more difficult. Furthermore, it can cause overvoltage damage to the power semiconductor device and pose a safety hazard.

[0055] Based on this, the present disclosure provides a dynamic parameter test circuit for the test phase between photolithography and packaging during the wafer manufacturing process. This circuit is used to test the dynamic parameters of multiple MOS transistors without lead electrodes on the wafer. The MOS transistors are arranged in a common drain configuration, enabling the test circuit to effectively evaluate the performance of the MOS transistors under actual working conditions, providing important electrical characteristic data for subsequent packaging and application. Figure 4 , which shows a schematic diagram of the module composition of a dynamic parameter test circuit 10 of a wafer provided by the present disclosure, the test circuit 10 includes: a power supply module 11, a path selector 12, an energy storage module 13, a companion test device 14, a test module 15, a main test device 16, an auxiliary test device 17 and a wafer carrier 18, wherein the power supply module 11 is used to provide a current signal for the test circuit; the energy storage module 13 is used to store the current signal; the path selector 12 is used to transmit the current signal to the main test device 16 and / or the auxiliary test device via the energy storage module 13 and the wafer carrier 18 The auxiliary test device 17 or the current signal is transmitted to the main test device 16 via the auxiliary test device 17 and the energy storage module 13; the accompanying test device 14 is connected between the auxiliary test device 17 and the power module 11, and is used to assist in conducting the current signal provided by the power module 11 when testing dynamic parameters to complete the test of the main test device 16; the wafer stage 18 is used to fix the main test device 16 and transmit the current signal provided by the power module 11; the test module 15 is used to obtain the voltage and current of the main test device 16 to determine the test results based on the voltage and current.

[0056] According to the above scheme, when testing wafer dynamic parameters, the different states of the path selector 12 and the companion test device 14 provide more test configuration options, precisely controlling the direction of the current signal, allowing the test circuit 10 to adapt to different types of main test devices 16 and test requirements, and quickly switching test conditions, improving test repeatability and test efficiency. The configuration of the energy storage module 13 allows for rapid release and recovery of energy, enabling the test circuit 10 to support complex tests and improving test efficiency in test scenarios that require frequent switching of the main test device 16. By precisely controlling the current signal path, errors during the test process are reduced and the accuracy of the test results is improved. In addition, by precisely controlling voltage and current, the connection between the energy storage module 13 and the wafer stage 18 of the main test device 16 can also be used to test wafer dynamic parameters. This significantly reduces the impact of stray inductance in the test circuit 10 and effectively avoids excessive voltage or current shocks to the main test device 16, thereby protecting the main test device 16 from damage and ensuring its safety.

[0057] In some examples, the main test device 16 and the auxiliary test device 17 are adjacent to each other and arranged in series, a plurality of auxiliary test devices 17 are arranged in parallel, and the main test device 16 and the auxiliary test devices 17 are integrated on the same semiconductor substrate.

[0058] For example, when there is one auxiliary test device 17, the auxiliary test device 17 is set in series with the main test device 16. When there are multiple auxiliary test devices 17, the multiple auxiliary test devices 17 are first set in parallel, and then the multiple auxiliary test devices 17 connected in parallel are connected in series with the main test device 16.

[0059] For some examples, see Figure 5 The main test device 16 may include a first transistor Q1, wherein the first end of the first transistor Q1 is connected to the second end of the power supply module 11, the second end is connected to the wafer stage 18, and the first control end is used to control the first transistor Q1 to enter the on state or the off state; the auxiliary test device 17 may include a second transistor Q2, wherein the first end of the second transistor Q2 is connected to the first end of the accompanying test device 14, the second end is connected to the wafer stage 18, and the second control end is used to control the second transistor Q2 to enter the continuous on state.

[0060] For the above example, the main test device 16 and the auxiliary test device 17 are integrated on the same semiconductor substrate, such as Figure 6As shown, the main test device 16 is the first transistor Q1, and the auxiliary test device 17 is the second transistor Q2. The drains of the first transistor Q1 and the second transistor Q2 are integrated on the same semiconductor substrate. The semiconductor substrate can serve as part of the transistor drain and has good conductivity. The drain current can flow through the semiconductor substrate.

[0061] In some cases, for dynamic parameter testing of wafers, both the die under test and the auxiliary die need to be probed simultaneously. Since every adjacent die in the wafer needs to be tested, each die is probed once, acting as both the die under test and the auxiliary die. To ensure the reliability of the bonding process, excessive probe marks on the wafer are generally undesirable, so the number of probes should be minimized, ideally with only one probe per die.

[0062] Based on this, for Figure 5 and Figure 6 As shown in FIG, the first transistor Q1 and its adjacent MOS transistor, the second transistor Q2, are selected. In some possible implementations, the first transistor Q1 serves as the die under test, and the second transistor Q2 serves as an auxiliary die. The probe positions of the die under test and the auxiliary die are set to be exactly the same, so that each repeated probe will be in the same position, eliminating probe marks. In some examples, two auxiliary dies are selected adjacent to the die under test. One can be selected on each side of the die under test, or one can be selected on each side above and below the die under test. In this implementation, each die is probed three times during a wafer test. In some examples, three or four auxiliary dies can be selected adjacent to the die under test. One can be selected on each side above and below the die under test. The main circuits of the auxiliary dies are connected in parallel. This way, as long as any of the three or four auxiliary dies can conduct normally, the dynamic parameters of the die under test can be tested normally. The three or four auxiliary dies and the probe circuit of the die under test can form a good loop, further reducing stray inductance. In this case, the wafer is tested once and each die is needled 4 to 5 times.

[0063] In some possible implementations, to increase the complexity of the probe card design, the die under test and auxiliary dies can be swapped during the same probe insertion process, testing two dies at a time, with the two dies acting as adjacent dies. For example, multiple dies can be selected for dynamic testing, and during the test, these dies can serve as auxiliary dies. For example, four auxiliary dies can be selected from the upper left, upper right, lower left, and lower right sides of the die under test for dynamic testing. These four auxiliary dies are arranged in a grid pattern to form a dynamic test circuit. For the first test, the probe card is not lifted, and the circuit is switched on the probe card. The same approach is used to test the remaining dies. This allows dynamic parameter testing of all four dies in a single probe insertion and single stage 18 movement. As long as any two of the four auxiliary dies pass the test, dynamic parameters can be tested without omission. Even at the wafer edge, most dies can be tested normally. This approach reduces the number of probe insertions and stage 18 movements, improving testing efficiency.

[0064] For some examples, see Figure 7 The main test device 16 may include a first diode D1, wherein a first end of the first diode D1 is connected to the second end of the power module 11, and a second end is connected to the wafer stage 18. The auxiliary test device 17 may include a second diode D2, wherein a first end of the second diode D2 is connected to the first end of the dependent test device 14, and a second end is connected to the wafer stage 18.

[0065] Combine Figure 7 , see Figure 8 , which shows a schematic diagram of another integration method of the main test device and the auxiliary test device provided by the present disclosure, wherein the cathodes (negative electrodes) of the first diode D1 and the second diode D2 are integrated on the same semiconductor substrate to form a common cathode connection point. This integration method allows multiple diodes to share a common current path, while the anodes are respectively connected to their respective pins or contacts. The semiconductor substrate can serve as part of the diode cathode and has good conductivity, and the current signal can flow through the semiconductor substrate.

[0066] For some examples, see Figure 9 The main test device 16 may include a first insulated gate bipolar transistor IG1, wherein the first end of the first insulated gate bipolar transistor IG1 is connected to the second end of the power supply module 11, the second end is connected to the wafer carrier 18, and the first control end is used to control the first insulated gate bipolar transistor IG1 to enter the on state or the off state; the auxiliary test device 17 may include a second insulated gate bipolar transistor IG2, the first end of the second insulated gate bipolar transistor IG2 is connected to the second end of the accompanying test device 14, the second end is connected to the wafer carrier 18, and the second control end is used to control the second insulated gate bipolar transistor IG2 to enter the continuous on state or the off state.

[0067] Combine Figure 9 , see Figure 10 , which shows a schematic diagram of another integration method of the main test device and the auxiliary test device provided by the present disclosure, integrating the collectors (C poles) of the first insulated gate bipolar transistor IG1 and the second insulated gate bipolar transistor IG2 on the same semiconductor substrate to form a common collector connection point. This integration method allows multiple IGBT transistors to share a common current path, while the emitters (E poles) and gates (G poles) are respectively connected to their respective pins or contacts, wherein the semiconductor substrate can serve as part of the collector of the IGBT transistor and has good conductivity, and the current signal can flow through the semiconductor substrate.

[0068] For some examples, see Figure 11 The accompanying test device 14 may include a switching transistor Q3, wherein a first end of the switching transistor Q3 is connected to a first end of the auxiliary test device 17, a second end is connected to a first end of the power supply module 11, and a third control end is used to control the switching transistor Q3 to enter an on state or an off state.

[0069] For some examples, see Figure 12 The accompanying test device 14 may include a third diode D3 , wherein a first end of the third diode D3 is connected to a first end of the power module 11 , and a second end of the third diode D3 is connected to a first end of the auxiliary test device 17 .

[0070] For some examples, see Figure 13 , which shows a schematic diagram of the composition of a power module 11, an energy storage module 13, a test module 15, a controller and a path selector 12 provided by the present disclosure, wherein,

[0071] In some examples, the power module 11 may include a capacitor array C1 connected in parallel, wherein a first end of the capacitor array C1 is connected to the energy storage module 13 through the router 12 , and a second end of the capacitor array C1 is connected to the main test device 16 .

[0072] Exemplarily, the power module 11 may further include a power management circuit, a pulse generator, or a battery simulator.

[0073] In some examples, the first end of the energy storage module 13 is connected to the first end or the second end of the power module 11, and the second end of the energy storage module 13 is connected to the wafer stage 18 for storing the current signal provided by the power module 11 or discharging to the main test device 16.

[0074] Exemplarily, the energy storage module 13 may include a freewheeling inductor L1 .

[0075] In some examples, the test module 15 may include a high-speed oscilloscope G2 for measuring the voltage and current of the main test device 16 .

[0076] It should be noted that if Figure 5 and Figure 11 As shown, specifically, the first transistor Q1, the second transistor Q2, and the switching transistor Q3 can be transistors of the same type, and can be N-channel transistors or P-channel transistors. The first terminal is the source of the transistor, the second terminal is the drain of the transistor, and the control terminal is the gate of the transistor, which is in an on state and an off state. The switching between the on state and the off state of the N-channel transistor and the P-channel transistor is controlled by the controller changing the gate voltage relative to the source voltage. Specifically, a high-level or low-level driving signal is applied to the first control terminal, the second control terminal, and the third control terminal by the first controller, the second controller, and the third controller, respectively, to control the first transistor Q1, the second transistor Q2, and the switching transistor Q3 to be in an on state or an off state.

[0077] This disclosure uses the first transistor Q1 as an example to specifically explain the control principle of controlling the on / off state of the first transistor Q1 through a first controller. The first transistor Q1 is an N-channel transistor. The control principle is as follows: When the gate-source voltage (VGS) of the first transistor Q1 is greater than or equal to the threshold voltage (Vth), that is, when the first controller outputs a high-level drive signal, the first transistor Q1 is in the on state. Specifically, the first controller applies a sufficient positive voltage to the gate of the first transistor Q1 such that VGS ≥ Vth. This creates a sufficient positive voltage between the gate and source to form a conductive channel, allowing current to flow from the source to the drain, thereby turning on the first transistor Q1. When the gate-source voltage (VGS) is less than the threshold voltage (Vth), that is, when the first controller outputs a low-level drive signal, the first transistor Q1 enters the off state. At this point, there is insufficient voltage to form a conductive channel, and therefore, no current can flow from the source to the drain. The first controller maintains the gate voltage below Vth, thereby turning off the first transistor Q1.

[0078] Exemplarily, the first transistor Q1 is a P-channel transistor. Its control principle is as follows: when the gate-source voltage (VGS) of the first transistor Q1 is less than or equal to a negative threshold voltage (-Vth), that is, when the first controller outputs a high-level drive signal, the first transistor Q1 is turned on. Specifically, the first controller provides a sufficient negative voltage to the gate such that VGS ≤ -Vth. This creates a sufficient negative voltage between the gate and source to form a conductive channel, allowing current to flow from the source to the drain, thereby turning on the first transistor Q1. When the gate-source voltage (VGS) is greater than the negative threshold voltage (-Vth), that is, when the first controller outputs a low-level drive signal, the first transistor Q1 enters the off state. At this point, there is insufficient negative voltage to form a conductive channel, and therefore, no current can flow from the source to the drain. The first controller maintains the gate voltage above -Vth, thereby turning off the first transistor Q1.

[0079] In some examples, the first controller, the second controller, and the third controller may include a microcontroller, a transistor driver circuit, an operational amplifier, or other electronic circuits, which provide appropriate voltage signals to control the on and off states of the transistors as needed. This control method allows the transistors to function as switches in digital circuits and as amplifiers or switches in analog circuits.

[0080] In some examples, the router 12 may include a first switch K1 and a second switch K2 , whose states include a closed state and an open state. The first switch K1 and the second switch K2 are arranged in parallel, and only one of the first switch K1 and the second switch K2 is in the closed state.

[0081] In some examples, the first switch K1 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the energy storage module 13, the wafer stage 18, and the main test device 16 in sequence, or to transmit the current signal provided by the power module 11 back to the power module via the energy storage module 13, the wafer stage 18, the auxiliary test device 17, and the accompanying test device 14 in sequence.

[0082] The second switch K2 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the auxiliary test device 17, the wafer carrier 18 and the energy storage module 13 in sequence, or to transmit the current signal provided by the power module 11 back to the power module 11 via the main test device 16, the wafer carrier 18 and the energy storage module 13 in sequence.

[0083] Optionally, the wafer switching parameters may include a first switching parameter and a second switching parameter. When testing the first switching parameter of the main test device 16, the first switch K1 is in a closed state, and the first switch K1 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the energy storage module 13, the wafer stage 18, and the main test device 16 in sequence. When testing the second switching parameter of the main test device 16, the first switch K1 can also be used to transmit the current signal provided by the power module 11 back to the power module 11 via the energy storage module 13, the wafer stage 18, the auxiliary test device 17, and the accompanying test device 14 in sequence.

[0084] Optionally, the parameter test of the reverse recovery process of the wafer may include a first stage and a second stage, namely, a charging stage of the energy storage module 13 and a discharging stage of the energy storage module 13. In the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is in a closed state, and the second switch K2 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the auxiliary test device 17, the wafer stage 18 and the energy storage module 13 in sequence. In the second stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 can also be used to transmit the current signal provided by the power module 11 back to the power module 11 via the main test device 16, the wafer stage 18, and the energy storage module 13 in sequence.

[0085] The following example illustrates that the main test device 16 is the first transistor Q1, the auxiliary test device 17 is the second transistor Q2, and the accompanying test device 14 is the switching transistor Q3. The first transistor Q1, the second transistor Q2, and the switching transistor Q3 are N-channel transistors, and the number of the second transistor Q2 is one.

[0086] Combine Figure 4 In the test circuit 10 shown, in some examples, when testing the first switch parameter of the main test device 16, the first switch K1 is closed, the main test device 16 is in the on state, the auxiliary test device 17 is in the on state, and the companion test device 14 is in the off state, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the energy storage module 13, the cable, the wafer carrier 18 and the main test device 16.

[0087] For the above examples, see Figure 14 , which shows a schematic diagram of the current signal flow direction of a switch parameter test of a main test device 16 and a companion test device 14 provided by the present disclosure, wherein both the main test device 16 and the companion test device 14 are MOS tubes. In the present disclosure, as Figure 14As shown in FIG, when testing the first switch parameter of the main test device 16, the second controller outputs a high-level drive signal to control at least one second transistor Q2 to be continuously on. The first controller outputs a high-level drive signal to control the first transistor Q1 to be on. At this time, current can flow freely in both the forward and reverse directions, providing a feasible method for utilizing adjacent chip units, namely, at least one second transistor Q2, to assist in testing switch parameters. The third controller outputs a low-level drive signal to control the switching transistor Q3 to be off, thus forming a test circuit 10 for performing switch parameter testing on a wafer. Figure 14 The arrows of the test circuit 10 are shown as follows: Figure 16 The current signal flow direction of the T1 phase of the waveform diagram in FIG is that the current signal provided by the first end of the power module 11 is transmitted from the energy storage module 13, the cable, the wafer stage 18 and the first transistor Q1 back to the second end of the power module 11. Figure 14 In this example, power module 11 is actually discharging energy to energy storage module 13. The current slope in energy storage module 13 increases from 0 to the set current limit value I1 during phase T1. At this point, a high-speed oscilloscope G2, an ammeter, or a voltmeter is used to test the gate-source voltage and drain-source voltage of first transistor Q1, as well as the current in the test circuit.

[0088] In some examples, when testing the second switch parameter of the main test device 16, the first switch K1 is closed, the main test device 16 is in the off state, the auxiliary test device 17 is in the on state, and the accompanying test device 14 is in the off state, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the first end of the power supply module 11 in sequence through the energy storage module 13, the cable, the wafer carrier 18, the auxiliary test device 17 and the accompanying test device 14.

[0089] For the above examples, see Figure 15 , which shows another current signal flow diagram of a switch parameter test of a main test device 16 and a companion test device 14 provided by the present disclosure, wherein both the main test device 16 and the companion test device 14 are MOS tubes. When testing the second switch parameter of the main test device 16, as shown in FIG. Figure 15 The arrows in the figure describe the direction of the Figure 16 At this time, the first switch K1 is closed, and the first and third controllers respectively output low-level drive signals to control the first transistor Q1 and the switching transistor Q3 to be in the off state. The second controller outputs a high-level drive signal to control the second transistor Q2 to be in the continuously on state. The current signal provided by the first end of the power module 11 is transmitted back to the first end of the power module 11 through the energy storage module 13, the cable, the wafer stage 18, the second transistor Q2, and the switching transistor Q3.

[0090] exist Figure 15In the process, the energy storage module 13 is actually discharging, and the current on the energy storage module 13 remains basically unchanged in the T2 stage.

[0091] In some examples, Figure 16 In the T3 phase, the current signal of the test circuit 10 flows into Figure 14 The arrow in the figure shows the direction of the current. At this time, the current in the test circuit 10 does not start from 0, but starts from the set current limit value I1 and increases to I2. After the T3 stage ends, it enters the Figure 15 As shown in the arrow direction, the first transistor Q1 enters the cut-off state, and the current on the energy storage module 13 slowly decreases to 0.

[0092] It should be noted that, through Figure 14 and Figure 15 After obtaining the first and second switch parameters, the test circuit 10 performs data verification to ensure that there are no errors or abnormal values. Based on the first and second switch parameters, the final switch parameters are obtained, for example, by calculating statistical parameters such as average, maximum, and minimum values, according to test requirements and standards.

[0093] Based on the above examples, the comparison Figure 3 and Figure 16 As shown in the waveform diagram of the switching parameters of the main test device 16, it can be seen that Figure 16 Compare Figure 3 The drain-source voltage on the first transistor Q1 and the current on the freewheeling inductor L1 are added to more clearly describe the change process of voltage and current, but the switching parameters such as the turn-on delay time Ton, the turn-off delay time Toff, the rise time Tr, the fall time Tf, the on-time Tdon and the turn-off time Tdoff are not described, wherein VGS is the change of the gate-source voltage of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; IDS is the change of the drain-source current of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; VDS is the change of the drain-source voltage of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; L1 (CURRENT) is the estimated waveform of the current change flowing through the freewheeling inductor L1.

[0094] Based on the above description, the comparison Figure 14 and Figure 15The path of the current signal flow during the switch parameter test, as indicated by the arrow, shows that the non-overlapping portion of the current loop through which the main current flows in the test circuit 10 has been significantly reduced. In the present disclosure, although the circuitry of the wafer stage 18 and the cable connection portion is retained, the current signal primarily flows directly between the auxiliary test device 17 and the accompanying test device 14. The cable connection portion is only used to connect the current loop with the energy storage module 13, and therefore bears a smaller portion of the sudden current, thereby reducing the effect of the cable's stray inductance on the overall circuit. Therefore, the test circuit 10 can significantly reduce the effect of stray inductance on the test circuit.

[0095] It should be noted that the switching transistor Q3 in the test circuit 10 described above is always in the off state, utilizing only its internal parasitic anti-parallel body diode as a freewheeling diode. A body diode, also known as a parasitic diode, is naturally formed during the MOS transistor manufacturing process. It is located between the drain and substrate of the MOS transistor and is a parasitic element within the MOS transistor. In an N-channel transistor, the body diode is formed by the PN junction between the source and drain, while in a P-channel transistor, the body diode is formed by the PN junction between the drain and source. Its primary function is to provide a current path from the drain to the source when the MOS transistor is turned off. When the gate drive signal of the MOS transistor is removed and the MOS transistor is turned off, if a voltage exists between the drain and source, the body diode conducts, allowing current to flow from the drain to the source in the N-channel transistor, thereby protecting the MOS transistor from voltage spikes. In switching applications, the body diode acts as a freewheeling diode to maintain current continuity in inductive circuits. When the MOS transistor turns off during switching, the energy stored in the inductor circuit is released through the body diode, providing a circuit path and preventing a sudden current interruption that would otherwise cause a high-level spike. This ensures current continuity in the test circuit, which is crucial for test accuracy and device safety. In some examples, a higher-speed diode can be connected in parallel with the switching transistor Q3 to replace the body diode.

[0096] In some examples, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, the main test device 16 is in the off state, the auxiliary test device 17 is in the on state, and the accompanying test device 14 is in the on state, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 to charge the energy storage module 13.

[0097] For the above examples, specifically, see Figure 17 , which shows a schematic diagram of the current signal flow direction of a parameter test of a reverse recovery process of a MOS tube in which both the main test device 16 and the accompanying test device 14 provided by the present disclosure are tested, such as Figure 17 As shown, the first transistor Q1, the second transistor Q2 and the switch transistor Q3 all have built-in body diodes for freewheeling, and their dynamic parameters, i.e., the parameters of the reverse recovery process, need to be tested, mainly including the reverse recovery time Trr, the reverse recovery current Irr and the reverse recovery charge Qrr. It should be noted that, Figure 17 With the aforementioned Figure 14 The difference is that the second switch K2 is closed, the first switch K1 is open, the first controller outputs a low-level drive signal to control the first transistor Q1 to be in the off state, the second controller outputs a high-level drive signal to control at least one second transistor Q2 to be in the on state, and the third controller outputs a high-level drive signal to control the switching transistor Q3 to be in the on state. Figure 17 The arrows shown in the figure describe the direction of the Figure 19 The flow direction of the current signal in the T1 phase is that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 from the switching transistor Q3, the second transistor Q2, the wafer stage 18, the cable and the energy storage module 13 to charge the energy storage module 13.

[0098] exist Figure 17 In this case, power module 11 is actually discharging energy storage module 13, i.e., energy storage module 13 is charging. This causes the current slope in energy storage module 13 to rise from 0 to the set current limit value I1 during phase T1. The body diode in first transistor Q1 is subject to reverse voltage. At this point, the current signal does not flow through main test device 16. Therefore, there is no need to test the gate-source voltage, drain-source voltage, or current in the test circuit of main test device 16. Accordingly, the parameters of main test device 16 during reverse recovery are not tested.

[0099] In some examples, in the second stage of testing the parameters of the reverse recovery process of the main test device 16, the energy storage module 13 is discharged, the second switch K2 is closed, the main test device 16 is in the off state, the auxiliary test device 17 is in the on state, and the companion test device 14 is in the off state, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 in sequence through the main test device 16, the wafer carrier 18 and the cable.

[0100] For the above examples, specifically, see Figure 18 , which shows another current signal flow diagram of a parameter test of the reverse recovery process of a MOS tube in which both the main test device 16 and the accompanying test device 14 provided by the present disclosure are tested. In the second stage of testing the parameters of the reverse recovery process of the main test device 16, that is, the discharge stage of the energy storage module 13, as shown in FIG. Figure 18 The arrows shown in the figure describe the direction of the Figure 19At this time, the second switch K2 is closed, and the first controller outputs a low-level drive signal to control the first transistor Q1 to be in the off state, the second controller outputs a high-level drive signal to control at least one second transistor Q2 to be in the continuously on state, and the third controller outputs a low-level drive signal to control the switching transistor Q3 to be in the off state. The current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 through the first transistor Q1, the wafer carrier 18, and the cable.

[0101] exist Figure 18 In the example, the energy storage module 13 is actually discharging, and the current in the energy storage module 13 remains substantially unchanged during the T2 period. At this point, the gate-source voltage and drain-source voltage of the first transistor Q1 and the current value in the test circuit are tested using a high-speed oscilloscope G2, an ammeter, or a voltmeter.

[0102] In some examples, such as Figure 19 The T3 stage, and then entered Figure 17 The current signal flow direction indicated by the arrow in the figure indicates that the current in the energy storage module 13 does not start at zero, but instead increases from the current limit value I1 to I2. The current in the first transistor Q1, i.e., the current conducted in reverse through the diode, rapidly drops from the current limit value I1 to zero. The voltage drop between the drain and source of the first transistor Q1 rapidly changes from -0.7V (the diode forward voltage drop) to a high level. Because the body diode of the first transistor Q1 has reverse recovery characteristics, when a reverse voltage is applied instantaneously, the current does not drop directly from the current limit value I1 to zero. Instead, it experiences a reverse overshoot. The amplitude of the reverse recovery current, i.e., the overshoot duration, i.e., the reverse recovery time, is Irr. These parameters can be measured using a high-speed oscilloscope G2. The current rate of change condition, di / dt, is determined by the gate drive speed of the switching transistor Q3. Di / dt represents the rate at which the current i changes with time t.

[0103] like Figure 19 As shown in the waveform diagram of the parameters of the reverse recovery process of the main test device 16, it can be seen that the reverse recovery characteristics of the diode can be tested at the moment when the T2 stage ends and the T3 stage begins. Among them, VGS is the change in the gate-source voltage of the switching transistor Q3; IDS is the change in the drain-source current of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; VDS is the change in the drain-source voltage of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; L1 (CURRENT) is the estimated waveform of the current change flowing through the energy storage module 13.

[0104] It should be noted that, through Figure 18The test circuit 10 shown by the middle arrow obtains the reverse recovery process parameters of the energy storage module 13 during the discharge phase, and then performs data verification to ensure that there are no errors or abnormal values. The final reverse recovery process parameters are obtained according to the test requirements and standards.

[0105] Based on the above description, the comparison Figure 17 and Figure 18 The path of the current signal shown in the figure shows that the non-overlapping part of the current signal flow in the test circuit 10 has been greatly reduced. The overlapping part includes the circuit of the wafer stage and the cable connection part. The cable is only used to connect to the current loop of the energy storage module. The current mutation signal mainly flows directly between the auxiliary test device 17 and the accompanying test device 14, thereby reducing the impact of the cable stray inductance on the overall process. The stray inductance generated by other non-overlapping parts, such as the inductance generated by the distance between two adjacent dies, can be reduced to a level that meets the test requirements through wiring and space optimization. Therefore, the above-mentioned test circuit 10 can significantly reduce the impact of stray inductance.

[0106] The following example illustrates that the main test device 16 is the first diode D1 , the auxiliary test device 17 is the second diode D2 , the accompanying test device 14 is the switching transistor Q3 , the switching transistor Q3 is an N-channel transistor, and the number of the second diode D2 is one.

[0107] In some examples, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, the companion test device 14 is in the on state, the main test device 16 is reverse biased, and the auxiliary test device 17 is forward biased, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the companion test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 to charge the energy storage module 13.

[0108] For the above examples, specifically, see Figure 20 , which shows a current signal flow diagram of a parameter test of the reverse recovery process of a main test device 16 provided by the present disclosure, which is a diode and the auxiliary test device 14 is a MOS tube. Since the diode is not a controllable semiconductor device, but can be in a unidirectional conduction state, the first diode D1 and the second diode D2 do not need to be controlled to conduct. Figure 20 As shown, taking the common cathode diode as an example, the wafer testing method of the common anode diode can also be deduced based on this principle, which will not be described in detail in this disclosure. Figure 20 , the switching transistor Q3 has a built-in body diode for freewheeling. Figure 20 With the aforementioned Figure 17 The difference is that the main test device 16 and the auxiliary test device 17 are both diodes, which can be unidirectionally conducted.

[0109] For example, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, and the third controller outputs a high-level driving signal to control the switching transistor Q3 to be in a continuous conduction state, the first diode D1 is reverse biased, and the second diode D2 is forward biased. Figure 20 The arrows shown in the figure describe the direction of the Figure 19 The direction of the current signal in the T1 phase is that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 from the switching transistor Q3, the second diode D2, the wafer stage 18, the cable and the energy storage module 13 to charge the energy storage module 13.

[0110] exist Figure 20 In the embodiment, the power module 11 actually discharges to the energy storage module 13, so that the current slope of the energy storage module 13 increases from 0 to the set current limit value I1 during the T1 phase. The first diode D1 withstands the reverse voltage.

[0111] In some examples, in the second stage of testing the parameters of the reverse recovery process of the main test device 16, the energy storage module 13 is in the discharge stage, the second switch K2 is closed, the companion test device 14 is in the cut-off state, the main test device 16 is forward biased, and the auxiliary test device 17 is forward biased, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 in sequence through the main test device 16, the wafer carrier 18 and the cable.

[0112] For the above examples, see Figure 21 This is the discharge phase of the energy storage module 13, and the second phase of testing the parameters of the reverse recovery process of the main test device 16, such as Figure 21 The arrows shown in the figure describe the direction of the Figure 19 The direction of the current signal during phase T2 in FIG. At this time, the second switch K2 is closed, and the third controller outputs a low-level drive signal to turn off the switching transistor Q3. The first diode D1 is forward-biased, and the second diode D2 is forward-biased. The current signal provided by the first terminal of the energy storage module 13 is transmitted back to the second terminal of the energy storage module 13 via the first diode D1, the wafer stage 18, and the cable.

[0113] exist Figure 21 In the process, the energy storage module 13 is actually discharging, and the current on the energy storage module 13 remains substantially unchanged during the T2 period. At this time, the voltage of the first diode D1 and the current value in the test circuit 10 are tested using a high-speed oscilloscope G2, an ammeter or a voltmeter.

[0114] In some examples, such as Figure 19 The T3 stage, and then entered Figure 20The current signal flows in the direction shown by the arrow. At this time, the current of the energy storage module 13 does not start from 0, but starts from the current limit value I1 and increases to I2. The current on the first diode D1 quickly drops to 0 due to the reverse conduction of the diode; the voltage drop of the first diode D1 quickly changes from the diode forward voltage drop of -0.7V to a high voltage. Because the main test device 16 is a diode, it has a reverse recovery characteristic. When the reverse voltage is applied instantaneously, the I1 current will not drop directly to 0, but there will be a reverse overshoot, the amplitude of which, that is, the reverse recovery current is Irr, and the time width of the overshoot, that is, the reverse recovery time is Trr. These parameters can be measured with a high-speed oscilloscope G2. The condition of the current change rate di / dt is determined by the gate drive speed of the switching transistor Q3, where di / dt represents how fast the current i changes with time t. For other contents, please refer to the explanation of the above example and will not be repeated here.

[0115] In some examples, the test circuit 10 may further include a constant current device for providing a constant direct current bias to the auxiliary test device 17 .

[0116] For example, the constant current device provides a constant DC current bias for the auxiliary test device 17. In some examples, the constant current device can be configured as a constant current source and a simple current mirror circuit or operational amplifier feedback circuit can be used to keep the output current constant. By setting appropriate resistance and power supply voltage, the constant current device can provide a stable current at a specific operating point. In some examples, the constant current device can also be combined with other field effect transistors to form a current mirror circuit. By adjusting the reference current, the constant current device can copy the reference current, thereby providing a constant bias current for the auxiliary test device 17, so that the auxiliary test device 17 is always in the best state during the test process, wherein the reference current is determined by a known resistance and power supply voltage.

[0117] In some examples, the constant current device may include a constant current transistor Q4, wherein a first end of the constant current transistor Q4 is connected to a first end of the power module 11, and a second end is connected to a first end of the auxiliary test device 17, for replicating the current signal provided by the power module 11 and transmitting it to the first end of the auxiliary test device 17.

[0118] For the above example, the constant current transistor Q4 can be a field effect transistor (MOS), a bipolar transistor (BJT), a junction field effect transistor (JFET), a metal semiconductor field effect transistor (MESFET) and an insulated gate bipolar transistor (IGBT). In the present disclosure, the constant current transistor Q4 is taken as a MOS transistor as an example.

[0119] In some examples, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K1 is closed, the accompanying test device 14 is in the on state, the main test device 16 is reverse biased, and the auxiliary test device 17 is forward biased, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13, and the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the constant current device, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13.

[0120] For the above examples, see Figure 22 , which shows a schematic diagram of the current signal flow direction of a parameter test of a reverse recovery process of a main test device 16 provided by the present disclosure, in which the main test device 16 is a diode, the accompanying test device 14 is a MOS tube, and a constant current device is included. Figure 22 and Figure 20 It can be seen from the current path when testing the parameters of the reverse recovery process of the main test device 16 that, Figure 20 The diode reverse recovery time wafer level test method is based on the consideration that the diode reverse recovery time is much longer than the forward conduction time, and the forward current response of the auxiliary test device 17, that is, the second diode D2, is an ideal condition. Figure 19 In the T2 phase, the cathode (common) is about -0.7V, the switching transistor Q3 is in the cut-off state, and the anode of the second diode D2 is equivalent to being suspended; Figure 19 In the T3 phase, the switching transistor Q3 is turned on instantaneously, and the anode of the second diode D2 suddenly changes to a high voltage.

[0121] In some examples, when the switching transistor Q3 is in the off state, the voltage drop of the second diode D2 is approximately 0 (the current is 0) and the current of the second diode D2 quickly becomes the current limit value I1. Its response speed will affect the parameter test of the reverse recovery process of the first diode D1. Figure 22 In the main current signal flow direction Figure 20 Same, such as Figure 22 As shown by the black solid arrow in the figure, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, the third controller outputs a high-level signal to control the switching transistor Q3 to be in the on state, the first diode D1 is reverse biased, and the second diode D2 is forward biased, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 through the switching transistor Q3, the second diode D2, the wafer stage 18, the cable and the energy storage module 13 in sequence to charge the energy storage module 13.

[0122] In the present disclosure, a constant current branch is added to provide a DC current bias, i.e., Ibias, to the second diode D2 during the entire test cycle. Ibias is a current intentionally introduced to set or maintain a specific operating point in the circuit, ensuring that the transistor operates in a specific area, such as the amplification area, to achieve the required circuit function. At this time, the current of the second diode D2 does not change from 0 to the current limit value I1, but changes from Ibias to Ibias+I1. The second diode D2 is continuously in forward bias, and its speed will be significantly improved, which will have less impact on the parameter test of the reverse recovery process of the first diode D1. Figure 22 The black solid arrow in the figure indicates the sudden change current loaded by the switching transistor Q3, and the black dotted arrow indicates that the constant current Ibias is added to the second diode D2 through the constant current transistor Q4. This constant current Ibias does not pass through the first diode D1. Figure 22 As shown by the black dotted arrow in FIG, the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 through the constant current transistor Q4, the second diode D2, the wafer stage 18, the cable and the energy storage module 13 in sequence. Figure 22 It can be seen that the addition of the constant current transistor Q4 has no other effect on the main test circuit, but only improves the response speed of the second diode D2. The current change rate condition di / dt is determined by the gate drive speed of the switching transistor Q3, where di / dt represents the speed at which the current i changes with time t. In the second stage of testing the parameters of the reverse recovery process of the main test device 16, the details are as follows: Figure 21 The description and examples are not repeated here.

[0123] It should be noted that for Figure 22 The test circuit shown in Figure 1 is designed according to the standard reverse recovery test method. The defined conditions are forward current I1, current rate of change di / dt, and reverse voltage. During period T1, forward current I1 is controlled, di / dt is controlled by the gate drive speed of switching transistor Q3, and the reverse voltage can be directly set. In some cases, the parameters of the diode's reverse recovery process are defined differently. For example, for low-voltage, low-current diodes, the speed is faster (e.g., less than 10nS), making di / dt difficult to accurately determine. Therefore, the defined conditions are often changed to forward current, reverse current, reverse bias voltage, and load resistance.

[0124] Based on this, in order to meet the defined conditions, such as forward current, reverse current, reverse bias, and load resistance, in some examples, the power supply module 11 includes a first power supply module C3 and a second power supply module C2, wherein the first power supply module C3 and the second power supply module C2 are arranged in parallel, and the first end of the first power supply module C3 is connected to the second end of the companion test device 14 through a first resistor, and the second end of the first power supply module C3 is connected to the first end of the main test device 16; the first end of the second power supply module C2 is connected to the first end of the auxiliary test device 17 through a second resistor, and the second end of the second power supply module C2 is connected to the first end of the main test device 16, for providing bias current to the auxiliary test device 17.

[0125] For the above example, Figure 23 As shown, the power module 11 may include a first power module C3 and a second power module C2, wherein the first end of the first power module C3 is connected to the first end of the first resistor RL1, the second end of the first resistor RL1 is connected to the second end of the switching transistor Q3, and the second end of the first power module C3 is connected to the first end of the first diode D1. The first end of the second power module C2 is connected to the first end of the second resistor RL2, the second end of the second resistor RL2 is connected to the first end of the second diode D2, and the second end of the second power module C2 is connected to the first end of the first diode D1. The first power module C3 is used to determine the reverse bias voltage; the second power module C2 and the second resistor RL2 are used to determine the bias current of the second diode D2; the first resistor RL1 is used to determine the forward current; and the freewheeling inductor L1 is used to store energy. However, because the time T1 is too short, the freewheeling inductor L1 is not used to determine the forward current.

[0126] In some examples, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, the companion test device 14 is in the on state, the main test device 16 is reverse biased, and the auxiliary test device 17 is forward biased, so that the current signal provided by the first end of the first power module C3 is transmitted back to the second end of the first power module C3 via the companion test device 14, the auxiliary test device 17, the wafer carrier 18, the cable and the energy storage module 13 in sequence to charge the energy storage module 13; and the current signal provided by the first end of the second power module C2 is transmitted back to the second end of the second power module via the auxiliary test device 17, the wafer carrier 18, the cable and the energy storage module 13.

[0127] For the above example, compare Figure 23 and Figure 20 It can be seen from the current path when testing the parameters of the reverse recovery process of the main test device 16 that Figure 23In the embodiment, a current path is added to determine the bias current of the second diode D2. The second switch K2 is closed, and the third controller controls the switching transistor Q3 to be in the on state. The first diode D1 is reverse biased, and the second diode D2 is forward biased. In the first stage of testing the parameters of the reverse recovery process of the main test device 16, that is, the charging stage of the energy storage module 13, as shown in FIG. Figure 23 shown Figure 19 The flow direction of the current signal in the T1 phase is to transmit the current signal provided by the first end of the first power module C3 back to the second end of the first power module C3 through the first resistor RL1, the switching transistor Q3, the second diode D2, the wafer stage 18, the cable and the energy storage module 13 in sequence.

[0128] In this disclosure, Figure 23 The direction of the increased current signal, such as Figure 24 As shown, when the second switch K2 is closed, the current signal provided by the first end of the second power module C2 is transmitted back to the second end of the second power module C2 via the second resistor RL2, the second diode D2, the wafer stage 18, the cable and the energy storage module 13.

[0129] It should be noted that in Figure 23 In fact, the first power module C3 is used to discharge the energy storage module 13 so that the current slope on the energy storage module 13 rises from 0 to the set current limit value I1 in the T1 stage. The first diode D1 withstands the reverse voltage. The second power module C2 is used to determine the bias current of the second diode D2. At this time, the direction of the current signal does not pass through the first diode D1. Therefore, there is no need to test the voltage of the main test device 16 and the current value in the test circuit. Accordingly, the parameters in the reverse recovery process of the main test device 16 are not tested. In the second stage of testing the parameters of the reverse recovery process of the main test device 16, the specific content is shown in the above Figure 21 The description and examples are not repeated here.

[0130] The following example illustrates that the main test device 16 is a first insulated gate bipolar transistor IG1 , the auxiliary test device 17 is a second insulated gate bipolar transistor IG2 , both of which are N-channel IGBT transistors, the accompanying test device 14 is a third diode D3 , and there is one second insulated gate bipolar transistor IG2 .

[0131] In some examples, when testing the switching parameters of the main test device 16, the first switch K1 is closed, the main test device 16 is in the on state, the auxiliary test device 17 is in the on state, and the companion test device 14 is reverse biased, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the energy storage module 13, the cable, the wafer carrier 18 and the main test device 16.

[0132] For the above example, Figure 25 As shown, the main test device 16 is a first insulated gate bipolar transistor IG1, the auxiliary test device 17 is a second insulated gate bipolar transistor IG2, and the dependent test device 14 is a third diode D3. The first insulated gate bipolar transistor IG1 and the second insulated gate bipolar transistor IG2 can be IGBTs or bipolar junction transistors (BJTs). Because IGBTs or bipolar junction transistors (BJTs) have different characteristics than MOS transistors, specifically, MOS transistors can be approximated as a resistance path when conducting, while IGBTs or bipolar junction transistors (BJTs) can only conduct in the forward direction, not in the reverse direction, and lack a built-in body diode. Therefore, there is no need to test the parameters of the reverse recovery process during wafer testing. This disclosure uses IGBTs as an example, but can also be extended to bipolar junction transistors (BJTs). When testing the first switch parameters of the main test device 16, the first switch K1 is closed, the first controller outputs a high-level drive signal to control the first insulated gate bipolar transistor IG1 to be in the conducting state, the second controller outputs a high-level drive signal to control the second insulated gate bipolar transistor IG2 to be in the continuously conducting state, and the third diode D3 is reverse biased. Figure 25 The arrows in the test circuit 10 are used to describe the Figure 16 The flow direction of the current signal in the T1 phase of the waveform diagram is that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 through the energy storage module 13, the cable, the wafer stage 18 and the first insulated gate bipolar transistor IG1 in sequence.

[0133] It should be noted that the high level signal or low level signal output by the first controller and the second controller drives the G / B poles of the first insulated gate bipolar transistor IG1 and the second insulated gate bipolar transistor IG2. Figure 14 The description of the contents shown will not be repeated in detail here.

[0134] In some examples, when testing the switching parameters of the main test device 16, the first switch K1 is closed, the main test device 16 is in the cut-off state, the auxiliary test device 17 is in the on state, and the accompanying test device 14 is forward biased, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the first end of the power supply module 11 in sequence through the energy storage module 13, the cable, the wafer stage 18, the auxiliary test device 17, and the accompanying test device 14.

[0135] For the above examples, see Figure 26 , which shows another current signal flow diagram for a switch parameter test in which the main test device 16 is an insulated gate bipolar transistor and the accompanying test device 14 is a diode, provided by the present disclosure. Figure 26 The arrows in the Figure 16At this time, when testing the second switch parameter of the main test device 16, the first switch K1 is closed, the first controller outputs a low-level drive signal to control the first insulated gate bipolar transistor IG1 to be in the off state, and the second controller outputs a high-level drive signal to control the second insulated gate bipolar transistor IG2 to be in the on state and the third diode D3 to be forward biased. The current signal provided by the first end of the power supply module 11 is transmitted from the energy storage module 13, the cable, the wafer stage 18, the second insulated gate bipolar transistor IG2, and the third diode D3 back to the first end of the power supply module 11. For other contents, see Figure 15 The description of the contents shown will not be repeated in detail here.

[0136] It should be noted that, through Figure 25 and Figure 26 After obtaining the first and second switch parameters, the test circuit 10 performs data verification to ensure that there are no errors or abnormal values. Based on the first and second switch parameters, the final switch parameters are obtained, for example, by calculating statistical parameters such as average, maximum, and minimum values, according to test requirements and standards.

[0137] For some examples, see Figure 27 The test circuit 10 further includes a sampling resistor, a first end of which is connected to the second end of the power module 11 , and a second end of which is connected to the main test device 16 .

[0138] For example, the sampling resistor can be Figure 27 The sampling resistor RS is shown in FIG.

[0139] In the present disclosure, a dynamic parameter testing method for a wafer is also provided. The testing method is applied to the above-mentioned test circuit 10. The testing method may include: determining a driving signal according to the parameters to be tested; controlling the states of the main test device 16, the accompanying test device 14 and the auxiliary test device 17 in the test circuit 10 according to the driving signal, and obtaining the voltage and current of the main test device 16 corresponding to the parameters to be tested; determining the parameters to be tested according to the voltage and current of the main test device 16, wherein the parameters to be tested include the switching parameters of the wafer and the parameters of the reverse recovery process.

[0140] Regarding the technical solution of the above-mentioned test method, a driver is used to generate a precise drive signal, which can be a voltage pulse or a current pulse, to control the switching action of the main test device 16, the closing and opening of the selector 12 to select the current path, and the current signal is transmitted from the energy storage module 13 to the main test device 16, or reversely transmitted back to the power module 11 and the switching between the on state and the off state of the accompanying test device 14 to cooperate with the test of the main test device 16, provide the necessary current return path or simulate different load conditions. The voltage and current direction of the main test device 16 are measured under different types and states of each device to obtain the switching parameters and reverse recovery process parameters of the main test device 16. This method can comprehensively evaluate the switching parameters of the main test device 16 and the parameters of the reverse recovery process, improve the accuracy and efficiency of the test, while protecting the safety of the main test device 16, and provide important data for device design and performance optimization.

[0141] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal and a third drive signal. The test method may include: controlling the first switch K1 to be closed, controlling the main test device 16 to be in an on state through the first drive signal, controlling the auxiliary test device 17 to be in an on state through the second drive signal, and controlling the companion test device 14 to be in an off state through the third drive signal, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the energy storage module 13, the cable, the wafer stage 18 and the main test device 16, obtaining the changes in the voltage and current of the main test device 16, and obtaining the switching parameters of the main test device 16 according to the changes in the voltage and current of the main test device 16.

[0142] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal, and a third drive signal. The test method may include: controlling the first switch K1 to be closed, controlling the main test device 16 to be in an off state through the first drive signal, controlling the auxiliary test device 17 to be in an on state through the second drive signal, and controlling the accompanying test device 14 to be in an off state through the third drive signal, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the first end of the power supply module 11 in sequence through the energy storage module 13, the cable, the wafer stage 18, the auxiliary test device 17, and the accompanying test device 14, to obtain the changes in the voltage and current of the main test device 16, and obtain the switching parameters of the main test device 16 based on the changes in the voltage and current of the main test device 16.

[0143] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal, and a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the main test device 16 to be in an off state through the first drive signal, controlling the auxiliary test device 17 to be in an on state through the second drive signal, and controlling the accompanying test device 14 to be in an on state through the third drive signal, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable, and the energy storage module 13 to charge the energy storage module 13.

[0144] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal, and a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the main test device 16 to be in an off state through the first drive signal, controlling the auxiliary test device 17 to be in an on state through the second drive signal, and controlling the accompanying test device 14 to be in an off state through the third drive signal, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 through the main test device 16, the wafer stage 18, and the cable in sequence, obtaining the changes in voltage and current of the main test device 16, and obtaining the parameters of the reverse recovery process of the main test device 16 based on the changes in voltage and current of the main test device 16.

[0145] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the accompanying test device 14 to be in an on state through the third drive signal, the main test device 16 to be reverse biased, and the auxiliary test device 17 to be forward biased, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 to charge the energy storage module 13.

[0146] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the accompanying test device 14 to be in the cut-off state through the third drive signal, the main test device 16 to be forward biased, and the auxiliary test device 17 to be forward biased, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 via the main test device 16, the wafer stage 18 and the cable in sequence, obtaining the changes in the voltage and current of the main test device 16, and obtaining the parameters of the reverse recovery process of the main test device 16 based on the changes in the voltage and current of the main test device 16.

[0147] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the accompanying test device 14 to be in the on state through the third drive signal, the main test device 16 to be reverse biased, and the auxiliary test device 17 to be forward biased, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 to charge the energy storage module 13; and the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the constant current device, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13.

[0148] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the accompanying test device 14 to be in the on state through the third drive signal, the main test device 16 to be reverse biased, and the auxiliary test device 17 to be forward biased, so that the current signal provided by the first end of the first power supply module C3 is transmitted back to the second end of the first power supply module C3 via the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 in sequence to charge the energy storage module 13; and the current signal provided by the first end of the second power supply module C2 is transmitted back to the second end of the second power supply module C2 via the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13.

[0149] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal and a second drive signal. The test method may include: controlling the first switch K1 to be closed, controlling the main test device 16 to be in an on state through the first drive signal, and controlling the auxiliary test device 17 to be in an on state through the second drive signal, and reverse biasing the companion test device 14, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 in sequence through the energy storage module 13, the cable, the wafer stage 18 and the main test device 16, obtaining the changes in the voltage and current of the main test device 16, and obtaining the switching parameters of the main test device 16 based on the changes in the voltage and current of the main test device 16.

[0150] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal and a second drive signal. The test method may include: controlling the first switch K1 to be closed, controlling the main test device 16 to be in an off state through the first drive signal, and controlling the auxiliary test device 17 to be in an on state through the second drive signal, and forward biasing the accompanying test device 14, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the first end of the power supply module 11 in sequence through the energy storage module 13, the cable, the wafer stage 18, the auxiliary test device 17, and the accompanying test device 14, to obtain the changes in the voltage and current of the main test device 16, and obtain the switching parameters of the main test device 16 based on the changes in the voltage and current of the main test device 16.

[0151] For the specific details of the above-mentioned dynamic parameter testing method of the wafer that have not been described in detail, please refer to the description of the dynamic parameter testing circuit of the wafer mentioned above, and will not be repeated here.

[0152] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily without conflict.

[0153] The above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or replacements that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in this disclosure should be covered by the protection scope of the present disclosure.

Claims

1. A dynamic parameter test circuit for a wafer, characterized in that: The wafer is in the testing stage between photolithography and packaging. The wafer includes multiple transistors, and the drains of the multiple transistors constitute the substrate of the wafer. The test circuit includes: a power module, a path selector, an energy storage module, a companion test device, a wafer carrier, a test module, a main test device, and multiple auxiliary test devices. The main test device and the auxiliary test device are adjacent and arranged in series, and multiple auxiliary test devices are arranged in parallel. The main test device and the auxiliary test device are integrated on the same semiconductor substrate, wherein, The power supply module is used to provide a current signal to the test circuit; The energy storage module is used to store the current signal; The accompanying test device is connected between the auxiliary test device and the power module; The wafer stage is used to fix the main test device and transmit the current signal provided by the power module; The test module is configured to obtain the voltage and current of the main test device to determine a test result based on the voltage and current; The router includes a first switch and a second switch, and the states thereof include a closed state and an open state. The first switch and the second switch are arranged in parallel, and only one of the first switch and the second switch is in the closed state. The first switch is used to transmit the current signal provided by the power module back to the power module via the energy storage module, the wafer stage, and the main test device in sequence, or to transmit the current signal provided by the power module back to the power module via the energy storage module, the wafer stage, the auxiliary test device, and the accompanying test device in sequence; The second switch is used to transmit the current signal provided by the power module back to the power module via the auxiliary test device, the wafer stage and the energy storage module in sequence, or to transmit the current signal provided by the power module back to the power module via the main test device, the wafer stage and the energy storage module in sequence.

2. The test circuit according to claim 1, wherein: The accompanying test device includes: A switching transistor has a first end connected to the first end of the auxiliary test device, a second end connected to the first end of the power module, and a third control end used to control the switching transistor to enter an on state or an off state.

3. The test circuit according to claim 2, wherein: The main test device includes: a first transistor, a first end of which is connected to the second end of the power module, a second end of which is connected to the wafer stage, and a first control end for controlling the first transistor to enter an on state or an off state; The auxiliary test device includes: A second transistor has a first end connected to the first end of the switch transistor, a second end connected to the wafer stage, and a second control end used to control the second transistor to enter a continuously conducting state.

4. The test circuit according to claim 1, wherein: When testing the switching parameters of the main test device, the first switch is closed, the main test device is in the on state, the auxiliary test device is in the on state, and the accompanying test device is in the off state, so that the current signal provided by the first end of the power supply module is transmitted back to the second end of the power supply module in sequence through the energy storage module, the cable, the wafer carrier and the main test device.

5. The test circuit according to claim 1, wherein: When testing the switching parameters of the main test device, the first switch is closed, the main test device is in the off state, the auxiliary test device is in the on state, and the accompanying test device is in the off state, so that the current signal provided by the first end of the power supply module is transmitted back to the first end of the power supply module in sequence through the energy storage module, the cable, the wafer carrier, the auxiliary test device and the accompanying test device.

6. The test circuit according to claim 1, wherein: In the first stage of testing the parameters of the reverse recovery process of the main test device, the second switch is closed, the main test device is in the off state, the auxiliary test device is in the on state, and the accompanying test device is in the on state, so that the current signal provided by the first end of the power supply module is transmitted back to the second end of the power supply module in sequence through the accompanying test device, the auxiliary test device, the wafer stage, the cable and the energy storage module to charge the energy storage module.

7. The test circuit according to claim 6, characterized in that: In the second stage of testing the parameters of the reverse recovery process of the main test device, the energy storage module is discharged, the second switch is closed, the main test device is in the off state, the auxiliary test device is in the on state, and the companion test device is in the off state, so that the current signal provided by the first end of the energy storage module is transmitted back to the second end of the energy storage module via the main test device, the wafer carrier and the cable in sequence.

8. The test circuit according to claim 2, wherein: The main test device includes: a first diode, a first end of which is connected to the second end of the power module, and a second end of which is connected to the wafer stage; The auxiliary test device includes: A second diode has a first end connected to the first end of the switch transistor in the accompanying test device, and a second end connected to the wafer stage.

9. The test circuit according to claim 1, wherein: In the first stage of testing the parameters of the reverse recovery process of the main test device, the second switch is closed, the companion test device is in the on state, the main test device is reverse biased, and the auxiliary test device is forward biased, so that the current signal provided by the first end of the power supply module is transmitted back to the second end of the power supply module in sequence through the companion test device, the auxiliary test device, the wafer stage, the cable and the energy storage module to charge the energy storage module.

10. The test circuit according to claim 1, wherein: In the second stage of testing the parameters of the reverse recovery process of the main test device, the energy storage module is discharged, the second switch is closed, the accompanying test device is in the cut-off state, the main test device is forward biased, and the auxiliary test device is forward biased, so that the current signal provided by the first end of the energy storage module is transmitted back to the second end of the energy storage module via the main test device, the wafer carrier and the cable in sequence.

11. The test circuit according to claim 1, wherein: The test circuit further includes: a constant current device for providing a constant direct current bias for the auxiliary test device.

12. The test circuit according to claim 11, characterized in that: The constant current device comprises: A constant current transistor has a first end connected to the first end of the power module and a second end connected to the first end of the auxiliary test device, and is used to replicate the current signal provided by the power module and transmit it to the first end of the auxiliary test device.

13. The test circuit according to claim 11, wherein: In the first stage of testing the parameters of the reverse recovery process of the main test device, the second switch is closed, the accompanying test device is in the on state, the main test device is reverse biased, and the auxiliary test device is forward biased, so that the current signal provided by the first end of the power supply module is transmitted back to the second end of the power supply module in sequence through the accompanying test device, the auxiliary test device, the wafer carrier, the cable and the energy storage module to charge the energy storage module, and the current signal provided by the first end of the power supply module is transmitted back to the second end of the power supply module in sequence through the constant current device, the auxiliary test device, the wafer carrier, the cable and the energy storage module.

14. The test circuit according to claim 1, wherein: The power supply module includes a first power supply module and a second power supply module, wherein the first power supply module and the second power supply module are arranged in parallel, the first end of the first power supply module is connected to the second end of the accompanying test device through a first resistor, and the second end of the first power supply module is connected to the first end of the main test device; the first end of the second power supply module is connected to the first end of the auxiliary test device through a second resistor, and the second end of the second power supply module is connected to the first end of the main test device, for providing a bias current to the auxiliary test device.

15. The test circuit according to claim 14, characterized in that: In the first stage of testing the parameters of the reverse recovery process of the main test device, the second switch is closed, the accompanying test device is in the on state, the main test device is reverse biased, and the auxiliary test device is forward biased, so that the current signal provided by the first end of the first power supply module is transmitted back to the second end of the first power supply module via the accompanying test device, the auxiliary test device, the wafer carrier, the cable and the energy storage module in sequence to charge the energy storage module; and the current signal provided by the first end of the second power supply module is transmitted back to the second end of the second power supply module via the auxiliary test device, the wafer carrier, the cable and the energy storage module.

16. The test circuit according to claim 1, wherein: The accompanying test device includes: A third diode has a first end connected to the first end of the power module and a second end connected to the first end of the auxiliary test device.

17. The test circuit according to claim 16, wherein: The main test device includes: a first insulated gate bipolar transistor, a first end of which is connected to the second end of the power module, a second end of which is connected to the wafer stage, and a first control end for controlling the first insulated gate bipolar transistor to enter an on state or an off state; The auxiliary test device includes: A second insulated gate bipolar transistor has a first end connected to the second end of the third diode, a second end connected to the wafer stage, and a second control end used to control the second insulated gate bipolar transistor to enter an on state or an off state.

18. The test circuit according to claim 1, wherein: When testing the switching parameters of the main test device, the first switch is closed, the main test device is in the on state, the auxiliary test device is in the on state, and the companion test device is reverse biased, so that the current signal provided by the first end of the power supply module is transmitted back to the second end of the power supply module in sequence through the energy storage module, cable, wafer stage and the main test device.

19. The test circuit according to claim 1, wherein: When testing the switching parameters of the main test device, the first switch is closed, the main test device is in the off state, the auxiliary test device is in the on state, and the companion test device is forward biased, so that the current signal provided by the first end of the power supply module is transmitted back to the first end of the power supply module in sequence through the energy storage module, cable, wafer stage, auxiliary test device, and the companion test device.

20. A method for testing dynamic parameters of a wafer, characterized in that: The test method includes: Determine the driving signal according to the parameters to be tested; Controlling the states of the main test device, the companion test device, and the auxiliary test device in the test circuit according to any one of claims 1 to 19 according to the drive signal, and obtaining the voltage and current of the main test device corresponding to the parameter to be tested; The parameters to be tested are determined according to the voltage and current of the main test device, wherein the parameters to be tested include switching parameters of the wafer and parameters of the reverse recovery process.

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