First configuration method and system of FPGA (Field Programmable Gate Array) chip

Abstract

The invention relates to a first configuration method and system for FPGA chips, and the method comprises the steps: carrying out the cascading of JTAG interfaces of a plurality of FPGA chips, obtaining a chained FPGA, and connecting the chained FPGA with a JTAG protocol device; the JTAG protocol device is configured with a preset data caching rule and a preset data output rule; obtaining configuration instructions and configuration data of the plurality of FPGA chips; performing format conversion on the JTAG configuration information of the plurality of FPGA chips according to a data caching rule and a data output rule to obtain a configuration instruction and configuration data; the configuration instruction comprises an initialization instruction before configuration and a JTAG configuration starting instruction after configuration data transmission is completed; sending a configuration instruction and configuration data to the plurality of FPGA chips to complete JTAG configuration of the FPGA chips of the whole automatic test equipment; and solidifying the configuration data in a nonvolatile memory of the corresponding FPGA chip. According to the scheme, the method is a universal first-time configuration method, JTAG configuration of FPGAs of different manufacturers can be achieved, the program to be configured can be solidified into the Flash, and good universality is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and more particularly to a method and system for first configuration of an FPGA chip. Background Art

[0002] Automatic Test Equipment (ATE) contains many boards. Generally, ATE includes interface boards, high-speed boards, high-voltage boards, etc. The core chips of the boards are mostly FPGA chips. The number of FPGA chips on each board is different (for example, the interface board has 1 FPGA chip, and the high-speed board has 4 FPGA chips), and the FPGA chips on each board are mostly not from the same manufacturer (for example, the interface board is a Xilinx FPGA chip, and the high-speed board is an Altera FPGA chip). After the FPGA is powered on, its internal logic is blank and needs to be configured before it can work. At present, there are many commonly used configuration schemes for FPGA, such as: JTAG configuration, active serial (AS) configuration, passive serial (PS) configuration, HPS configuration, CvP configuration (Configuration via Protocol), etc. These configuration schemes are all provided to users by manufacturers.

[0003] In the field of automatic testing, most FPGA chips of ATE boards use active serial configuration, that is, after the FPGA chip is powered on, it actively sends a read signal to read the configuration data from the non-volatile program memory, then verifies the data, and finally executes the configuration program. In this configuration mode, the non-volatile program memory (Flash) is fixed. Figure 1 As shown, the dedicated downloader connection ( Figure 1 Connect the SFL (Serial Flash Loader) in the FPGA to the JTAG interface of the FPGA, then open the firmware provided by the corresponding manufacturer, and fix the configuration program into the Flash according to the process in the user manual to complete the configuration.

[0004] However, for example, in a test device, it can be fully loaded with 8 high-speed boards and 1 interface board, and a total of 33 FPGA program memories (Flash) need to be solidified. During the batch configuration process, if the above solution is followed, the configuration process is cumbersome and inefficient, and this configuration method is highly dependent on a dedicated downloader. Since the chips produced by different FPGA manufacturers require different dedicated downloaders, the configuration is even more complicated. Summary of the invention

[0005] In view of the above problems in the prior art, the present application provides a method and system for the first configuration of an FPGA chip, which can realize JTAG configuration of FPGAs from different manufacturers, has good versatility, and can simplify the configuration process, realize automatic configuration, and improve configuration efficiency.

[0006] To achieve the above-mentioned purpose, the first aspect of the present application provides a method for the first configuration of an FPGA chip, comprising: in the configuration of multiple FPGA chips of an automatic test equipment, the method comprises: cascading the JTAG interfaces of the multiple FPGA chips to obtain a chained FPGA, and connecting the chained FPGA to a JTAG protocol device to form a configuration path; wherein the JTAG protocol device is configured with preset data caching rules and preset data output rules; obtaining the configuration instructions and configuration data of the multiple FPGA chips; wherein the JTAG configuration information of the multiple FPGA chips is configured according to the data caching rules and the data output rules Perform format conversion to obtain the configuration instructions and configuration data; the configuration instructions include initialization instructions before configuration, and / or JTAG configuration startup instructions after the configuration data transmission is completed; send the configuration instructions and configuration data to the multiple FPGA chips via the JTAG protocol device to complete the JTAG configuration of the multiple FPGA chips of the automatic test equipment; solidify the configuration data in the non-volatile memory of the corresponding FPGA chip via a parallel bus path, wherein the communication bus path includes a host, an interface board and the multiple FPGA chips connected in sequence, and the interface board and the multiple FPGA chips are connected via a communication bus.

[0007] From the above, the present application first connects each FPGA and the JTAG protocol device, thereby constructing a configuration path, providing a basis for subsequent configuration work. In addition, based on the pre-set data cache rules and pre-set data output rules in the JTAG protocol device of the present application, unified storage and output rules of signals are implemented, so that JTAG configuration of FPGAs from different manufacturers can be realized, which has good versatility. Moreover, by solidifying the configuration data in a non-volatile memory, the solidification of the configuration program is realized, so that the relevant configuration can be directly loaded the next time the power is turned on. The configuration method provided by the present application can realize automatic configuration, thereby improving configuration efficiency.

[0008] As an implementation method of the present aspect, the JTAG interfaces of the multiple FPGA chips are cascaded to obtain a chained FPGA, and the chained FPGA is connected to a JTAG protocol device to form a configuration path, including: connecting the clock signals of the JTAG interfaces in each FPGA chip to each other and to the clock signal in the JTAG protocol device; connecting the mode control signals of the JTAG interfaces in each FPGA chip to each other and to the mode control signal in the JTAG protocol device; connecting the output signal of the JTAG interface in each FPGA chip to the input signal of the JTAG interface in the next adjacent FPGA chip, connecting the input signal of the JTAG interface in the FPGA chip at the head end to the output signal in the JTAG protocol device, and connecting the output signal of the JTAG interface in the FPGA chip at the end to the input signal in the JTAG protocol device.

[0009] From the above, through the above connection relationship among the clock signal, mode control signal, input signal and output signal, the cascade between multiple FPGA chips and the connection with the JTAG protocol device are realized, thereby forming a configuration path and providing a basis for subsequent configuration work.

[0010] As an implementation method of the first aspect, the pre-set data caching rules include: when data with a data bus address of a first address is received, the data is cached in a cache area corresponding to the clock signal state of the JTAG protocol device; when data with a data bus address of a second address is received, the data is cached in a cache area corresponding to the output signal state of the JTAG protocol device; when data with a data bus address of a third address is received, the data is cached in a cache area corresponding to the mode control signal state of the JTAG protocol device; when data with a data bus address of a fourth address is received, the data is cached in a cache area corresponding to the input signal state of the JTAG protocol device; when data with a data bus address of a fifth address is received, all received data is cached in a first-in-first-out queue of the JTAG protocol device, wherein all the data includes the clock signal, the output signal, the mode control signal, and / or the input signal.

[0011] From the above, a rule for caching data is provided so that it has no model distinction, thereby improving the versatility of the method.

[0012] As an implementation of the first aspect, it also includes: when the first-in-first-out queue is not empty, reading the data in the first-in-first-out queue, and outputting it according to the preset data output rule.

[0013] As an implementation method of the first aspect, the pre-set data output rules include: each signal outputs a state corresponding to at least two clock cycles, and starts from the low bit and outputs in order from the low bit to the high bit; or, starts from the high bit and outputs in order from the high bit to the low bit; wherein the signal includes a clock signal, a mode control signal, and / or an output signal.

[0014] As an implementation method of the first aspect, the pre-set data output rules include: each signal outputs one state corresponding to two clock cycles; for the clock signal: when the state value of the clock signal is 1, set the first clock cycle to output 0 and the second clock cycle to output 1; when the state value of the clock signal is 0, set the two clock cycles to output 0; for the mode control signal: when the state value of the mode control signal is 1, set the two clock cycles to output 1; when the state value of the mode control signal is 0, set the two clock cycles to output 0; for the output signal: when the state value of the output signal is 1, set the two clock cycles to output 1; when the state value of the output signal is 0, set the two clock cycles to output 0.

[0015] From the above, a data output rule is provided, so that no matter what type of FPGA, the data received is data in a unified format, thus getting rid of the constraint of requiring a specific downloader, supporting unified first-time slave configuration of all types of FPGA, thereby realizing automatic configuration and improving the efficiency of the first-time configuration.

[0016] As an implementation manner of the first aspect, it also includes: determining whether the JTAG protocol device receives data according to a state value of an input signal of the JTAG protocol device.

[0017] As an implementation method of the first aspect, it also includes: when configuring the specified FPGA chip in the chain FPGA, controlling other FPGA chips in the chain FPGA to execute bypass instructions, wherein a bypass register is set between the input signal and the output signal of each FPGA chip that executes the bypass instruction, and the bypass register is used to pass data to the next FPGA chip adjacent to it.

[0018] From the above, by setting the bypass register to execute the instruction command, the configuration process can be made more flexible, so that the user can select the FPGA to be configured according to the needs.

[0019] The second aspect of the present application provides a first configuration system for an FPGA chip, the system comprising: a host, the host being connected to an interface board and a JTAG protocol device respectively, for sending configuration instructions and configuration data to the JTAG protocol device, and for solidifying the configuration data in a non-volatile memory of a corresponding FPGA chip through the interface board; wherein the process of acquiring the configuration instructions and configuration data comprises: converting the format of the JTAG configuration information of the FPGA chip according to data caching rules and data output rules to obtain configuration instructions and configuration data; wherein the configuration instructions include initialization instructions before configuration, and / or JTAG initialization instructions after configuration data transmission is completed; G configuration startup instruction; multiple FPGA chips, the JTAG interfaces of the multiple FPGA chips are cascaded to obtain a chain FPGA, each FPGA chip is connected to at least one non-volatile memory for storing configuration data; a JTAG protocol device, the JTAG protocol device is connected to the multiple FPGA chips through the JTAG interface, and is used to send configuration instructions and configuration data to the multiple FPGA chips to complete the JTAG configuration of the multiple FPGA chips of the automatic test equipment; wherein the JTAG protocol device is configured with pre-set data caching rules and data output rules; an interface board, the interface board is connected to the multiple FPGA chips through a communication bus.

[0020] As an implementation method of the second aspect, the JTAG protocol device includes: a communication module, connected to the host, used to receive configuration instructions and configuration data sent by the host, and also used to send data received from the FPGA to the host; a JTAG status cache module, connected to the communication module, used to cache the configuration instructions and configuration data; a JTAG output module, connected to the JTAG status cache module, used to output according to a preset data output rule when a preset condition is met; a JTAG receiving module, connected to the FPGA chip, used to receive data sent by the FPGA chip; and also connected to the communication module, used to send the data to the communication module.

[0021] The beneficial effects of this aspect can also be found in the description of the beneficial effects of each part of the first aspect above.

[0022] The third aspect of the present application provides a first configuration device for an FPGA chip, including a path configuration module, which is used to cascade the JTAG interfaces of the multiple FPGA chips to obtain a chain FPGA, and connect the chain FPGA to a JTAG protocol device to form a configuration path; wherein the JTAG protocol device includes a pre-set data cache rule and a pre-set data output rule. A format conversion module obtains the configuration instructions and configuration data of the multiple FPGA chips; wherein the JTAG configuration information of the multiple FPGA chips is format-converted according to the data cache logic rule and the data output logic rule to obtain the configuration instructions and configuration data; the configuration instructions include initialization instructions before configuration, and / or JTAG configuration startup instructions after the configuration data transmission is completed; the configuration execution module is used to send the configuration instructions and configuration data to the multiple FPGA chips via the JTAG protocol device to complete the JTAG configuration of the multiple FPGA chips of the automatic test equipment. A configuration solidification module is used to solidify the configuration data in the non-volatile memory of the corresponding FPGA chip via a communication bus path, wherein the communication bus path includes a host, an interface board and the multiple FPGA chips connected in sequence, and the interface board and the multiple FPGA chips are connected via a communication bus.

[0023] The beneficial effects of this aspect can also be found in the description of the beneficial effects of each part of the first aspect above.

[0024] The fourth aspect of the present application provides a computing device, comprising: at least one processor; and at least one memory, which is connected to the processor and stores program instructions, and when the program instructions are executed by the at least one processor, the at least one processor executes the first configuration method of the FPGA chip described in any one of the first aspects above.

[0025] The beneficial effects of this aspect can also be found in the description of the beneficial effects of each part of the first aspect above.

[0026] The fifth aspect of the present application provides a computer-readable storage medium having program instructions stored thereon. When the program instructions are executed by a computer, the computer executes the first configuration method of the FPGA chip described in any one of the first aspects above.

[0027] The beneficial effects of this aspect can also be found in the description of the beneficial effects of each part of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The various technical features of the present application and the relationship between them are further explained below with reference to the accompanying drawings. The accompanying drawings are exemplary, and some technical features are not shown in actual proportion. In addition, some drawings may omit technical features that are commonly used in the technical field to which the present application belongs and are not essential for understanding and implementing the present application, or additional technical features that are not essential for understanding and implementing the present application may be shown. In other words, the combination of the various technical features shown in the accompanying drawings is not used to limit the present application. In addition, throughout the present application, the same figure numbers refer to the same content. The specific description of the drawings is as follows:

[0029] Figure 1 A schematic diagram of the first configuration process of an FPGA chip provided by the prior art;

[0030] Figure 2 A flowchart of a method for first configuring an FPGA chip provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of the cascade connection of the JTAG interface in the FPGA chip provided in the embodiment of the present application;

[0032] Figure 4 A schematic diagram of data cache rule execution in a JTAG protocol device provided in an embodiment of the present application;

[0033] Figure 5 Output waveform diagram of each signal after parsing the data output rule provided in the embodiment of the present application;

[0034] Figure 6 A connection diagram for FPGA configuration of the ATE machine provided in the embodiment of the present application;

[0035] Figure 7 A schematic diagram of the structure of a JTAG protocol device provided in an embodiment of the present application;

[0036] Figure 8 A connection diagram of the Altera Cyclone 10 and Kintex 7 series FPGAs provided in the embodiments of the present application;

[0037] Fig. 9 A schematic diagram of the transmission process of the input signal TDI under the IR command provided in an embodiment of the present application;

[0038] Fig.10 A schematic diagram of data storage of final configuration results of the Altera Cyclone 10 and Kintex 7 series FPGAs provided in an embodiment of the present application;

[0039] Fig.11 A schematic diagram of the structure of a first configuration device for an FPGA chip provided in an embodiment of the present application;

[0040] Fig.12 A structural schematic diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solution provided by the present application is further described below with reference to the accompanying drawings and examples. It should be understood that the system structure and business scenarios provided in the examples of the present application are mainly to illustrate the possible implementation methods of the technical solution of the present application and should not be interpreted as the only limitation on the technical solution of the present application. It is known to those of ordinary skill in the art that with the evolution of the system structure and the emergence of new business scenarios, the technical solution provided by the present application is also applicable to similar technical problems.

[0042] It should be understood that the embodiments of the present application provide a first configuration solution for an FPGA chip. Since the principles of solving the problems in these technical solutions are the same or similar, some repetitions may not be repeated in the following specific embodiments, but it should be considered that these specific embodiments have been referenced to each other and can be combined with each other.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. In case of any inconsistency, the meaning described in this specification or the meaning derived from the contents recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0044] First, the scenario in which the first configuration solution of the FPGA chip provided in the embodiment of the present application is applied is introduced.

[0045] The first configuration scheme of the FPGA chip provided by the present application has the advantages of high configuration efficiency and strong versatility, and is therefore particularly suitable for use in the unified configuration scenario of FPGA chips produced by many different manufacturers. For example, the scheme can be applied to the whole machine configuration of automatic test equipment. The whole machine of the automatic test equipment generally includes many boards, and the FPGA chips of each board are mostly not from the same manufacturer. Based on the first configuration scheme of the FPGA chip provided by the present application, many FPGA chips from different manufacturers can be uniformly and automatically configured, thereby saving manpower and improving configuration efficiency. For another example, the scheme can also be applied to the configuration of network switching equipment. In the field of network switching, FPGAs are often used to process high-speed signals. Based on the configuration scheme of the present application, the efficiency of the first configuration can be improved. For another example, the scheme can also be applied to the configuration of medical equipment or military aerospace equipment. In these fields, there are requirements for fast real-time performance. The first configuration of FPGA chips in related equipment can be realized through the scheme provided by the present application, which can improve configuration efficiency and save time costs.

[0046] It should be understood that the above application scenarios are exemplary descriptions and are not intended to limit the scope of this application.

[0047] Referring to the accompanying drawings below, a method for first configuring an FPGA chip provided in an embodiment of the present application is described in detail.

[0048] like Figure 2 As shown, the first configuration method of the FPGA chip includes steps S110-S140:

[0049] S110: cascading the JTAG interfaces of multiple FPGA chips to obtain a chained FPGA, and connecting the chained FPGA to a JTAG protocol device to form a configuration path; wherein the JTAG protocol device is configured with a preset data cache rule and a preset data output rule.

[0050] In this embodiment, the JTAG interface of the FPGA chip includes a clock signal TCK, a mode control signal TMS, an output signal TDO, and an input signal TDI. Among them, the clock signal TCK is used to provide a clock signal, thereby providing a synchronization and timing mechanism for the system to ensure that the various components inside the system work in a coordinated manner; the mode control signal TMS is used to control the state of the TAP (Test Access Port, located in the FPGA chip) controller, thereby realizing the conversion between various test modes and operation modes; the input signal TDI is the input signal of the FPGA chip; the output signal TDO is the output signal of the FPGA chip.

[0051] In this embodiment, the JTAG protocol device may specifically be an FPGA chip, or other processors, etc., but this embodiment is not limited thereto.

[0052] See next Figure 3 The connection diagram shown in the figure is used to illustrate the specific connection method of this step. Figure 3 As shown, this example includes two boards (board 1 and board 2), each board includes two FPGA chips (that is, a total of 4 FPGA chips in this example), each FPGA chip includes a clock signal TCK, a mode control signal TMS, an output signal TDO, an input signal TDI, and a Flash configuration module, the Flash configuration module is used to configure the corresponding Flash, so that the configuration data can be solidified in the Flash; this example also includes a JTAG socket, the JTAG socket is a physical interface for connecting the JTAG protocol device and the FPGA chip, it should be understood that in other examples, the JTAG protocol device and the FPGA chip can be directly connected without the JTAG socket. Figure 3As shown, the clock signal TCK of the JTAG interface in each FPGA chip is interconnected and connected to the TCK pin of the JTAG socket; the mode control signal TMS of the JTAG interface in each FPGA chip is interconnected and connected to the TMS pin of the JTAG socket; the output signal TDO of the JTAG interface in each FPGA chip is connected to the input signal TDI of the JTAG interface in the next adjacent FPGA chip, for example, the output signal TDO of the first FPGA chip is connected to the input signal TDI of the second FPGA chip, thereby obtaining a chained FPGA; in addition, by analogy, the output signal TDO of the last FPGA chip is connected to the TDO pin of the JTAG socket, and correspondingly, the input signal TDI of the first FPGA chip is connected to the TDI pin of the JTAG socket, thereby realizing the connection between the FPGA chip and the JTAG socket. It should be understood that the JTAG socket is also connected to the JTAG protocol device (not shown in FIG. 1 ). Figure 3 ), the clock signal TCK of the JTAG socket is connected to the clock signal of the JTAG protocol device, the mode control signal TMS of the JTAG socket is connected to the mode control signal of the JTAG protocol device, the input signal TDI of the JTAG socket is connected to the output signal TDI of the JTAG protocol device (it should be understood that since the output signal of the JTAG protocol device is the input signal of the FPGA chip, the output signal of the JTAG protocol device is represented by TDI here), and the output signal TDO of the JTAG socket is connected to the input signal TDO of the JTAG protocol device (TDO here refers to the TDO data sent by the FPGA chip). It should be understood that the JTAG protocol device has two TDO input signals, one of which is the TDO status signal sent by the host to the JTAG protocol device, and the other is the TDO data sent by the FPGA chip, wherein the TDO status signal sent by the host is used to indicate whether the TDO data sent by the FPGA is saved.

[0053] Through the above connection, a chain FPGA is formed and the connection between the chain FPGA and the JTAG protocol device is realized, thereby forming a configuration path.

[0054] S120: Obtain configuration instructions and configuration data of the multiple FPGA chips; wherein, the JTAG configuration information of the multiple FPGA chips is formatted according to the data cache logic rules and the data output logic rules to obtain the configuration instructions and configuration data; the configuration instructions include initialization instructions before configuration, and / or JTAG configuration start instructions after the configuration data transmission is completed.

[0055] As an implementation method, the format conversion process of the JTAG configuration information in this step can be performed by a research and development engineer; as another implementation method, this step can also be performed by a pre-set program via a computer.

[0056] In this embodiment, the JTAG configuration information may specifically include the instruction bit width, instruction code, instruction big and small endianness, reset state, delay, etc. of the configuration instruction. Since the above-mentioned JTAG configuration information of FPGA chips from different manufacturers (such as Xilinx, Altera) is different, in order to enable the configuration method provided in this embodiment to support the JTAG configuration of FPGAs from different manufacturers, the JTAG configuration information is formatted according to the data cache rules and data output rules, so that the formats of JTAG configuration instructions in different formats can be normalized, and JTAG configuration of FPGA chips from different manufacturers can be realized, so that the configuration method of this application has strong versatility.

[0057] Specifically, the pre-set data cache rule includes: receiving the TCK signal sent by the host through the bus of the first address, so when the data with the bus address of the first address is received, the received data is cached in the cache area corresponding to the clock signal state of the JTAG protocol device; receiving the TDI signal sent by the host through the bus of the second address (for the JTAG protocol device, it is an output signal, for the next level FPGA, it is an input signal), so when the data with the bus address of the second address is received, the received data is cached in the cache area corresponding to the TDI signal state of the JTAG protocol device; receiving the mode control signal TMS sent by the host through the bus of the third address, so when the total When the line address is data of the third address, the received data is cached in the cache area corresponding to the mode control signal state of the JTAG protocol device; the TDO status signal sent by the host is received through the bus of the fourth address (the TDO status signal here refers to: whether to save the TDO data sent by the FPGA. Indication information), therefore, when the bus address is the fourth address, the received data is cached in the cache area corresponding to the TDO status signal of the JTAG protocol device; in addition, the deposit flag sent by the host is received through the bus of the fifth address, that is, when the bus address is the fifth address, All the above-mentioned received data are cached in the first-in-first-out queue (First Input First Output, FIFO) of the JTAG protocol device. It should be understood that the above-mentioned received data may include one or more data corresponding to any one or more addresses from the first address to the fourth address.

[0058] Also, see Figure 4The cache flow chart shown continues to explain the cache rules in detail. In this example, the depth of the FIFO is 512 and the bit width is 64; in addition, in this example, for example, the width of the communication data bus is 16 (that is, each data transmission can send or receive 16 bits of data at the same time), and the number of bits of the address bus is 3 (that is, it can directly address 8 different storage locations or addresses, generally address 0 to address 7). It should be understood that the above-mentioned depth, bit width, width of the communication bus, and number of bits of the address bus are all exemplary descriptions and are not used to limit the scope of this application. In other examples, they can all be adjusted according to actual needs.

[0059] Next, combine Figure 4 Detailed description. The JTAG protocol device first receives the data sent by the host through the communication data bus, specifically:

[0060] If data with a data bus address of the first address (ie, addr == 1) is received, the data needs to be cached in a cache area corresponding to the clock signal TCK of the JTAG protocol device, that is:

[0061] Address is 1: cache bus data is 16 states of TCK.

[0062] If data with a data bus address of the second address (i.e., addr==2) is received, the data needs to be cached to the cache area corresponding to the output signal of the JTAG protocol device (i.e., the input signal TDI of the FPGA chip), that is:

[0063] Address 2: Cache bus data is 16 states of TDI

[0064] If data with a data bus address of the third address (ie, addr == 3) is received, the data needs to be cached in a cache area corresponding to the mode control signal TMS of the JTAG protocol device; that is:

[0065] The address is 3, and the cache bus data is 16 states of TMS.

[0066] If data with a data bus address of the fourth address (i.e., addr==4) is received, the data needs to be cached to the cache area corresponding to the TDO status signal of the JTAG protocol device (wherein the TDO status signal is used to indicate whether to save the TDO data sent by the FPGA), that is:

[0067] The address is 4, and the cache bus data is 16 states of TDO.

[0068] If data with the fifth address (addr==5) is received, the "write enable signal (wr_en)" needs to be executed, that is, the received data is written into the FIFO, that is:

[0069] The address is 5, and the 16 status values ​​of any one or more of the above TCK, TDO, TMS, and TDI are stored in FIFO at the same time.

[0070] In this embodiment, the storage format of each signal in the FIFO can be stored in the following format:

[0071] FIFO storage format

[0072] 16 states of TCK 16 states of TDI 16 states of TMS 16 states of TDO

[0073] In this example, as shown in the table above, each row of the FIFO storage queue caches 16 states of TCK, TDI, TMS, and TDO respectively.

[0074] Next, when it is detected that the FIFO is not empty (i.e., there is data), the "read enable signal (rd_en)" is executed, so that the corresponding data is output from the FIFO of the JTAG protocol device (the output here is output according to the preset data output rule, and the output rule is described in detail below). It should be understood that the signal output to the FPGA chip here is generally the clock signal of the JTAG protocol device, the mode control signal of the JTAG protocol device, and the output signal of the JTAG protocol device, and the input signal of the JTAG protocol device is the data sent by the FPGA chip, which is generally fed back to the host and will not be output to the FPGA chip.

[0075] Next, see Figure 5 The output waveform diagram of each signal shown is used to explain the preset data output rule in detail. Continuing with the above example, this example still takes the width of the communication data bus as 16 as an example. Similarly, the data bit width is not used as a limitation on the scope of this application, and it can be changed to other values ​​in other examples.

[0076] In the output rules formulated in the present embodiment, each signal needs at least 2 clocks to output each state. This embodiment is explained by taking exactly 2 clock cycles as an example. Then, for each signal, 32 clocks are required. In addition, in the output rules formulated in the present embodiment, for example, it is possible to start from the high bit and output in order from the high bit to the low bit, or it is possible to start from the low bit and output in order from the low bit to the high bit. It should be understood that whether the output starts from the high bit or the low bit, the output rules are the same, only the output starting point and the output order are different. Since the output of the JTAG protocol device of the present embodiment to the FPGA chip is only TCK, TMS and TDI, the following takes starting from the low bit and outputting in order from the low bit to the high bit as an example to explain in detail how each signal is output, specifically:

[0077] 1. For the clock signal TCK of the JTAG protocol device: when the state value of the clock signal is 1, set the first clock cycle to output 0 and the second clock cycle to output 1; when the state value of the clock signal is 0, set both clock cycles to output 0.

[0078] 2. For the mode control signal TMS of the JTAG protocol device: when the state value of the mode control signal is 1, both clock cycles are set to output 1; when the state value of the mode control signal is 0, both clock cycles are set to output 0.

[0079] 3. For the output signal TDI of the JTAG protocol device: when the state value of the output signal is 1, set the output of 1 in both clock cycles; when the state value of the output signal is 0, set the output of 0 in both clock cycles.

[0080] For example, when the clock signal TCK is 0xF007, its corresponding binary is 1111 0000 0000 0111. According to the above output rule (output from the low bit, and state value 1→01, state value 0→00), it is parsed as follows:

[0081] 1 (least significant bit) → 01, 1 → 01, 1 → 01, 0 → 00

[0082] 0→00,0→00,0→00,0→00

[0083] 0→00,0→00,0→00,0→00

[0084] 1→01, 1→01, 1→01, 1(highest bit)→01

[0085] Connecting them together, the output should be: 01 01 01 01 00 00 00 00 00 00 00 00 00 01 0101, which corresponds to Figure 5 The output waveform of TCK.

[0086] For example, when the mode control signal TMS is 0x5004, its corresponding binary is 0101 0000 0000 0100. According to the above output rule (output from the low bit, and state value 1→11, state value 0→00), it is parsed as follows:

[0087] 0 (least significant bit) → 00, 0 → 00, 1 → 11, 0 → 00

[0088] 0→00,0→00,0→00,0→00

[0089] 0→00,0→00,0→00,0→00

[0090] 1→11, 0→00, 1→11, 0(highest bit)→00

[0091] Connecting them together, the output should be: 00 11 00 11 00 00 00 00 00 00 00 00 00 11 0000, which corresponds to Figure 5 Output waveform of TMS.

[0092] For example, when the output signal is 0x3001, its corresponding binary is 0011 0000 0000 0001. According to the above output rule (output from the low bit, and state value 1→11, state value 0→00), it is parsed as follows:

[0093] 1 (least significant bit) → 11, 0 → 00, 0 → 00, 0 → 00

[0094] 0→00,0→00,0→00,0→00

[0095] 0→00,0→00,0→00,0→00

[0096] 1→11, 1→11, 0→00, 0(highest bit)→00

[0097] Connecting them together, the output should be: 00 00 11 11 00 00 00 00 00 00 00 00 00 00 0011, which corresponds to Figure 5 Here, it should be noted that, as described above, TDI represents the TDI signal sent by the host to the JTAG protocol device, that is, the TDI signal output by the JTAG protocol device to the FPGA chip, that is, the input signal TDI of the FPGA chip. Figure 5 In the example, the TDO status signal refers to the TDO status signal sent by the host to the JTAG protocol device, which is used to indicate whether to save the TDO data sent by the FPGA chip. Figure 5 In the example shown in Figure 1, the TDO status signal is 0x0000.

[0098] In some embodiments, it is also possible to determine whether the JTAG protocol device receives the TDO data sent by the FPGA based on the status value of the TDO status signal of the JTAG protocol device (sent by the host to the JTAG protocol device). For example, when the status value of the TDO status signal is 0, it is defined as not receiving the TDO data sent by the FPGA; when its status value is 1, it is defined as receiving the TDO data sent by the FPGA and when the clock signal is a rising edge, it is defined as saving the TDO data sent by the FPGA.

[0099] S130: Sending the configuration instructions and configuration data to the multiple FPGA chips via the JTAG protocol device to complete the JTAG configuration of the multiple FPGA chips of the automatic test equipment.

[0100] It should be understood that step S120 and step S130 are a complete JTAG configuration process, the purpose of which is to enable the FPGA chip to run a program including a Flash configuration module and a parallel communication function, thereby laying the foundation for subsequent Flash curing operations.

[0101] Based on the above-mentioned predefined data cache rules and predefined data output rules, and according to the configuration path constructed in step S110, the configuration instructions and configuration data are sent to the corresponding FPGA to realize the first configuration of the FPGA. In this embodiment, based on the above-mentioned cache rules and output rules, no matter which type of PFGA chip corresponds to, no matter what kind of configuration instructions (such as bit width, different big and small ends, etc.), the method provided by this application can use a prescribed format for signal storage and signal output, thereby improving the adaptability of the method. In addition, based on the output rules formulated by this application, the output signal and the mode control signal both change on the falling edge of the clock signal, and the rising edge remains unchanged, which also ensures the stability of the output.

[0102] In addition, since the JTAG of the FPGA chip of this embodiment is in a cascade state, in some scenarios, there may be a situation where only part of the FPGA chips need to be configured. Those skilled in the art can understand that a bypass register is also set between the input signal and the output signal of each FPGA chip, and each bypass register is used to execute a bypass instruction, thereby controlling the FPGA chip to bypass and passing the data to the next FPGA chip adjacent to it. That is, when only part of the FPGA chips need to be configured, it is necessary to control the other chips in the cascaded FPGA except the chip to be configured to execute the bypass instruction, so that the configuration data bypasses the FPGA and reaches the target FPGA. It should also be noted that when there is a bypassed FPGA chip, it is necessary to send more data with a preset number of bits when sending configuration data. For FPGA, when the IR instruction is set to bypass, there are actually 2 TCK cycles of delay between TDI and TDO. After multiple devices are cascaded, only the TDI signal of the first level can be controlled. When it is necessary to send N bit data to the second level device, it is necessary to send N+2 bit data to the first level device. In this embodiment, for example: if there is a bypassed FPGA chip, 2 more bits of data need to be sent, of which 1 bit of data is retained in the bypass register of the bypassed FPGA chip, and the other 1 bit of data is retained in the input signal (TDI) of the bypassed FPGA chip.

[0103] Based on this setting, the configuration process can be made more flexible, allowing users to select the target FPGA for configuration according to their needs.

[0104] S140: Solidify the configuration data in the non-volatile memory of the corresponding FPGA chip via a communication bus path, wherein the communication bus path includes a host, an interface board and the multiple FPGA chips connected in sequence, and the interface board and the multiple FPGA chips are connected via a communication bus.

[0105] After executing S130, the configuration program has been loaded into the target FPGA, and the configuration program needs to be solidified next. The implementation methods of non-volatile memory (Flash) configuration corresponding to FPGAs of different manufacturers are also different. For example, Xilinx 7 series FPGA is implemented through the internal primitive STARTUPE2, which provides users with the authority to control the Flash interface. Users can customize the design of the Flash control module according to the erase, write, read and other operations in the Flash manual; another example: Altera Cyclone 10 / Arria 10 series FPGA does not have a primitive similar to STARTUPE2, and it is impossible to customize the design of the Flash control module, but it provides the ASMI IP core, through which the Flash erase, write, read and other operations can be completed. ASMIIP has great limitations, and the Generic Serial Flash Interface Intel FPGA IP can be used to replace the above solidification tool. In the process of curing configuration data in this embodiment, the curing data is sent through the host, and sequentially passes through the communication bus (such as optical fiber), the interface board, the communication bus, and then reaches the Flash configuration module of the FPGA of the corresponding board (that is, the data flow is: host→communication bus→interface board→communication bus→board), and then the Flash configuration module controls the Flash to complete the corresponding curing. It should be understood that for different models of FPGA, the corresponding Flash configuration module is different.

[0106] In this embodiment, the host includes but is not limited to a PC, an industrial computer, and a microcontroller, and its function is to run the control main program and transmit the control data through optical fiber. The function of the interface board is to convert the received control data into parallel data and then send it to the board through a parallel bus. The board is the last level of the system. There are one or more FPGA chips on the board, and each FPGA chip is equipped with a serial Flash memory for storing configuration data.

[0107] In this way, the entire process of the first configuration of the FPGA chip is completed, and the configured program can be automatically loaded at the next power-on.

[0108] The configuration scheme provided in this embodiment supports the configuration of FPGAs from different manufacturers, gets rid of the constraints of specific downloaders, and has good versatility. In addition, the scheme supports automatic configuration, thereby improving the efficiency of the first configuration of the ATE whole machine FPGA.

[0109] Another embodiment of the present application provides a first configuration system 20 for an FPGA chip, and the system 20 is described in detail below with reference to the accompanying drawings.

[0110] like Figure 6 The system 20 is shown as being applied to an ATE machine. In this application scenario, the system 20 includes a plurality of boards (i.e. Figure 6 The boards 1 to n are shown in the figure, each of which is provided with one or more FPGA chips ( Figure 6 Not shown, see Figure 3 To understand the relationship between the board and the FPGA chip), the system also includes a JTAG protocol device, an interface board, and a host. The following describes each part in detail:

[0111] The JTAG interfaces of multiple FPGA chips on multiple boards are cascaded to obtain a chain FPGA. The specific connection method here can be found in the record of step S110 of the above embodiment, which will not be repeated here. In this embodiment, each FPGA chip is connected to at least one Flash, which is used to store configuration data to realize the solidification of the configuration data so that the corresponding configuration is automatically loaded at the next power-on. Specifically, the connection method of each FPGA chip to the Flash can be a serial interface connection or a parallel interface connection, and this embodiment is not limited to this.

[0112] The JTAG protocol device is connected to the FPGA chip via the JTAG interface. The specific connection method here can also be found in the record of step S110 of the above embodiment. It is used to send configuration instructions and configuration data to multiple FPGA chips during the first configuration to complete the JTAG configuration of multiple FPGA chips of the automatic test equipment.

[0113] The process of acquiring configuration instructions and configuration data here includes: converting the JTAG configuration information of multiple FPGA chips according to data cache rules and data output rules to obtain configuration instructions and configuration data; wherein the configuration instructions include initialization instructions before configuration, and / or JTAG configuration startup instructions after the configuration data transmission is completed. wherein, the pre-configured data storage rules and pre-configured data output rules can refer to the relevant records in step S120 of the above embodiment.

[0114] The interface board is connected to multiple FPGA chips on the board through a communication bus. As an implementation method, the communication bus here can be a parallel bus.

[0115] The host is connected to the interface board and the JTAG protocol device respectively. The host is connected to the JTAG protocol device to send configuration instructions and configuration data to the JTAG protocol device. In addition, the host is also connected to the interface board to send the configuration data to the Flash configuration module of the FPGA chip via the interface board. The Flash configuration module solidifies the configuration data in the Flash corresponding to the FPGA chip, so as to realize automatic loading of the configuration at the next power-on.

[0116] The host obtains the configuration instructions and configuration data and sends them to the JTAG protocol device. It should be understood that the process of converting the JTAG configuration information format of multiple FPGA chips to obtain configuration instructions and configuration data can be implemented by computer software or by engineers, and this embodiment is not limited to this.

[0117] As an implementation method, the host computer, the interface board and the JTAG protocol device may be connected via optical fibers.

[0118] As another implementation method, the host and the interface board and the JTAG protocol device may be connected via common cables, wireless, Ethernet, or other methods.

[0119] In this embodiment, if Figure 7 The structure of a JTAG protocol device is shown, and the JTAG protocol device includes a communication module, a JTAG status cache module, a JTAG output module, and a JTAG receiving module. Specifically:

[0120] The communication module is connected to the host and is used to receive configuration instructions and configuration data sent by the host; the communication module is also connected to the JTAG receiving module and is used to send the received data sent by the FPGA chip to the host.

[0121] The JTAG status cache module has an input end connected to the output end of the communication module, and is used to cache the configuration instructions and configuration data. It should be understood that the JTAG status cache module includes, in addition to the FIFO (used to store the data of bus address 5), a storage area for caching the data of bus address 1 to bus address 4 (the data stored in address 1 to address 5 can refer to the description of the above embodiment).

[0122] The JTAG output module, whose input end is connected to the output end of the JTAG status cache module, is used to output data according to the preset data output rules when the preset conditions are met (such as when the received FIFO is not empty). It should be understood that the data output here includes the clock signal TCK, the mode control signal TMS, and the output signal TDI of the JTAG protocol device (the output signal of the JTAG protocol device is the input signal of the FPGA chip, so TDI is used here to represent the output signal of the JTAG protocol device). In addition, the preset data output rules can refer to the records of the above embodiment.

[0123] The JTAG receiving module has an input end connected to the FPGA chip and is used to receive TDO data sent by the FPGA chip. Since one of the input signals of the JTAG receiving module is the output signal of the FPGA chip, Figure 7 TDO represents the input signal of the JTAG receiving module (i.e., the TDO data sent by the FPGA). Its output end is connected to the communication module, which is used to pass the TDO data sent by the FPGA chip to the communication module, and then send the data to the host through the communication module. In addition, the JTAG receiving module is also connected to the JTAG status cache module to receive the data sent by the JTAG status cache module.

[0124] Another embodiment of the present application takes Xilinx 7 series FPGA as an example to illustrate the process of performing the first configuration on the FPGA based on the configuration method.

[0125] First, the components are connected according to the method of step S110 in the above embodiment to form a configuration path.

[0126] Then, via the JTAG protocol device, configuration instructions are sent to the multiple FPGA chips according to the data cache rules and the data output rules preset in step S120 of the above embodiment, thereby completing the initialization before configuration (i.e., the preparation of the system before transmitting the configuration data). For Xilinx 7 series FPGAs, the process includes:

[0127] 1. The JTAG protocol device controls the TAP controller to reset, that is, the mode control signal TMS is set to 1 for 5 consecutive positions (5 bits) starting from the low bit, and the clock signal TCK is set to 1 for 5 consecutive positions starting from the low bit. At this time, the corresponding states of the FPGA chip clock signal TCK, FPGA chip output signal TDO, FPGA chip mode control signal TMS, and FPGA chip input signal TDI are: 0x001F, 0x0000, 0x001F, 0x0000.

[0128] 2. The JTAG protocol device outputs the IR instruction 0x0B to the FPGA. At this time, the corresponding states of the FPGA chip clock signal TCK, the FPGA chip output signal TDO, the FPGA chip mode control signal TMS, and the FPGA chip input signal TDI are: 0x1FFF, 0x0000, 0x0C06, and 0x0160, respectively.

[0129] In this example, the IR instruction is used to instruct the FPGA to perform a specific operation or enter a certain mode. The IR instruction 0x0B is a specific instruction code, which is used to instruct "trigger or start the programming function of the FPGA."

[0130] In this example, the bit width of the IR instruction is 6 and the output is in little-endian format. It should be understood that in different types of FPGAs, the bit width and output mode of the corresponding IR instruction may be different.

[0131] 3. The JTAG protocol device controls the TAP controller to reset, so that the TAP controller enters the RUN-TEST-IDLE (TAP controller scan operation idle state, that is, no test operation) mode, and specifies a delay of at least 10ms in this state (the 10ms here is an exemplary description), so as to provide the system with enough time to process state transitions or complete internal operations. At this time, the corresponding states of the FPGA chip clock signal TCK, FPGA chip output signal TDO, FPGA chip mode control signal TMS, and FPGA chip input signal TDI are: 0x003F, 0x0000, 0x001F, 0x0000.

[0132] 4. The JTAG protocol device controls the TAP controller to output the IR instruction 0x05 to the FPGA. At this time, the corresponding states of the FPGA chip clock signal TCK, the FPGA chip output signal TDO, the FPGA chip mode control signal TMS, and the FPGA chip input signal TDI are: 0x1FFF, 0x0000, 0x0C06, and 0x00A0, respectively.

[0133] In this example, the IR instruction 0x05 is used to indicate "trigger configuration data import", that is, this instruction enables the FPGA to receive configuration data. In this example, the bit width of the IR instruction is 6 and it is a little-endian output.

[0134] 5. The JTAG protocol device controls the TAP controller to enter the Shift-DR state. At this time, the corresponding states of the FPGA chip clock signal TCK, the FPGA chip output signal TDO, the FPGA chip mode control signal TMS, and the FPGA chip input signal TDI are: 0xF, 0x0000, 0x0002, and 0x0000, respectively.

[0135] The Shift-DR state indicates a data register shift state, which is used to shift data into or out of the data register DR, that is, to enter a data read or write state.

[0136] 6. In the Shift-DR state, write the configuration data via the JTAG protocol device. The writing process in this example starts with the big end.

[0137] In Xilinx 7 series FPGA, the configuration data stream is a bit file, binary, read by byte, and the state cache is specified to write 16 states at a time. Therefore, each time 2 bytes of data are read from the bit file, for example, when the 2 bytes read are 0x12 and 0x34, the corresponding state cache data written in the big end is 0x2C48. At this time, the states corresponding to the FPGA chip clock signal TCK, the FPGA chip output signal TDO, the FPGA chip mode control signal TMS, and the FPGA chip input signal TDI are: 0xFFFF, 0x0000, 0x0000, 0x2C48. This step ends after all the data in the bit file corresponding to the configuration data is written.

[0138] 7. The JTAG protocol device controls the TAP controller to output the IR instruction 0x0C to the FPGA. At this time, the corresponding states of the FPGA chip clock signal TCK, the FPGA chip output signal TDO, the FPGA chip mode control signal TMS, and the FPGA chip input signal TDI are: 0x1FFF, 0x0000, 0x0C06, and 0x0180, respectively.

[0139] In this example, the IR instruction 0x0C is used to start the PFGA. The bit width of the IR instruction is 6 and the output is little endian.

[0140] 8. The JTAG protocol device controls the TAP controller to enter RUN-TEST-IDLE, and specifies to maintain 2000 TCKs in this state (the 2000 TCKs here are for example description). At this time, the corresponding states of the FPGA chip clock signal TCK, the FPGA chip output signal TDO, the FPGA chip mode control signal TMS, and the FPGA chip input signal TDI are: 0xFFFF, 0x0000, 0x0000, 0x0000. In this example, the signal is sent in a manner of sending 16 TCK states each time. Therefore, sending 2000 TCKs requires repeating 0xFFFF, 0x0000, 0x0000, 0x0000 for a total of 125 times.

[0141] 9. The JTAG protocol device controls the TAP controller to reset, that is, the mode control signal TMS is set to 1 for 5 consecutive positions (5 bits) from the low position, and the clock signal TCK is set to 1 for 5 consecutive positions from the low position, thereby indicating that the configuration process is completed. At this time, the corresponding states of the FPGA chip clock signal TCK, the FPGA chip output signal TDO, the FPGA chip mode control signal TMS, and the FPGA chip input signal TDI are: 0x001F, 0x0000, 0x001F, 0x0000.

[0142] Based on the above steps 1 to 9, the configuration of the Xilinx 7 series FPGA is completed. It should be understood that the above steps 1 to 4 are preparations before sending the configuration data, and the data reading and writing phase begins from the above step 5 to send the configuration data.

[0143] It should be understood that for different types of FPGAs, the mode control instructions involved may be different, which can be obtained by referring to the product manual.

[0144] Another embodiment of the present application uses the chain FPGA structure including different types of FPGA as an example to illustrate the configuration process. Specifically, taking the Altera Cyclone 10 and Kintex 7 series FPGA as examples, the configuration method is similar to the configuration process of the Xilinx 7 series FPGA in the above embodiment, and both use the pre-set data cache rules and data output rules provided in the above embodiment for data processing. The difference is that the respective instruction codes, instruction bit widths, and data import endianness are different.

[0145] like Figure 8 As shown, each FPGA chip in this embodiment is regarded as a device, which includes four devices (i.e. Figure 8 Device1 to Device4 in the example, where Device1 and Device3 are Cyclone 10, and Device2 and Device4 are Kintex 7. In addition, in this embodiment, the target FPGA chip is Device4, that is, the configuration data needs to be input into Device4, while Device1 to Device3 do not need this configuration. The configuration process is described in detail below:

[0146] First, in this example, even if the chip models are different, they are still cascaded in the manner described in step S110 of the above embodiment to obtain a chain FPGA, specifically: all FPGA chips share the clock signal TCK and the mode control signal TMS, that is, the clock signals TCK of all FPGA chips are connected to each other, and the mode control signals TMS of all FPGA chips are connected to each other; the output signals of all FPGA chips are connected to the input signals of the next-level FPGA chip, that is: the output signal TDO of Device 1 is connected to the input signal TDI of Device 2, the output signal TDO of Device 2 is connected to the input signal TDI of Device 3, and the output signal TDO of Device 3 is connected to the input signal TDI of Device 4, thereby completing the cascading of Device 1 to Device 4.

[0147] Then, the TAP controller is controlled by the JTAG protocol device to enter the Shift-IR state. Then, in this state, the binary IR instruction sequence of the input signal TDI 1111111111_1111111_1111111111_001011 passes through Device1, Device2, Device3, and reaches Device4. Fig. 9 The transmission process of the input signal TDI is shown, that is, the input signal TDI first passes through Device1 and then outputs TDO, then the TDO (ie, TDI_1) passes through Device2 and then outputs TDO_1, then the TDO_1 (ie, TDI_2) passes through Device3 and then outputs TDO_2, then the TDO_2 (ie, TDI_3) passes through Device4 and then outputs TDO_3.

[0148] However, it should be noted that since Device4 is the target FPGA, Device1, Device2 and Device3 should be bypassed FPGAs. Therefore, bypass instructions are executed in Device1, Device2 and Device3 respectively, only data transmission paths are provided, and JTAG programming operations are not performed, while JTAG programming operations are performed in Device4.

[0149] In this embodiment, the Shift-IR state represents the shift instruction register state. In the Shift-IR state, at each rising edge of the clock signal TCK, the TDI-shift register-TDO serial channel shifts one bit to the right, and the JTAG instruction is shifted into the shift register bit by bit from the TDI pin, while the data in the shift register is shifted out from the TDO pin bit by bit.

[0150] Next, when writing configuration data, the JTAG protocol device controls the TAP controller to enter the Shift-DR state (indicating the data register shift state, used to move data into or out of the data register DR, i.e., enter the data read or write state), and the data flow passes through Device1, Device2, and Device3 in sequence until it is transmitted to Device4. It should be noted that the data flow here includes the target data (i.e., the data transmitted to the target device Device4) and the data retained in the bypass registers of the bypassed devices (Device1, Device2, and Device3) and the data in their corresponding output signals. Among them, the bypass register of Device1 retains 1 bit of data, and the output signal of Device1 retains 1 bit of data; the bypass register of Device2 retains 1 bit of data, and the output signal of Device2 retains 1 bit of data; the bypass register of Device3 retains 1 bit of data, and the output signal of Device3 retains 1 bit of data. It should be understood that the data retained in the bypass register of the bypass device and its output signal can be any value of 0 or 1. Therefore, for this transmission process, since there are three bypassed devices before the target device, a total of N+6 bits of data need to be sent when sending data. Finally, the configuration data is solidified by the method provided in the above embodiment, such as Fig.10 The final configuration result is shown, in which 1 bit of data is retained in the bypass registers of Device1 to Device3 respectively, 1 bit of data is retained in the output signals of Device1 to Device3 respectively, and N bits of target configuration data is retained in Device4.

[0151] In this way, the configuration of the target FPGA chip Device4 is realized and the FPGA chips Device1 to Device3 are bypassed.

[0152] Another embodiment of the present application provides a first configuration device 30 for an FPGA chip. It should be understood that: Fig.11 This is only a structural schematic diagram of an FPGA chip first configuration device 30, and the present application does not limit the division of functional modules in the FPGA chip first configuration device. Fig.11 As shown, the device 30 can be logically divided into multiple modules, each module can have different functions, and the functions of each module can be implemented by a processor in a computing device reading and executing instructions in a memory. Exemplarily, the device 30 includes a path configuration module 310, a format conversion module 320, a configuration execution module 330, and a configuration solidification module 340. In one implementation, the first configuration device 30 of the FPGA chip is used to execute Figure 2The content shown.

[0153] Specifically: the path configuration module 310 is used to cascade the JTAG interfaces of the multiple FPGA chips to obtain a chain FPGA, and connect the chain FPGA to the JTAG protocol device to form a configuration path; wherein the JTAG protocol device includes a pre-set data cache rule and a pre-set data output rule. The format conversion module 320 is used to obtain the configuration instructions and configuration data of multiple FPGA chips; wherein the JTAG configuration information of multiple FPGA chips is format-converted according to the data cache rule and the data output rule to obtain the configuration instructions and configuration data; the configuration instructions include the initialization instructions before configuration, and / or the JTAG configuration startup instructions after the configuration data transmission is completed. The configuration execution module 330 is used to send configuration instructions and configuration data to multiple FPGA chips via the JTAG protocol device to complete the JTAG configuration of multiple FPGA chips of the automatic test equipment. The configuration solidification module 340 is used to solidify the configuration data in the non-volatile memory of the corresponding FPGA chip via the communication bus path, wherein the communication bus path includes a host, an interface board and multiple FPGA chips connected in sequence, and the interface board and the multiple FPGA chips are connected through a communication bus.

[0154] The specific implementation of each functional module in this embodiment can refer to the introduction of the above embodiments, and this embodiment will not describe it in detail.

[0155] Fig.12 900 is a schematic structural diagram of a computing device 900 provided in an embodiment of the present application. The computing device can execute the optional embodiments of the above-mentioned first configuration method of the FPGA chip. The computing device can be a terminal, or a chip or chip system inside the terminal. Fig.12 As shown, the computing device 900 includes: a processor 910 , a memory 920 , and a communication interface 930 .

[0156] It should be understood that Fig.12 The communication interface 930 in the computing device 900 shown may be used to communicate with other devices, and may specifically include one or more transceiver circuits or interface circuits.

[0157] The processor 910 may be connected to a memory 920. The memory 920 may be used to store the program code and data. Therefore, the memory 920 may be a storage unit inside the processor 910, or an external storage unit independent of the processor 910, or a component including a storage unit inside the processor 910 and an external storage unit independent of the processor 910.

[0158] Optionally, the computing device 900 may further include a bus. The memory 920 and the communication interface 930 may be connected to the processor 910 via the bus. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.12 A line without an arrow is used to represent the bus, but this does not mean that there is only one bus or one type of bus.

[0159] It should be understood that in the embodiment of the present application, the processor 910 may adopt a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. Alternatively, the processor 910 may adopt one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiment of the present application.

[0160] The memory 920 may include a read-only memory and a random access memory, and provides instructions and data to the processor 910. A portion of the processor 910 may also include a nonvolatile random access memory. For example, the processor 910 may also store information on the device type.

[0161] When the computing device 900 is running, the processor 910 executes the computer-executable instructions in the memory 920 to perform any operation step of the above method and any optional embodiment thereof.

[0162] It should be understood that the computing device 900 according to the embodiment of the present application can correspond to the corresponding subjects in the methods according to the embodiments of the present application, and the above-mentioned and other operations and / or functions of each module in the computing device 900 are respectively for implementing the corresponding processes of each method of the present embodiment. For the sake of brevity, they will not be repeated here.

[0163] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0164] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0165] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0166] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0167] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0168] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0169] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, it is used to execute the above method, which includes at least one of the solutions described in the above embodiments.

[0170] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive lists) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing programs, which can be used by instruction execution systems, devices or devices or used in combination with them.

[0171] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0172] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0173] Computer program code for performing the operation of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., using an Internet service provider to connect through the Internet).

[0174] In addition, the words "first, second, third, etc." or module A, module B, module C and other similar terms in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that the specific order or sequence can be interchanged where permitted so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0175] In the above description, the numbers representing the steps, such as S110, S120, etc., do not necessarily mean that the steps will be executed in this manner. If permitted, the order of the steps can be interchanged or they can be executed simultaneously.

[0176] The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the features, integers, steps or components mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components and groups thereof. Therefore, the expression "a device comprising means A and B" should not be limited to a device consisting of components A and B only.

[0177] References to "one embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. In addition, in one or more embodiments, the particular features, structures, or characteristics can be combined in any appropriate manner, as would be apparent to one of ordinary skill in the art from this disclosure.

[0178] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present application, all of which belong to the scope of protection of the present application.

Claims

1. A method for first configuration of an FPGA chip, characterized in that: Applied to the configuration of multiple FPGA chips of an automatic test equipment, the method includes: Cascading the JTAG interfaces of the plurality of FPGA chips to obtain a chained FPGA, and connecting the chained FPGA to a JTAG protocol device to form a configuration path; wherein the JTAG protocol device is configured with a preset data cache rule and a preset data output rule; Obtaining configuration instructions and configuration data of the multiple FPGA chips; wherein the JTAG configuration information of the multiple FPGA chips is formatted according to the data cache rule and the data output rule to obtain the configuration instructions and configuration data; the configuration instructions include initialization instructions before configuration, and / or JTAG configuration startup instructions after the configuration data transmission is completed; Sending the configuration instructions and configuration data to the multiple FPGA chips via the JTAG protocol device to complete the JTAG configuration of the multiple FPGA chips of the automatic test equipment; The configuration data is solidified in the non-volatile memory of the corresponding FPGA chip via a communication bus path, wherein the communication bus path includes a host, an interface board and the multiple FPGA chips connected in sequence, and the interface board and the multiple FPGA chips are connected via a communication bus.

2. The method according to claim 1, characterized in that The step of cascading the JTAG interfaces of the plurality of FPGA chips to obtain a chained FPGA, and connecting the chained FPGA to a JTAG protocol device to form a configuration path includes: Connecting the clock signals of the JTAG interfaces in the FPGA chips to each other and to the clock signal in the JTAG protocol device; Connecting the mode control signals of the JTAG interfaces in the FPGA chips to each other and to the mode control signals in the JTAG protocol device; Connect the output signal of the JTAG interface in each FPGA chip with the input signal of the JTAG interface in the next adjacent FPGA chip, connect the input signal of the JTAG interface in the FPGA chip at the head end with the output signal in the JTAG protocol device, and connect the output signal of the JTAG interface in the FPGA chip at the end with the input signal in the JTAG protocol device.

3. The method according to claim 1, characterized in that The pre-set data cache rules include: When receiving data whose data bus address is a first address, cache the data in a cache area corresponding to the clock signal state of the JTAG protocol device; When receiving data whose data bus address is the second address, cache the data in a cache area corresponding to the output signal state of the JTAG protocol device; When receiving data whose data bus address is a third address, cache the data in a cache area corresponding to the state of the JTAG protocol device mode control signal; When receiving data whose data bus address is a fourth address, cache the data in a cache area corresponding to the input signal state of the JTAG protocol device; When data with a data bus address of the fifth address is received, all received data is cached in a first-in-first-out queue of the JTAG protocol device, wherein all the data includes the clock signal, the output signal, the mode control signal, and / or the input signal.

4. The method according to claim 3, characterized in that Also includes: When the FIFO queue is not empty, the data in the FIFO queue is read and output according to the preset data output rule.

5. The method according to claim 1, characterized in that Also includes: Whether the JTAG protocol device receives data is determined according to a state value of an input signal of the JTAG protocol device.

6. The method according to claim 1, characterized in that The preset data output rules include: Each signal outputs a state corresponding to at least two clock cycles, and is output in order from low to high starting from the low bit; or, is output in order from high to low starting from the high bit; wherein the signal includes a clock signal, a mode control signal, and / or an output signal.

7. The method according to claim 6, characterized in that The preset data output rules include: each signal outputs one state corresponding to two clock cycles; For the clock signal: when the state value of the clock signal is 1, the first clock cycle is set to output 0 and the second clock cycle is set to output 1; when the state value of the clock signal is 0, both clock cycles are set to output 0; For the mode control signal: when the state value of the mode control signal is 1, the two clock cycles are set to output 1; when the state value of the mode control signal is 0, the two clock cycles are set to output 0; For the output signal: when the state value of the output signal is 1, the two clock cycles are set to output 1; when the state value of the output signal is 0, the two clock cycles are set to output 0.

8. The method according to claim 1, characterized in that Also includes: When configuring the specified FPGA chip in the chain FPGA, the other FPGA chips in the chain FPGA are controlled to execute bypass instructions, wherein a bypass register is set between the input signal and the output signal of each FPGA chip that executes the bypass instruction, and the bypass register is used to pass data to the next FPGA chip adjacent to it.

9. A first configuration system for an FPGA chip, characterized in that: The system comprises: A host, the host is connected to the interface board and the JTAG protocol device respectively, and is used to send configuration instructions and configuration data to the JTAG protocol device, and is also used to fix the configuration data in the non-volatile memory of the corresponding FPGA chip through the interface board; wherein the process of obtaining the configuration instructions and configuration data includes: converting the format of the JTAG configuration information of the FPGA chip according to the data cache rule and the data output rule to obtain the configuration instructions and configuration data; wherein the configuration instructions include initialization instructions before configuration, and / or JTAG configuration start instructions after the configuration data transmission is completed; Multiple FPGA chips, wherein the JTAG interfaces of the multiple FPGA chips are cascaded to obtain a chain FPGA, and each FPGA chip is connected to at least one non-volatile memory for storing configuration data; A JTAG protocol device, wherein the JTAG protocol device is connected to the multiple FPGA chips via a JTAG interface, and is used to send the configuration instructions and configuration data to the multiple FPGA chips to complete the JTAG configuration of the multiple FPGA chips of the automatic test equipment; wherein the JTAG protocol device is configured with the pre-set data cache rules and the data output rules; An interface board is connected to the multiple FPGA chips via a communication bus.

10. The system according to claim 9, characterized in that The JTAG protocol device comprises: A communication module, connected to the host, used to receive the configuration instruction and the configuration data sent by the host, and also used to send data received from the FPGA to the host; A JTAG status cache module, connected to the communication module, for caching the configuration instructions and the configuration data; A JTAG output module, connected to the JTAG status cache module, for outputting according to the preset data output rule when a preset condition is met; The JTAG receiving module is connected to the FPGA chip and is used to receive data sent by the FPGA chip; it is also connected to the communication module and is used to send the data to the communication module.

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