Detection method and circuit for peripheral device connection output by chip

Abstract

The embodiments of the present disclosure provide a detection method and circuit for the connection of peripheral devices output by a chip, the method comprising: pulling down the voltage of the second pin to zero potential through the first transistor inside the chip; pulling down the voltage of the output end to zero potential through the second transistor inside the chip; charging the first capacitor through the third transistor inside the chip, so that the first capacitor, the inductor, the second capacitor, and the second transistor form a resonant circuit; obtaining the voltage waveform of the second pin, and detecting the voltage waveform according to a preset detection rule, and outputting a waveform detection result signal; performing logical processing on the waveform detection result signal to obtain a safety detection result signal, and judging whether all peripheral devices output by the chip are connected normally according to the safety detection result signal. The method solves the problem that the existing detection method for the connection of peripheral devices output by a chip cannot simultaneously monitor the connection of all peripheral devices output by the chip, thus affecting the actual results of the functional safety detection of the chip.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of power supply technology, and in particular, to a detection method and circuit for peripheral device connection output by a chip. Background Art

[0002] With the development of integrated circuits, functional safety mechanisms are becoming more and more perfect. Functional safety mechanisms require chips (such as switching power supplies, etc.) to be able to detect whether the output peripheral devices are connected properly after power-on. If the peripheral devices have open circuits due to cold soldering, the error status needs to be indicated.

[0003] like Figure 1 As shown in the figure, it is an application block diagram of a switching power supply (BUCK type). In actual applications, if VOUT is to have a normal output, the corresponding output function safety mechanism requires that the BUCK can detect whether the output peripheral devices, the bootstrap capacitor CBST, the output inductor L1 and the load capacitor COUT are all connected after power-on. Only when all peripheral devices are connected normally can the chip output be considered normal and the function is safe.

[0004] Regarding the detection of the connection of peripheral devices output by the chip, the existing technology only detects whether one of the peripheral devices, such as the load capacitor or the output inductor, is disconnected, and cannot monitor the connection of all peripheral devices output by the chip at the same time, which affects the actual results of the chip functional safety detection. Summary of the invention

[0005] The embodiments described in the present disclosure provide a method and circuit for detecting the connection of peripheral devices output by a chip, in order to solve the problem that the above-mentioned existing method for detecting the connection of peripheral devices output by a chip cannot simultaneously monitor the connections of all peripheral devices output by the chip, thus affecting the actual results of the chip functional safety detection.

[0006] According to a first aspect of the present disclosure, a method for detecting the connection of a peripheral device output by a chip is provided, wherein the peripheral device comprises a first capacitor, a second capacitor, and an inductor, wherein the first capacitor is coupled between a first pin and a second pin of the chip, the second capacitor is coupled between an output terminal and a ground terminal of the chip, and the inductor is coupled between the second pin and the output terminal, and the method comprises: pulling down the voltage of the second pin to zero potential through a first transistor inside the chip; pulling down the voltage of the output terminal to zero potential through a second transistor inside the chip; charging the first capacitor through a third transistor inside the chip, so that the first capacitor, the inductor, and the third transistor are connected to each other. The two capacitors and the second transistor form a resonant circuit; the voltage waveform of the second pin is obtained, and the voltage waveform is detected according to a preset detection rule, and a waveform detection result signal is output, wherein the preset detection rule is that when the peak of the voltage waveform of the second pin is between the first voltage and the second voltage, the waveform detection result signal is a high level, and when the peak of the voltage waveform is not between the first voltage and the second voltage, the waveform detection result signal is a low level, and the first voltage is less than the second voltage; the waveform detection result signal is logically processed to obtain a safety detection result signal, and based on the safety detection result signal, it is judged whether all peripheral devices output by the chip are connected normally.

[0007] Optionally, performing logical processing on the waveform detection result signal to obtain a safety detection result signal includes: determining whether a high-level pulse signal within a preset range is detected within the detection window, wherein the preset range is determined based on the time it takes for the peak of the voltage waveform of the second pin to decay from the second voltage to the first voltage when all peripheral devices are connected normally; if a high-level pulse signal within the preset range is detected, the safety detection result signal is a high level; if no high-level pulse signal within the preset range is detected, the safety detection result signal is a low level.

[0008] Optionally, judging whether all peripheral devices output by the chip are connected normally according to the safety detection result signal includes: if the safety detection result signal is at a high level, determining that all peripheral devices output by the chip are connected normally; if the safety detection result signal is at a low level, determining that all peripheral devices output by the chip are not connected normally.

[0009] Optionally, after determining that not all peripheral devices output by the chip are connected normally, the method further includes: determining the device in which an open circuit occurs among all peripheral devices based on the voltage waveform of the second pin and the waveform of the waveform detection result signal; and / or determining the device in which a short circuit occurs among all peripheral devices based on the voltage waveform of the second pin and the voltage waveform of the first pin.

[0010] According to a second aspect of the present disclosure, a detection circuit for connecting peripheral devices output by a chip is provided, wherein the peripheral devices include a first capacitor, a second capacitor, and an inductor, wherein the first capacitor is coupled between a first pin and a second pin of the chip, the second capacitor is coupled between an output terminal and a ground terminal of the chip, and the inductor is coupled between the second pin and the output terminal, and the circuit includes: a first discharge module, a second discharge module, a charging module, a waveform detection module, and a logic processing module, wherein the first discharge module is configured to pull down the voltage of the second pin to zero potential through a first transistor inside the chip; the second discharge module is configured to pull down the voltage of the output terminal to zero potential through a second transistor inside the chip; and the charging module is configured to charge the first capacitor through a third transistor inside the chip, so that the first The capacitor, the inductor, the second capacitor, and the second discharge module form a resonant circuit; the waveform detection module is configured to obtain the voltage waveform of the second pin, detect the voltage waveform of the second pin according to a preset detection rule, and output a waveform detection result signal, wherein the preset detection rule is that when the peak of the voltage waveform of the second pin is between the first voltage and the second voltage, the waveform detection result signal is a high level, and when the peak of the voltage waveform of the second pin is not between the first voltage and the second voltage, the waveform detection result signal is a low level, and the first voltage is less than the second voltage; the logic processing module is configured to receive the waveform detection result signal, perform logic processing on the waveform detection result signal to obtain a safety detection result signal, and determine whether all peripheral devices output by the chip are connected normally according to the safety detection result signal.

[0011] Optionally, the first discharge module includes: the first transistor, wherein the first electrode of the first transistor is coupled to the second pin, and the second electrode of the first transistor is coupled to the ground terminal, and when the first transistor is in an open state, the voltage of the second pin is pulled down to zero potential.

[0012] Optionally, the second discharge module includes: the second transistor and a resistor, wherein the first electrode of the second transistor is coupled to one end of the resistor, the second electrode of the second transistor is coupled to the ground, and the second transistor is used to control whether the voltage of the output end is discharged to zero potential; the other end of the resistor is coupled to the output end.

[0013] Optionally, the charging module includes: the third transistor and a switch, wherein the first electrode of the third transistor is coupled to the power supply voltage, and the second electrode of the third transistor is coupled to one end of the switch; the other end of the switch is coupled to the first pin, and the switch is used to control whether the power supply voltage charges the first capacitor.

[0014] Optionally, the logic processing of the waveform detection result signal to obtain a safety detection result signal, and judging whether all peripheral devices output by the chip are connected normally according to the safety detection result signal include: judging whether a high-level pulse signal within a preset range is detected in the detection window, and the preset range is determined according to the time length for the peak of the voltage waveform of the second pin to decay from the second voltage to the first voltage when all peripheral devices are connected normally; if a high-level pulse signal within the preset range is detected, the safety detection result signal is a high level, and it is determined that all peripheral devices output by the chip are connected normally; if no high-level pulse signal within the preset range is detected, the safety detection result signal is a low level, and it is determined that not all peripheral devices output by the chip are connected normally.

[0015] Optionally, the chip is a switching voltage converter, and the first transistor is a lower power transistor of the switching voltage converter.

[0016] In the detection method and circuit of the peripheral device connection of the chip output of the embodiment of the present disclosure, the first capacitor, the second capacitor, and the inductor are combined into a resonant circuit, and the voltage waveform of the resonant circuit is detected and logically processed to obtain a safety detection result signal, and the signal is used to determine whether all peripheral devices (first capacitor, second capacitor, inductor) are connected normally. Compared with the prior art, all peripheral devices at the chip output end can be monitored, and one signal can be used to determine whether all peripheral devices are connected normally, which is convenient and comprehensive, ensuring the effectiveness and comprehensiveness of functional safety detection. In addition, the first transistor, the second transistor, the third transistor, etc. in the embodiment of the present disclosure are all devices inside the chip itself, which is equivalent to fully reusing the devices inside the chip, reducing the occupied area. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0018] Figure 1 An application block diagram corresponding to an existing switching power supply is shown;

[0019] Figure 2A flow chart showing a method for detecting peripheral device connections output by a chip according to an embodiment of the present disclosure;

[0020] Figure 3 A schematic block diagram showing a detection circuit for connecting peripheral devices output by a chip according to an embodiment of the present disclosure;

[0021] Figure 4 An exemplary circuit diagram showing a detection circuit for peripheral device connections of a chip output according to an embodiment of the present disclosure;

[0022] Figure 5-8 Schematic diagrams of waveforms corresponding to the detection circuit of the peripheral device connection output by the chip of the embodiment of the present disclosure under four working conditions: all peripheral devices are connected normally, the first capacitor is disconnected, the inductor is disconnected, and the second capacitor is disconnected;

[0023] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the specification and the relevant technology, and will not be interpreted in an idealized or overly formal form unless otherwise clearly defined herein. As used herein, statements that two or more parts are "connected" or "coupled" together should refer to these parts being directly combined together or combined through one or more intermediate components. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0026] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as a control terminal, and the remaining two terminals of the MOS transistor are referred to as a first terminal and a second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0027] In order to solve the problem that the existing detection method for the connection of peripheral devices output by the chip cannot monitor the connection of all peripheral devices output by the chip at the same time, thus affecting the actual results of the functional safety detection of the chip. A new detection method (method and circuit) for the connection of peripheral devices output by the chip is proposed. The detection method for the connection of peripheral devices output by the chip of the embodiment disclosed in the present invention forms a resonant circuit by using the peripheral devices at the output end of the chip, obtains a safety detection result signal by detecting and logically processing the voltage waveform of the resonant circuit, and uses the signal to determine whether all peripheral devices are connected normally. The detection method and circuit for the connection of peripheral devices output by the chip disclosed in the present invention are described in detail below.

[0028] Figure 2 The flowchart of the detection method 100 of the peripheral device connection of the chip output of the embodiment of the present disclosure is shown. First of all, it should be noted that the peripheral device of the chip output in the embodiment of the present disclosure includes a first capacitor, a second capacitor, and an inductor, wherein the first capacitor is coupled between the first pin and the second pin of the chip, the second capacitor is coupled between the output terminal and the ground terminal of the chip, and the inductor is coupled between the second pin and the output terminal. Figure 2 As shown, the detection method for the connection of the peripheral devices output by the chip includes steps S101-S105: S101. Pull down the voltage of the second pin to zero potential through the first transistor inside the chip; S102. Pull down the voltage of the output end to zero potential through the second transistor inside the chip; S103. Charge the first capacitor through the third transistor inside the chip, so that the first capacitor, the inductor, the second capacitor, and the second transistor form a resonant circuit; S104. Obtain the voltage waveform of the second pin, and detect the voltage waveform according to the preset detection rule, and output the waveform detection result signal; S105. Perform logical processing on the waveform detection result signal to obtain a safety detection result signal, and judge whether all the peripheral devices output by the chip are connected normally according to the safety detection result signal.

[0029] In step S101, the first transistor is a transistor coupled between the second pin and the ground terminal. The voltage of the second pin is pulled down to zero potential by the first transistor in order to reset the resonant circuit in the subsequent steps to an initial state to ensure the accuracy of the subsequent detection results. In step S102, the second transistor is a transistor coupled between the output terminal and the ground terminal. The voltage of the chip output terminal is pulled down to zero potential by the second transistor in order to form a resonant circuit with the first capacitor, inductor, second capacitor, and second transistor in the subsequent steps, which is not affected by the output terminal, and ensures that the output terminal is at zero potential during the entire detection process.

[0030] In step S103, the inventor combines the types and connection structures of all the output peripheral devices to integrate all the peripheral devices of the chip into a resonant circuit, so as to judge whether the peripheral devices constituting the resonant circuit are connected normally through the change of the resonant circuit waveform.

[0031] In step S104, the preset detection rule is that when the peak of the voltage waveform of the second pin is between the first voltage and the second voltage, the waveform detection result signal is a high level, and when the peak of the voltage waveform is not between the first voltage and the second voltage, the waveform detection result signal is a low level, and the first voltage is less than the second voltage. The theoretical basis of the detection in step S104 is that only when the devices in the resonant circuit are connected normally, the voltage waveform of the resonant circuit will be a gradual decay process. The first voltage and the second voltage are set to determine whether there is a gradual decay process, and then to determine whether all connections are normal. In addition, the preset detection rule is also set to convert the voltage waveform (resonance waveform) of the second pin into a square wave, which is convenient for the processing of subsequent steps.

[0032] In step S105, the waveform detection result signal is logically processed to obtain a safety detection result signal, including: determining whether a high-level pulse signal within a preset range is detected within the detection window, and the preset range is determined according to the time length of the peak of the voltage waveform of the second pin decaying from the second voltage to the first voltage when all peripheral devices are connected normally; if a high-level pulse signal within the preset range is detected, the safety detection result signal is a high level; if a high-level pulse signal within the preset range is not detected, the safety detection result signal is a low level. Wherein, assuming that the time length of the peak of the voltage waveform of the second pin decaying from the second voltage to the first voltage is T, the preset range is an interval range near T including T, for example, if T is 100μs, the preset range can be set to (80μs, 120μs), or (85μs, 115μs) and other intervals. Because when the parameters of all peripheral devices remain unchanged, theoretically, the time it takes for the peak of the voltage waveform of the second pin to decay from the second voltage to the first voltage is almost unchanged. In this way, it can be determined within the detection window whether a high-level pulse signal with a fixed duration, such as a high-level pulse of 100 microseconds, is detected. However, in actual applications, there may be some discrepancies with the theory. Therefore, it is set to determine whether a high-level pulse within a preset range can be detected.

[0033] Further, in step S105, judging whether all peripheral devices outputted by the chip are connected normally according to the safety detection result signal includes: if the safety detection result signal is at a high level, then judging whether all peripheral devices outputted by the chip are connected normally; if the safety detection result signal is at a low level, then judging whether all peripheral devices outputted by the chip are not connected normally. It can be seen that judging whether all peripheral devices outputted by the chip are connected normally can be judged according to the state of the safety detection result signal.

[0034] From the above description, it can be seen that in the detection method of the peripheral device connection of the chip output of the embodiment of the present disclosure, the first capacitor, the second capacitor, and the inductor are combined into a resonant circuit, and the voltage waveform of the resonant circuit is detected and logically processed to obtain a safety detection result signal, and the signal is used to determine whether all peripheral devices (first capacitor, second capacitor, inductor) are connected normally. Compared with the prior art, all peripheral devices at the output end of the chip can be monitored, and one signal can be used to determine whether all peripheral devices are connected normally. It is convenient and comprehensive, and the effectiveness and comprehensiveness of functional safety detection are guaranteed. In addition, the first transistor, the second transistor, the third transistor, etc. in the embodiment of the present disclosure are all devices inside the chip itself, which is equivalent to fully reusing the devices inside the chip, reducing the occupied area.

[0035] Further, in practical applications, after determining that all peripheral devices output by the chip are not connected normally, if one wants to further determine which device is abnormally connected, the following method can be used to determine: determine the device with an open circuit among all peripheral devices according to the voltage waveform of the second pin and the waveform of the waveform detection result signal; and / or determine the device with a short circuit among all peripheral devices according to the voltage waveform of the second pin and the voltage waveform of the first pin. Wherein, determining the device with an open circuit among all peripheral devices according to the voltage waveform of the second pin and the waveform of the waveform detection result signal includes: if the voltage waveform of the second pin and the waveform of the waveform detection result signal are both always at a low level, then it is determined that the first capacitor is abnormally connected and there is an open circuit; if the voltage waveform of the second pin is at a high level, but the waveform of the waveform detection result signal is always at a low level, then it is determined that the inductor is abnormally connected and there is an open circuit; if the voltage waveform of the second pin and the waveform of the waveform detection result signal are both at a high level, then it is determined that the second capacitor is abnormally connected and there is an open circuit. In determining whether the second capacitor is short-circuited, it is also possible that when the second capacitor is short-circuited, the waveform detection result signal is always at a low level. In this case, it is impossible to determine whether the second capacitor is short-circuited or the inductor is short-circuited by "if the voltage waveform of the second pin and the waveform of the waveform detection result signal are both at a high level, it is determined that the second capacitor is abnormally connected and there is a short circuit". In this case, it is necessary to determine whether the voltage waveform of the second pin decays to zero quickly, and if so, it is determined that the second capacitor is abnormally connected and there is a short circuit". Among them, determining the short-circuited device among all peripheral devices based on the voltage waveform of the second pin and the voltage waveform of the first pin includes: if the voltage waveform of the second pin rises to a lower voltage value along with the voltage waveform of the first pin, and then gradually decreases to 0, it is determined that the inductor is short-circuited.

[0036] Furthermore, the embodiment of the present disclosure also provides a chip output peripheral device connection detection circuit 200 for implementing the chip output peripheral device connection detection method in the above embodiment, such as Figure 3 As shown, it is a schematic block diagram of a detection circuit 200 connected to a peripheral device output by a chip according to an embodiment of the present disclosure, wherein the peripheral device includes a first capacitor C1, a second capacitor C2, and an inductor L, wherein the first capacitor C1 is coupled between a first pin A and a second pin B of the chip, the second capacitor C2 is coupled between an output terminal Vout and a ground terminal of the chip, and the inductor L is coupled between a second pin B and an output terminal Vout. The detection circuit 200 connected to the peripheral device output by the chip includes: a first discharge module 210, a second discharge module 220, a charging module 230, a waveform detection module 240, and a logic processing module 250.

[0037] Among them, the first discharge module 210 is configured to pull down the voltage of the second pin B to zero potential through the first transistor M1 inside the chip. The first transistor M1 can be any transistor coupled between the second pin B and the ground terminal inside the chip. The function of the first discharge module 210 is to discharge the second pin B end, reset the resonant circuit composed of the first capacitor C1, the inductor L, the second capacitor C2, and the second discharge module 220 to the initial state, and does not affect the subsequent detection results. Further, in the case where the chip is a switching voltage converter, the first transistor M1 can be a lower power tube.

[0038] The second discharge module 220 is configured to pull down the voltage of the output terminal Vout to zero potential through the second transistor M2 inside the chip. The second transistor M2 is a transistor coupled between the output terminal Vout and the ground terminal in the chip. The function of the second discharge module 220 is to pull down the voltage of the chip output terminal Vout to zero potential, ensuring that the output terminal Vout is at zero potential during the entire detection process. Further, in the case where the chip is a switching voltage converter, the second discharge module 220 can be a module in the chip for reducing Vout when Vout is too high, and the module can pull Vout down to zero voltage under certain operating conditions. The embodiment of the present disclosure can reuse this module to achieve the function of pulling Vout down to zero potential.

[0039] The charging module 230 is configured to charge the first capacitor C1 through the third transistor M3 inside the chip, so that the first capacitor C1, the inductor L, the second capacitor C2, and the second discharge module 220 form a resonant circuit. Among them, the third transistor M3 is a transistor inside the chip coupled between the power supply voltage VCC and the first pin A, and can charge the first capacitor C1 through the third transistor M3. In addition, in order to prevent the voltage of the first pin A from being charged to "VCC-VD" through the parasitic diode of the third transistor M3, where VD is the conduction voltage of the parasitic diode, a switch K is set in the charging module 230 to control the opening or closing of the charging. Further, for the switching voltage converter, the first capacitor C1 is a bootstrap capacitor, the inductor L is the output inductor L, and the second capacitor C2 is a load capacitor.

[0040] The waveform detection module 240 is configured to obtain the voltage waveform of the second pin B, detect the voltage waveform of the second pin B according to the preset detection rule, and output the waveform detection result signal QDET. The preset detection rule is that when the peak of the voltage waveform of the second pin B is between the first voltage V1 and the second voltage V2, the waveform detection result signal QDET is high level, and when the peak of the voltage waveform of the second pin B is not between the first voltage V1 and the second voltage V2, the waveform detection result signal QDET is low level, and the first voltage V1 is less than the second voltage V2. The detection theoretical basis of the waveform detection module 240 is that when the devices in the resonant circuit are connected normally, the voltage waveform of the resonant circuit will be a gradual decay process. The first voltage V1 and the second voltage V2 are set to determine whether there is a gradual decay process, and then to determine whether the peripheral device connections are all normal. In addition, the preset detection rule is also set to convert the voltage waveform (resonance waveform) of the second pin B into a square wave to facilitate the processing of subsequent steps. The waveform detection module 240 in the embodiment of the present disclosure can be implemented by a Q value detection circuit (resonance quality factor detection circuit). When all peripheral device connections are normal, the pulse width of the high-level signal in the waveform detection result signal QDET is related to the Q value. Therefore, the waveform detection in the waveform detection module 240 can be implemented by the Q value detection circuit.

[0041] The logic processing module 250 is configured to receive the waveform detection result signal QDET, perform logic processing on the waveform detection result signal QDET to obtain the safety detection result signal Vout_OK, and judge whether all peripheral devices at the chip output end are connected normally according to the safety detection result signal Vout_OK. The specific implementation of performing logic processing on the waveform detection result signal QDET to obtain the safety detection result signal Vout_OK is as follows: judging whether a high-level pulse signal within a preset range is detected within the detection window, and the preset range is determined according to the time length of the peak of the voltage waveform of the second pin B decaying from the second voltage V2 to the first voltage V1 when all peripheral devices are connected normally; if a high-level pulse signal within the preset range is detected, the safety detection result signal Vout_OK is high; if a high-level pulse signal within the preset range is not detected, the safety detection result signal Vout_OK is low. Assuming that the time length of the peak of the voltage waveform of the second pin B decaying from the second voltage V2 to the first voltage V1 is T, the preset range is an interval near T including T, for example, if T is 100μs, the preset range can be set to (80μs, 120μs), or (85μs, 115μs) and other intervals. Because when the parameters of all peripheral devices remain unchanged, the time length of the peak of the voltage waveform of the second pin B decaying from the second voltage V2 to the first voltage V1 is usually almost unchanged in theory, so it can be determined within the detection window whether a high-level pulse signal of a fixed duration, such as a high-level pulse of 100 microseconds, is detected, but there may be some discrepancies in actual applications, so it is set to whether a high-level pulse within a preset range can be detected.

[0042] According to the safety detection result signal Vout_OK, it is judged whether all peripheral devices output by the chip are connected normally, including: if the safety detection result signal Vout_OK is at a high level, it is determined that all peripheral devices output by the chip are connected normally; if the safety detection result signal Vout_OK is at a low level, it is determined that all peripheral devices output by the chip are not connected normally. It can be seen that the state of the safety detection result signal Vout_OK can be used to judge whether all peripheral devices output by the chip are connected normally.

[0043] From the above description, it can be seen that in the detection circuit 200 of the peripheral device connection of the chip output of the embodiment of the present disclosure, the first capacitor C1, the second capacitor C2, and the inductor L are combined into a resonant circuit, and the voltage waveform of the resonant circuit is detected and logically processed to obtain the safety detection result signal Vout_OK, and the signal is used to determine whether all peripheral devices (first capacitor C1, second capacitor C2, inductor L) are connected normally. Compared with the prior art, all peripheral devices can be monitored, and one signal can be used to determine whether all peripheral devices are connected normally, which is convenient and comprehensive, ensuring the effectiveness and comprehensiveness of functional safety detection. In addition, the first transistor M1, the second transistor M2, the third transistor M3, etc. in the embodiment of the present disclosure are all devices inside the chip itself, which is equivalent to fully reusing the devices inside the chip, reducing the occupied area.

[0044] Further, as shown in FIG4 , the first discharge module 210 includes: a first transistor M1, wherein a first electrode of the first transistor M1 is coupled to a second pin B, and a second electrode of the first transistor M1 is coupled to a ground terminal, and when the first transistor M1 is in an open state (turned on), the voltage of the second pin B is pulled down to zero potential.

[0045] Further, as shown in Figure 4, the second discharge module 220 includes: a second transistor M2, a resistor R, wherein the first electrode of the second transistor M2 is coupled to one end of the resistor R, the second electrode of the second transistor M2 is coupled to the ground terminal, and the second transistor M2 is used to control whether to discharge the voltage at the output terminal to zero potential; the other end of the resistor R is coupled to the output terminal Vout. When the second transistor M2 is in the open state (turned on), the output terminal voltage Vout is pulled down to zero potential. Among them, the resistor R has the function of current limiting, limiting the size of the pull-down current, and is used to protect the circuit.

[0046] Further, as shown in Figure 4, the charging module 230 includes: a third transistor M3, a switch K, wherein the first electrode of the third transistor M3 is coupled to the power supply voltage VCC, and the second electrode of the third transistor M3 is coupled to one end of the switch K; the other end of the switch K is coupled to the first pin A, and the switch K is used to control whether the power supply voltage VCC charges the first capacitor C1. When the switch K is closed, the power supply voltage VCC is controlled to charge the first pin A, that is, to charge the first capacitor C1; when the switch K is opened, the charging stops.

[0047] Combination Figure 4The working principle of the detection circuit 200 connected to the peripheral devices output by the chip in the embodiment of the present disclosure is explained as follows: after the chip is turned on, first, the first transistor M1 is turned on to pull the voltage of the second pin B down to zero potential; then the second transistor M2 is turned on to pull the output voltage Vout down to zero potential; then the switch K in the charging module 230 is turned on, and VCC will quickly charge the first capacitor C1 and quickly increase the voltage of the first pin A to VCC. At this time, the voltage of the first pin A, the first capacitor C1, the inductor L, the second capacitor C2 and the second discharge module 220 form an LC oscillation circuit. When all peripheral devices are connected normally, the voltage of the second pin B will oscillate and gradually decay to zero. If any peripheral device is not connected normally (open circuit or short circuit), the voltage of the second pin B will not oscillate and gradually decay to zero. For example, if the first capacitor C1 is abnormally connected and a circuit is broken, since the first capacitor C1 is disconnected, after the voltage of the first pin A is charged from 0V to VCC, the voltage of the second pin B is always 0V, so there is no oscillation attenuation; if the inductor L is abnormally connected and a circuit is broken, since the inductor L is disconnected, after the voltage of the first pin A is charged from 0V to VCC, the voltage of the second pin B follows the first pin A to change from 0V to VCC, and the voltage of the second pin B does not oscillate and attenuate; if the second capacitor C2 is abnormally connected and a circuit is broken, since the second capacitor C2 is disconnected, the energy of the resonant system composed of the first capacitor C1, the inductor L and the second discharge module 220 will quickly decay to 0 (the first capacitor C1 and the second capacitor C2 are both relatively large capacitors), and the voltage of the second pin B will increase with the increase of the voltage of the first pin A, and then quickly decay to 0V, instead of oscillating and gradually decaying to zero. After the waveform detection module 240 receives the voltage waveform of the second pin B, it performs waveform detection according to the preset detection rules. Only when the voltage of the second pin B oscillates and gradually decays to zero, the waveform detection result signal QDET can output a high-level pulse width signal with a pulse width of T, where T is the time length for the peak of the voltage waveform of the second pin B to decay from the second voltage V2 to the first voltage V1. In the case where the voltage of the second pin B is not oscillating and gradually decays to zero, a high-level pulse width signal with a pulse width of T cannot be output. For example, when the first capacitor C1 or the inductor L is abnormally connected and a short circuit occurs, the voltage of the second pin B does not oscillate and decay, and the waveform detection result signal QDET is always at a low level, and a high-level pulse width signal with a pulse width of T cannot be output; when the second capacitor C2 is abnormally connected and a short circuit occurs, the voltage of the second pin B increases with the increase of the voltage of the first pin A, and then quickly decays to 0V, so the waveform detection result signal QDET will output a high-level pulse width signal with a pulse width much smaller than T. Figure 5-8, which respectively show the waveforms of the voltage waveform of the first pin A, the voltage waveform of the second pin B, the waveform detection result signal QDET and the waveform diagram of the safety detection result signal Vout_OK corresponding to the four working conditions of all peripheral devices being connected normally, the first capacitor C1 being disconnected, the inductor L being disconnected, and the second capacitor C2 being disconnected, Figure 5-8 It can also be seen that only when all peripheral devices are connected normally, the voltage of the second pin B will oscillate and gradually decay to zero, and then the waveform detection result signal QDET can output a high-level pulse width signal with a pulse width of T. After the waveform detection result signal QDET is obtained, it is input into the logic processing module 250 for processing to obtain the safety detection result. Only when the waveform detection result signal QDET is a high-level pulse width signal with a pulse width of T, the safety detection result signal Vout_OK can output a high level, indicating that all peripheral devices output by the chip are connected normally. Figure 5-8 It can also be seen that the safety detection result signal Vout_OK can only output a high level when all peripheral devices are connected normally, otherwise it is a low level signal. From the above circuit description, it can be seen that in actual applications, as long as the safety detection result signal Vout_OK cannot output a high level signal, it means that the peripheral devices output by the chip are not connected normally. When the safety detection result signal Vout_OK outputs a high level signal, it means that the peripheral devices output by the chip are connected normally.

[0048] Usually in current applications, as long as it can be determined whether all peripheral devices output by the chip are connected normally, the application requirements can be met, that is, if all are connected normally, the functional safety test will be passed. If not all are connected normally, the functional safety test will not be passed. However, if you want to further determine which peripheral device is not connected normally, you can also determine it in the following way: determine the device with an open circuit among all peripheral devices based on the voltage waveform of the second pin B and the waveform of the waveform detection result signal QDET; and / or, determine the device with a short circuit among all peripheral devices based on the voltage waveform of the second pin B and the voltage waveform of the first pin A. Among them, the device that has a short circuit among all peripheral devices is determined based on the voltage waveform of the second pin B and the waveform of the waveform detection result signal QDET: if the voltage waveform of the second pin B and the waveform of the waveform detection result signal QDET are always at a low level, it is determined that the first capacitor C1 is connected abnormally and there is a short circuit; if the voltage waveform of the second pin B is at a high level, but the waveform of the waveform detection result signal QDET is always at a low level, it is determined that the inductor L is connected abnormally and there is a short circuit; if the voltage waveform of the second pin B and the waveform of the waveform detection result signal QDET are both at a high level, it is determined that the second capacitor C2 is connected abnormally and there is a short circuit. Figure 5-8In the waveform diagram, it can also be seen that the above determination method can be used to determine which peripheral device has a short circuit. In addition, in the judgment of whether the second capacitor C2 has a short circuit, in actual applications, there may also be a situation where C2 is short-circuited and the waveform detection result signal QDET is always at a low level. At this time, it is impossible to determine whether the second capacitor C2 is short-circuited or the inductor L is short-circuited by "if the voltage waveform of the second pin B and the waveform of the waveform detection result signal QDET are both high-level, it is determined that the second capacitor C2 is abnormally connected and there is a short circuit". At this time, it is necessary to judge according to "judging whether the voltage waveform of the second pin B is rapidly decaying to zero, if it is, it is determined that the second capacitor C2 is abnormally connected and there is a short circuit".

[0049] In addition, the short-circuited device among all peripheral devices is determined based on the voltage waveform of the second pin B and the voltage waveform of the first pin A. If the voltage waveform of the second pin B rises to a lower voltage value along with the voltage waveform of the first pin A and then gradually decreases to 0, it is determined that the inductor L is short-circuited.

[0050] In addition, the detection method and circuit for connecting the peripheral devices output by the chip in the embodiment of the present disclosure can be better applied in the switching voltage converter. The first discharge module 210, the second discharge module 220, and the charging module 230 can all be implemented by the devices inside the switching voltage converter chip, and can be fully reused. The switching voltage converter can specifically be BUCK, Boost, etc. When applied to the switching voltage converter, the first capacitor C1 can be a bootstrap capacitor CBST, the second capacitor C2 can be a load capacitor COUT, the inductor L can be an output inductor, the first pin A can be a bootstrap pin BST, and the second pin B can be a switch node SW. The detection method and circuit for connecting the peripheral devices output by the chip in the embodiment of the present disclosure can detect whether the bootstrap capacitor CBST, the load capacitor COUT, and the output inductor are all connected normally.

[0051] In summary, the detection method and circuit of the peripheral device connection of the chip output in the embodiment of the present disclosure forms a resonant circuit by combining the first capacitor, the second capacitor, and the inductor, and obtains a safety detection result signal by detecting and logically processing the voltage waveform of the resonant circuit, and uses the signal to determine whether all peripheral devices are connected normally, thereby ensuring the effectiveness and comprehensiveness of functional safety detection. In addition, the devices inside the chip are fully reused to reduce the occupied area.

[0052] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is placed after a group of terms, "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0053] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

[0054] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A method for detecting the connection of a peripheral device output by a chip, wherein the peripheral device comprises a first capacitor, a second capacitor, and an inductor, wherein the first capacitor is coupled between a first pin and a second pin of the chip, the second capacitor is coupled between an output terminal and a ground terminal of the chip, and the inductor is coupled between the second pin and the output terminal, characterized in that: The method comprises: Pulling down the voltage of the second pin to zero potential through the first transistor inside the chip; Pulling the voltage of the output terminal down to zero potential through the second transistor inside the chip; The first capacitor is charged by a third transistor inside the chip, so that the first capacitor, the inductor, the second capacitor, and the second transistor form a resonant circuit; Acquire the voltage waveform of the second pin, detect the voltage waveform according to a preset detection rule, and output a waveform detection result signal, wherein the preset detection rule is that when the peak of the voltage waveform of the second pin is between the first voltage and the second voltage, the waveform detection result signal is at a high level, and when the peak of the voltage waveform is not between the first voltage and the second voltage, the waveform detection result signal is at a low level, and the first voltage is less than the second voltage; The waveform detection result signal is logically processed to obtain a safety detection result signal, and it is determined whether all peripheral devices output by the chip are connected normally according to the safety detection result signal.

2. The method for detecting the connection of peripheral devices output by a chip according to claim 1, characterized in that: Performing logical processing on the waveform detection result signal to obtain a safety detection result signal includes: Determining whether a high-level pulse signal within a preset range is detected within the detection window, wherein the preset range is determined according to the time length for the peak of the voltage waveform of the second pin to decay from the second voltage to the first voltage when all peripheral devices are connected normally; If a high level pulse signal within the preset range is detected, the safety detection result signal is at a high level; If no high level pulse signal within the preset range is detected, the safety detection result signal is at a low level.

3. The method for detecting the connection of peripheral devices output by a chip according to claim 2, characterized in that: The step of judging whether all peripheral devices output by the chip are connected normally according to the safety detection result signal comprises: If the safety detection result signal is at a high level, it is determined that all peripheral devices output by the chip are connected normally; If the safety detection result signal is at a low level, it is determined that all peripheral devices output by the chip are not connected normally.

4. The method for detecting the connection of peripheral devices output by a chip according to claim 3, characterized in that: After determining that all peripheral devices output by the chip are not connected properly, the method further includes: Determine the device having a circuit breaker among all peripheral devices according to the voltage waveform of the second pin and the waveform of the waveform detection result signal; and / or, The short-circuited device among all peripheral devices is determined according to the voltage waveform of the second pin and the voltage waveform of the first pin.

5. A detection circuit for connecting peripheral devices outputted by a chip, wherein the peripheral devices include a first capacitor, a second capacitor, and an inductor, wherein the first capacitor is coupled between a first pin and a second pin of the chip, the second capacitor is coupled between an output terminal and a ground terminal of the chip, and the inductor is coupled between the second pin and the output terminal, characterized in that: The circuit includes: a first discharge module, a second discharge module, a charging module, a waveform detection module, and a logic processing module. Wherein, the first discharge module is configured to pull down the voltage of the second pin to zero potential through the first transistor inside the chip; The second discharge module is configured to pull down the voltage of the output terminal to zero potential through a second transistor inside the chip; The charging module is configured to charge the first capacitor through a third transistor inside the chip, so that the first capacitor, the inductor, the second capacitor, and the second discharge module form a resonant circuit; The waveform detection module is configured to obtain the voltage waveform of the second pin, detect the voltage waveform of the second pin according to a preset detection rule, and output a waveform detection result signal, wherein the preset detection rule is that when the peak of the voltage waveform of the second pin is between the first voltage and the second voltage, the waveform detection result signal is a high level, and when the peak of the voltage waveform of the second pin is not between the first voltage and the second voltage, the waveform detection result signal is a low level, and the first voltage is less than the second voltage; The logic processing module is configured to receive the waveform detection result signal, perform logic processing on the waveform detection result signal to obtain a safety detection result signal, and determine whether all peripheral devices output by the chip are connected normally according to the safety detection result signal.

6. The detection circuit for connecting peripheral devices outputted by a chip according to claim 5, characterized in that: The first discharge module includes: the first transistor, The first electrode of the first transistor is coupled to the second pin, and the second electrode of the first transistor is coupled to the ground terminal. When the first transistor is in an on state, the voltage of the second pin is pulled down to zero potential.

7. The detection circuit for connecting peripheral devices outputted by a chip according to claim 5, characterized in that: The second discharge module includes: the second transistor, a resistor, Wherein, a first electrode of the second transistor is coupled to one end of the resistor, a second electrode of the second transistor is coupled to a ground end, and the second transistor is used to control whether to discharge the voltage of the output end to zero potential; The other end of the resistor is coupled to the output end.

8. The detection circuit for connecting peripheral devices outputted by a chip according to claim 5, characterized in that: The charging module includes: the third transistor, a switch, Wherein, a first electrode of the third transistor is coupled to a power supply voltage, and a second electrode of the third transistor is coupled to one end of the switch; The other end of the switch is coupled to the first pin, and the switch is used to control whether the power supply voltage charges the first capacitor.

9. The detection circuit for connecting peripheral devices to chip output according to claim 5, characterized in that: The step of performing logical processing on the waveform detection result signal to obtain a safety detection result signal, and judging whether all peripheral devices output by the chip are connected normally according to the safety detection result signal comprises: Determining whether a high-level pulse signal within a preset range is detected within the detection window, wherein the preset range is determined according to the time length for the peak of the voltage waveform of the second pin to decay from the second voltage to the first voltage when all peripheral devices are connected normally; If a high level pulse signal within the preset range is detected, the safety detection result signal is at a high level, and it is determined that all peripheral devices output by the chip are connected normally; If no high-level pulse signal within the preset range is detected, the safety detection result signal is at a low level, and it is determined that all peripheral devices output by the chip are not connected normally.

10. The detection circuit for connecting peripheral devices outputted by a chip according to claim 6, characterized in that: The chip is a switching voltage converter, the first transistor is a lower power tube of the switching voltage converter, the first capacitor is a bootstrap capacitor, the second capacitor is a load capacitor, and the inductor is an output inductor.

Images