Peripheral management equipment and system

Abstract

The invention discloses peripheral management equipment and a peripheral management system in the technical field of computers. According to the peripheral management equipment provided by the invention, the processor is used as a master controller, and the control module, the data analysis module, the transceiving module, the clock module and the at least two universal bus interfaces included in the peripheral controller are utilized to perform data transmission management on the at least two universal bus equipment connected with the at least two universal bus interfaces; ordered management of the multiple pieces of universal bus equipment is realized; moreover, if necessary, the universal bus equipment which does not work temporarily can be hung up to save energy, so that the power consumption of the equipment can be reduced. When the method is applied to the server, the influence of the USB peripheral on the power consumption of the server can be reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a peripheral management device and system. Background Art

[0002] Currently, servers can obtain data from USB peripherals and transmit local data to USB peripherals. Frequent data transmission between the two will increase server power consumption and affect server stability. In addition, data transmission between servers and USB peripherals is not uninterrupted. When no data is transmitted, USB peripherals will also increase server power consumption.

[0003] Therefore, how to reduce the impact of USB peripherals on device power consumption is a problem that those skilled in the art need to solve. Summary of the invention

[0004] In view of this, the purpose of this application is to provide a peripheral management device and system to reduce the impact of USB peripherals on device power consumption. The specific solution is as follows:

[0005] In a first aspect, the present application provides a peripheral management device, comprising: a processor and a peripheral controller; the processor and the peripheral controller are connected via a target bus;

[0006] The peripheral controller includes: a control module, a data analysis module, a transceiver module, a clock module and at least two universal bus interfaces;

[0007] The processor is used to control at least two universal bus devices connected to the at least two universal bus interfaces through the target bus;

[0008] The control module is used to assign a corresponding target address to the current universal bus device when detecting a universal bus device connected to any universal bus interface, and generate a corresponding endpoint number according to the target address; and distinguish different universal bus devices by the endpoint numbers corresponding to different universal bus devices;

[0009] The data analysis module is used to confirm whether the transmission data packet of any universal bus device connected to the universal bus interface is valid according to the data valid status bit;

[0010] The transceiver module is used to control the data transceiver operation according to the data transmission mode of different universal bus devices, the transceiver state machine and the data valid signal output by the data analysis module;

[0011] The clock module is used to determine that the universal bus device is in a suspended state if no frame start packet transmitted by any universal bus device connected to the universal bus interface is detected within a preset time period and the bus signal of the corresponding universal bus device is confirmed to be invalid.

[0012] Optionally, the peripheral controller further includes: a state control module;

[0013] Correspondingly, the state control module is used to control the device state; the device state includes: power-on state, default state, configured address state, configured information state and suspended state;

[0014] Correspondingly, the state control module is used to control the corresponding universal bus device to enter the power-on state when detecting that the device reset signal of any universal bus device connected to the universal bus interface is valid;

[0015] If a valid bus signal is detected in the power-on state, the corresponding universal bus device is controlled to enter the default state;

[0016] If an invalid bus signal is detected and a suspend confirmation message sent by the clock module is received in the power-on state, the corresponding universal bus device is controlled to enter the suspend state;

[0017] In the default state, sending an allocatable message to the control module to enable the control module to perform an address allocation operation; if the control module completes the address allocation operation, controlling the corresponding universal bus device to enter the configured address state; if the control module does not complete the address allocation operation, detecting the validity of the bus signal and the suspend confirmation message to confirm whether to control the corresponding universal bus device to enter the suspend state;

[0018] In the configured address state, if an information configured message of the corresponding universal bus device is detected, the corresponding universal bus device is controlled to enter the configured information state;

[0019] In the suspended state, if a wake-up signal of a corresponding universal bus device is detected, the corresponding universal bus device is controlled to enter the default state.

[0020] Optionally, the peripheral controller further includes: a data selection module;

[0021] Correspondingly, the data selection module is used to determine the type of transmission data packet of any universal bus device connected to the universal bus interface; the types include: token packet, frame start packet, data packet and handshake packet.

[0022] Optionally, the peripheral controller further includes: a verification module;

[0023] Correspondingly, the verification module is used to verify the transmission data packet of any universal bus device connected to the universal bus interface.

[0024] Optionally, the peripheral controller further includes: a register module;

[0025] Correspondingly, the register module is used to respectively record the device information of at least two universal bus devices connected to the at least two universal bus interfaces.

[0026] Optionally, the peripheral controller further includes: a handshake module;

[0027] Correspondingly, the handshake module is used to determine the data transmission mode of any universal bus device connected to the universal bus interface; the data transmission mode includes: full-speed transmission mode and low-speed transmission mode.

[0028] Optionally, the peripheral controller further includes: a security module;

[0029] Accordingly, the security module comprises:

[0030] The encryption accelerator is used to encrypt the transmission data packets of any universal bus device connected to the universal bus interface and accelerate the transmission.

[0031] In a second aspect, the present application provides a peripheral management system, comprising: at least one peripheral management device as described in any one of the above items; different peripheral management devices are connected to the same baseboard management controller.

[0032] Optionally, the baseboard management controller is built into the server.

[0033] Optionally, the server is connected to at least one acceleration card.

[0034] It can be seen from the above scheme that the present application provides a peripheral management device, including: a processor and a peripheral controller; the processor and the peripheral controller are connected through a target bus; the peripheral controller includes: a control module, a data analysis module, a transceiver module, a clock module and at least two universal bus interfaces; the processor is used to control at least two universal bus devices connected to the at least two universal bus interfaces through the target bus; the control module is used to assign a corresponding target address to the current universal bus device when detecting a universal bus device connected to any universal bus interface, and generate a corresponding endpoint number according to the target address; different universal bus devices are distinguished by the endpoint numbers corresponding to different universal bus devices; the data analysis module is used to confirm whether the transmission data packet of the universal bus device connected to any universal bus interface is valid according to the data valid status bit; the transceiver module is used to control the data transceiver operation according to the data transmission mode of different universal bus devices, the transceiver state machine and the data valid signal output by the data analysis module; the clock module is used to determine that the universal bus device is in a suspended state if a frame start packet transmitted by a universal bus device connected to any universal bus interface is not detected within a preset time length, and the bus signal of the corresponding universal bus device is confirmed to be invalid.

[0035] It can be seen that the peripheral management device provided by the present application uses the processor as the main control, and uses the control module, data analysis module, transceiver module, clock module and at least two universal bus interfaces included in the peripheral controller to manage data transmission of at least two universal bus devices connected to at least two universal bus interfaces, thereby realizing orderly management of multiple universal bus devices; and, if necessary, the universal bus device that is temporarily not working can be suspended to save energy and reduce device power consumption. When applied to a server, it can reduce the impact of USB peripherals on server power consumption.

[0036] Correspondingly, a peripheral management device, equipment and medium provided by the present application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0038] Figure 1 A schematic diagram of a peripheral management device disclosed in this application;

[0039] Figure 2 A USB communication schematic diagram disclosed in this application;

[0040] Figure 3 A schematic diagram of another peripheral management device disclosed in this application;

[0041] Figure 4 A schematic diagram of a peripheral controller disclosed in this application;

[0042] Figure 5 A schematic diagram of an electronic device disclosed in this application;

[0043] Figure 6 A server structure diagram provided for this application;

[0044] Figure 7 A terminal structure diagram provided for this application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other examples obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] Currently, the server can obtain data from USB peripherals and transmit local data to USB peripherals. Frequent data transmission between the two will increase the power consumption of the server and affect the stability of the server. In addition, the data transmission between the server and the USB peripheral is not uninterrupted. When no data is transmitted, the USB peripheral will also increase the power consumption of the server. To this end, the present application provides a peripheral management solution that can reduce the impact of USB peripherals on device power consumption.

[0047] See also Figure 1 As shown, an embodiment of the present application discloses a peripheral management device, including: a processor and a peripheral controller; the processor and the peripheral controller are connected through a target bus (such as APB); the peripheral controller includes: a control module, a data analysis module, a transceiver module, a clock module and at least two universal bus interfaces.

[0048] The processor is used to control at least two universal bus devices connected to at least two universal bus interfaces through a target bus.

[0049] The control module is used to assign a corresponding target address to the current universal bus device when detecting a universal bus device connected to any universal bus interface, and generate a corresponding endpoint number according to the target address; and distinguish different universal bus devices by the endpoint numbers corresponding to different universal bus devices.

[0050] The data analysis module is used to confirm whether the transmission data packet of any universal bus device connected to the universal bus interface is valid according to the data valid status bit.

[0051] The transceiver module is used to control the data transmission and reception operations according to the data transmission mode of different universal bus devices, the transceiver state machine and the data valid signal output by the data analysis module.

[0052] The clock module is used to determine that the universal bus device is in a suspended state if no frame start packet transmitted by any universal bus device connected to the universal bus interface is detected within a preset time period and the bus signal of the corresponding universal bus device is confirmed to be invalid.

[0053] The peripheral management device provided in this embodiment uses a processor as the main control, and uses the control module, data analysis module, transceiver module, clock module and at least two universal bus interfaces included in the peripheral controller to manage data transmission of at least two universal bus devices connected to at least two universal bus interfaces, thereby realizing orderly management of multiple universal bus devices; and, if necessary, the universal bus device that is temporarily not working can be suspended to save energy and reduce device power consumption. When applied to a server, it can reduce the impact of USB peripherals on server power consumption.

[0054] In one example, the peripheral controller further includes: a state control module; accordingly, the state control module is used to control the device state; the device state includes: a power-on state, a default state, a configured address state, a configured information state, and a suspended state; accordingly, the state control module is used to control the corresponding universal bus device to enter a power-on state when it is detected that the device reset signal of the universal bus device connected to any universal bus interface is valid; if a valid bus signal is detected in the power-on state, the corresponding universal bus device is controlled to enter a default state; if an invalid bus signal is detected in the power-on state and a suspension confirmation message sent by the clock module is received, the corresponding universal bus device is controlled Enter the suspended state; in the default state, send an assignable message to the control module to enable the control module to perform the address assignment operation; if the control module completes the address assignment operation, control the corresponding universal bus device to enter the configured address state; if the control module does not complete the address assignment operation, detect the validity of the bus signal and the suspend confirmation message to confirm whether to control the corresponding universal bus device to enter the suspended state; in the configured address state, if the information of the corresponding universal bus device is detected to be configured, control the corresponding universal bus device to enter the configured information state; in the suspended state, if the wake-up signal of the corresponding universal bus device is detected, control the corresponding universal bus device to enter the default state.

[0055] In one example, the peripheral controller also includes: a data selection module; accordingly, the data selection module is used to determine the type of transmission data packet of any universal bus device connected to the universal bus interface; the types include: token packet, frame start packet, data packet and handshake packet.

[0056] In one example, the peripheral controller further includes: a verification module; accordingly, the verification module is used to verify the transmission data packet of any universal bus device connected to the universal bus interface.

[0057] In one example, the peripheral controller further includes: a register module; accordingly, the register module is used to respectively record device information of at least two universal bus devices connected to at least two universal bus interfaces.

[0058] In one example, the peripheral controller further includes: a handshake module; accordingly, the handshake module is used to determine the data transmission mode of any universal bus device connected to the universal bus interface; the data transmission mode includes: a full-speed transmission mode and a low-speed transmission mode.

[0059] In one example, the peripheral controller further includes: a security module; correspondingly, the security module includes: an encryption accelerator for encrypting transmission data packets of any universal bus device connected to the universal bus interface and accelerating transmission.

[0060] It should be noted that when a USB (Universal Serial Bus) device is inserted into the USB interface, the host server detects the voltage on the D+ / D- line and confirms that the device is connected. If it is a USB3.0 device, that is, when the device is high-speed, the pin D+ will be pulled up, and the host will detect that it is a high-speed device by judging the high and low levels of the pin. After the device is connected to the USB interface and waits for the host to generate a reset signal, all registers on the device and their status values ​​are restored to the default values, and the USB device is initialized. After the initialization is completed, the host sends a token packet (Token) to start the request transmission process. If there is data transmission in the request statement, the data process is confirmed, and finally the communication is ended through the status process. For details, please refer to Figure 2 .

[0061] During the communication process, a USB transaction is divided into three packets, namely token packet, data packet and handshake packet. The token packet specifies the type of transmission of the transaction, including the address and endpoint of the target device; the data packet is the data in the transmission process, and the handshake packet provides feedback on the results of the transmission. A complete USB transmission packet has the following components: start packet, synchronization domain, transmission data packet, and end packet; the transmission data packet generally includes: PID, address, frame number, data and CRC check.

[0062] In one example, a RISC-V processor and APB (Advanced Peripheral Bus) are used to connect to a peripheral controller. The peripheral controller has the following modules: USB transceiver module, USB register module, CRC check module, USB clock module, and USB data processing module. For details, see Figure 3 .

[0063] Please refer to Figure 3 The USB transceiver module is responsible for transmitting with the USB device and communicating the generated data with the host. After the data is transmitted to the USB peripheral system through the transceiver module, the USB data processing module and the CRC check module perform data processing and CRC check on the transmitted USB data. Depending on the type of USB data, this module is responsible for functions such as frame header identification, PID generation and verification, CRC generation and verification, and handshake packet processing. Signals are generated based on events corresponding to the USB and endpoint-related events to generate interrupts, mainly including signals such as USB reset, frame header packet transmission, and data transmission errors.

[0064] During the transmission process, the data transmitted by the USB peripheral will be stored in the register submodule of the USB peripheral system. For example, each USB endpoint type and status will be stored in the corresponding endpoint register. The status information transmitted by the USB peripheral will be stored in the control register after parsing. When the current state is the normal transmission state, the USB peripheral system works normally; when the system recognizes that the USB peripheral is in a dormant state, the corresponding USB peripheral will be suspended. If no USB peripheral is working, the peripheral controller and its connected USB peripherals will be suspended and enter low power mode. When an interrupt occurs, the interrupt source and interrupt status in the USB device are stored in the interrupt register. In addition, the interrupt register can clear the unprocessed interrupt status as needed to skip the processing of the interrupt.

[0065] The clock module generates a clock pulse synchronized with the frame start message. After the clock pulse is generated, if there is no data transmission in the USB device within 3ms, the system will be globally suspended and enter low power consumption mode.

[0066] In USB transmission, first identify the valid token packet and perform the relevant data transmission. During the data transmission process, the data exchange between the endpoint and the buffer is realized by the 16-bit register inside the USB. After the transmission is completed, the handshake packet is sent or received to communicate with the host according to the transmission direction, and the interrupt related to the endpoint is triggered. The USB module can be put into suspend mode, that is, low power mode, by writing the control register to reduce power consumption. In low power mode, the USB module clock is slowed down or stopped, and the clock system can be immediately restored or the clock can be started / stopped by detecting data transmission or connecting the interrupt source to the wake-up pin.

[0067] For more details, see Figure 4 More modules can be set in the peripheral controller, including: USB data selection module, USB clock generation module, USB status module, USB data analysis module, USB receiving and sending module, CRC check module, USB control module, USB register module and USB handshake module. Figure 4 The four channels shown can transmit clock signals, reset signals, data signals and control signals respectively.

[0068] Please refer to Figure 4 , according to the different USB peripherals inserted into the server, the USB data selection module determines the type of data packet for the corresponding USB transmission. When the transmission enable is detected to be high, the USB transmission starts. First, the type of the transmitted packet is determined, which is divided into token packets, SOF packets, data packets and handshake packets. Each packet has a different PID. When the USB recognizes different PIDs, it can determine the type of packet and the transmission method. After the entire USB transmission is completed, the handshake signal is returned to the server, and then the CRC check bit is transmitted to indicate that the transmission is complete.

[0069] The USB clock generation module detects the sampling point and transmission point of the USB module, as well as acts as a frame timer and calculates the SOF packet loss count. When the USB samples the SOF packet, it samples the current count value as the standard count value of 1ms. If the SE0 state is maintained for 120 clock cycles, it is treated as a reset signal and the USB enters the reset state; when three SOF packets are lost, that is, the USB peripherals in the server are not recognized for a period of time, the system will switch to the J state, the USB peripherals will be suspended, and enter the suspended state. At this time, the host must send a wake-up signal before the USB device can be activated from the suspended state.

[0070] The USB status module defines all states in the USB. This module is implemented by a state machine, and the defined states include device power-on state, device default state, configured address state, configured state, and suspended state. When the reset signal is valid, the device enters the power-on state. In the power-on state, the device detects the bus reset signal. If the reset signal is valid, it enters the device default state. If it is invalid, it enters the suspended state. In the device default state, the device will respond to the requirements of the device and configuration descriptors. If a unique address is assigned at this time, it enters the configured address state. If not assigned, it enters the suspended state. In the configured address state, the USB device will be configured. If configured, it will enter the configured state. If the suspend signal is valid, it will enter the suspended state. If reset at this time, it will enter the device power-on state. In the suspended state, the device will enter the configured state or the configured address state and the device default state according to different signals.

[0071] The USB data analysis module transmits the packet type selected by the USB data selection module. The hardware circuit of this module is completed by the state machine. When the USB has received the PID data, the USB starts to transmit data. When the received status bit is 0, it detects whether the data analysis module is valid. If it is valid, it detects the state of the sending signal or receiving signal. When the status bit is valid, data transmission starts. According to different PIDs, the USB will send or receive different packets.

[0072] The USB receiving and transmitting module is responsible for the sending and receiving of the USB. In the implementation of the transmitting module, 8 states will be defined, namely IDLE, SOP, DATA, EOP1, E0P2, WAIT, WAIT1 and WAIT2. When the USB is in the reset state or the transmit enable is low, the USB state is the IDLE state. At this time, the transmit success bit is low and the USB transmission is invalid. If the USB is not in the reset state and the transmit enable is valid, the USB starts to send. First, the USB will switch to the SOP state and start transmitting data. The USB will switch to the DATA state and the EOP state respectively, and finally enter the waiting state, indicating that the USB transmission is completed. The implementation of the receiving module is similar to that of the transmitting module.

[0073] The CRC check module is used for CRC check when sending and receiving USB peripherals. CRC check is a cyclic redundancy check (Cyclic Redundancy Check). Based on a set of data, a set of check codes will be calculated. The check code is used to check whether there is an error or change during the data transmission process. In the CRC check, the data to be checked is the dividend, and a suitable divisor is selected for modulo 2 division. The remainder obtained is the CRC check value.

[0074] The USB control module controls which USB endpoint is used for transmission. After the endpoint configuration is completed, different USB peripheral devices are identified. After the USB peripheral system is parsed, different PIDs will be generated. According to the different PIDs, the USB will transmit different data packets to achieve communication with the host. Among them, when each USB device is connected to the host, it will be assigned a unique address, which will be parsed to obtain a certain identifier, which is the endpoint number. After the USB peripheral system identifies these endpoint numbers, it will confirm which device this endpoint comes from, and initialize the configuration of these devices, confirming different data packet transmission methods according to different devices. In addition, if the peripheral on the server does not respond for a period of time, the control module will control the USB peripheral to enter the suspend mode.

[0075] The USB register module stores the data, control bits and status of the entire USB module. The USB handshake module defines USB full-speed and low-speed transmission. Depending on the transmission mode, the corresponding clock is also different. After determining the transmission mode, the USB peripheral system performs sending and receiving operations.

[0076] This embodiment uses a RISC-V architecture processor and an APB bus to mount USB peripherals. When USB transmission is not needed, the USB peripheral module can be suspended and enter a low-power mode, which can effectively overcome the shortcomings of high USB power consumption and complex circuits under the traditional ARM architecture, and is applied to USB data transmission in the server, which can reduce server power consumption.

[0077] A peripheral management system provided in an embodiment of the present application is introduced below. The peripheral management system described below can be cross-referenced with other embodiments described in this document.

[0078] An embodiment of the present application discloses a peripheral management system, comprising: at least one peripheral management device as described in any of the above embodiments; different peripheral management devices are connected to the same baseboard management controller.

[0079] In one example, the baseboard management controller is built into the server.

[0080] In one example, at least one accelerator card is connected to the server.

[0081] In this example, the peripheral management device includes: a processor and a peripheral controller; the processor and the peripheral controller are connected through a target bus; the peripheral controller includes: a control module, a data analysis module, a transceiver module, a clock module and at least two universal bus interfaces.

[0082] The processor is used to control at least two universal bus devices connected to at least two universal bus interfaces through a target bus.

[0083] The control module is used to assign a corresponding target address to the current universal bus device when detecting a universal bus device connected to any universal bus interface, and generate a corresponding endpoint number according to the target address; and distinguish different universal bus devices by the endpoint numbers corresponding to different universal bus devices.

[0084] The data analysis module is used to confirm whether the transmission data packet of any universal bus device connected to the universal bus interface is valid according to the data valid status bit.

[0085] The transceiver module is used to control the data transmission and reception operations according to the data transmission mode of different universal bus devices, the transceiver state machine and the data valid signal output by the data analysis module.

[0086] The clock module is used to determine that the universal bus device is in a suspended state if no frame start packet transmitted by any universal bus device connected to the universal bus interface is detected within a preset time period and the bus signal of the corresponding universal bus device is confirmed to be invalid.

[0087] In one example, the peripheral controller further includes: a state control module; accordingly, the state control module is used to control the device state; the device state includes: a power-on state, a default state, a configured address state, a configured information state, and a suspended state; accordingly, the state control module is used to control the corresponding universal bus device to enter a power-on state when it is detected that the device reset signal of the universal bus device connected to any universal bus interface is valid; if a valid bus signal is detected in the power-on state, the corresponding universal bus device is controlled to enter a default state; if an invalid bus signal is detected in the power-on state and a suspension confirmation message sent by the clock module is received, the corresponding universal bus device is controlled Enter the suspended state; in the default state, send an assignable message to the control module to enable the control module to perform the address assignment operation; if the control module completes the address assignment operation, control the corresponding universal bus device to enter the configured address state; if the control module does not complete the address assignment operation, detect the validity of the bus signal and the suspend confirmation message to confirm whether to control the corresponding universal bus device to enter the suspended state; in the configured address state, if the information of the corresponding universal bus device is detected to be configured, control the corresponding universal bus device to enter the configured information state; in the suspended state, if the wake-up signal of the corresponding universal bus device is detected, control the corresponding universal bus device to enter the default state.

[0088] In one example, the peripheral controller also includes: a data selection module; accordingly, the data selection module is used to determine the type of transmission data packet of any universal bus device connected to the universal bus interface; the types include: token packet, frame start packet, data packet and handshake packet.

[0089] In one example, the peripheral controller further includes: a verification module; accordingly, the verification module is used to verify the transmission data packet of any universal bus device connected to the universal bus interface.

[0090] In one example, the peripheral controller further includes: a register module; accordingly, the register module is used to respectively record device information of at least two universal bus devices connected to at least two universal bus interfaces.

[0091] In one example, the peripheral controller further includes: a handshake module; accordingly, the handshake module is used to determine the data transmission mode of any universal bus device connected to the universal bus interface; the data transmission mode includes: a full-speed transmission mode and a low-speed transmission mode.

[0092] In one example, the peripheral controller further includes: a security module; correspondingly, the security module includes: an encryption accelerator for encrypting transmission data packets of any universal bus device connected to the universal bus interface and accelerating transmission.

[0093] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0094] It can be seen that this embodiment provides a peripheral management system that can suspend a temporarily inactive universal bus device to save energy and reduce device power consumption. When applied to a server, it can reduce the impact of USB peripherals on server power consumption.

[0095] The following is an introduction to an electronic device provided in an embodiment of the present application. The electronic device described below can refer to other embodiments described herein. The electronic device described in this embodiment can include any functional module described in the previous embodiments, such as a processor, a control module, a data analysis module, a transceiver module, a clock module, etc.

[0096] See also Figure 5 As shown, the embodiment of the present application discloses an electronic device, including:

[0097] Memory 501, used for storing computer programs;

[0098] The processor 502 is used to execute the computer program to implement the method disclosed in any of the above embodiments.

[0099] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: controlling at least two universal bus devices connected to at least two universal bus interfaces through the target bus.

[0100] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: when detecting a universal bus device connected to any universal bus interface, assigning a corresponding target address to the current universal bus device, and generating a corresponding endpoint number according to the target address; different universal bus devices are distinguished by the endpoint numbers corresponding to different universal bus devices.

[0101] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: confirming whether a transmission data packet of any universal bus device connected to the universal bus interface is valid according to the data valid status bit.

[0102] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: controlling the data receiving and sending operations according to the data transmission mode of different universal bus devices, the transceiver state machine and the data valid signal output by the data analysis module.

[0103] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: if no frame start packet transmitted by any universal bus device connected to the universal bus interface is detected within a preset time length, and it is confirmed that the bus signal of the corresponding universal bus device is invalid, then the universal bus device is determined to be in a suspended state.

[0104] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: controlling the device state; the device state includes: power-on state, default state, configured address state, configured information state and suspended state; accordingly, the state control module is used to control the corresponding universal bus device to enter the power-on state when it detects that the device reset signal of the universal bus device connected to any universal bus interface is valid; if a valid bus signal is detected in the power-on state, the corresponding universal bus device is controlled to enter the default state; if an invalid bus signal is detected in the power-on state and a suspension confirmation message sent by the clock module is received, the corresponding universal bus is controlled to enter the default state; The control module controls the corresponding universal bus device to enter the suspended state; in the default state, sends an assignable message to the control module so that the control module performs the address assignment operation; if the control module completes the address assignment operation, the corresponding universal bus device is controlled to enter the configured address state; if the control module does not complete the address assignment operation, the validity of the bus signal and the suspend confirmation message are detected to confirm whether to control the corresponding universal bus device to enter the suspended state; in the configured address state, if the information configured message of the corresponding universal bus device is detected, the corresponding universal bus device is controlled to enter the configured information state; in the suspended state, if the wake-up signal of the corresponding universal bus device is detected, the corresponding universal bus device is controlled to enter the default state.

[0105] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: determining the type of transmission data packet of any universal bus device connected to the universal bus interface; the types include: token packet, frame start packet, data packet and handshake packet.

[0106] In one example, the peripheral controller further includes: a verification module; accordingly, the verification module is used to verify the transmission data packet of any universal bus device connected to the universal bus interface.

[0107] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: device information of at least two universal bus devices connected to at least two universal bus interfaces is respectively recorded.

[0108] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: determining the data transmission mode of the universal bus device connected to any universal bus interface; the data transmission mode includes: full-speed transmission mode and low-speed transmission mode.

[0109] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: encrypting transmission data packets of any universal bus device connected to the universal bus interface and accelerating transmission.

[0110] Furthermore, the present application also provides an electronic device. The electronic device can be Figure 6 The server shown can also be Figure 7 Terminal shown. Figure 6 and Figure 7 All of them are structural diagrams of electronic devices according to an exemplary embodiment, and the contents in the diagrams cannot be regarded as any limitation on the scope of use of the present application.

[0111] Figure 6 A schematic diagram of the structure of a server provided in an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, which is loaded and executed by the processor to implement the relevant steps in the peripheral management disclosed in any of the aforementioned embodiments.

[0112] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0113] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0114] The operating system is used to manage and control the hardware devices and computer programs on the server to realize the operation and processing of the data in the memory by the processor, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the peripheral management method disclosed in any of the above embodiments, the computer program can further include computer programs that can be used to complete other specific tasks. In addition to data such as application update information, the data can also include data such as application developer information.

[0115] Figure 7 A schematic diagram of the structure of a terminal provided in an embodiment of the present application, the terminal may specifically include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer, etc.

[0116] Generally, the terminal in this embodiment includes: a processor and a memory.

[0117] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0118] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the peripheral management method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of the application.

[0119] In some embodiments, the terminal may also include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0120] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation on the terminal, and may include more or fewer components than those shown in the figure.

[0121] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be cross-referenced with other embodiments described herein.

[0122] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the peripheral management method disclosed in the above-mentioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier for resource storage, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system, a computer program and data, etc., and the storage method can be temporary storage or permanent storage.

[0123] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be cross-referenced with other embodiments described in this document.

[0124] A computer program product includes a computer program / instruction, which implements the steps of the aforementioned disclosed peripheral management method when executed by a processor.

[0125] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0126] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0127] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A peripheral management device, characterized in that: include: Processor and peripheral controllers; The processor and the peripheral controller are connected via a target bus; The peripheral controller includes: a control module, a data analysis module, a transceiver module, a clock module and at least two universal bus interfaces; The processor is used to control at least two universal bus devices connected to the at least two universal bus interfaces through the target bus; The control module is used to assign a corresponding target address to the current universal bus device when detecting a universal bus device connected to any universal bus interface, and generate a corresponding endpoint number according to the target address; and distinguish different universal bus devices by the endpoint numbers corresponding to different universal bus devices; The data analysis module is used to confirm whether the transmission data packet of any universal bus device connected to the universal bus interface is valid according to the data valid status bit; The transceiver module is used to control the data transceiver operation according to the data transmission mode of different universal bus devices, the transceiver state machine and the data valid signal output by the data analysis module; The clock module is used to determine that the universal bus device is in a suspended state if no frame start packet transmitted by any universal bus device connected to the universal bus interface is detected within a preset time period and the bus signal of the corresponding universal bus device is confirmed to be invalid.

2. The peripheral management device according to claim 1, characterized in that: The peripheral controller also includes: a state control module; Correspondingly, the state control module is used to control the device state; the device state includes: power-on state, default state, configured address state, configured information state and suspended state; Correspondingly, the state control module is used to control the corresponding universal bus device to enter the power-on state when detecting that the device reset signal of any universal bus device connected to the universal bus interface is valid; If a valid bus signal is detected in the power-on state, the corresponding universal bus device is controlled to enter the default state; If an invalid bus signal is detected and a suspend confirmation message sent by the clock module is received in the power-on state, the corresponding universal bus device is controlled to enter the suspend state; In the default state, sending an allocatable message to the control module to enable the control module to perform an address allocation operation; if the control module completes the address allocation operation, controlling the corresponding universal bus device to enter the configured address state; if the control module does not complete the address allocation operation, detecting the validity of the bus signal and the suspend confirmation message to confirm whether to control the corresponding universal bus device to enter the suspend state; In the configured address state, if an information configured message of the corresponding universal bus device is detected, the corresponding universal bus device is controlled to enter the configured information state; In the suspended state, if a wake-up signal of a corresponding universal bus device is detected, the corresponding universal bus device is controlled to enter the default state.

3. The peripheral management device according to claim 1, characterized in that: The peripheral controller also includes: a data selection module; Correspondingly, the data selection module is used to determine the type of transmission data packet of any universal bus device connected to the universal bus interface; the types include: token packet, frame start packet, data packet and handshake packet.

4. The peripheral management device according to claim 1, characterized in that: The peripheral controller further includes: a verification module; Correspondingly, the verification module is used to verify the transmission data packet of any universal bus device connected to the universal bus interface.

5. The peripheral management device according to claim 1, characterized in that: The peripheral controller also includes: a register module; Correspondingly, the register module is used to respectively record the device information of at least two universal bus devices connected to the at least two universal bus interfaces.

6. The peripheral management device according to claim 1, characterized in that: The peripheral controller also includes: a handshake module; Correspondingly, the handshake module is used to determine the data transmission mode of any universal bus device connected to the universal bus interface; the data transmission mode includes: full-speed transmission mode and low-speed transmission mode.

7. The peripheral management device according to any one of claims 1 to 6, characterized in that: The peripheral controller further includes: a security module; Accordingly, the security module comprises: The encryption accelerator is used to encrypt the transmission data packets of any universal bus device connected to the universal bus interface and accelerate the transmission.

8. A peripheral management system, characterized in that: include: At least one peripheral management device according to any one of claims 1 to 7; Different peripheral management devices are connected to the same baseboard management controller.

9. The peripheral management system according to claim 8, characterized in that: The baseboard management controller is built in the server.

10. The peripheral management system according to claim 9, characterized in that: The server is connected to at least one acceleration card.

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