Multiplying, shifting and adding combined operation device and operation method

Abstract

The invention relates to the field of operation in digital circuits, and discloses a multiplication, shift and addition combined operation device and method, the operation device comprises a multiplication operation part, a shift operation part and an addition operation part, the multiplication operation part comprises four Booth coding units, five Wallace compression units and two 32-bit carry lookahead addition units, a 64-bit carry lookahead addition unit and a multiplication output selector; the shift operation part comprises a shift input data selector, a 64-bit shift unit and a 32-bit shift unit, and the addition operation part comprises an addition input selector and two 32-bit carry lookahead addition units. The operation device disclosed by the invention not only can realize a multiplication, shift and addition combined operation method, but also can realize independent multiplication, shift and addition operation, the used logic resources are few, and the required time is short.

Description

Technical Field

[0001] The present invention relates to the field of operations in digital circuits, and in particular to a multiplication, shift and addition combined operation device and an operation method. Background Art

[0002] Basic arithmetic units are the basis for building various complex calculations and functions in digital circuit design. Adders, multipliers, and shifters are the basis of digital operations, which can perform core operations, support data processing, and execute algorithms. In the central processing unit (CPU) and other processor units, these basic arithmetic units are key components for implementing various instructions in the instruction set architecture. The design of basic arithmetic units can be optimized according to requirements to reduce power consumption, increase speed, or reduce area. In digital signal processing systems, these arithmetic units are used to process signals and data, such as filtering, Fourier transform, and other operations, which usually require a combination of these arithmetic units to implement complex arithmetic operations.

[0003] In the reduced instruction set, the operation unit only performs a single operation of multiplication, shift, and addition in each cycle. However, in the complex instruction set, multiple operations are required to be implemented in a single cycle, so multiple basic operation units are needed to implement them together. In order to realize 32-bit multiplication, 16-bit multiplication and two parallel 16-bit multiplication operations, there are two conventional solutions. Solution 1 is to use a structure of 1 32-bit multiplication and 2 16-bit multiplications, and solution 2 is to use a structure of 1 32-bit multiplication and 1 16-bit multiplication. Among them, solution 1 uses an additional 16-bit multiplication structure to ensure that the time consumed when performing two parallel 16-bit multiplication operations is less, but more logic resources are used. Solution 2 reuses the 32-bit multiplication structure to realize 32-bit multiplication and 16-bit multiplication, using fewer logic resources, but the 32-bit multiplication structure consumes more time when performing 16-bit multiplication operations than directly using the 16-bit multiplication structure.

[0004] Therefore, current computing devices and methods use more logic resources and consume more time, and cannot meet existing fast computing requirements. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a multiplication, shift and addition combination operation device and operation method to achieve the purpose of using less logical resources and shortening the required time.

[0006] To achieve the above object, the technical solution of the present invention is as follows: A multiplication, shift and addition combined operation device comprises a multiplication operation part, a shift operation part and an addition operation part, wherein the multiplication operation part comprises Booth coding unit 1, Booth coding unit 2, Booth coding unit 3 and Booth coding unit 4; compression unit 1, compression unit 2, compression unit 3, compression unit 4 and compression unit 5; carry lookahead addition unit 1, carry lookahead addition unit 2 and carry lookahead addition unit 3; and a multiplication output selector; The Booth encoding unit 1, Booth encoding unit 2, Booth encoding unit 3 and Booth encoding unit 4 are connected to compression unit 1, compression unit 2, compression unit 3 and compression unit 4 respectively; the outputs of compression unit 1, compression unit 2, compression unit 3 and compression unit 4 are combined and then connected to compression unit 5; compression unit 1 is connected to carry lookahead addition unit 1 and then connected to multiplication output selector; compression unit 5 is connected to carry lookahead addition unit 3 and then connected to multiplication output selector; compression unit 4 is connected to carry lookahead addition unit 2; The shift operation part includes a shift input selector, a shift unit 1 and a shift unit 2; the multiplication output selector is connected to the shift input selector, the shift input selector is connected to the shift unit 1, and the carry lookahead addition unit 2 is connected to the shift unit 2; The addition operation part includes an addition input selector, an addition unit 1 and an addition unit 2, the shift unit 2 is connected to the addition unit 2, the shift unit 1 is connected to the addition input selector, and the addition input selector is connected to the addition unit 1.

[0007] In the above scheme, the compression unit one, compression unit two, compression unit three, compression unit four and compression unit five are Wallace compression units, the carry lookahead addition unit one and carry lookahead addition unit two are 32-bit carry lookahead addition units, and the carry lookahead addition unit three is a 64-bit carry lookahead addition unit.

[0008] In the above solution, the first shift unit is a 64-bit shift unit, and the second shift unit is a 32-bit shift unit.

[0009] In the above scheme, the adding unit 1 and the adding unit 2 are 32-bit carry-lookahead adding units.

[0010] In the above scheme, the input of the multiplication operation part is multiplication input data 1, multiplication input data 2 and multiplication control signal. After the multiplication operation, the multiplication operation result 1 and the multiplication operation result 2 are output to the shift operation part. At the same time, the multiplication operation result 1 is also directly output as the multiplication output data.

[0011] In the above scheme, the shift operation part receives the multiplication operation result 1 and the multiplication operation result 2 sent by the multiplication operation part, and simultaneously receives the shift input data and the shift control signal, and outputs the shift operation result 1 and the shift operation result 2 to the addition operation part after the shift operation, and simultaneously the shift operation result 1 is also directly output as the shift output data.

[0012] In the above scheme, the addition operation part receives shift operation result 1 and shift operation result 2 sent by the shift operation part, and simultaneously receives addition input data 1, addition input data 2 and addition control signal, and outputs addition output data 1 and addition output data 2 after addition operation.

[0013] A multiplication, shift and addition combined operation method adopts a multiplication, shift and addition combined operation device as described above. When performing parallel multiplication, shift and addition operations of two 16-bit signed numbers, it is necessary to simultaneously and sequentially calculate multiplication, shift and addition, and finally output the calculation result. The specific process includes the following steps: (1) The lower 16 bits of multiplication input data 1 and multiplication input data 2 are used to generate a partial product using Booth encoding unit 1, and the compressed result is obtained by compression unit 1, and then the carry-lookahead addition unit 1 performs an addition operation to obtain a multiplication result; the multiplication output selector selects the multiplication result output according to the multiplication control signal, that is, the multiplication result 1; The high 16 bits of multiplication input data 1 and multiplication input data 2 are used to generate partial products by Booth encoding unit 4, compressed by compression unit 4 to obtain compressed results, and then carried-ahead addition unit 2 performs addition operation to output multiplication operation result 2; (2) The shift input selector selects multiplication result 1 according to the shift control signal, enters shift unit 1 for shift operation, and obtains shift operation result 1; shift unit 2 receives multiplication result 2 for shift operation, and obtains shift operation result 2; (3) The addition input selector selects shift operation result 1 to enter addition unit 1 according to the addition control signal, performs addition operation to obtain addition output data 1; addition unit 2 receives shift operation result 2 and performs addition operation to obtain addition output data 2.

[0014] A multiplication shift addition combined operation method adopts a multiplication shift addition combined operation device as described above. When a 32-bit multiplication operation is performed, the lower 16 bits of multiplication input data 1 and multiplication input data 2 pass through Booth encoding unit 1 and compression unit 1, the lower 16 bits of multiplication input data 1 and the upper 16 bits of multiplication input data 2 pass through Booth encoding unit 2 and compression unit 2, the upper 16 bits of multiplication input data 1 and the lower 16 bits of multiplication input data 2 pass through Booth encoding unit 3 and compression unit 3, the upper 16 bits of multiplication input data 1 and the upper 16 bits of multiplication input data 2 pass through Booth encoding unit 4 and compression unit 4, the outputs of compression unit 1, compression unit 2, compression unit 3 and compression unit 4 are compressed by compression unit 5, and finally addition operation is performed by carry look-ahead addition unit 3 to output a 64-bit multiplication operation result. At this time, the multiplication operation result is output as multiplication operation result 1 and multiplication output data under the control of a multiplication control signal.

[0015] A multiplication shift addition combined operation method, using a multiplication shift addition combined operation device as described above, when performing a single 16-bit multiplication operation, the lower 16 bits of multiplication input data 1 and multiplication input data 2 are used to generate a partial product using Booth encoding unit 1, and compressed result 1 and compressed result 2 are obtained through compression unit 1, and then carry lookahead addition unit 1 performs addition operation to obtain a 32-bit multiplication operation result, and finally a multiplication control signal controls a multiplication output selector to select the result output; When performing a separate shift operation, the shift control signal selects the shift input data to enter the shift unit 1 through the shift input selector; the shift control signal controls the shift unit 1 to perform a shift operation to obtain a shift operation result 1 output; When performing a separate addition operation, the addition control signal selects the addition input data 2 to enter the addition unit 1 through the addition input selector, and performs an addition operation with the addition input data 1 to obtain an addition result output.

[0016] Through the above technical solution, the multiplication, shift and addition combined operation device and operation method provided by the present invention have the following beneficial effects: The present invention balances the two existing schemes, which is equivalent to using four 16-bit multiplication structures. In terms of logic resources, one 32-bit multiplication structure uses less logic resources than two 16-bit multiplication structures, and in terms of time resources, the time consumption of the 32-bit multiplication structure is greater than that of the 16-bit multiplication structure. Therefore, the present invention reduces the use of logic resources compared to the first scheme, and takes less time than the second scheme.

[0017] In addition, the three computing parts have both internal data paths and external input and output ports. The internal paths realize data transmission between computing units and ensure the realization of combined operations. The external ports realize independent operation of computing units and ensure the reading and writing of data for individual operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0019] Figure 1 A schematic diagram of a multiplication, shift and addition combined operation device disclosed in an embodiment of the present invention; Figure 2 This is a schematic diagram of the multiplication operation part; Figure 3 It is a schematic diagram of the shift operation part; Figure 4 This is a schematic diagram of the addition operation part. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0021] According to the operation type classification, the instruction set requires the implementation of three operations: multiplication, shift and addition. Among them, the multiplication operation requires support for 16-bit multiplication and 32-bit multiplication, including signed number multiplication and unsigned number multiplication, and requires support for up to 2 16-bit signed number multiplications in parallel. The shift operation requires support for 16-bit data shift, 32-bit data shift and 64-bit data shift, and supports arithmetic (left and right) shift, logical (left and right) shift and circular shift. It requires support for up to 2 32-bit data shift units to work simultaneously. The addition operation supports up to 32-bit data addition, and requires support for up to 2 32-bit data addition units to work simultaneously. The other three operations can be executed separately, so they can be transmitted to external data separately.

[0022] According to the above requirements, the present invention provides a multiplication, shift and addition combination operation device, such as Figure 1 As shown, it includes a multiplication operation part, a shift operation part and an addition operation part.

[0023] The input of the multiplication operation part is multiplication input data 1, multiplication input data 2 and multiplication control signal. After the multiplication operation, the multiplication operation result 1 and the multiplication operation result 2 are output to the shift operation part. At the same time, the multiplication operation result 1 is also directly output as the multiplication output data.

[0024] The shift operation part receives the multiplication operation result 1 and the multiplication operation result 2 sent by the multiplication operation part, and also receives the shift input data and the shift control signal. After the shift operation, it outputs the shift operation result 1 and the shift operation result 2 to the addition operation part. At the same time, the shift operation result 1 is also directly output as the shift output data.

[0025] The addition operation part receives shift operation result 1 and shift operation result 2 sent by the shift operation part, and simultaneously receives addition input data 1, addition input data 2 and addition control signal, and outputs addition output data 1 and addition output data 2 after addition operation.

[0026] 1. Multiplication operation part like Figure 2 As shown, the multiplication operation part includes 4 Booth encoding units (Booth encoding unit 1, Booth encoding unit 2, Booth encoding unit 3 and Booth encoding unit 4), 5 Wallace compression units (compression unit 1, compression unit 2, compression unit 3, compression unit 4 and compression unit 5), 2 32-bit carry lookahead addition units (carry lookahead addition unit 1 and carry lookahead addition unit 2), 1 64-bit carry lookahead addition unit (carry lookahead addition unit 3) and 1 output data selector (multiplication output selector).

[0027] The specific connection relationship is as follows: Booth encoding unit 1, Booth encoding unit 2, Booth encoding unit 3 and Booth encoding unit 4 are respectively connected to compression unit 1, compression unit 2, compression unit 3 and compression unit 4; the outputs of compression unit 1, compression unit 2, compression unit 3 and compression unit 4 are combined and connected to compression unit 5; compression unit 1 is connected to carry lookahead addition unit 1 and then to the multiplication output selector; compression unit 5 is connected to carry lookahead addition unit 3 and then to the multiplication output selector; compression unit 4 is connected to carry lookahead addition unit 2.

[0028] The multiplication control signal controls the multiplication output selector to select the operation result output as multiplication result one and multiplication output data. The multiplication output data is the data to be written back to the register. The multiplication result one is input into the shift input selector, and the multiplication result two is input into the shift unit two.

[0029] The Booth encoding unit is responsible for performing Booth encoding on the multiplication input data 1 and converting the multiplication input data 2 into corresponding partial products according to the encoding result. The number of partial products is determined by the bit width N of the multiplication input data 1, and its value is .

[0030] The compression unit uses a carry-save adder to compress the partial products, and finally obtains two compressed results.

[0031] The carry-lookahead addition unit is used to perform addition operation on two compressed results.

[0032] The multiplication output selector selects the corresponding calculation result for output under the control of the control signal.

[0033] When performing a 16-bit multiplication calculation, the lower 16 bits of the multiplication input data one and the lower 16 bits of the multiplication input data two are sequentially passed through Booth encoding unit one, compression unit one, and carry look-ahead addition unit one to obtain the multiplication result. The multiplication control signal controls the multiplication output selector to select the multiplication result output, that is, the multiplication operation result one and the multiplication output data. At this time, the data of other branches are invalid.

[0034] When performing 32-bit multiplication calculation, the multiplication input data 1 and the multiplication input data 2 use 4 Booth encoding units (Booth encoding unit 1, Booth encoding unit 2, Booth encoding unit 3 and Booth encoding unit 4) and 4 compression units (compression unit 1, compression unit 2, compression unit 3 and compression unit 4), that is, the low 16 bits of the multiplication input data 1 and the multiplication input data 2 pass through the Booth encoding unit 1 and the compression unit 1, the low 16 bits of the multiplication input data 1 and the high 16 bits of the multiplication input data 2 pass through the Booth encoding unit 2 and the compression unit 2, and the multiplication input data 2 passes through the Booth encoding unit 2 and the compression unit 2. The high 16 bits of input data one and the low 16 bits of multiplication input data two pass through Booth encoding unit three and compression unit three, the high 16 bits of multiplication input data one and the high 16 bits of multiplication input data two pass through Booth encoding unit four and compression unit four, the outputs of compression unit one, compression unit two, compression unit three and compression unit four are compressed by compression unit five, and finally added by carry look-ahead addition unit three, and a 64-bit multiplication result is output. At this time, the multiplication result is output as multiplication result one and multiplication output data under the control of the multiplication control signal.

[0035] In the dual 16-bit multiplication calculation, the first multiplication calculation is consistent with the single 16-bit multiplication calculation. The second 16-bit multiplication calculation uses Booth encoding unit 4, compression unit 4 and carry lookahead addition unit 2 to perform addition operation on the high 16 bits of multiplication input data one and the high 16 bits of multiplication input data two, and outputs a 32-bit multiplication result, i.e., multiplication result two.

[0036] 2. Shift operation part like Figure 3 As shown, the shift operation part includes a shift input data selector, a 64-bit shift unit (shift unit 1) and a 32-bit shift unit (shift unit 2). The specific connection relationship is: the multiplication output selector is connected to the shift input selector, the shift input selector is connected to the shift unit 1, and the carry-lookahead addition unit 2 is connected to the shift unit 2.

[0037] The multiplication result 1 and the multiplication result 2 come from the multiplication operation part. The shift operation result 1 is input to the addition input selector, and the shift operation result 2 is input to the addition unit 2. The shift control signal controls the shift input selector to select the input data, and also controls the number of shift bits, the shift mode (arithmetic shift and logical shift) and the shift direction (left shift and right shift). The shift input selector selects the data input to the shift unit 1 according to the shift control signal. The shift unit 1 supports 16-bit, 32-bit and 64-bit data shifts, including arithmetic (left and right) shifts, logical (left and right) shifts and circular shifts. The shift unit 2 supports arithmetic shifts of 32-bit data.

[0038] 3. Addition Operation like Figure 4 As shown, the addition operation part includes 1 addition input selector and 2 32-bit carry-lookahead addition units (addition unit 1 and addition unit 2). The specific connection relationship is: shift unit 2 is connected to addition unit 2, shift unit 1 is connected to the addition input selector, and the addition input selector is connected to addition unit 1.

[0039] The shift operation result one and the shift operation result two come from the shift operation part, and the addition control signal controls the addition input selector to select the data input addition unit one.

[0040] By adopting a multiplication, shift and addition combined operation device as above, the present invention can realize a multiplication, shift and addition combined operation method, and can also realize separate multiplication, shift and addition operations. The ultimate purpose of the result of the operation is to write it back to the register, so whether the output is valid also requires a write enable signal. Only when the write enable signal is valid is the output data valid and can it be written back normally. Since the write enable signal is parallel to the present design and does not need to be operated, it will not be described in detail. In addition, all paths and outputs of the combinational logic are inherent in any application scenario, but not all outputs are valid, so only valid paths and outputs are described, and other paths and outputs are ignored.

[0041] Application scenario 1: Performing a single multiplication, shift or addition operation.

[0042] (I) 16-digit multiplication: Output result = multiplication input data 1 * multiplication input data 2; The processing steps of the present invention are as follows: 1. Data input; 2. The lower 16 bits of multiplication input data 1 and multiplication input data 2 use Booth encoding unit 1 to generate partial products, and then pass through compression unit 1 to obtain compressed result 1 and compressed result 2, and then carry-lookahead addition unit 1 performs addition operation to obtain a 32-bit multiplication operation result. Finally, the multiplication control signal controls the multiplication output selector to select the result output.

[0043] (ii) 32-bit multiplication: Output result = multiplication input data 1 * multiplication input data 2; The processing steps of the present invention are as follows: 1. Data input; 2. The multiplication input data 1 and the multiplication input data 2 use 4 Booth encoding units to generate 4 groups of partial products, and pass through 4 compression units (compression unit 1, compression unit 2, compression unit 3 and compression unit 4) to obtain 4 groups of compressed results, and then pass through compression unit 5 to obtain 2 compressed results, and finally carry lookahead addition unit 3 performs addition operation to obtain a 64-bit multiplication operation result, which is output through the multiplication output selector.

[0044] (III) Shift operation: Output result = shift input data << PM; The processing steps of the present invention are as follows: 1. Data input; 2. The shift control signal selects the shift input data to enter the shift unit 1 through the shift input selector; 3. The shift control signal controls the shift unit to perform a shift operation and obtain a shift operation result to output.

[0045] (IV) Addition operation: Output result = addition input data 1 + addition input data 2; The processing steps of the present invention are as follows: 1. Data input; 2. The addition control signal selects the addition input data 2 to enter the addition unit 1 through the addition input selector, and performs an addition operation with the addition input data 1 to obtain the addition result output.

[0046] Application scenario 2: Perform 32-bit multiplication and shift operations.

[0047] Output result 1 = (multiplication input data 1 * multiplication input data 2) << PM; The processing steps of the present invention are as follows: 1. Data input; 2. The multiplication input data 1 and the multiplication input data 2 use 4 Booth encoding units to generate 4 groups of partial products, which are then compressed by 4 compression units (compression unit 1, compression unit 2, compression unit 3 and compression unit 4) to obtain 4 groups of compressed results, and then compressed by compression unit 5 to obtain 2 compressed results, and finally the carry lookahead addition unit 3 performs addition operation to obtain a 64-bit multiplication operation result; 3. The multiplication control signal selects the 64-bit multiplication result to be output through the multiplication output selector, i.e., the multiplication result 1; 4. The shift control signal selects the multiplication result, enters the shift unit through the shift input selector, performs the shift operation, and then outputs the result, that is, the shift output result.

[0048] Application scenario three: When performing parallel operations of multiplication, shift, and addition of two 16-bit signed numbers, it is necessary to calculate the multiplication, shift, and addition sequentially at the same time and finally output the calculation results.

[0049] The calculation process is to multiply the lower 16 bits of multiplication input data 1 and multiplication input data 2, and the multiplication result is input to shift unit 1 through the shift input data selector for shifting. The shift number is PM. The shift output result is added through the addition input selector and addition input data 1. The addition result is the final output result. Another parallel path is to multiply the upper 16 bits of multiplication input data 1 and multiplication input data 2, and the multiplication result is input to shift unit 2 for shifting. The shift number is PM. The shift output result and addition input data 2 are added, and the addition result is the final output result. The details are as follows:

[0050] Output result 1 = addition input data 1 + (multiplication input data 1 low 16 bits * multiplication input data 2 low 16 bits) << PM; Output result 2 = addition input data 2 + multiplication input data 1 lower 16 bits * multiplication input data 2 lower 16 bits) << PM; The processing steps of the present invention are as follows: 1. Data input; 2. The lower 16 bits of multiplication input data 1 and multiplication input data 2 are used to generate partial products by Booth encoding unit 1, and compressed results are obtained by compression unit 1, and then addition operation is performed by carry-lookahead addition unit 1 to obtain multiplication result. The multiplication control signal selects the multiplication result to be output through the multiplication output selector, i.e., multiplication result 1.

[0051] The high 16 bits of multiplication input data one and multiplication input data two use Booth encoding unit four to generate partial products, which are compressed by compression unit four, and then carry-lookahead addition unit two performs addition operation to output the multiplication operation result, i.e., multiplication operation result two.

[0052] 3. The shift input selector selects the multiplication result 1 according to the shift control signal, enters the shift unit 1 for shift operation, and obtains the shift operation result 1; the shift unit 2 receives the multiplication result 2 for shift operation, and obtains the shift operation result 2; 4. The addition input selector selects shift operation result 1 to enter addition unit 1 according to the addition control signal, performs addition operation to obtain addition output data 1; addition unit 2 receives shift operation result 2 to perform addition operation to obtain addition output data 2.

[0053] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multiplication, shift and addition combined operation device, characterized in that: It includes a multiplication operation part, a shift operation part and an addition operation part, wherein the multiplication operation part includes Booth coding unit 1, Booth coding unit 2, Booth coding unit 3 and Booth coding unit 4; compression unit 1, compression unit 2, compression unit 3, compression unit 4 and compression unit 5; carry lookahead addition unit 1, carry lookahead addition unit 2 and carry lookahead addition unit 3; and a multiplication output selector; The Booth encoding unit 1, Booth encoding unit 2, Booth encoding unit 3 and Booth encoding unit 4 are connected to compression unit 1, compression unit 2, compression unit 3 and compression unit 4 respectively; the outputs of compression unit 1, compression unit 2, compression unit 3 and compression unit 4 are combined and then connected to compression unit 5; compression unit 1 is connected to carry lookahead addition unit 1 and then connected to multiplication output selector; compression unit 5 is connected to carry lookahead addition unit 3 and then connected to multiplication output selector; compression unit 4 is connected to carry lookahead addition unit 2; The shift operation part includes a shift input selector, a shift unit 1 and a shift unit 2; the multiplication output selector is connected to the shift input selector, the shift input selector is connected to the shift unit 1, and the carry lookahead addition unit 2 is connected to the shift unit 2; The addition operation part includes an addition input selector, an addition unit 1 and an addition unit 2, the shift unit 2 is connected to the addition unit 2, the shift unit 1 is connected to the addition input selector, and the addition input selector is connected to the addition unit 1.

2. A multiplication, shift and addition combined operation device according to claim 1, characterized in that: The compression unit one, compression unit two, compression unit three, compression unit four and compression unit five are Wallace compression units, the carry lookahead addition unit one and carry lookahead addition unit two are 32-bit carry lookahead addition units, and the carry lookahead addition unit three is a 64-bit carry lookahead addition unit.

3. The multiplication, shift and addition combined operation device according to claim 1, characterized in that: The first shift unit is a 64-bit shift unit, and the second shift unit is a 32-bit shift unit.

4. The multiplication, shift and addition combined operation device according to claim 1, characterized in that: The adding unit 1 and the adding unit 2 are 32-bit carry-lookahead adding units.

5. The multiplication, shift and addition combined operation device according to claim 1, characterized in that: The input of the multiplication operation part is multiplication input data 1, multiplication input data 2 and a multiplication control signal. After the multiplication operation, the multiplication operation result 1 and the multiplication operation result 2 are output to the shift operation part. At the same time, the multiplication operation result 1 is also directly output as the multiplication output data.

6. The multiplication, shift and addition combined operation device according to claim 5, characterized in that: The shift operation part receives multiplication operation result 1 and multiplication operation result 2 sent by the multiplication operation part, and simultaneously receives shift input data and shift control signal, and outputs shift operation result 1 and shift operation result 2 to the addition operation part after shift operation, and simultaneously shift operation result 1 is also directly output as shift output data.

7. The multiplication, shift and addition combined operation device according to claim 6, characterized in that: The addition operation part receives shift operation result 1 and shift operation result 2 sent by the shift operation part, and simultaneously receives addition input data 1, addition input data 2 and addition control signal, and outputs addition output data 1 and addition output data 2 after addition operation.

8. A multiplication, shift and addition combined operation method, using a multiplication, shift and addition combined operation device as claimed in any one of claims 1 to 7, characterized in that: When performing parallel operations of multiplication, shift and addition of two 16-bit signed numbers, it is necessary to calculate the multiplication, shift and addition in sequence at the same time and finally output the calculation result. The specific process includes the following: (1) The lower 16 bits of multiplication input data 1 and multiplication input data 2 are used to generate a partial product using Booth encoding unit 1, and the compressed result is obtained by compression unit 1, and then the carry-lookahead addition unit 1 performs an addition operation to obtain a multiplication result; the multiplication output selector selects the multiplication result output according to the multiplication control signal, that is, the multiplication result 1; The high 16 bits of multiplication input data 1 and multiplication input data 2 are used to generate partial products by Booth encoding unit 4, compressed by compression unit 4 to obtain compressed results, and then carried-ahead addition unit 2 performs addition operation to output multiplication operation result 2; (2) The shift input selector selects multiplication result 1 according to the shift control signal, enters shift unit 1 for shift operation, and obtains shift operation result 1; shift unit 2 receives multiplication result 2 for shift operation, and obtains shift operation result 2; (3) The addition input selector selects shift operation result 1 to enter addition unit 1 according to the addition control signal, performs addition operation to obtain addition output data 1; addition unit 2 receives shift operation result 2 and performs addition operation to obtain addition output data 2.

9. A multiplication, shift and addition combined operation method, using a multiplication, shift and addition combined operation device as claimed in any one of claims 1 to 7, characterized in that: When performing a 32-bit multiplication operation, the low 16 bits of the multiplication input data 1 and the multiplication input data 2 pass through the Booth encoding unit 1 and the compression unit 1, the low 16 bits of the multiplication input data 1 and the high 16 bits of the multiplication input data 2 pass through the Booth encoding unit 2 and the compression unit 2, the high 16 bits of the multiplication input data 1 and the low 16 bits of the multiplication input data 2 pass through the Booth encoding unit 3 and the compression unit 3, the high 16 bits of the multiplication input data 1 and the high 16 bits of the multiplication input data 2 pass through the Booth encoding unit 4 and the compression unit 4, the outputs of the compression unit 1, the compression unit 2, the compression unit 3 and the compression unit 4 are compressed by the compression unit 5, and finally the addition operation is performed by the carry look-ahead addition unit 3, and a 64-bit multiplication operation result is output. At this time, the multiplication operation result is output as the multiplication operation result 1 and the multiplication output data under the control of the multiplication control signal.

10. A multiplication, shift and addition combined operation method, using a multiplication, shift and addition combined operation device as claimed in any one of claims 1 to 7, characterized in that: When performing a separate 16-bit multiplication operation, the lower 16 bits of the multiplication input data 1 and the multiplication input data 2 are used to generate a partial product using the Booth encoding unit 1, and the compressed result 1 and the compressed result 2 are obtained by the compression unit 1, and then the carry-lookahead addition unit 1 performs an addition operation to obtain a 32-bit multiplication operation result, and finally the multiplication control signal controls the multiplication output selector to select the result output; When performing a separate shift operation, the shift control signal selects the shift input data to enter the shift unit 1 through the shift input selector; the shift control signal controls the shift unit 1 to perform a shift operation to obtain a shift operation result 1 output; When performing a separate addition operation, the addition control signal selects the addition input data 2 to enter the addition unit 1 through the addition input selector, and performs an addition operation with the addition input data 1 to obtain an addition result output.

Images