Data cache access method and device

Abstract

The invention provides a data cache access method and device, and is applied to the technical field of computer processors. The method comprises the following steps: acquiring an access request, and performing blocking judgment by adopting a cache group blocking strategy under the condition that a path operated by the access request for data cache access is not determined; under the condition that a path operated by the access request to the data cache access is determined, adopting a cache group blocking strategy and a cache path blocking strategy to carry out blocking judgment; wherein the cache group blocking strategy is that if the group addresses are the same, the request is blocked, and otherwise, the request is not blocked; the cache path blocking strategy is that if the path addresses are the same, the request is blocked, and otherwise, the request is not blocked.

Description

Technical Field

[0001] The present application relates to the technical field of computer processors, and in particular to a data cache access method and device. Background Art

[0002] As processor technology evolves from single-core to multi-core, the load and store instructions in the processor usually access the data cache first to improve data access efficiency. However, cache misses may occur during the access process, and multi-core processors will receive external consistency requests from other processor cores to ensure data cache consistency. There are also many situations that may cause data cache access address conflicts.

[0003] At present, a relatively simple method for handling data cache access address conflicts is to block subsequent access operations to conflicting addresses. When a cache access failure occurs, data is retrieved from the next-level storage system such as the main memory, and the original cache blocks in the data cache are replaced and filled according to strategies such as the least recently used (Least Recently Used, LRU). For the cache consistency problem in multi-core processors, it is maintained through an external consistency request mechanism between cores.

[0004] However, since data cache access, especially cache invalidation processing, takes a long time, this blocking operation will cause the memory access pipeline to be blocked, thereby significantly reducing the parallelism of program execution and ultimately hindering the improvement of processor performance. Summary of the invention

[0005] The present application provides a data cache access method and device to solve the problem of data cache access address conflict.

[0006] The present application provides a data cache access method, including: obtaining an access request; in the case where the way operated by the access request for the data cache access is not determined, using a cache group blocking strategy to make a blocking judgment; in the case where the way operated by the access request for the data cache access is determined, using a cache group blocking strategy and a cache way blocking strategy to make a blocking judgment; wherein the cache group blocking strategy is to block the request if the group address is the same, otherwise the request is not blocked; the cache way blocking strategy is to block the request if the way address is the same, otherwise the request is not blocked.

[0007] According to a data cache access method provided by the present application, in the case where the way operated by the access request for data cache access is not determined, a cache group blocking strategy is used to perform blocking judgment; in the case where the way operated by the access request for data cache access is determined, a cache group blocking strategy and a cache way blocking strategy are used to perform blocking judgment, including: when the access request enters the main pipeline, if the group address of the access request meets a first condition, the access request is blocked; wherein the first condition includes: the group address of the access request is the same as the group address of the pipeline stage after the main pipeline accesses the data cache tag and label, or the group address of the access request is the same as the group address of the pipeline stage after the replacement pipeline reads the tag and data, or the group address of the access request is the same as the group address of the fill pipeline.

[0008] According to a data cache access method provided by the present application, in the case where the way operated by the access request for data cache access is not determined, a cache group blocking strategy is used to perform blocking judgment; in the case where the way operated by the access request for data cache access is determined, a cache group blocking strategy and a cache way blocking strategy are used to perform blocking judgment, including: when the access request enters the replacement pipeline to replace the target cache block, if the group address of the access request is the same as the group address of the main pipeline access request to access the data cache tag and tag pipeline stage, or is the same as the group address of the pipeline stage after the main pipeline access request to access the data cache tag and tag pipeline stage and is the same way, then the access request is blocked.

[0009] According to a data cache access method provided by the present application, when the way on which the access request operates on the data cache access is not determined, a cache group blocking strategy is used to perform a blocking judgment; when the way on which the access request operates on the data cache access is determined, a cache group blocking strategy and a cache way blocking strategy are used to perform a blocking judgment, including: when the access request enters the fill pipeline, if the access request and the main pipeline access request have the same group address of the read data pipeline stage and are the same way, then the access request is blocked.

[0010] According to a data cache access method provided by the present application, when the way operated by the access request for data cache access is not determined, a cache group blocking strategy is used to perform blocking judgment; when the way operated by the access request for data cache access is determined, a cache group blocking strategy and a cache way blocking strategy are used to perform blocking judgment, including: when the access request enters a memory access invalidation queue, if the access request and any existing item in the memory access invalidation queue are replacement fills of the same group address and are replacement fills of the same way, then the access request is blocked.

[0011] The present application also provides a data cache access device, comprising the following modules: an acquisition module and a processing module; the acquisition module is used to acquire an access request; the processing module is used to use a cache group blocking strategy to make a blocking judgment when the way operated by the access request for the data cache access is not determined; when the way operated by the access request for the data cache access is determined, a cache group blocking strategy and a cache way blocking strategy are used to make a blocking judgment; wherein, the cache group blocking strategy is to block the request if the group address is the same, otherwise the request is not blocked; the cache way blocking strategy is to block the request if the way address is the same, otherwise the request is not blocked.

[0012] According to a data cache access device provided by the present application, the processing module is used to block the access request when the access request enters the main pipeline if the group address of the access request meets the first condition; wherein the first condition includes: the group address of the access request is the same as the group address of the pipeline stage after the main pipeline accesses the data cache tag and label, or the group address of the access request is the same as the group address of the pipeline stage after the replacement pipeline reads the tag and data, or the group address of the access request is the same as the group address of the fill pipeline.

[0013] According to a data cache access device provided by the present application, the processing module is used to block the access request when the access request enters the replacement pipeline to replace the target cache block if the group address of the access request is the same as the group address of the main pipeline access request to access the data cache tag and tag pipeline stage, or is the same as the group address of the pipeline stage after the main pipeline access request to access the data cache tag and tag pipeline stage and is in the same way.

[0014] According to a data cache access device provided by the present application, the processing module is used to block the access request when the access request enters the fill pipeline if the access request has the same group address as the main pipeline access request read data pipeline stage and is in the same way.

[0015] According to a data cache access device provided by the present application, the processing module is used to block the access request when the access request enters the memory access failure queue if the access request and any existing item in the memory access failure queue are replacement fills of the same group address and are replacement fills of the same way.

[0016] The present application also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the data cache access method described above is implemented.

[0017] The present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the data cache access method described in any one of the above is implemented.

[0018] The present application also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned data cache access methods.

[0019] The data cache access method and device provided in the present application can accurately handle data cache access address conflicts, reduce blockages caused by conflicts, thereby improving the parallel processing capability of data cache access address conflicts, and ultimately improving processor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 is a schematic diagram of the structure of the cache memory provided by the present application; Figure 2 It is a pipeline architecture diagram of the data cache system provided by this application; Figure 3 It is a flowchart of the data cache access method provided by the present application; Figure 4 It is a structural diagram of a data cache access device provided by the present application; Figure 5 It is a structural schematic diagram of the electronic device provided by this application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] It should be noted that, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0024] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0025] In order to facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and order of execution.

[0026] The embodiments of the present application describe some exemplary embodiments for the purpose of explanation. It should be understood that the present application can be implemented in other ways that are not specifically shown in the drawings.

[0027] As computer processor technology develops from single-core to multi-core, the performance of the processor storage system has an increasingly significant impact on overall performance. When the processor executes load instructions and store instructions, it involves access to the data cache (DCache). Both of these instructions may cause data cache access failures (Miss), and in the case of failures, data needs to be retrieved from the next-level storage system, which involves replacing the original blocks in the data cache and filling them with the retrieved data (Refill). In addition, the data cache of a multi-core processor will also receive external consistency requests (Probe) from other processor cores to maintain cache coherence (Cache Coherence).

[0028] These different types of accesses to the data cache may have the same cache block address, such as the same tag and index bit, which means access to the same cache block; or although the cache block address is different, the index bit of the access address is the same, which means operations on the same cache set. As long as the address of the cache set is the same (that is, the index bit is the same), it is possible to operate on the same cache block, which will cause a conflict in data cache access, resulting in inconsistent data and status, so this type of data cache access address conflict must be handled.

[0029] The simplest way to handle data cache access address conflicts is the blocking strategy, that is, before the previous conflicting access operation is resolved, only process the operation and block the subsequent access operations of the conflicting address. This method is relatively easy to implement, but it has obvious disadvantages. Because the data cache access processing time is often long, especially when dealing with data cache misses. If other operations are blocked during this period, the memory access pipeline will be blocked, greatly reducing the parallelism of the processor program execution, thereby hindering the improvement of processor performance.

[0030] The processing performance of data cache access requests is crucial to processor performance, and there are many key points that need to be weighed in its design process. Due to the access addresses of multiple Load instructions and multiple Store instructions to the data cache, the replacement addresses and fill addresses of the data cache returned by the lower-level storage system, and the addresses of the external consistency requests of other processor cores in the multi-core processor to the data cache, the same cache block address or operations on the same cache group may appear, thus causing access address conflicts. The processing of these conflicting operations can be performed either serially or in parallel. The efficiency and parallelism of data cache access address conflict processing are particularly important for the out-of-order execution performance of high-performance processors and the multi-core parallelism of multi-core processors. This means that when designing a data cache access request processing mechanism, it is necessary to comprehensively consider how to improve processing efficiency and maintain high parallelism as much as possible while avoiding problems caused by conflicts, so as to improve the overall performance of the processor.

[0031] In order to solve the above problems, the embodiment of the present application provides a data cache access method, which makes blocking judgment by combining a cache set (Cache Set) and a way (Way), and only implements blocking at a specific pipeline level, so that blocking is more fine-grained, thereby reducing the frequency of unnecessary blocking. In order to clearly describe the method provided by the embodiment of the present application, the technology involved in the embodiment of the present application is described in detail below.

[0032] 1. The function and principle of Cache (cache memory) Cache is located between the processor and the memory, and is usually composed of SRAM (static random access memory). The processor has an extremely fast computing speed, while the memory access speed is much slower. When the processor directly accesses data from the memory, it needs to wait for many clock cycles. The cache has a fast access speed, and it can store some data that the processor has just used or will use in a loop. In this way, when the processor needs this part of data again, it can be directly retrieved from the cache without having to obtain it from the memory with a longer delay, thereby effectively reducing the waiting time of the processor and greatly improving the overall efficiency of the system.

[0033] 2. Cache structure Cache mainly consists of two parts, namely the tag part and the data part. The data part is responsible for storing a piece of data with a continuous address, while the tag part is used to store the public address of this piece of continuous data.

[0034] A tag and all the corresponding data together form a row, which is called a cache line. In addition, the data part of a cache line is called a data block. If a piece of data can be stored in multiple locations in the cache, then these multiple cache lines that can be found through the same address index are called a cache set.

[0035] 3. Classification of Cache Composition There are three types of cache composition: direct associative, set associative, and fully associative. This application focuses on the set associative method. In fact, direct associative and fully associative can be regarded as special set associative composition methods with a way number of 1 and a way number equal to the number of cache lines, respectively.

[0036] 4. Address processing in group-associative mode like Figure 1 As shown in the figure, in the set-associated cache structure, the access address of the processor to the memory will be divided into three parts, namely, tag, index and block offset, which are used to locate data in the cache. The cache consists of multiple cache ways and cache groups. Each cache group contains multiple cache lines. The cache line number is used to identify the specific line in the cache, and the byte number is used to locate the specific byte in the cache line. The tag RAM is used to store the tag of the corresponding data. The tag is used to identify the location in the main memory where the data in the cache line comes from. The data RAM is used to store data loaded from the main memory. By comparing the tag in the access address with the tag in the tag RAM, it can be determined whether it is a hit (Hit). If it is a hit, the data can be read from the data RAM (Read data). If there are multiple ways, the way number (Way number) of the data storage needs to be determined.

[0037] The Index can be used to find a group of Cache Lines from the Cache, that is, a Cache Set. Then, the Tag part read out by the Index is compared with the Tag in the access address. Only when the two are equal, it means that this Cache Line is what is needed.

[0038] There are many memory access data in a Cache Line. With the help of the Block Offset part in the memory address and the access width of the memory access instruction, the data you really want can be found accurately, and it can locate each byte.

[0039] 5. Multi-core processor cache line tag (Meta) and status There is also a tag bit (Meta) in the cache line of a multi-core processor. Its main function is to mark whether the data is valid, whether the data is dirty (i.e., whether it has been modified), and mark the cache consistency status of the multi-core processor. If there is an ECC (error checking and correction) check, it is generally placed in the tag storage array (Meta Array).

[0040] Each cache block of the multi-core processor data cache has the following three states: INV (invalid state): indicates that the corresponding data cache block is in an invalid state, that is, the data in the block is currently unavailable.

[0041] SHD (Shared State): Indicates that the corresponding data cache block is in a shared state. In this state, when the processor core reads the block, it can directly hit it, but if a write operation is performed on the block, a write failure will occur.

[0042] EXC (exclusive state): indicates that the corresponding data cache block is in an exclusive state. At this time, the processor can directly hit the read and write operations on the block. In addition, each cache block has a dirty bit (w bit) indicating whether the block has been written. If the block has been written, the w bit is set to 1. It should be noted that when a write failure operation on a cache block retrieves the corresponding cache block from the lower-level storage system, it will first be set to the EXC state. Only when the cache block is actually written will the w bit be set to 1. At this time, the EXC state plus the w bit represents the M (Modify) state.

[0043] Combine the following Figure 2 The functions, operation processes and relationships between different pipelines, queues and storage arrays in a data cache processing system are described in detail.

[0044] 1. Load instruction access pipeline Access process and clock cycle: The access process of the load instruction is divided into three beats (each beat corresponds to a processor clock cycle). The first beat reads the tag (Meta) and label (Tag), which may be to determine the location of the data to be obtained in the cache and other related information; the second beat reads the data (Data); the third beat performs the data selection (Sel Data) operation, that is, selects the part that meets the requirements from the read data.

[0045] Hit and miss processing: If the data cache access is hit (Hit), the required data is returned directly. If the data cache access is miss (Miss), it will enter the memory access miss queue (MissQueue) after these 3 beats. And on the access pipeline of the data access instruction (Load), it is necessary to determine the cache way (Way) that the failed cache block is replaced by, and send the information of the replaced block to the memory access miss queue (Miss Queue) for subsequent related processing.

[0046] 2. Main Pipe Processing tasks and access flow: The main pipeline is mainly responsible for processing store instructions (Store) and external consistency requests (Probe), and their access flow is 4 beats. The first beat reads the tag (Meta) and label (Tag), which is similar to the first beat of the data fetch instruction and is used to initially locate the data; the second beat reads the data (Data); the third beat obtains the result of reading the data (Data) and combines it with the data to be written; the fourth beat updates the tag (Meta), label (Tag) and data (Data) according to the result of the operation. For external consistency requests, if it is necessary to initiate a write back to the next level storage system, an access request to the writeback queue (Writeback Queue) is generated at this level and written to the writeback queue (Writeback Queue).

[0047] Subsequent processing of store instructions: After the store instruction is submitted, the data in it will be moved to the store buffer. The store buffer will merge the store write requests in units of cache lines. When it is close to full, the merged multiple store write requests will be written into the data cache at the same time.

[0048] Failure handling: Similar to the data load instruction, if the data cache access by the store instruction fails (Miss), it will enter the memory access failure queue (Miss Queue) after 3 beats. Similarly, the cache way (Way) to replace the failed cache block must be determined on the store instruction (Store) access pipeline, and the information of the replaced block must be sent to the memory access failure queue (Miss Queue).

[0049] 3. Refill Pipe Backfill function and operation flow: The main function of the refill pipeline is to backfill the failed (Miss) load request. The operation only takes one beat, that is, after getting the refill data, it is directly written into the data cache (DCache), thereby completing the supplement of the data missing due to the failure of the load instruction.

[0050] 4. Replace Pipe Replacement operation process: The Replace Pipe is responsible for reading the data of the block to be replaced, with a total of 2 beats. The first beat reads the tag (Meta) and data (Data), which may be to obtain relevant information about the block to be replaced for subsequent processing; the second beat invalidates the tag (Meta) and generates a write-back request (Release) to the lower-level storage system to the write-back queue (Writeback Queue), completing the processing of the block to be replaced so that its data status meets the replacement requirements.

[0051] 5. Miss Queue Function and processing flow: The responsibility of the memory miss queue is to retrieve the cache blocks or permissions that need to be refilled. For example, for a storage instruction access, when a cache block in the shared (SHD) state is hit, it may be necessary to retrieve the exclusive (EXC) permission. After retrieving these required contents, they will be sent to the refill pipeline (Refill Pipe) to complete the data backfill operation.

[0052] 6. External consistency request queue (Probe Queue) Function and data flow: The external consistency request queue (Probe Queue) mainly accepts external consistency requests (Probe) and then sends these requests to the main pipeline (Main Pipe). These external consistency requests are requests from other processor cores to access data cache in order to maintain cache coherence (Cache Coherence) in the multi-core processor.

[0053] 7. Writeback Queue Processing tasks: The Writeback Queue mainly processes writebacks (Release) and sends responses to external consistency requests (ProbeAck). It plays a role in processing writeback operations and external consistency request responses in the entire data processing flow.

[0054] 8. Data RAM, Tag RAM, and MetaArray Storage media and features: Data RAM and Tag RAM are generally implemented using SRAM (Static Random Access Memory). MetaArray is generally implemented using registers. And there is such a relationship: writing a tag (Tag) will definitely write a tag (Meta), but sometimes only writing a tag (Meta) without writing a tag (Tag) is related to different operating scenarios and data processing requirements. For example, in some cases, only the tag-related information needs to be updated without involving the update of the tag.

[0055] like Figure 3 As shown, an embodiment of the present application provides a data cache access method, which can be applied to a data cache access device. The data cache access method may include S301-S302: S301: The data cache access device obtains an access request.

[0056] Optionally, the above access request may be a request to modify the data cache or a request not to modify the data cache, wherein the request to modify the data cache may be one of a store instruction access request, an external consistency request, a replacement request, a fill request, a memory invalidation queue request, and a write back queue request; and the request not to modify the data cache may be a fetch instruction access request.

[0057] It should be noted that the request to modify the data cache refers to a request that needs to be blocked, and the request not to modify the data cache refers to a request that does not need to be blocked.

[0058] It should be noted that the present application does not block access requests to the fetch instruction pipeline because access to the fetch instruction does not involve modifying the data cache, so there is no need to block it, thereby ensuring the execution efficiency of the fetch instruction.

[0059] S302. The data cache access device uses a cache group blocking strategy to perform a blocking judgment when the way operated by the access request to the data cache access is not determined; and uses a cache group blocking strategy and a cache way blocking strategy to perform a blocking judgment when the way operated by the access request to the data cache access is determined.

[0060] The cache group blocking strategy is to block requests if the group addresses are the same, otherwise the requests are not blocked; the cache way blocking strategy is to block requests if the way addresses are the same, otherwise the requests are not blocked.

[0061] Optionally, when the access request enters the main pipeline, if the group address of the access request satisfies a first condition, the access request is blocked; wherein the first condition includes: the group address of the access request is the same as the group address of the pipeline stage after the main pipeline accesses the data cache tag and label, or the group address of the access request is the same as the group address of the pipeline stage after the replacement pipeline reads the tag and data, or the group address of the access request is the same as the group address of the fill pipeline.

[0062] For example, the first condition may be that the group address of the access request is the same as the group address of the 2nd, 3rd, and 4th beats of the main pipeline, or the group address of the access request is the same as the group address of the 2nd beat of the replacement pipeline, or the group address of the access request is the same as the group address of the fill pipeline.

[0063] Specifically, when a store instruction (Store) access request and an external consistency request (Probe) enter the main pipeline MainPipe, if its Set address is the same as the Set address of the 2nd, 3rd, and 4th beats of the main pipeline or the 2nd beat of the replacement pipeline or the fill pipeline, it will be blocked. Because the cache way (Way) of the operation is not determined at this time, the blocking is determined by the relatively coarse-grained condition of the Set address.

[0064] The first beat of the main pipeline usually does not need to be blocked. The reason is that even if the store instruction Store is hit when reading Meta and Tag in the first beat of the main pipeline MainPipe, and the reading of Meta and Tag is interrupted by writing, the read Data will not be inconsistent with the Meta and Tag read in the previous beat.

[0065] Optionally, when the access request enters the replacement pipeline to replace the target cache block, if the group address of the access request is the same as the group address of the main pipeline access request to access the data cache tag and tag pipeline stage, or is the same as the group address of the pipeline stage after the main pipeline access request to access the data cache tag and tag pipeline stage and is in the same way, the access request is blocked.

[0066] For example, when the access request enters the replacement pipeline to replace the target cache block, if the group address of the access request is the same as the group address of the first access request of the main pipeline, or is the same as the group address of the second, third, and fourth access requests of the main pipeline and is in the same way, the access request is blocked.

[0067] Specifically, when entering the Replace Pipe to replace the target cache block A, if the Set address is the same as the access request of the first beat of the main pipeline, or the Set address is the same as the access request of the second, third, and fourth beats of the main pipeline and is the same way, the request to replace A will be blocked. Considering that the cache way (Way) where the replacement block is located has been determined when the Load and Store instructions fail, different precisions of blocking judgment are used according to whether the way is determined when the number of beats of different main pipelines corresponds (the first beat is based on the Set address, and the 2nd, 3rd, and 4th beats are based on Set + Way).

[0068] Optionally, when the access request enters the fill pipeline, if the access request has the same group address as the main pipeline access request read data pipeline stage and is in the same way, the access request is blocked.

[0069] For example, when the access request enters the fill pipeline, if the access request has the same group address and the same way as the access request of the second beat of the main pipeline, the access request is blocked.

[0070] Specifically, when entering the Refill Pipe, if the fill request has the same Set address as the access request of the second beat of the Main Pipe and is on the same way, it will be blocked. Because the Refill Pipe determines the way to be written and only affects the data read by the Main Pipe, it only needs to perform this blocking judgment with the second beat of the Main Pipe.

[0071] Optionally, when the access request enters the memory access failure queue, if the access request and any existing item in the memory access failure queue are replacement fills of the same group address and are replacement fills of the same way, the access request is blocked.

[0072] Specifically, when the Miss Queue is entered, if the invalidation request to be entered has the same group address as the existing item in the Miss Queue and is a replacement fill for the same way, the invalidation request will be blocked from entering the Miss Queue; for requests with the same address, a flexible processing method is adopted, in which the invalidation request is directly passed to the data access (Load) pipeline or merged into the memory access invalidation queue item to wait for backfill.

[0073] It should be noted that there are only three writes in the access of the data cache, namely the 4th beat of the Main Pipe, the 2nd beat of the Replace Pipe, and the Refill Pipe. For these three write situations, the relationship between the read operations of each pipeline is analyzed respectively. The above blocking strategy ensures that there will be no problems such as data inconsistency caused by write operations interrupting read operations between different pipelines. For example, the Main Pipe adopts the Set blocking method to avoid related problems; the Replace Pipe and the Main Pipe use mutual blocking strategies to ensure that the Store and Replace of the same address will not exist in both at the same time, thereby ensuring that the reading of the Meta tag and the Tag will not be interrupted by the reading of the Data; the Refill Pipe will be blocked by the Set + Way of the 2nd beat of the Main Pipe when entering, and there will be no situation where the write interrupts the read.

[0074] In the embodiment of the present application, since data cache access address conflicts can be accurately processed, blocking situations caused by conflicts are reduced, thereby improving the parallel processing capability of data cache access address conflicts, and ultimately improving the performance of the processor.

[0075] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. In order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiment disclosed herein, the embodiment of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0076] It should be noted that the device in the embodiment of the present application includes a virtual device and a physical device. The virtual device may be a data cache access device, and the physical device may include an electronic device, a computer storage medium, and a computer program product.

[0077] The data cache access method provided in the embodiment of the present application can be executed by a data cache access device or a control module for data cache access in the data cache access device. In the embodiment of the present application, the data cache access device provided in the embodiment of the present application is described by taking the data cache access device executing the data cache access method as an example.

[0078] It should be noted that the embodiment of the present application can divide the data cache access device into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. Optionally, the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation.

[0079] like Figure 4 As shown, an embodiment of the present application provides a data cache access device 400. The data cache access device 400 includes: an acquisition module 401 and a processing module 402. The acquisition module 401 can be used to acquire an access request; the processing module 402 can be used to use a cache group blocking strategy to make a blocking judgment when the way operated by the access request to the data cache access is not determined; when the way operated by the access request to the data cache access is determined, a cache group blocking strategy and a cache way blocking strategy are used to make a blocking judgment; wherein, the cache group blocking strategy is to block the request if the group address is the same, otherwise the request is not blocked; the cache way blocking strategy is to block the request if the way address is the same, otherwise the request is not blocked.

[0080] Optionally, the above-mentioned processing module 402 can be used to block the access request when the access request enters the main pipeline if the group address of the access request meets a first condition; wherein the first condition includes: the group address of the access request is the same as the group address of the pipeline stage after the main pipeline accesses the data cache tag and label, or the group address of the access request is the same as the group address of the pipeline stage after the replacement pipeline reads the tag and data, or the group address of the access request is the same as the group address of the fill pipeline.

[0081] Optionally, the above-mentioned processing module 402 can be used to block the access request when the access request enters the replacement pipeline to replace the target cache block if the group address of the access request is the same as the group address of the main pipeline access request to access the data cache tag and tag pipeline stage, or is the same as the group address of the pipeline stage after the main pipeline access request to access the data cache tag and tag pipeline stage and is in the same way.

[0082] Optionally, the processing module 402 may be used to block the access request when it enters the fill pipeline if the access request has the same group address and the same path as the main pipeline access request read data pipeline stage.

[0083] Optionally, the processing module 402 may be used to block the access request when the access request enters the memory access failure queue if the access request and any existing item in the memory access failure queue are replacement fills of the same group address and are replacement fills of the same way.

[0084] In the embodiment of the present application, since data cache access address conflicts can be accurately processed, blocking situations caused by conflicts are reduced, thereby improving the parallel processing capability of data cache access address conflicts, and ultimately improving the performance of the processor.

[0085] Figure 5 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 5 As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the data cache access method, the method comprising: obtaining an access request; in the case where the way operated by the access request to the data cache access is not determined, using the cache group blocking strategy to perform blocking judgment; in the case where the way operated by the access request to the data cache access is determined, using the cache group blocking strategy and the cache way blocking strategy to perform blocking judgment; wherein the cache group blocking strategy is to block the request if the group address is the same, otherwise the request is not blocked; the cache way blocking strategy is to block the request if the way address is the same, otherwise the request is not blocked.

[0086] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0087] On the other hand, the present application also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the data cache access method provided by the above methods, which method includes: obtaining an access request; in the case where the way operated by the access request for data cache access is not determined, using a cache group blocking strategy to make a blocking judgment; in the case where the way operated by the access request for data cache access is determined, using a cache group blocking strategy and a cache way blocking strategy to make a blocking judgment; wherein, the cache group blocking strategy is to block the request if the group address is the same, otherwise the request is not blocked; the cache way blocking strategy is to block the request if the way address is the same, otherwise the request is not blocked.

[0088] On the other hand, the present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the data cache access method provided by the above-mentioned methods, the method comprising: obtaining an access request; in the case where the way operated by the access request for the data cache access is not determined, using a cache group blocking strategy to make a blocking judgment; in the case where the way operated by the access request for the data cache access is determined, using a cache group blocking strategy and a cache way blocking strategy to make a blocking judgment; wherein, the cache group blocking strategy is to block the request if the group address is the same, otherwise the request is not blocked; the cache way blocking strategy is to block the request if the way address is the same, otherwise the request is not blocked.

[0089] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0090] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data cache access method, characterized in that: include: Get access request; In the case where the way operated by the access request to the data cache is not determined, a cache group blocking strategy is used to perform blocking judgment; in the case where the way operated by the access request to the data cache is determined, a cache group blocking strategy and a cache way blocking strategy are used to perform blocking judgment; The cache group blocking strategy is to block requests if the group addresses are the same, otherwise the requests are not blocked; the cache way blocking strategy is to block requests if the way addresses are the same, otherwise the requests are not blocked.

2. The data cache access method according to claim 1, characterized in that: The method of using a cache group blocking strategy to perform blocking judgment when the way operated by the access request to the data cache access is not determined; and using a cache group blocking strategy and a cache way blocking strategy to perform blocking judgment when the way operated by the access request to the data cache access is determined, includes: When the access request enters the main pipeline, if the group address of the access request meets the first condition, blocking the access request; Among them, the first condition includes: the group address of the access request is the same as the group address of the pipeline stage after the main pipeline accesses the data cache tag and label, or the group address of the access request is the same as the group address of the pipeline stage after the replacement pipeline reads the tag and data, or the group address of the access request is the same as the group address of the fill pipeline.

3. The data cache access method according to claim 1, characterized in that: The method of using a cache group blocking strategy to perform blocking judgment when the way operated by the access request to the data cache access is not determined; and using a cache group blocking strategy and a cache way blocking strategy to perform blocking judgment when the way operated by the access request to the data cache access is determined, includes: When the access request enters the replacement pipeline to replace the target cache block, if the group address of the access request is the same as the group address of the main pipeline access request to access the data cache tag and tag pipeline stage, or is the same as the group address of the pipeline stage after the main pipeline access request to access the data cache tag and tag pipeline stage and is in the same way, the access request is blocked.

4. The data cache access method according to claim 1, characterized in that: The method of using a cache group blocking strategy to perform blocking judgment when the way operated by the access request to the data cache access is not determined; and using a cache group blocking strategy and a cache way blocking strategy to perform blocking judgment when the way operated by the access request to the data cache access is determined, includes: When the access request enters the fill pipeline, if the access request has the same group address as the main pipeline access request read data pipeline stage and is in the same way, the access request is blocked.

5. The data cache access method according to claim 1, characterized in that: The method of using a cache group blocking strategy to perform blocking judgment when the way operated by the access request to the data cache access is not determined; and using a cache group blocking strategy and a cache way blocking strategy to perform blocking judgment when the way operated by the access request to the data cache access is determined, includes: When the access request enters the memory access failure queue, if the access request and any existing item in the memory access failure queue are replacement fills of the same group address and are replacement fills of the same way, the access request is blocked.

6. A data cache access device, characterized in that: include: Acquisition module and processing module; The acquisition module is used to acquire the access request; The processing module is used to use the cache group blocking strategy to make a blocking judgment when the way operated by the access request to the data cache is not determined; and use the cache group blocking strategy and the cache way blocking strategy to make a blocking judgment when the way operated by the access request to the data cache is determined; The cache group blocking strategy is to block requests if the group addresses are the same, otherwise the requests are not blocked; the cache way blocking strategy is to block requests if the way addresses are the same, otherwise the requests are not blocked.

7. The data cache access device according to claim 6, characterized in that: The processing module is used to block the access request when the access request enters the main pipeline if the group address of the access request meets the first condition; wherein the first condition includes: the group address of the access request is the same as the group address of the pipeline stage after the main pipeline accesses the data cache tag and label, or the group address of the access request is the same as the group address of the pipeline stage after the replacement pipeline reads the tag and data, or the group address of the access request is the same as the group address of the fill pipeline.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the data cache access method according to any one of claims 1 to 5 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data cache access method according to any one of claims 1 to 5 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the data cache access method according to any one of claims 1 to 5 is implemented.

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