A method for dynamic voltage and frequency regulation of a RISC-V processor core

Abstract

This invention relates to a dynamic voltage and frequency adjustment method for a RISC-V processor core. The method includes: monitoring and recording the critical path time of memory access requests for each missing state processing register to update the global critical path counter; monitoring prefetch instructions and extracting their delay parameters; collecting cache access events based on a time window to calculate bandwidth utilization and dynamically determining a bandwidth threshold according to preset performance parameters; and correcting the global critical path counter value by combining the prefetch delay and the bandwidth threshold, thereby triggering a dynamic voltage and frequency adjustment instruction. This method achieves fine-grained adaptive DVFS for the RISC-V processor core under complex loads, significantly improving energy efficiency and performance stability.

Description

Technical Field

[0001] This invention relates to the field of low-power management technology in microprocessor architecture design, specifically to a dynamic voltage and frequency adjustment method for a RISC-V processor core. Background Technology

[0002] In modern high-performance computing scenarios, processors must balance performance and energy efficiency. Dynamic Voltage and Frequency Scaling (DVFS), as a core power control mechanism, dynamically adjusts the processor's operating voltage and frequency to achieve a balance between power consumption and performance. However, the accuracy of DVFS adjustment directly affects the overall system efficiency. Especially in high-load, high-concurrency applications such as AI inference and big data processing, memory access behavior is complex and variable. Traditional DVFS methods often fail to accurately predict memory latency, leading to lagging or over-adjustment, resulting in significant performance loss and energy waste.

[0003] Currently, the mainstream DVFS implementation methods in the industry mainly include the following three categories:

[0004] 1. Cache Miss Rate (MPKI): This method assesses memory access pressure by statistically analyzing the L2 / L3 cache miss rate. When the MPKI exceeds a set threshold, it triggers a frequency reduction operation. This method is simple to implement, but it cannot distinguish the actual latency impact of different types of memory requests.

[0005] 2. Leading Loads: This method estimates memory latency based on the time it takes for the first L2 cache miss and is suitable for processor architectures such as AMD. However, it assumes constant memory access latency and is prone to failure in real-world variable-latency memory systems.

[0006] 3. Stall Time Method: This method directly measures the time the processor pipeline pauses due to memory access and uses this time as a basis for performance tuning. It is commonly used in Intel processor designs. This method requires high precision in hardware monitoring and cannot effectively distinguish the causes of pauses.

[0007] In addition, there are voltage regulation strategies such as Vdd-Hopping and Vdd-Dithering. The former achieves power management by switching discrete voltage levels, while the latter uses a time-sharing strategy to approximate the ideal DVFS effect. However, these methods are all based on the assumption of a linear system model and do not fully consider the complex memory access behavior in actual loads, such as nonlinear factors like instruction prefetching, data prefetching, and memory bandwidth contention.

[0008] Existing technologies suffer from the following drawbacks: Traditional linear models cannot simulate the nonlinear dynamic changes in memory access latency in real-world scenarios. For example, when the CPU performs intensive computational tasks, memory requests may exhibit sub-microsecond bursts, while traditional methods typically use millisecond-level monitoring intervals, causing opportunities for fine-grained adjustments to be missed. Existing methods (such as the initial load method) assume constant memory access latency, but in real systems, instruction prefetching and data prefetching cause dynamic changes in memory access bandwidth, rendering prediction models based on fixed latency ineffective. The voltage switching overhead of a DC-DC converter is typically 4~10μs, while memory operation latency is only a few hundred processor cycles. The existing DVFS management granularity is mismatched with the rapid changes in actual load, resulting in energy waste and performance loss. Although critical path estimation methods (such as CRIT) can identify the impact of a single path, they do not consider the bandwidth competition between multiple concurrent memory access requests, leading to significant prediction bias in high-concurrency scenarios.

[0009] Therefore, how to implement a DVFS performance prediction method in a high-performance RISC-V processor core that can accurately predict memory access latency, adapt to prefetching mechanisms, respond quickly, and handle multiple request conflicts has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0010] This invention provides a dynamic voltage and frequency adjustment method for RISC-V processor cores. Its purpose is to solve the technical problem that existing dynamic voltage and frequency adjustment (DVFS) technology cannot simultaneously optimize processor energy efficiency and performance in high-concurrency, variable-latency memory access scenarios due to inaccurate prediction models, resulting in inaccurate adjustment timing and magnitude.

[0011] To achieve the above objectives, the first aspect of the present invention provides a method for dynamic voltage and frequency adjustment of a RISC-V processor core, comprising the following steps:

[0012] During processor core execution, monitor and record the critical path time of memory access requests processed by each missing state handling register;

[0013] Update the global critical path counter based on the critical path time of each missing state processing register, and obtain the current global critical path counter value.

[0014] Monitor the prefetch instructions issued by the processor core and extract the prefetch delay parameters corresponding to the prefetch instructions;

[0015] Based on a predetermined time window, cache access events are collected, and the bandwidth utilization of the current memory access bandwidth is calculated in real time.

[0016] The current bandwidth threshold is dynamically determined based on the bandwidth utilization rate and preset performance parameters;

[0017] By combining the prefetch delay parameter and the bandwidth threshold, the current global critical path counter value is corrected to obtain the corrected global critical path counter value.

[0018] Based on the corrected global critical path counter value, a corresponding dynamic voltage frequency adjustment command is generated and triggered.

[0019] Furthermore, methods for monitoring and recording the critical path time of memory access requests processed by each missing state handling register include:

[0020] Initialize hardware counters, assign a critical path timestamp to each missing state processing register, and initialize a global critical path counter.

[0021] When a memory access request is allocated to the first When a missing state processing register is processed, the current value of the global critical path counter is copied to the critical path timestamp corresponding to the missing state processing register.

[0022] In the first After each missing status processing register completes the refilling process for the memory access request, it records the actual number of processing cycles.

[0023] Add the critical path timestamp value to the actual number of processing cycles to obtain the estimated completion time of the memory access request;

[0024] Update the value of the global critical path counter to the larger value between the current global critical path counter value and the estimated completion time.

[0025] Furthermore, methods for updating the global critical path counter and obtaining the current global critical path counter value include:

[0026] After updating the global critical path counter for any memory access request processed by the missing state handling register, the global critical path counter value is maintained until the next memory access request triggers an update.

[0027] The value of the global critical path counter maintained at the current moment is obtained as the current global critical path counter value for subsequent correction steps.

[0028] Furthermore, the method for monitoring prefetch instructions issued by the processor core and extracting the prefetch delay parameters corresponding to the prefetch instructions includes:

[0029] The hardware instruction recognizer decodes the opcode of the instructions issued by the processor core.

[0030] When the decoded opcode matches the preset prefetch instruction code, a prefetch flag signal is generated;

[0031] In response to the prefetch flag signal, a delay counter is started, and the delay counter is reset when the prefetch instruction execution begins;

[0032] When the data prefetch operation corresponding to the prefetch instruction is completed, the current value of the delay counter is latched;

[0033] The latched delay counter value is output as the prefetch delay parameter.

[0034] Furthermore, methods for calculating the bandwidth utilization of current memory access bandwidth in real time include:

[0035] Within the predetermined statistical window, the counter of the performance monitoring unit collects the data for the first time. L2 cache hit flags for each cycle;

[0036] At the end of the statistical window, the actual amount of data transmitted within the window is calculated based on the total number of L2 cache hit flags collected and the predicted cache line size.

[0037] Based on the processor's bus width and current clock speed, obtain the theoretical maximum transmission capacity;

[0038] Bandwidth utilization is calculated using the following formula:

[0039]

[0040] in, For bandwidth utilization; This represents the i-th processor cycle within the statistics window; This indicates the total number of processor cycles contained within the statistics window; Indicates the first Whether the L2 cache is hit within a cycle, 1 is the value for a hit, otherwise 0 is the value for a hit; Indicates the size of the cache line; Indicates the scheduled statistical window time; This represents the theoretical maximum transfer capacity of the memory access bus.

[0041] Furthermore, the method for dynamically determining the current bandwidth threshold based on the bandwidth utilization rate and preset performance parameters includes:

[0042] Read the preset bandwidth threshold base value and adjustment coefficient from the chip configuration register of the processor core;

[0043] It can obtain the current processor core performance indicators and the preset theoretical maximum performance indicators in real time from the operating system.

[0044] Calculate the current performance ratio based on the current processor core performance index and the theoretical maximum performance index;

[0045] Based on the baseline bandwidth threshold, the adjustment coefficient, and the current performance ratio, the current bandwidth threshold is calculated and dynamically set using the following formula:

[0046]

[0047] in, This is the current bandwidth threshold; This is the base value for the bandwidth threshold; This is the adjustment coefficient; This refers to the current processor core performance metrics; This is the preset theoretical maximum performance index.

[0048] Furthermore, the method for correcting the current global critical path counter value to obtain the corrected global critical path counter value includes:

[0049] Obtain the extracted prefetch delay parameters and the dynamically determined current bandwidth threshold;

[0050] Calculate the ratio of the prefetch delay parameter to the current bandwidth threshold;

[0051] Based on the aforementioned ratio, perform mathematical operations on the current global critical path counter value;

[0052] The result of the mathematical operation is output as the corrected global critical path counter value.

[0053] Furthermore, the method for generating and triggering the corresponding dynamic voltage frequency adjustment command based on the corrected global critical path counter value includes:

[0054] Compare the corrected global critical path counter value with the preset performance threshold;

[0055] If the corrected global critical path counter value is less than the performance threshold, an upsampling adjustment command is generated;

[0056] If the corrected global critical path counter value is greater than or equal to the performance threshold, an adjustment command is generated to reduce the frequency or maintain the current frequency.

[0057] Furthermore, the current processor core performance metrics are written to a specific register in real time by the operating system, while the theoretical maximum performance metrics are preset in another specific register by the operating system during the initialization phase.

[0058] The beneficial effects of this invention are:

[0059] Compared with existing technologies, this invention provides a dynamic voltage and frequency adjustment method for RISC-V processor cores. By adding a prefetch latency monitoring module to the traditional critical path tracing method, it extracts the latency parameters of prefetch instructions in real time, thereby accurately characterizing the dynamic impact of instruction / data prefetching on memory access bandwidth and overcoming the failure problem of traditional linear models in prefetch scenarios. Secondly, it uses a hardware counter to collect L2 cache hit events in real time at microsecond-level windows and calculates bandwidth utilization. Combined with performance parameters fed back by the operating system, it dynamically adjusts the bandwidth threshold, achieving instantaneous perception of the system's memory access status. Based on this, it combines the prefetch latency parameters with the real-time bandwidth threshold to dynamically correct the global critical path counter (Pglobal), thereby accurately distinguishing the critical path contribution when multiple memory access requests are concurrent, avoiding prediction bias caused by bandwidth contention. Finally, based on the corrected Pglobal value, it triggers DVFS instructions at the microsecond granularity, enabling voltage and frequency adjustment to closely follow sudden changes in load. This significantly improves the processor's energy efficiency and performance balance while reducing adjustment lag and over-adjustment in high-concurrency memory access scenarios. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0061] Figure 1 This is a flowchart of a dynamic voltage and frequency adjustment method for a RISC-V processor core disclosed in an embodiment of the present invention.

[0062] Figure 2 This is a diagram of a variable-length memory access model for an out-of-order execution processor core disclosed in an embodiment of the present invention.

[0063] Figure 3 This is a schematic diagram of a processor core dynamic voltage and frequency adjustment system disclosed in an embodiment of the present invention. Detailed Implementation

[0064] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0065] According to embodiments of the present invention, it should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the following methods, in some cases the steps shown or described may be executed in a different order than that shown here.

[0066] like Figure 1 As shown, this invention provides a dynamic voltage and frequency adjustment method for a RISC-V processor core, the method comprising:

[0067] Step S100: During the execution of the processor core, monitor and record the critical path time of memory access requests processed by each missing state processing register;

[0068] Missing Status Registers (MSHRs) are hardware queue structures in the processor's memory subsystem used to manage and track memory access instructions that require data requests to higher-level caches or main memory due to cache misses. This step is based on the estimation algorithm of the "Critical Path Through Memory Requests" (CRIT). In an out-of-order processor, multiple incomplete memory access requests may have dependencies, and the longest sequence of requests constitutes the "critical path" affecting the overall program execution progress. Its latency (i.e., critical path time) is a key indicator for determining the processor's current performance bottleneck and making power consumption adjustment decisions.

[0069] In practice, initialization first needs to be performed at the hardware level: allocating a local critical path timestamp (denoted as ) to each MSHR unit within the processor core. ,in Representing the Each MSHR is initialized, and a global critical path counter (denoted as Pglobal) is also initialized. The global critical path counter is cleared after system power-on or reset. When a memory access request is generated and assigned to a specific MSHR for processing, the CRIT mechanism immediately copies the current value of Pglobal to the local timestamp corresponding to that MSHR. This is used to record the "start time" when the request enters the processing queue.

[0070] Subsequently, the MSHR (Memory Controller Receiver) initiates a request to the memory controller and waits for the data to be returned (i.e., "refill"). After several processor clock cycles, when the requested data is returned and refilling is complete, the system records the actual number of cycles consumed from the time the request entered the MSHR to its completion. .

[0071] Next, the estimated completion time for the request is calculated. Finally, the global state is updated by comparison: the current value of Pglobal is updated to its original value plus the calculated estimated completion time. The larger of the two, i.e.:

[0072]

[0073] By continuously performing the above operation on each memory access request entering the MSHR, the value of Pglobal is dynamically maintained as the time estimate of the path with the longest cumulative latency among all processed memory access requests in the critical path. Therefore, the step of "monitoring and recording the critical path time of each memory access request processed by the MSHR" is essentially achieved through the aforementioned hardware counter ( This is achieved through the collaborative operation and continuous updating of Pglobal, and the final real-time representation of the "critical path time" is the current value of Pglobal. For example... Figure 2 The out-of-order execution processor variable-length memory access model shown in the diagram allows the CRIT method to identify the key memory access request sequences and their timings that affect performance.

[0074] Step S200: Update the global critical path counter according to the critical path time of each missing state processing register, and obtain the current global critical path counter value;

[0075] Specifically, this step is implemented as a dynamic, iterative process. Whenever a memory access request tracked by the MSHR (e.g., data refilling after a cache miss) completes, the hardware logic associated with that MSHR triggers a potential update to the global critical path counter. The update logic follows a maximization principle: it modifies the current Pglobal value with the "estimated completion time" calculated for the just-completed memory access request (i.e., the local critical path timestamp corresponding to that request). In addition to its actual processing cycle number The two values ​​are compared, and Pglobal is updated to the larger value. This operation is performed in hardware by a circuit consisting of a comparator and a multiplexer within one clock cycle, i.e.: In this way, the value of Pglobal is always maintained as the time length of the longest path in all observed chains of memory access requests with dependencies.

[0076] Pglobal is typically stored in a dedicated hardware register. Therefore, the "fetch" operation essentially involves directly reading its latest value from this register when input is needed for subsequent decisions (such as the correction in step S600). Since Pglobal updates occur immediately upon completion of each MSHR request, the read value is the latest critical path time estimate calculated in real-time by the system based on historical memory access events. This value serves as the basis for subsequent performance prediction and Dynamic Voltage-to-Frequency Regulating (DVFS) decisions, reflecting the critical latency bottleneck currently faced by the processor core, determined by the memory subsystem performance. The entire update and fetch process is automated by hardware without software intervention, ensuring extremely low latency and the ability to achieve fine-grained management.

[0077] Step S300: Monitor the prefetch instructions issued by the processor core and extract the prefetch delay parameters corresponding to the prefetch instructions;

[0078] Prefetching is a special instruction used by processors to load data from lower-level memory (such as main memory) into a cache (such as L2 cache) before it is actually accessed, in order to improve performance. However, prefetching itself consumes memory bandwidth and can introduce latency. Traditional DVFS methods often ignore this impact, leading to prediction bias. This step aims to quantify this impact, providing crucial input for subsequent accurate corrections.

[0079] The specific implementation utilizes a dedicated hardware circuitry called the "Prefetch Delay Monitoring Module." This module primarily comprises two components: an instruction recognizer and a delay counter. First, the instruction recognizer continuously monitors the opcodes of instructions issued by the processor core. Internally, it includes a decoder and a matching circuit that pre-stores specific prefetch instruction codes. When a passing instruction opcode matches these pre-stored codes, the recognizer immediately outputs a high-level 'Prefetch_Flag' signal, indicating the start of a prefetch operation.

[0080] Subsequently, the flag signal triggers the delay counter to start operating. The delay counter is a high-precision synchronous timing hardware device, consisting of a 32-bit counter and a latching flip-flop. The delay counter activates at the instant the 'Prefetch_Flag' signal becomes valid (i.e., the prefetch instruction begins execution) (denoted as...). At a certain time (i.e.), the counter is reset to zero. Afterward, the counter begins counting at a pace completely synchronized with the processor core's main clock. A completion signal is generated when the prefetch operation is complete and the requested data block is sent to the target cache. This signal is received at a certain time (denoted as ). At the specified moment, the counter immediately stops counting and latches and outputs its current count value via a flip-flop. This latched value represents the number of processor clock cycles elapsed from the issuance of the prefetch instruction to the completion of data prefetching. Multiplying this value by the clock cycle converts it into a prefetch delay parameter in time. .

[0081] Ultimately, the module outputs The value is a real-time, dynamic measurement that directly reflects the actual time consumed by a single prefetch operation under the current system load and bandwidth contention environment. This parameter will be fed into subsequent correction algorithms to accurately assess the impact of prefetching behavior on the overall critical path of memory access, thereby overcoming the shortcomings of traditional methods that assume constant memory access latency or ignore the impact of prefetching. The entire monitoring and extraction process is completed fully automatically by hardware, achieving nanosecond-level real-time performance and meeting the stringent requirements for DVFS adjustment accuracy in high-performance computing scenarios.

[0082] Step S400: Based on a predetermined time window, collect cache access events and calculate the bandwidth utilization of the current memory access bandwidth in real time;

[0083] Traditional DVFS methods often ignore or simplify the impact of bandwidth contention, while this step provides a precise data basis for subsequent dynamic adjustment of bandwidth thresholds (step S500) and correction of critical path time (step S600) through real-time hardware-level measurement.

[0084] The specific implementation relies on the performance monitoring unit (PMU) integrated within the processor core and dedicated computing circuitry. First, a fixed statistical time window is set ( For example, a window of 50 nanoseconds (ns) is controlled and periodically triggered by a high-precision hardware timer. During this window, a dedicated PMU hardware counter continuously operates, sampling and recording the L2 cache (Level 2 cache) hit status each processor clock cycle. A "hits" occur each time a memory access request finds the required data in the L2 cache. The counter records a flag during that cycle (e.g., setting...). Recorded as 1 if a cache miss is not recorded as 0. When the 50ns statistical window ends, the hardware timer triggers a read signal. At this time, the system first reads the total number of L2 cache hits accumulated within the window, and then combines this with the known cache line size ( The basic unit of data exchange in the buffer is 64 bytes, which is the basic unit of data exchange. The actual amount of data transferred within this window is calculated using the following formula:

[0085] Actual data transmitted = total number of hits × 64 bytes

[0086] At the same time, the system needs to obtain the theoretical maximum transmission capacity of the memory access channel ( This value is determined by the processor chip's physical design and is equal to the product of the data bus width (e.g., 64 bits, or 8 bytes) and the current operating clock speed (e.g., 2 GHz). These parameters (bus width, current clock speed) can be read in real-time from the chip's configuration registers. According to the example, = 8 bytes / time × 2 × 10^9 times / second = 16 GB / s.

[0087] Ultimately, bandwidth utilization ( The value is calculated in real time using a hardware division circuit (or an optimized computing unit). The calculation formula is shown below, where the numerator is the actual amount of data transmitted within the window, and the denominator is the amount of data that the theoretical maximum transmission capacity can handle within the same window time:

[0088]

[0089] in, For bandwidth utilization; This represents the i-th processor cycle within the statistics window; This indicates the total number of processor cycles contained within the statistics window; For the first L2 cache hit flag (0 or 1) for each cycle; This is the cache line size, typically 64 bytes; To achieve the statistical window time (e.g., 50ns), a hardware timer is used. The theoretical maximum transmission capacity = bus width × clock frequency.

[0090] Calculation results This is a value between 0 and 1 (or between 0% and 100%), which directly represents the current memory access bandwidth utilization. For example, if 35 L2 cache hits are recorded within a 50ns window, the actual amount of data transferred is 35 × 64 bytes = 2240 bytes, and the theoretical maximum data transfer amount is 16GB / s × 50ns = 800 bytes. The bandwidth utilization can then be calculated. (Or 280%, indicating that in sudden scenarios, actual demand may instantly exceed the theoretical steady-state bandwidth, revealing the pressure of bandwidth competition). The entire measurement and calculation process is automatically completed by hardware in microseconds, realizing fine-grained, low-overhead real-time monitoring of memory access bandwidth status.

[0091] Step S500: Dynamically determine the current bandwidth threshold based on the bandwidth utilization rate and preset performance parameters;

[0092] During the initialization configuration phase, two preset static parameters are read from the processor core's chip configuration register: one is the base value of the bandwidth threshold ( The first value is preset based on the chip's physical design (such as bus architecture and typical operating frequency); the second is the adjustment coefficient. This is a configurable parameter between 0.2 and 0.5 used to control the sensitivity of the threshold to performance changes. Its specific value can be determined during chip design or system startup based on the target application scenario (such as AI inference, general computing).

[0093] During the dynamic adjustment phase at runtime, the following operations are continuously performed:

[0094] First, obtain the current processor core performance metrics fed back by the operating system (OS) in real time. This metric is a value reflecting the instantaneous performance level calculated by the operating system kernel based on scheduling information, task progress, etc., and is periodically written to a specific register agreed upon with the hardware. Simultaneously, it reads the theoretical maximum performance metric preset by the operating system during the initialization phase from another specific register. This value represents the upper limit of the system's performance under ideal, bottleneck-free conditions. Next, the current performance ratio is calculated, i.e. Finally, calculate and update the current bandwidth threshold using the following formula:

[0095]

[0096] in, This is the current bandwidth threshold; This is the base value for the bandwidth threshold; This is the adjustment coefficient; This refers to the current processor core performance metrics; This is the preset theoretical maximum performance index.

[0097] For example, in AI inference scenarios, the base value is 8 GB / s. The threshold is set to 0.3. When the current performance reaches 92% of the theoretical maximum performance (i.e., a ratio of 0.92), the calculated dynamic threshold is approximately 8 × (1 + 0.3 × 0.92) ≈ 10.2 GB / s. This adjustment allows the threshold to increase accordingly when performance demands are high, more accurately reflecting the upper limit of the system's tolerable bandwidth pressure. The entire dynamic determination process is executed periodically by the hardware logic and works in conjunction with the operating system's performance management module to ensure that the threshold always matches the global load state.

[0098] Step S600: Combine the prefetch delay parameter and the bandwidth threshold to correct the current global critical path counter value to obtain the corrected global critical path counter value;

[0099] The prefetch delay parameters obtained in step S300 and the current bandwidth threshold dynamically determined in step S500 In combination, the current global critical path counter value Pglobal obtained in step S200 is corrected in real time, thereby obtaining a corrected global critical path counter value that more accurately reflects the true performance of the system. This step aims to address the shortcomings of traditional CRIT methods and existing DVFS prediction techniques in effectively handling dynamic memory bandwidth contention caused by instruction / data prefetching, as well as the biases in critical path estimation caused by conflicts between multiple concurrent memory access requests.

[0100] This embodiment is accomplished through a correction calculation unit, which receives three inputs: 1) the uncorrected Pglobal value (representing the critical path time estimated solely based on memory access request dependencies); 2) the prefetch latency obtained from real-time monitoring. (Represents the actual time cost of the most recent prefetch operation or within a certain period); 3) Dynamically updated bandwidth threshold (This represents the upper limit of bandwidth that can be effectively utilized under the current system load). The correction algorithm is implemented in hardware using multiplier, divider, and subtractor circuits:

[0101]

[0102] The following explains the operations in the formula and their physical meaning:

[0103] Proportion calculation ( This part calculates the prefetch delay. The ratio to the system's current available bandwidth capacity (a threshold normalized to time). The unit is usually time (such as nanosecond), while The unit is data transfer rate (e.g., GB / s). To perform the division, the bandwidth threshold needs to be converted to an equivalent "time capacity" reference value in the hardware implementation, or the ratio needs to be dimensionless through unit conversion. Its physical meaning is to evaluate the proportion of time resources consumed by a single prefetch operation to the system's currently allowed bandwidth time resources. The larger the ratio, the greater the bandwidth contention pressure from the prefetch operation, and the more significant the "drag" effect on the overall critical path.

[0104] Correction factor calculation (1 - ratio): Subtract the above ratio from 1 to obtain a new correction factor. When the prefetch latency is small relative to the bandwidth threshold (the ratio approaches 0), the correction factor approaches 1, meaning that prefetching has little impact on the critical path and almost no correction is needed. Conversely, when the prefetch latency is large or the bandwidth threshold is tight (the ratio increases), the correction factor will decrease.

[0105] Final correction (Pglobal × correction factor): Multiply the original Pglobal by this correction factor to obtain the corrected value. The effect is that when there is significant bandwidth contention caused by prefetching in the system, the algorithm dynamically lowers the estimate of the critical path time. This is because the original CRIT estimate of Pglobal may include waiting time that is "artificially" lengthened due to bandwidth contention, and this correction aims to remove this part of the latency caused by resource contention (rather than actual memory access latency), thereby more accurately predicting the computational performance potential of the processor core itself.

[0106] For example, in AI inference tasks, when encountering dense convolutional layers, the original value of Pglobal is updated to 10.7ns, which is measured... =7.8ns, dynamic bandwidth threshold adjusted to 10.2 GB / s (after conversion or normalization for calculation). Corrected according to the formula:

[0107]

[0108] The significant reduction from 10.7ns to 2.5ns indicates that the system has identified the current performance bottleneck primarily as stemming from bursts of bandwidth consumption and contention caused by prefetch requests, rather than absolute latency in the processor core computing units or memory itself. The revised value (2.5ns) will serve as a more reliable basis for subsequent DVFS decisions. The entire correction process was pipelined in hardware with extremely low latency, achieving microsecond-level adaptive optimization for critical path prediction and significantly improving the foresight and accuracy of DVFS tuning.

[0109] Step S700: Generate and trigger the corresponding dynamic voltage frequency adjustment command based on the corrected global critical path counter value.

[0110] The corrected global critical path counter value calculated in step S600 ( It generates and triggers corresponding Dynamic Voltage and Frequency Scaling (DVFS) instructions in real time, thereby achieving precise control over the processor core operating voltage and clock frequency, and ultimately achieving the optimal balance between performance and power consumption.

[0111] Specifically, this is implemented through the DVFS decision logic unit. This DVFS decision logic unit first receives data from the correction calculation unit. The unit internally stores or connects to a register that stores a preset performance threshold (e.g., 3.0 nanoseconds). This preset performance threshold represents the target memory access critical path latency set by the system designer or operating system and intended to be maintained. If the actual latency is lower than this target, it indicates that the memory subsystem is not currently the bottleneck, and the processor has the potential to run at a higher frequency to improve performance; conversely, it indicates that memory access has become the bottleneck, increasing the frequency has limited benefits, and the frequency should be reduced to save power.

[0112] The decision-making logic is very simple and efficient: it is accomplished by a digital comparator. This comparator compares Pglobal_adjusted with a preset performance threshold in real time and generates corresponding control codes within one or several clock cycles based on the comparison result.

[0113] if A value below the performance threshold indicates that the estimated critical memory access path latency is lower than expected, the memory subsystem is under less pressure, and the processor core's computing power is not being fully utilized. Therefore, the decision logic will generate a frequency increase instruction. This instruction specifies a frequency increase amount, such as "20% increase." This aims to increase the clock speed and unlock potential performance.

[0114] if A latency greater than or equal to the performance threshold indicates that the current critical memory access path latency has reached or exceeded the tolerance limit, making memory access the primary bottleneck. At this point, further increasing the processor frequency will have little effect on improving overall performance and will instead linearly increase dynamic power consumption. Therefore, the decision logic will generate either a frequency reduction instruction or an instruction to maintain the current frequency. The frequency reduction instruction aims to reduce power consumption, while the maintenance instruction is suitable when the current frequency is already within a reasonable range.

[0115] The generated DVFS adjustment instructions (containing specific parameters for boosting, downscaling, or holding) are immediately sent to the processor core's Clock and Power Management Unit (P-unit). This P-unit is the hardware controller responsible for executing voltage and frequency switching. Instruction triggering is automated in hardware, creating a closed loop from performance monitoring to adjustment action with extremely low latency. By reducing the granularity of DVFS management from milliseconds in traditional methods to microseconds based on MSHR status monitoring, this approach enables instantaneous adjustment in scenarios with sudden load changes, such as AI inference, thereby effectively reducing energy waste while avoiding performance loss.

[0116] In summary, step S700 will provide an accurate performance prediction ( This is transformed into direct energy efficiency optimization actions. Through rapid hardware decision-making and triggering, the entire chain from "prediction" to "control" in this method is completed, realizing fine-grained, adaptive dynamic voltage and frequency adjustment of high-performance RISC-V processor cores under complex loads.

[0117] Understandably, this invention, by introducing the CRIT+ extension mechanism, integrates real-time prefetch latency monitoring and dynamic bandwidth utilization analysis on the basis of traditional critical path tracing methods. It can accurately characterize the instantaneous impact of instruction / data prefetching on memory access bandwidth, and achieve dynamic correction of the global critical path counter value through adaptive adjustment of bandwidth threshold and optimization of multi-request conflicts. This generates precise DVFS adjustment instructions at the microsecond level, significantly improving the response speed and prediction accuracy of dynamic voltage and frequency adjustment in high-concurrency, variable-latency memory access scenarios. It effectively solves the problems of adjustment lag and energy efficiency imbalance caused by ignoring prefetch behavior and bandwidth contention in existing technologies. Ultimately, it realizes fine-grained, adaptive dynamic voltage and frequency adjustment of high-performance RISC-V processor cores under complex loads, greatly improving the system's energy efficiency ratio and performance stability. It is especially suitable for application scenarios with highly dynamic changes in memory access behavior, such as AI inference and big data processing.

[0118] To achieve the aforementioned precise CRIT+ extension mechanism, the system architecture of this invention is as follows: Figure 3 As shown in the diagram, this architecture integrates a prefetch latency monitoring module and a bandwidth utilization calculation unit on the data path of a traditional processor core. The prefetch latency monitoring module captures prefetch instructions in real time through an instruction recognizer and extracts the prefetch latency parameter τ using a high-precision latency counter. The bandwidth utilization calculation unit calculates the current memory access bandwidth utilization in real time based on L2 cache hit events collected by the performance monitoring unit (PMU) within a microsecond-level time window, combined with bus width and clock frequency parameters. The prefetch latency parameter and bandwidth threshold obtained by the above hardware modules are input to the CRIT+ correction unit, which performs nonlinear correction on the global critical path counter Pglobal, dynamically maintained by the Missing State Processing Register (MSHR), ultimately generating accurate DVFS adjustment instructions. Through this tightly coupled hardware collaborative architecture, this invention achieves full hardware closed-loop control from memory access behavior perception and critical path prediction to voltage and frequency adjustment, ensuring the efficiency and accuracy of adjustment decisions under complex concurrent loads, thereby providing stable and adaptive energy efficiency optimization guarantees for high-performance RISC-V processor cores at the hardware level.

[0119] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0121] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0122] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0123] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for dynamic voltage and frequency adjustment of a RISC-V processor core, characterized in that, Includes the following steps: During the execution of the processor core, the critical path time of the memory access requests processed by each missing state processing register is monitored and recorded. The critical path time is the critical path time that affects the overall program execution progress, which consists of a series of requests with the longest time consumption among multiple incomplete memory access requests that have a dependency relationship. Update the global critical path counter based on the critical path time of each missing state processing register, and obtain the current global critical path counter value. Monitor the prefetch instructions issued by the processor core and extract the prefetch delay parameters corresponding to the prefetch instructions; Based on a predetermined time window, cache access events are collected, and the bandwidth utilization of the current memory access bandwidth is calculated in real time. The current bandwidth threshold is dynamically determined based on the bandwidth utilization rate and preset performance parameters; By combining the prefetch delay parameter and the bandwidth threshold, the current global critical path counter value is corrected to obtain the corrected global critical path counter value. Based on the corrected global critical path counter value, a corresponding dynamic voltage frequency adjustment command is generated and triggered.

2. The dynamic voltage and frequency adjustment method for a RISC-V processor core as described in claim 1, characterized in that, Methods for monitoring and recording the critical path time of memory access requests processed by each missing state handling register include: Initialize hardware counters, assign a critical path timestamp to each missing state processing register, and initialize a global critical path counter. When a memory access request is allocated to the first When a missing state processing register is processed, the current value of the global critical path counter is copied to the critical path timestamp corresponding to the missing state processing register. In the first After each missing status processing register completes the refilling process for the memory access request, it records the actual number of processing cycles. Add the critical path timestamp value to the actual number of processing cycles to obtain the estimated completion time of the memory access request; Update the value of the global critical path counter to the larger value between the current global critical path counter value and the estimated completion time.

3. The dynamic voltage and frequency adjustment method for a RISC-V processor core as described in claim 2, characterized in that, Methods for updating the global critical path counter and obtaining the current global critical path counter value include: After updating the global critical path counter for any memory access request processed by the missing state handling register, the global critical path counter value is maintained until the next memory access request triggers an update. The value of the global critical path counter maintained at the current moment is obtained as the current global critical path counter value for subsequent correction steps.

4. The dynamic voltage and frequency adjustment method for a RISC-V processor core as described in claim 1, characterized in that, A method for monitoring prefetch instructions issued by the processor core and extracting the prefetch delay parameters corresponding to the prefetch instructions includes: The hardware instruction recognizer decodes the opcode of the instructions issued by the processor core. When the decoded opcode matches the preset prefetch instruction code, a prefetch flag signal is generated; In response to the prefetch flag signal, a delay counter is started, and the delay counter is reset when the prefetch instruction execution begins; When the data prefetch operation corresponding to the prefetch instruction is completed, the current value of the delay counter is latched; The latched delay counter value is output as the prefetch delay parameter.

5. The dynamic voltage and frequency adjustment method for a RISC-V processor core as described in claim 1, characterized in that, Methods for calculating the bandwidth utilization of current memory access bandwidth in real time include: Within the predetermined statistical window, the counter of the performance monitoring unit collects the data for the first time. L2 cache hit flags for each cycle; At the end of the statistical window, the actual amount of data transmitted within the window is calculated based on the total number of L2 cache hit flags collected and the predicted cache line size. Based on the processor's bus width and current clock speed, obtain the theoretical maximum transmission capacity; Bandwidth utilization is calculated using the following formula: in, For bandwidth utilization; This represents the i-th processor cycle within the statistics window; This indicates the total number of processor cycles contained within the statistics window; Indicates the first Whether the L2 cache is hit within a cycle, 1 is the value for a hit, otherwise 0 is the value for a hit; Indicates the size of the cache line; Indicates the scheduled statistical window time; This represents the theoretical maximum transfer capacity of the memory access bus.

6. The dynamic voltage and frequency adjustment method for a RISC-V processor core as described in claim 1, characterized in that, The method for dynamically determining the current bandwidth threshold based on the bandwidth utilization and preset performance parameters includes: Read the preset bandwidth threshold base value and adjustment coefficient from the chip configuration register of the processor core; It can obtain the current processor core performance indicators and the preset theoretical maximum performance indicators in real time from the operating system. Calculate the current performance ratio based on the current processor core performance index and the theoretical maximum performance index; Based on the baseline bandwidth threshold, the adjustment coefficient, and the current performance ratio, the current bandwidth threshold is calculated and dynamically set using the following formula: in, This is the current bandwidth threshold; This is the base value for the bandwidth threshold; This is the adjustment coefficient; This refers to the current processor core performance metrics; This is the preset theoretical maximum performance index.

7. The dynamic voltage and frequency adjustment method for a RISC-V processor core as described in claim 1, characterized in that, The method for correcting the current global critical path counter value to obtain the corrected global critical path counter value includes: Obtain the extracted prefetch delay parameters and the dynamically determined current bandwidth threshold; Calculate the ratio of the prefetch delay parameter to the current bandwidth threshold; Based on the aforementioned ratio, perform mathematical operations on the current global critical path counter value; The result of the mathematical operation is output as the corrected global critical path counter value.

8. The dynamic voltage and frequency adjustment method for a RISC-V processor core as described in claim 1, characterized in that, The method for generating and triggering the corresponding dynamic voltage frequency adjustment command based on the corrected global critical path counter value includes: Compare the corrected global critical path counter value with the preset performance threshold; If the corrected global critical path counter value is less than the performance threshold, an upsampling adjustment command is generated; If the corrected global critical path counter value is greater than or equal to the performance threshold, an adjustment command is generated to reduce the frequency or maintain the current frequency.

9. The dynamic voltage and frequency adjustment method for a RISC-V processor core as described in claim 6, characterized in that, The current processor core performance metrics are written to a specific register in real time by the operating system, while the theoretical maximum performance metrics are preset in another specific register by the operating system during the initialization phase.

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