Compiling control method and device, medium and electronic equipment

Abstract

The invention provides a compiling control method and device, a medium and electronic equipment. The compiling control method comprises the steps of obtaining a to-be-compiled project; performing FPGA compiling on the to-be-compiled project to obtain a bit stream file of the to-be-compiled project; obtaining a tcl script based on the N preset comprehensive strategies and the M preset implementation strategies; performing parallel running processing on the preset comprehensive strategy based on the tcl script to obtain a comprehensive dcp file of the preset comprehensive strategy; performing parallel operation processing on the preset implementation strategy based on a comprehensive netlist in the comprehensive dcp file to obtain a time sequence result associated with the preset implementation strategy; and terminating the operation of the preset implementation strategy, otherwise, continuing to operate the preset implementation strategy until the implementation dcp file is obtained after the operation of the preset implementation strategy is completed. According to the compiling control method, the time sequence convergence efficiency of the FPGA can be improved, the iteration speed of engineering development is greatly increased, and the debugging efficiency of the engineering development is improved.

Description

Technical Field

[0001] The present application belongs to the field of FPGA engineering and relates to a compilation control method, and in particular to a compilation control method, device, medium and electronic equipment. Background Art

[0002] FPGA (Field Programmable Gate Array) is a programmable logic device. Due to its high flexibility and reconfigurability, it is widely used in various engineering fields. As the scale of FPGA design becomes larger and the design logic becomes more complex, the timing convergence problem of FPGA engineering has become more and more difficult and has become an increasingly greater challenge. Taking the widely used Xilinx XCVU9P-FLGA2104 as an example, its logic unit can reach the million level. When the FPGA resources are only used to about 30%, the timing convergence has become more difficult. In general projects, the FPGA resources are used to 70%-80% to be considered appropriate for FPGA selection, without causing resource waste. In this case, the timing convergence of FPGA will be a great challenge. Since FPGA needs to be repeatedly modified and debugged in the actual project development process, whether the timing convergence bit file can be quickly generated to accelerate the iteration of FPGA design has become the key to whether the project can be delivered on time.

[0003] When the design is very complex and difficult to achieve timing convergence, it is a common practice to traverse various strategies to produce the best result. When the actual compilation project generates a bitstream, the number of strategies that can be selected is limited by the compilation server. For example, if the server is configured with 16 cores / 128G RAM (Random Access Memory), and the resources are used at about 30%, the compilation of 8 strategies is run at the same time, and the comprehensive implementation time is about 6-8 hours. When more resources are used normally, the entire compilation process will be slower, so only a few strategies can be implemented in a day, and it may take several days to compile a bitstream file that can be used with timing convergence, so it has a great impact on the progress of project development and debugging. Therefore, the current compilation control method has the problem of low timing convergence efficiency. Summary of the invention

[0004] The purpose of the present application is to provide a compilation control method, device, medium and electronic device, which are used to solve the problem of low timing convergence efficiency existing in the current compilation control method.

[0005] In a first aspect, the present application provides a compilation control method, comprising: obtaining a project to be compiled; performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled, wherein during the FPGA compilation process of the project to be compiled: obtaining a tool command language tcl (tool command language) script based on N preset synthesis strategies and M preset implementation strategies, the preset synthesis strategy and the preset implementation strategy are used to solve the timing problem of the project to be compiled during the FPGA compilation process, and N and M are both positive integers; based on the tcl script, the preset synthesis strategy is run in parallel to obtain a synthesis design checkpoint dcp (design check point) file of the preset synthesis strategy; based on the synthesis netlist in the synthesis dcp file, the preset implementation strategy is run in parallel to obtain a timing result associated with the preset implementation strategy; if the timing result is less than a preset timing result threshold, the preset implementation strategy is terminated, otherwise the preset implementation strategy is continued to be run until the implementation dcp file is obtained after the preset implementation strategy is run.

[0006] In the compilation control method, by controlling whether the preset implementation strategy is running according to the timing results associated with the preset implementation strategy, it is possible to avoid wasting more time on strategies that are not suitable for this design. More strategies can be traversed within a given time, thereby obtaining the bitstream file faster, improving the timing convergence efficiency of the FPGA, greatly accelerating the iteration speed of engineering development, and improving the engineering development debugging efficiency.

[0007] In one embodiment of the present application, a method for implementing FPGA compilation of the project to be compiled to obtain a bitstream file of the project to be compiled includes: performing a timed detection on the project to be compiled based on a default path, a preset number of times, and a preset periodic interval of the project to be compiled to obtain a detection result; and based on the detection result, performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0008] In one embodiment of the present application, the detection result is that the version of the project to be compiled has changed or the version of the project to be compiled has not changed. Based on the detection result, FPGA compilation is performed on the project to be compiled to obtain a bitstream file of the project to be compiled: when the detection result is that the version of the project to be compiled has changed, FPGA compilation is performed on the project to be compiled to obtain a bitstream file of the project to be compiled; when the detection result is that the version of the project to be compiled has not changed, FPGA compilation is not performed on the project to be compiled.

[0009] In one embodiment of the present application, the preset implementation strategy includes an optimization design Opt Design (Optimization Design) stage, a layout design Place Design (Placement Design) stage and a routing design Route Design (Routing Design) stage, and the timing results associated with the preset implementation strategy include the timing results of the Opt Design stage, the timing results of the Place Design stage and the timing results of the Route Design stage. If the timing result is less than a preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise the preset implementation strategy is continued to be run. The implementation method of the preset implementation strategy includes: if the timing result of the Opt Design stage is less than a first preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise the preset implementation strategy is continued to be run; if the timing result of the Place Design stage is less than a second preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise the preset implementation strategy is continued to be run; if the timing result of the Route Design stage is less than a third preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise the preset implementation strategy is continued to be run.

[0010] In one embodiment of the present application, the implementation method of continuing to run the preset implementation strategy until obtaining the implementation DCP file after the preset implementation strategy is completed includes: performing a timing check on the preset implementation strategy after the preset implementation strategy is completed to obtain a timing check result; if the timing check result meets the requirements, obtaining the implementation DCP file, otherwise not obtaining the implementation DCP file.

[0011] In one embodiment of the present application, the preset implementation strategy is executed in parallel based on the integrated netlist in the integrated DCP file to obtain the timing result associated with the preset implementation strategy. The implementation method includes: executing the preset implementation strategy in parallel based on the integrated netlist in the integrated DCP file to obtain the worst negative timing margin WNS (worst negative slack) timing result and the total negative timing margin TNS (total negative slack) timing result associated with the preset implementation strategy.

[0012] In one embodiment of the present application, the compilation control method further includes: after the bitstream file is generated, automatically generating a report through a notifier; and automatically pushing the report to a user through a tool api (Application Programming Interface).

[0013] In a second aspect, the present application provides a compilation control device, which includes: a project acquisition module, which is used to acquire a project to be compiled and check whether the project to be compiled has a version update change; a project compilation module, which is used to perform FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled; a script acquisition module, which is used to acquire a tcl script based on N preset synthesis strategies and M preset implementation strategies, wherein the synthesis strategy and the implementation strategy are used to solve the timing problem of the project to be compiled during the FPGA compilation process, and N and M are both positive integers; a synthesis strategy running module, which is used to perform parallel operation processing on the preset synthesis strategy based on the tcl script to obtain a comprehensive dcp file of the preset synthesis strategy; an implementation strategy running module, which is used to perform parallel operation processing on the preset implementation strategy based on the synthesis netlist in the comprehensive dcp file to obtain the timing result associated with the preset implementation strategy; and an implementation dcp bitstream file acquisition module, which is used to terminate the operation of the preset implementation strategy if the timing result is less than a preset timing result threshold, otherwise continue to run the preset implementation strategy until the implementation dcp file is obtained after the preset implementation strategy is completed.

[0014] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the compilation control method described in any one of the first aspects of the present application.

[0015] In a fourth aspect, the present application provides an electronic device, comprising: a memory storing a computer program; a processor communicating with the memory, and executing the compilation control method described in any one of the first aspects of the present application when calling the computer program.

[0016] As described above, the compilation control method, device, medium and electronic device of the present application have the following beneficial effects:

[0017] In the compilation control method, by controlling whether the preset implementation strategy is running according to the timing results associated with the preset implementation strategy, it is possible to avoid wasting too much time on strategies that are not suitable for this design. More strategies can be traversed within a given time, thereby obtaining the bitstream file faster, improving the timing convergence efficiency of the FPGA, greatly accelerating the iteration speed of engineering development, and improving the engineering development debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a schematic diagram of the hardware structure of running the compilation control method according to an embodiment of the present application.

[0019] Figure 2Shown is a flowchart of the compilation control method of an embodiment of the present application.

[0020] Figure 3 Shown is a schematic diagram of the integrated strategy provided by Vivado in the embodiment of the present application.

[0021] Figure 4 Shown is a schematic diagram of the implementation strategy provided by Vivado in the embodiment of the present application.

[0022] Figure 5 Shown is a flowchart of an implementation method of the present application for performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0023] Figure 6 Shown is a flowchart of an implementation method of the present application for performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0024] Figure 7 Shown is a flowchart of an implementation method of the present application that terminates the execution of the preset implementation strategy, otherwise continues to execute the preset implementation strategy.

[0025] Figure 8 It shows a flowchart of an embodiment of the present application in which the preset implementation strategy continues to be executed until the implementation method of the DCP file is obtained after the preset implementation strategy is executed.

[0026] Fig. 9 Shown is a flowchart of the compilation control method described in an embodiment of the present application.

[0027] Fig.10 Shown is a flowchart of the compilation control method described in an embodiment of the present application.

[0028] Fig.11 Shown is a flowchart of the process of implementing the automated running of the script in the embodiment of the present application.

[0029] Fig.12 Shown is a flowchart of the compilation control method described in an embodiment of the present application.

[0030] Fig.13 Shown is a structural schematic diagram of the compiling control device described in an embodiment of the present application.

[0031] Component number description

[0032] 10 Computing Devices

[0033] 110 Memory

[0034] 120 processors

[0035] 130 Bus

[0036] 140 Access Device

[0037] 20 FPGA chips

[0038] 1300 Compiler control device

[0039] 1310 Project Acquisition Module

[0040] 1320 Project Compilation Module

[0041] 1330 Script acquisition module

[0042] 1340 Comprehensive Strategy Operation Module

[0043] 1350 Implementing the Strategy Operation Module

[0044] 1360 Implement dcp file acquisition module

[0045] Steps S11-S14

[0046] Steps S21-S23

[0047] S31-S32 Steps

[0048] Steps S41-S43

[0049] Steps S51-S53

[0050] Steps S61-S62 DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0052] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0053] The technical solutions in the embodiments of the present application are described in detail below in conjunction with the drawings in the embodiments of the present application.

[0054] The compilation control method provided in the embodiment of the present application can be executed in a computing device. Figure 1 For example, Figure 1 The hardware structure block diagram of the computing device running the compilation control method. The computing device 10 includes but is not limited to a memory 110 and a processor 120. The processor 120 is connected to the memory 110 via a bus 130, and the computing device 10 is in communication with the FPGA chip 20. The bit stream file obtained by running the compilation control method in the computing device 10 can be downloaded to the FPGA chip 20 for implementing specific hardware functions.

[0055] The computing device 10 also includes an access device 140 that enables the computing device 10 to communicate via one or more networks. Examples of these networks include a public switched telephone network, a local area network, a wide area network, a personal area network, or a combination of communication networks such as the Internet. The access device 140 may include any type of network interface, wired or wireless, for example, one or more of a network interface card, such as an IEEE 802.11 wireless LAN wireless interface, a global microwave interconnection access interface, an Ethernet interface, a universal serial bus interface, a cellular network interface, a Bluetooth interface, a near field communication interface, and the like.

[0056] In the embodiment of the present application, the above components of the computing device 10 and Figure 1 Other components not shown in the figure may also be connected to each other, for example, via a bus. It should be understood that Figure 1 The computing device structure block diagram shown is only for the purpose of illustration, and is not intended to limit the scope of the present application. Those skilled in the art may add or replace other components as needed.

[0057] The computing device 10 may be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., a tablet computer, a personal digital assistant, a laptop computer, a notebook computer, a netbook, etc.), a mobile phone (e.g., a smart phone), a wearable computing device (e.g., a smart watch, smart glasses, etc.), or other types of mobile devices, or a stationary computing device such as a desktop computer or PC. The computing device 10 may also be a mobile or stationary server.

[0058] like Figure 2 As shown, this embodiment provides a compile control method, which can be executed by a computer processor, and the compile control method includes:

[0059] S11, obtaining the project to be compiled.

[0060] Optionally, the project to be compiled may refer to a project to be compiled by FPGA, and the project to be compiled may include a higher-level circuit written in a hardware description language such as Verilog or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language).

[0061] S12, performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0062] In the FPGA compilation process of the project to be compiled, the following steps S13-S15 are also performed:

[0063] Optionally, the compilation process of FPGA may include: Synthesis - converting a higher-level circuit description written in a hardware description language such as Verilog or VHDL into a lower-level circuit description, that is, the process of generating a netlist file, which describes the connection method of logic gates and triggers. In this process, the synthesis tool will optimize the design to meet constraints such as timing and area; Implementation - mapping the netlist generated by synthesis to the actual physical resources on the FPGA. This process includes placement, routing, and bitstream generation. Placement is to place logic units in appropriate locations on the FPGA chip; routing is to connect these logic units to form a circuit. The result of implementation is the generation of a bitstream file that can be run on the FPGA, which describes the specific configuration of the circuit on the FPGA.

[0064] When using Xilinx Vivado to compile and generate bitstreams, each stage must be completed before entering the next stage, and the implementation process is particularly time-consuming. In response to various reasons that may cause timing convergence difficulties, Vivado provides a variety of synthesis and implementation strategies that can be optimized for various actual situations, such as strategies for avoiding congestion, optimizing fan-out, optimizing logic levels, and other reasons that may cause timing problems. Vivado provides synthesis strategies such as Figure 3 As shown, the implementation strategies provided by Vivado are as follows Figure 4 shown.

[0065] Optionally, the bitstream file is a binary file that meets the timing requirements and is generated after steps such as synthesis, layout and routing, and timing analysis. The file can be downloaded to the FPGA chip to implement specific hardware functions.

[0066] Optionally, the FPGA compilation of the project to be compiled has limitations on FPGA hardware. If this limitation is exceeded, resources are insufficient and the compilation will not succeed. Therefore, it is generally necessary to first evaluate whether resources are sufficient before subsequent processes are feasible.

[0067] S13, obtaining a tcl script based on N preset synthesis strategies and M preset implementation strategies, wherein the preset synthesis strategy and the preset implementation strategy are used to solve the timing problem of the to-be-compiled project during the FPGA compilation process, and N and M are both positive integers.

[0068] Optionally, the tcl script may be a script rewritten by calling a python program, combining n pre-set synthesis strategies and m implementation strategies, and the tcl script may be regarded as a configuration file of the preset synthesis strategy and the preset implementation strategy.

[0069] Optionally, the preset synthesis strategy may refer to the preset synthesis strategy provided by Vivado, and the preset implementation strategy may refer to the preset implementation strategy provided by Vivado. The values ​​of N and M may be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0070] S14, performing parallel operation processing on the preset comprehensive strategy based on the tcl script to obtain a comprehensive dcp file of the preset comprehensive strategy.

[0071] Optionally, the DCP file is a unique encrypted compressed file of Vivado that is equivalent to the HDL (hardware description language) source file in FPGA design, which can be easily loaded and replaced.

[0072] Optionally, the parallel running of the preset comprehensive strategies may refer to running the preset comprehensive strategies in parallel in a multi-process manner through a Python program, and a corresponding DCP file will be generated after each comprehensive strategy is completed. The comprehensive DCP file may refer to the DCP file generated after the comprehensive strategy is completed.

[0073] S15, performing parallel operation processing on the preset implementation strategy based on the integrated netlist in the integrated DCP file to obtain a timing result associated with the preset implementation strategy.

[0074] Optionally, the comprehensive DCP file contains a comprehensive netlist, which is an intermediate representation used to describe the logic structure of a digital circuit in the FPGA design process. It is converted from a high-level hardware description language and contains all logic elements in the circuit and the connection relationships between them.

[0075] Optionally, the implementation strategy may generally be divided into multiple phases and executed sequentially, and the timing result associated with the preset implementation strategy may refer to the timing result of the preset implementation strategy in a specified implementation phase.

[0076] Optionally, the stages of the preset implementation strategy include: Opt Design stage, Place Design stage and Route Design stage, etc., and the timing results associated with the preset implementation strategy may include: the timing results of the Opt Design stage, the timing results of the Place Design stage and the timing results of the Route Design stage.

[0077] Optionally, the associated timing results of the preset implementation strategy may also include timing results of various stages of the implementation strategy.

[0078] Optionally, the implementation method of parallel running the preset implementation strategy based on the integrated netlist in the integrated DCP file includes: when the Python program detects that the integrated DCP file is generated, the script will load the integrated DCP file and run the implementation strategy in parallel according to the integrated netlist in the integrated DCP file.

[0079] Optionally, the implementation method of performing parallel operation processing on the preset implementation strategy based on the integrated netlist in the integrated dcp file to obtain the timing result associated with the preset implementation strategy includes: performing parallel operation processing on the preset implementation strategy based on the integrated netlist in the integrated dcp file to obtain the WNS (Worst Negative Slack) timing result and TNS (Total Negative Slack) timing result associated with the preset implementation strategy. The WNS is the worst slack value, which represents the worst performance of the chip, and the TNS is the sum of all negative slack values, which represents a performance range of the chip.

[0080] S16, if the timing result is less than the preset timing result threshold, then terminate the operation of the preset implementation strategy, otherwise continue to operate the preset implementation strategy until the implementation DCP file is obtained after the preset implementation strategy is completed.

[0081] Optionally, the preset timing result threshold and the timing result are values ​​of the same implementation stage in the preset implementation strategy, and the preset timing result threshold can be flexibly set according to actual conditions, and this embodiment does not explicitly limit this. When the timing result is less than the preset timing result threshold, it means that Vivado is also difficult to converge in the subsequent implementation stage and complete the mapping of the integrated netlist to the actual physical resources on the FPGA, so the script will terminate the operation of the preset implementation strategy.

[0082] Optionally, a corresponding dcp file will be generated after each implementation strategy is completed, and the implementation dcp file may refer to the dcp file generated after the implementation strategy is completed.

[0083] According to the above description, the compilation control method includes: obtaining a project to be compiled; performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled, wherein during the FPGA compilation process of the project to be compiled: obtaining a tcl script based on N preset synthesis strategies and M preset implementation strategies, the preset synthesis strategy and the preset implementation strategy are used to solve the timing problem of the project to be compiled during the FPGA compilation process, and N and M are both positive integers; performing parallel operation processing on the preset synthesis strategy based on the tcl script to obtain a comprehensive dcp file of the preset synthesis strategy; performing parallel operation processing on the preset implementation strategy based on the comprehensive netlist in the comprehensive dcp file to obtain a timing result associated with the preset implementation strategy; if the timing result is less than a preset timing result threshold, terminating the operation of the preset implementation strategy, otherwise continuing to operate the preset implementation strategy until the implementation dcp file is obtained after the preset implementation strategy is completed.

[0084] In the compilation control method, by controlling whether the preset implementation strategy is running according to the timing results associated with the preset implementation strategy, it is possible to avoid wasting too much time on strategies that are not suitable for this design. More strategies can be traversed within a given time, thereby obtaining the bitstream file faster, improving the timing convergence efficiency of the FPGA, greatly accelerating the iteration speed of engineering development, and improving the engineering development debugging efficiency.

[0085] See also Figure 5 ,like Figure 5 As shown, this embodiment provides a method for implementing FPGA compilation of the project to be compiled to obtain a bitstream file of the project to be compiled, including:

[0086] S21 , performing a timed detection on the project to be compiled based on a default path, a preset number of times, and a preset periodic interval of the project to be compiled to obtain a detection result.

[0087] Optionally, the default path may refer to the default path set by the project plan to be compiled. The preset number of times may represent the preset number of detections, and more comprehensive and accurate detection results can be obtained through multiple detections. The preset cycle interval may represent the cycle interval between two adjacent detections. The preset number of times and the preset cycle interval may be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0088] Optionally, the detection result is that the version of the project to be compiled has changed or the version of the project to be compiled has not changed.

[0089] S22: Based on the detection result, perform FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0090] See also Figure 6 ,like Figure 6 As shown, this embodiment provides a method for implementing FPGA compilation of the project to be compiled based on the detection result to obtain a bit stream file of the project to be compiled, including:

[0091] S31, when the detection result is that the version of the project to be compiled has changed, performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0092] S32: When the detection result shows that the version of the project to be compiled has not changed, the project to be compiled is not FPGA compiled.

[0093] Optionally, the purpose of this step is to reduce the active intervention of engineers, increase the degree of automation, and improve the overall iteration efficiency.

[0094] See also Figure 7 ,like Figure 7 As shown, this embodiment provides a method for implementing the preset implementation strategy, which terminates the operation of the preset implementation strategy if the timing result is less than the preset timing result threshold, and continues to operate the preset implementation strategy otherwise, including:

[0095] S41, if the timing result of the Opt Design stage is less than a first preset timing result threshold, then terminate the operation of the preset implementation strategy, otherwise continue to operate the preset implementation strategy.

[0096] Optionally, the first preset timing result threshold is a timing result threshold preset in the Opt Design stage. The first preset timing result threshold can be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0097] S42: If the timing result of the Place Design stage is less than a second preset timing result threshold, then terminate the operation of the preset implementation strategy; otherwise, continue to operate the preset implementation strategy.

[0098] Optionally, the second preset timing result threshold is a timing result threshold preset in the Place Design stage. The second preset timing result threshold can be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0099] S43, if the timing result of the Route Design stage is less than a third preset timing result threshold, then terminate the operation of the preset implementation strategy, otherwise continue to operate the preset implementation strategy.

[0100] Optionally, the third preset timing result threshold is a timing result threshold preset in the Route Design stage. The third preset timing result threshold can be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0101] See also Figure 8 ,like Figure 8 As shown, this embodiment provides a method for continuing to run the implementation strategy until obtaining an implementation method of the DCP file after the preset implementation strategy is completed, including:

[0102] S51, after the preset implementation strategy is executed, a timing check is performed on the preset implementation strategy to obtain a timing check result.

[0103] Optionally, the timing check may refer to a check on the timing details involved in the implementation dcp file, and the timing check result may be that the timing check result meets the requirement, i.e., meets the timing requirement, or the timing check result does not meet the requirement, i.e., does not meet the timing requirement.

[0104] S52: If the timing check result meets the requirement, the implementation DCP file is obtained; otherwise, the implementation DCP file is not obtained.

[0105] See also Fig. 9 ,like Fig. 9 As shown, this embodiment provides a compile control method, further comprising:

[0106] S61, when the bitstream file is generated, a report is automatically generated through a notifier.

[0107] S62, automatically push the report to the user through a tool api (Application Programming Interface).

[0108] Optionally, the user, i.e. the corresponding engineer, automatically generates a report, i.e. a report, through notifer, i.e. a notifier, and sends a message to the corresponding engineer through an API, saving the trouble of frequently logging into a server, i.e. a server.

[0109] In one embodiment of the present application, the compilation control method sets the default path according to the project plan, and sets the number and cycle interval for regular detection. If a version change is found, the process will be automatically started, and multiple tasks will be carried out in parallel. By automating the entire compilation process, strategies with poor timing can be discovered and terminated at an early stage, and other strategies can be quickly replaced for compilation. In this way, various strategies can be traversed as much as possible within a limited time, thereby greatly increasing the probability of generating a timing convergence bit stream.

[0110] In the compilation process, you can use the report timing tool after each compilation stage is completed, and then the script will automatically analyze the timing results, mainly looking at the two indicators WNS and TNS, which are indicators in the timing report to measure the quality of the timing. WNS: worst negative slack, the worst slack value, represents the worst performance of the chip TNS: total negative slack, the sum of all negative slack values, represents a performance range of the chip. If these two values ​​are less than expected, the compilation will be terminated in advance, and other strategies that have not detected abnormalities will continue to be maintained, so as to avoid wasting time under inappropriate strategies. The compilation control method can automatically and quickly traverse multiple comprehensive implementation strategies, greatly accelerating the time to generate a bitstream with timing convergence, thereby greatly accelerating the time required for engineering development and debugging.

[0111] See also Fig.10 ,like Fig.10 As shown, the compilation control method firstly calls the python program in the script, combines n comprehensive strategies and m implementation strategies set in advance, and rewrites the tcl script (configuration file) accordingly.

[0112] Secondly, the Python program runs n synthesis strategies in parallel in a multi-process mode, and each synthesis strategy generates a corresponding synthesis DCP file after completion. The DCP file is a unique encrypted compressed file of Vivado that is equivalent to the HDL source file in FPGA design and can be easily loaded and replaced.

[0113] Afterwards, when the python program detects that a comprehensive dcp file has been generated, the script will load the dcp file and parallelly calculate m implementation strategies based on the comprehensive netlist in this dcp file. Among them, the implementation strategy is usually divided into multiple stages (such as OptDesign, Place Design, Route Design, etc.) and executed sequentially. The program will check the timing results WNS and TNS in the specified implementation stage. When it is checked that WNS and TNS in this stage are less than the specified threshold, it means that Vivado will also find it difficult to converge in the subsequent implementation stage and complete the mapping of the comprehensive netlist to the actual physical resources on the FPGA. Therefore, the script will terminate the operation of the implementation strategy. When the implementation strategy is finished running, the script will perform a timing check again. If the requirements are met, an implementation dcp file will be generated for subsequent generation of a bitstream file.

[0114] Finally, when the entire process is completed, this method will generate rpt and log files, and automatically push messages to corresponding engineers through the tool API, which can enable more effective collaboration and improve efficiency.

[0115] The compilation control method can automatically start the process at a fixed time and can automatically traverse various comprehensive implementation strategies in parallel in combination with computing resources, and monitor the compilation process, perform timing analysis after each compilation sub-process, and terminate the compilation in time if the running result at this time does not meet the requirements, select the next strategy to start a new compilation, which can avoid wasting time and computing resources on inappropriate strategies, and can traverse more strategies within a given time, so that FPGA bitstream files that can be downloaded and debugged can be generated faster, and reports are automatically generated through notifiers, and messages are sent to corresponding engineers through APIs, eliminating the trouble of frequently logging into the server. This semi-automatic method can greatly reduce the manual operation of engineers, while taking into account resources, efficiency and flexibility, and greatly improves the efficiency of engineering development and debugging by reducing iteration cycles.

[0116] See also Fig.11 ,like Fig.11 The flowchart of the script automation implementation process is shown. Fig.11 The phys_opt_design in the description may refer to the physical optimization design phase, which will not be described in detail in this embodiment.

[0117] In one embodiment of the present application, please refer to Fig.12 ,like Fig.12 As shown, the compilation control method may include the following steps:

[0118] 1Set the project warehouse and path according to the project arrangement.

[0119] 2. Predetermine the policy profiles that need to be tried.

[0120] 3. Implement regular program monitoring, set the number and interval period, generally according to the project cycle and milestone stages.

[0121] 4. Process execution: Whenever a version update is detected, the process of generating the project version will be executed.

[0122] 5Tasks will be monitored and controlled during the process.

[0123] 6 Generate results, generate reports, and send notification messages.

[0124] The protection scope of the compilation control method described in the embodiment of the present application is not limited to the execution order of the steps listed in the present embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.

[0125] See also Fig.13 ,like Fig.13 As shown, this embodiment provides a compile control device 1300, and the compile control device 1300 includes:

[0126] The project acquisition module 1310 is used to acquire the project to be compiled.

[0127] The project compiling module 1320 is used to perform FPGA compiling on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0128] The script acquisition module 1330 is used to acquire Tcl scripts based on N preset synthesis strategies and M preset implementation strategies, wherein the synthesis strategy and the implementation strategy are used to solve the timing problem of the to-be-compiled project during the FPGA compilation process, and N and M are both positive integers.

[0129] The comprehensive strategy running module 1340 is used to perform parallel running processing on the preset comprehensive strategy based on the tcl script to obtain a comprehensive dcp file of the preset comprehensive strategy.

[0130] The implementation strategy running module 1350 is used to perform parallel running processing on the preset implementation strategy based on the integrated netlist in the integrated DCP file to obtain the timing result associated with the preset implementation strategy.

[0131] The implementation DCP file acquisition module 1360 is used to terminate the operation of the preset implementation strategy if the timing result is less than the preset timing result threshold, otherwise continue to run the preset implementation strategy until the implementation DCP file is obtained after the preset implementation strategy is completed.

[0132] In the compilation control device 1300 provided in this embodiment, the project acquisition module 1310 and Figure 2 The project compilation module 1320 corresponds to step S11 of the compilation control method shown in FIG. Figure 2 The script acquisition module 1330 corresponds to step S12 of the compilation control method shown in FIG. Figure 2 The integrated strategy operation module 1340 corresponds to step S13 of the compilation control method shown in FIG. Figure 2 The implementation strategy operation module 1350 corresponds to step S14 of the compilation control method shown in FIG. Figure 2 The step S15 of the compiling control method shown in FIG. 1 corresponds to the step S16 of the compiling control method shown in FIG. 1 , wherein the dcp file acquisition module 1360 is implemented with Figure 2 This corresponds to step S16 of the compilation control method shown.

[0133] In the several embodiments provided in the present application, it should be understood that the disclosed device or method can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules / units is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules or units, which can be electrical, mechanical or other forms.

[0134] The modules / units described as separate components may or may not be physically separated, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, the functional modules / units in the various embodiments of the present application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0135] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0136] This embodiment provides an electronic device, the electronic device comprising a memory storing a computer program; a processor connected to the memory for communication, and executing the computer program when the computer program is called. Figure 2 The compilation control method shown.

[0137] The present application embodiment also provides a computer-readable storage medium. A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above embodiment can be completed by a program to instruct the processor, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state hard disk (SSD)), etc.

[0138] The present application embodiment may also provide a computer program product, the computer program product including one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer or data center.

[0139] When the computer program product is executed by a computer, the computer executes the method described in the above method embodiment. The computer program product may be a software installation package, and when the above method is required, the computer program product may be downloaded and executed on a computer.

[0140] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0141] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A compile control method, characterized in that: The compilation control method comprises: Get the project to be compiled; Perform FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled, wherein during the FPGA compilation process of the project to be compiled: Obtaining a tool command language tcl script based on N preset synthesis strategies and M preset implementation strategies, wherein the preset synthesis strategy and the preset implementation strategy are used to solve the timing problem of the to-be-compiled project during the FPGA compilation process, and N and M are both positive integers; Based on the tcl script, the preset synthesis strategy is run in parallel to obtain a synthesis design checkpoint dcp file of the preset synthesis strategy; based on the synthesis netlist in the synthesis dcp file, the preset implementation strategy is run in parallel to obtain a timing result associated with the preset implementation strategy; If the timing result is less than the preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise the preset implementation strategy continues to be executed until the implementation DCP file is obtained after the preset implementation strategy is executed.

2. The compile control method according to claim 1, characterized in that: The method for implementing FPGA compilation of the project to be compiled to obtain a bit stream file of the project to be compiled includes: Performing a timed detection on the project to be compiled based on a default path, a preset number of times and a preset periodic interval of the project to be compiled to obtain a detection result; Based on the detection result, FPGA compilation is performed on the project to be compiled to obtain a bitstream file of the project to be compiled.

3. The compile control method according to claim 2, characterized in that: The detection result is that the version of the project to be compiled has changed or the version of the project to be compiled has not changed. Based on the detection result, the implementation method of performing FPGA compilation on the project to be compiled to obtain the bitstream file of the project to be compiled includes: When the detection result indicates that the version of the project to be compiled has changed, performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled; When the detection result shows that the version of the project to be compiled has not changed, FPGA compilation is not performed on the project to be compiled.

4. The compile control method according to claim 1, characterized in that: The preset implementation strategy includes an optimization design OptDesign stage, a layout design Place Design stage, and a routing design Route Design stage. The timing results associated with the preset implementation strategy include the timing results of the Opt Design stage, the timing results of the Place Design stage, and the timing results of the RouteDesign stage. If the timing result is less than a preset timing result threshold, the preset implementation strategy is terminated. Otherwise, the preset implementation strategy is continued to be run. The implementation method includes: If the timing result of the Opt Design phase is less than a first preset timing result threshold, then the preset implementation strategy is terminated, otherwise the preset implementation strategy continues to be run; If the timing result of the Place Design phase is less than a second preset timing result threshold, then terminating the operation of the preset implementation strategy, otherwise continuing to operate the preset implementation strategy; If the timing result of the Route Design stage is less than the third preset timing result threshold, the operation of the preset implementation strategy is terminated; otherwise, the preset implementation strategy continues to be operated.

5. The compile control method according to claim 1, characterized in that: The implementation method of continuing to run the preset implementation strategy until obtaining the implementation DCP file after the preset implementation strategy is completed includes: After the preset implementation strategy is executed, a timing check is performed on the preset implementation strategy to obtain a timing check result; If the timing check result meets the requirement, the implementation DCP file is obtained, otherwise the implementation DCP file is not obtained.

6. The compile control method according to claim 1, characterized in that: The implementation method of performing parallel operation processing on the preset implementation strategy based on the integrated netlist in the integrated DCP file to obtain the timing result associated with the preset implementation strategy includes: The preset implementation strategies are run in parallel based on the synthesis netlist in the synthesis DCP file to obtain the worst negative timing margin WNS timing result and the total negative timing margin TNS timing result associated with the preset implementation strategy.

7. The compile control method according to claim 1, characterized in that: The compile control method further includes: When the bitstream file is generated, a report is automatically generated through a notifier; The report is automatically pushed to the user through the tool API.

8. A compiling control device, characterized in that: The compile control device comprises: Project acquisition module, used to obtain the project to be compiled; A project compilation module, used for performing FPGA compilation on the project to be compiled to obtain a bit stream file of the project to be compiled; A script acquisition module, used to acquire a tcl script based on N preset synthesis strategies and M preset implementation strategies, wherein the synthesis strategy and the implementation strategy are used to solve the timing problem of the to-be-compiled project during the FPGA compilation process, and N and M are both positive integers; A comprehensive strategy running module, used for performing parallel running processing on the preset comprehensive strategy based on the tcl script to obtain a comprehensive dcp file of the preset comprehensive strategy; An implementation strategy running module, used for performing parallel running processing on the preset implementation strategy based on the comprehensive netlist in the comprehensive DCP file to obtain a timing result associated with the preset implementation strategy; A dcp file acquisition module is implemented, which is used to terminate the operation of the preset implementation strategy through the tcl script if the timing result is less than the preset timing result threshold, otherwise continue to run the preset implementation strategy until the implementation dcp file is obtained after the preset implementation strategy is completed.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the compilation control method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: The electronic device comprises: A memory storing a computer program; A processor is communicatively connected to the memory, and executes the compilation control method according to any one of claims 1 to 7 when calling the computer program.

Images