Analog circuit design method based on neural network

Abstract

The invention relates to an analog circuit design method and device based on a neural network, equipment and a medium, and the method comprises the steps: obtaining a training data set of analog circuit design; designing an activation function type corresponding to the analog circuit design based on the training data set and the circuit model index; identifying the number of neurons corresponding to the initial neural network, and determining the processing mode and spatial distribution of the training data set by the neuron circuit module based on the number of neurons; performing analog circuit design according to the activation function type and the determined processing mode and spatial distribution, and constructing a neural network training circuit of a multi-level complex neuron group; and training the neural network training circuit of the multi-level complex neuron group by adopting the training data set to obtain a neural network circuit model for simulation verification. The whole scheme can realize efficient and accurate analog circuit design.

Description

Technical Field

[0001] The present application relates to the technical field of analog circuit design, and in particular to a method, apparatus, computer equipment, storage medium and computer program product for analog circuit design based on a neural network. Background Art

[0002] In recent years, neural networks have been widely used because of their ability to handle complex training tasks, becoming one of the important ways to achieve artificial intelligence. Neural network training algorithms require carefully designed network structures, which are often limited by resources, costs, and computing efficiency. Optimizing the neural network implementation structure by designing a circuit system composed of underlying devices and realizing hardware neural networks has become an effective solution while increasing the overall computing speed and reducing the cost of system components.

[0003] Neuron-level chip design mainly includes a variety of methods such as digital, analog, mixed digital and analog, and programmable chip implementation. Signal digitization is conducive to the system's detection, reception, processing and information extraction of complex signals. The existing hardware neuron implementation basis includes setting signal transmission thresholds, defining signal input / output lookup tables, and using computing units. Digital implementation is relatively simple, with a high signal-to-noise ratio and easy cascading, but digital neurons require powerful hardware support, and the operation speed of digital multipliers is slow, which not only consumes a large amount of chip area for storage and calculation, but also relies on analog control bits and output conversion, greatly increasing the power consumption of the entire chip.

[0004] It can be seen that an efficient and simple analog circuit design solution is urgently needed. Summary of the invention

[0005] Based on this, it is necessary to provide an efficient and simple neural network-based analog circuit design method, device, computer equipment, storage medium and computer program product to address the above technical problems.

[0006] In a first aspect, the present application provides a method for designing analog circuits based on a neural network. The method comprises:

[0007] Obtain training data sets for analog circuit design;

[0008] Based on the training data set and the circuit model index, design an activation function type corresponding to the analog circuit design;

[0009] Identifying the number of neurons corresponding to the initial neural network, and determining the processing mode and spatial distribution of the training data set by the neuron circuit module based on the number of neurons;

[0010] Perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution to construct a neural network training circuit of a multi-layer complex neuron group;

[0011] The training data set is used to train the neural network training circuit of the multi-level complex neuron group to obtain a neural network circuit model verified by simulation.

[0012] In one embodiment, obtaining a training data set for analog circuit design includes:

[0013] Obtain the required data and input voltage domain for analog circuit design;

[0014] Data mapping is performed according to the required data and the input voltage domain to obtain a training data set.

[0015] In one embodiment, the activation function type corresponding to the analog circuit design is designed based on the training data set and the circuit model indicator, including:

[0016] Based on the training data set and the circuit model indicators, determining the types of components of the analog circuit and the working modes of different components of the analog circuit;

[0017] Determine the target analog input signal type according to the analog circuit component type and the analog circuit operation mode;

[0018] According to the target analog input signal type, an activation function type corresponding to the analog circuit design is selected.

[0019] In one embodiment, the analog circuit component device types include NMOS and PMOS;

[0020] Determining the target analog input signal type according to the analog circuit component type and the analog circuit operation mode includes:

[0021] Determine the level signals corresponding to the input signals and output signals of the analog circuit according to the types of components of the analog circuit and the working mode of the analog circuit;

[0022] The target analog input signal type is determined according to the corresponding level signal.

[0023] In one embodiment, the activation function includes Sigmoid and Tanh.

[0024] In one embodiment, before obtaining the spatial distribution and processing mode corresponding to the analog circuit design based on the trained neural network, the method further includes:

[0025] Obtaining the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network of the neural network circuit model verified by simulation;

[0026] Adopting a negative feedback system to adjust the feedforward transmission mode, the input signal relationship function IN(s) and the output signal relationship function OUT(s) of the neural network circuit model verified by simulation are obtained;

[0027] Based on the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), detecting whether the neural network circuit model verified by simulation is qualified;

[0028] If it fails, the activation function type corresponding to the analog circuit design is designed based on the training data set and the circuit model index.

[0029] In one embodiment, based on the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), detecting whether the neural network circuit model verified by simulation is qualified includes:

[0030] Determine whether the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, and the input signal relationship function IN(s) and the output signal relationship function OUT(s) satisfy the output signal domain input signal relationship; wherein the output signal domain input signal relationship is:

[0031]

[0032] In a second aspect, the present application also provides a neural network-based analog circuit design device. The device comprises:

[0033] A data set acquisition module, used to acquire a training data set for analog circuit design;

[0034] A type selection module, used to design an activation function type corresponding to the analog circuit design based on the training data set and the circuit model indicator;

[0035] An identification module, used to identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the training data set by the neuron circuit module based on the number of neurons;

[0036] A model building module, used to perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution, and to build a neural network training circuit of a multi-level complex neuron group;

[0037] A model training module, used to train the neural network training circuit of the multi-level complex neuron group using the training data set to obtain a neural network circuit model verified by simulation;

[0038] The design module is used to obtain the spatial distribution and processing mode corresponding to the analog circuit design based on the trained neural network.

[0039] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0040] Obtain training data sets for analog circuit design;

[0041] Based on the training data set and the circuit model index, design an activation function type corresponding to the analog circuit design;

[0042] Identifying the number of neurons corresponding to the initial neural network, and determining the processing mode and spatial distribution of the training data set by the neuron circuit module based on the number of neurons;

[0043] Perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution to construct a neural network training circuit of a multi-layer complex neuron group;

[0044] The training data set is used to train the neural network training circuit of the multi-level complex neuron group to obtain a neural network circuit model verified by simulation.

[0045] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0046] Obtain training data sets for analog circuit design;

[0047] Based on the training data set and the circuit model index, design an activation function type corresponding to the analog circuit design;

[0048] Identifying the number of neurons corresponding to the initial neural network, and determining the processing mode and spatial distribution of the training data set by the neuron circuit module based on the number of neurons;

[0049] Perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution to construct a neural network training circuit of a multi-layer complex neuron group;

[0050] The training data set is used to train the neural network training circuit of the multi-level complex neuron group to obtain a neural network circuit model verified by simulation.

[0051] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0052] Obtain training data sets for analog circuit design;

[0053] Based on the training data set and the circuit model index, design an activation function type corresponding to the analog circuit design;

[0054] Identifying the number of neurons corresponding to the initial neural network, and determining the processing mode and spatial distribution of the training data set by the neuron circuit module based on the number of neurons;

[0055] Perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution to construct a neural network training circuit of a multi-layer complex neuron group;

[0056] The training data set is used to train the neural network training circuit of the multi-level complex neuron group to obtain a neural network circuit model verified by simulation.

[0057] The above-mentioned analog circuit design method, device, computer equipment, storage medium and computer program product based on neural network obtain the training data set of analog circuit design; design the activation function type corresponding to the analog circuit design based on the training data set and circuit model indicators; identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module for the training data set based on the number of neurons; perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution, and construct a neural network training circuit of a multi-level complex neuron group; use the training data set to train the neural network training circuit of the multi-level complex neuron group to obtain a neural network circuit model verified by simulation. In the whole process, the training data set and activation function type are obtained in a targeted manner according to the actual situation of the analog circuit, and the neural network training circuit of the multi-level complex neuron group is constructed and trained in a targeted manner based on the selected activation function type and the determined processing mode and spatial distribution, so as to realize efficient and accurate analog circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 is an application environment diagram of an analog circuit design method based on a neural network in one embodiment;

[0059] Figure 2 This is a basic MOSFET structure diagram;

[0060] Figure 3 It is an NMOS working in the deep triode region;

[0061] Figure 4 It is the block diagram of negative feedback system;

[0062] Figure 5 A schematic diagram of a flow chart of a method for designing an analog circuit based on a neural network in one embodiment;

[0063] Figure 6 is a flowchart of a method for designing an analog circuit based on a neural network in another embodiment;

[0064] Figure 7 Design block diagrams for some classification patterns;

[0065] Figure 8(a) shows the design of the PMOS+NMOS partial classification mode;

[0066] Figure 8(b) shows one of the PMOS+NMOS partial classification mode designs;

[0067] Figure 8(c) shows the second design of the PMOS+NMOS partial classification mode;

[0068] Figure 8(d) shows the third design of the PMOS+NMOS partial classification mode;

[0069] Figure 9(a) shows the design of the NMOS+PMOS partial classification mode;

[0070] Figure 9(b) shows one of the NMOS+PMOS partial classification mode designs;

[0071] Figure 9(c) shows the second design of the NMOS+PMOS partial classification mode;

[0072] Figure 9(d) shows the third design of the NMOS+PMOS partial classification mode;

[0073] Fig.10 is a structural block diagram of an analog circuit design device based on a neural network in one embodiment;

[0074] Fig.11 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0076] The analog circuit design method based on neural network provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. The terminal 102 sends a request for analog circuit design to the server 104, and the server 104 responds to the design request and obtains a training data set for the analog circuit design; based on the training data set and the circuit model index, the activation function type corresponding to the analog circuit design is designed; the number of neurons corresponding to the initial neural network is identified, and the processing mode and spatial distribution of the neuron circuit module for the training data set are determined based on the number of neurons; the analog circuit design is performed according to the activation function type and the determined processing mode and spatial distribution, and a neural network training circuit of a multi-level complex neuron group is constructed; the neural network training circuit of the multi-level complex neuron group is trained using the training data set to obtain a neural network circuit model verified by simulation. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices, and the Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The server 104 may be implemented as an independent server or a server cluster consisting of multiple servers.

[0077] In order to explain in detail the technical principles and effects of the neural network-based analog circuit design method of the present application, the basic principles and theoretical basis involved in the present application will be first introduced below.

[0078] 1. Basic principles of MOSFET

[0079] Figure 2 The basic MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, MOS), that is, the metal-oxide semiconductor field effect transistor, abbreviated as MOS tube. Among them, the MOS that conducts electricity by N-type (chemical bonds are 5-valent ions) carriers is called NMOS, and the MOS that conducts electricity by P-type (chemical bonds are 3-valent ions) carriers is called PMOS. A pair of complementary NMOS and PMOS constitutes CMOS.

[0080] Taking NMOS as an example, after being turned on, it satisfies the current formula:

[0081]

[0082] Among them, I D Indicates the current from the drain to the source of the MOS tube, in amperes, i.e. A; μ nIt represents the electron carrier mobility in square meters per volt-second, that is, m 2 / (V*s);C ox It represents the gate oxide capacitance per unit area, in farads per square meter, or F / m 2 ; L represents the lateral dimension of the gate along the source-drain channel - the gate length, in meters, i.e. m; W represents the dimension of the gate perpendicular to the gate length - the gate width, in meters, i.e. m. MOSFET consists of three terminals, namely the gate (G), source (S) and drain (D). V GS Indicates the gate-source voltage difference of the MOS tube, in volts, i.e. V; V TH Indicates the channel conduction threshold voltage of the MOS tube, in volts, i.e. V; V DS It represents the drain-source voltage difference of the MOS tube, in volts, i.e. V. λ represents the channel length modulation coefficient, which is dimensionless.

[0083] When V GS ≤V TH When the MOS tube channel cannot form a conductive path, no current flows through the source and drain of the MOS tube, and the current formula of the MOS tube is simplified to the following formula:

[0084] I D ≈0

[0085] When V GS >V TH And V DS <V GS -V TH , the MOS device will work in the "triode region". DS <<2(V GS -V TH ), the MOS device will work in the "deep triode region", and the channel length modulation effect can be ignored. According to the current formula of the MOS tube, the source and drain current at this time can be obtained:

[0086]

[0087] At this time, the drain current is about V DS The source-drain channel can be represented by a linear resistance. Figure 3 As shown in the figure, the NMOS tube working in the deep triode region is equivalent to a voltage-controlled drain-source resistor R on_linear According to Ohm's law, R = V / I, R on The resistance value is given by:

[0088]

[0089] When V GS >V TH And VDS ≥V GS -V TH , the MOS device will work in the "saturation region". According to the current formula of the MOS tube and the channel pinch-off characteristics of the MOS tube, the source-drain current at this time can be obtained as follows:

[0090]

[0091] At this time, the drain current is about V DS The source-drain channel can still be represented by a linear resistance. Figure 3 Similarly, an NMOS tube operating in the saturation region is also equivalent to a drain-source resistor R controlled by a drain-source voltage. on_sat According to Ohm's law, R = V / l, R on_sat The resistance value is given by:

[0092]

[0093] 2. Negative Feedback Regulation Principle

[0094] Figure 4 This is a typical negative feedback system diagram, where the transfer function of the feedforward transmission network is H(s), and the transfer function of the feedback transmission network is G(s). According to the signal feedback path, after the feedback network detects the output change ΔOUT(s), it passes through the inverting unit and is added to the input signal at the adder to obtain the error signal IN(s)-G(s)*OUT(s). The error is then amplified by the feedforward path and the output is corrected so that the output signal returns to the expected value. Therefore, the relationship of the output signal can be derived:

[0095] OUT n+1 (s)=H(s)*[IN(s)-G(s)*OUT n (s)]

[0096] When the feedback system is regulated and stabilized, there is OUT n+1 (s)=OUT n (s) = OUT(s), the above formula is:

[0097] OUT(s)=H(s)*[IN(s)-G(s)*OUT(s)]

[0098] Then we can get the relationship between the output signal and the input signal:

[0099]

[0100] When the gain of the feedforward transmission network approaches infinity, that is, H(s)≈∞, the above formula can be simplified to:

[0101]

[0102] By analyzing the above formula, three types of results can be obtained:

[0103] If G(s)≈∞, then OUT(s)≈0;

[0104] If G(s)≈0, then OUT(s)≈∞. In practice, due to conditional constraints, OUT(s) can only reach the conditional extreme value.

[0105] If G(s)≈N, where N is a finite number, then

[0106] Based on the principles of analog integrated circuits, the adopted design pattern is described from multiple angles such as data processing, neuron distribution, activation function selection and error training.

[0107] In one embodiment, Figure 5 As shown, a method for analog circuit design based on neural network is provided. Figure 1 Taking the server 104 in the example as an example, the following steps are included:

[0108] S100: Obtain a training data set for analog circuit design.

[0109] Obtain data related to analog circuit design to form a training data set. Specifically, you can first obtain the required data and input voltage domain for analog circuit design; perform data mapping based on the required data and input voltage domain to obtain a training data set. Here, you can perform data mapping based on the required data input and input voltage domain, fully explore the classification options that the existing data can provide, and prepare for subsequent model training.

[0110] Here, data mapping is performed based on the required data input and input voltage domain, including nonlinear feature processing and format screening, to fully explore the classification options that historical data can provide and prepare for subsequent model training.

[0111] S200: Based on the training data set and circuit model indicators, design the activation function type corresponding to the analog circuit design.

[0112] The circuit model is a mathematical model used to describe the interaction and energy conversion between various components in the circuit. The circuit model indicators here usually refer to a series of parameters and standards used to quantify, evaluate or describe the performance, behavior or characteristics of the circuit. Specifically, the circuit model indicators can include electrical characteristic indicators, frequency response indicators, dynamic performance indicators, stability indicators, power consumption and efficiency indicators, noise and interference indicators, etc. When designing analog circuits, different circuit models will be selected for analysis and design according to the specific application scenarios and performance requirements of the circuit. Here, the activation function type corresponding to the analog circuit design is selected based on the obtained training data. Specifically, in the process of analog circuit design, it is mainly necessary to consider the performance and resource balancing selection circuit controlled by transistors, switches or data, and analog control bits. Furthermore, the classification module can forward select the required activation function circuit implementation, with a resource tilt design that controls the forward selection by the control bit. The activation function can also support the backward selection of the processed classification module, with the computational performance advantage of the control bit controlling the backward selection.

[0113] S300: Identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module for the training data set based on the number of neurons.

[0114] For the initial neural network that needs to be trained this time, the corresponding number of neurons is identified, and based on the number of neurons, the processing mode and spatial distribution of the neuron circuit module for the training data set are determined.

[0115] Specifically, the on-state current formula of a transistor (taking NMOS as an example) is as follows:

[0116]

[0117] It is convenient to complete the nonlinear characteristic processing of the internal data of the neuron; the mode classification considers the input signal voltage domain. Under the stable working environment of the transistor, taking the high level and low level combination of the two inputs as an example, the circuit has the following working characteristics:

[0118] 1) V IN1 =V IN1，l The first branch inputs a low level, V IN2 =V IN2，l The second branch inputs low level, V out ∝V IN1，l +2VI N2，l ;

[0119] 2) V IN1 =V IN1，l The first branch inputs a low level, V IN2 =V IN2，h The second branch inputs high level, V out ∝VIN1，l +V IN2，h ;

[0120] 3) V IN1 =V IN1，h The first branch inputs a high level, V IN2 =V IN2，l The second branch inputs low level, V out ∝2V IN1，h +2V IN2，l ;

[0121] 4) V IN1 =V IN1，h The first branch inputs a high level, V IN2 =V IN2，h The second branch inputs high level, V out ∝2V IN1，h +V IN2，h ;

[0122] Set the working condition to V IN1，l <V low1 <V high1 <V IN1，h and V IN2，l <V low2 <V high2 <V IN2，h , affected by the threshold setting, has the following relationship:

[0123] V IN1，l <V IN2，l <<V IN1，h <V IN2，h

[0124] Further analysis shows that:

[0125] V IN1，l +2V IN2，l <V IN1，l +V IN2，h <2V IN1，h +2V IN2，l <2V IN1，h +V IN2，h

[0126] Obviously, according to the above inequality relationship, the circuit design achieves the purpose of having a maximum of four classification situations in the classification mode under two inputs, and the activation function selected by S200 can complete the implementation of subsequent classification compression.

[0127] S400: Perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution to construct a neural network training circuit of a multi-layer complex neuron group.

[0128] According to the activation function type and the determined processing mode and spatial distribution, the analog circuit design is performed, the number of network layers, the number of neurons in each layer, the communication relationship within the layer and the communication mode between the layers are designed, and the calculation efficiency is improved by parallel calculation within the layer. Specifically, here, according to the activation function type and the determined processing mode and spatial distribution, the analog circuit design is performed, the number of network layers, the number of neurons in each layer, the communication relationship within the layer and the communication mode between the layers are designed. After the circuit is started, the current signal will be transmitted layer by layer according to the design mode, with a significant intra-layer parallel effect until the final output is obtained. In short, the processing mode here refers to converting the four classifications into three classifications, two classifications, etc. required by the current application scenario. Spatial distribution refers to calling out the packaged neuron circuit for arrangement and connection, and then realizing the analog circuit design with subsequent processing. In the neural network training circuit of the constructed multi-level complex neuron group, the core neuron circuit has been pre-designed, and then the analog circuit design is specifically called according to the activation function type and the determined processing mode and spatial distribution.

[0129] S500: Using the training data set to train the neural network training circuit of the multi-layer complex neuron group to obtain.

[0130] The neural network training circuit of the multi-level complex neuron group is trained based on the training data set obtained in S100 to obtain a neural network circuit model verified by simulation. Specifically, during the training process, the network parameters in the neural network can be continuously adjusted based on the output signal and the input signal until the preset training end condition is finally reached to obtain a neural network circuit model verified by simulation. After the neural network training circuit of the multi-level complex neuron group is constructed, the entire circuit is started, feedback adjustment is performed based on the existing training data, and the neural network training circuit of the entire multi-level complex neuron group is continuously trained to finally obtain a neural network circuit model verified by simulation, which represents the analog circuit that has been designed.

[0131] The above-mentioned analog circuit design method based on neural network obtains the training data set of analog circuit design; designs the activation function type corresponding to the analog circuit design based on the training data set and circuit model indicators; identifies the number of neurons corresponding to the initial neural network, and determines the processing mode and spatial distribution of the neuron circuit module for the training data set based on the number of neurons; performs analog circuit design according to the activation function type and the determined processing mode and spatial distribution, and constructs a neural network training circuit of a multi-level complex neuron group; uses the training data set to train the neural network training circuit of the multi-level complex neuron group to obtain a neural network circuit model verified by simulation; obtains the spatial distribution and processing mode corresponding to the analog circuit design based on the trained neural network. In the whole process, the training data set and activation function type are obtained in a targeted manner according to the actual situation of the analog circuit, and based on the selected activation function type and the determined processing mode and spatial distribution, a neural network training circuit of a multi-level complex neuron group is constructed for training, so as to realize efficient and accurate analog circuit design.

[0132] like Figure 6 As shown, in one embodiment, S100 includes:

[0133] S120: Obtain required data and input voltage domain for analog circuit design.

[0134] Before building a training dataset, you first need to determine what data is necessary for training the model. This data usually includes but is not limited to: Circuit parameters: such as the values ​​of components such as resistors, capacitors, inductors, and model parameters of nonlinear components such as transistors and diodes; Working environment parameters: such as power supply voltage, temperature, frequency, etc., which affect the performance of the circuit; Design specifications: such as target output voltage range, current limit, power consumption requirements, etc., which define the goals of the circuit design; Historical design data: past successful or failed design data can be used as a reference to help the model learn the effective and invalid areas of the design space.

[0135] S140: Perform data mapping according to the required data and the input voltage domain to obtain a training data set.

[0136] The input voltage domain refers to the range or target value of the output voltage that is of interest in the circuit design. This is usually determined based on the design specifications. For example, an amplifier may need to output a specific voltage range to meet the needs of the subsequent circuit. Determining the input voltage domain is an important step in the construction of the training dataset because it will guide the data collection and preprocessing process. Once the required data is obtained and the input voltage domain is determined, the next step is to perform data mapping to build the training dataset. Data mapping involves converting circuit parameters, operating environment parameters, design specifications, etc. into a format that the model can understand and generate the corresponding output label (in this case, the output voltage or a value within the voltage domain).

[0137] like Figure 6 As shown, in one embodiment, S200 includes:

[0138] S220: Based on the training data set and the circuit model indicators, determine the types of components of the analog circuit and the working modes of different components of the analog circuit.

[0139] First, it is necessary to carefully analyze the analog circuit information contained in the training data set, especially the components of the circuit (such as resistors, capacitors, inductors, transistors, diodes, etc.) and the working modes of these components in the circuit (such as linear region, saturation region, cutoff region, etc.). This information is crucial to understanding the behavior and characteristics of the circuit.

[0140] S240: Determine the target analog input signal type according to the analog circuit component type and the analog circuit operation mode.

[0141] After understanding the components and operating mode of the circuit, the next step is to determine the type of target analog input signal. This usually depends on the design purpose and operating environment of the circuit. For example, if the circuit is an amplifier, then the target input signal may be some form of AC signal; if the circuit is a filter, then the target input signal may contain frequency components that need to be filtered out.

[0142] S260: Selecting an activation function type corresponding to the analog circuit design according to the target analog input signal type.

[0143] Activation functions are used in neural networks to introduce nonlinearity so that the model can learn complex mapping relationships. In analog circuit design, the concept of "activation function" can be analogized to nonlinear elements or circuit characteristics in the circuit, which determine how the circuit responds to different input signals. Depending on the type of target analog input signal and the characteristics of the circuit, a suitable "type of activation function" can be selected or designed. This actually refers to determining which nonlinear elements or characteristics in the circuit will dominate the circuit's response to the input signal. For example: If the transistor in the circuit operates in the saturation region, its output characteristics may be similar to a hard limiting function, that is, when the input exceeds a certain threshold, the output remains unchanged. If the circuit contains multiple cascaded amplifiers, its overall response may be a composite function of multi-stage amplification, similar to the multi-layer activation function in a deep neural network.

[0144] According to the CMOS principle and negative feedback system introduced, the core partial classification mode is designed. Figure 7 That is, the block diagram of the partial classification mode, in which the error amplifier EA with a high amplification factor and the active linear resistor Ract1 form a feedforward transmission network; the MOS tube switches MS1 and MS2 are under the control signal V ctrl1 、Vctrl2 Under the action of , a feedback transmission network is formed; the signal is introduced into the input port of the error amplifier EA to realize the anti-phase summation.

[0145] Based on the above classification mode block diagram design, two sets of feedback circuits are further designed to ensure the safety and normal operation of the circuit while forming a combined mode circuit for data classification. In order to establish the connection between digital signal representation and this design, it is possible to consider 0 and 1 logic signals as low and high levels of analog signal input for classification. Among them, the analog signal input voltage is lower than the threshold V low When the analog signal input voltage is higher than the threshold V high The default is high level.

[0146] Take the specific implementation of analog circuit as an example:

[0147] 1. PMOS+NMOS

[0148] The gate of M1 is connected to V G，PMOS1 Voltage, the gate of M2 is connected to V G，NMOS2 The voltage is connected to the drains of M1 and M2. The inverting input of the operational amplifier is connected to V IN1 Voltage, set V G，PMOS1 =V G，NMOS2 =V IN1 , the circuit has three configurable operating modes (as shown in Figure 8(a)).

[0149] 1.M1 does not work, M2 works

[0150] V IN1 Input high level, the working principle of this mode is shown in Figure 8(b). When M1 is not working, it is equivalent to an open switch. When M2 is working, it is equivalent to a closed switch and a resistor in series. At this time, V fb1 = 0, the high gain characteristic of the error operational amplifier EA will reduce the active resistance M p1 resistance value, so that the output V out1 is strongly pulled up to the supply voltage V DD That is, V is obtained through negative feedback regulation of the circuit. out1 =V DD .

[0151] 2.M1 work, M2 work

[0152] V IN1 Input intermediate level, the working principle of this mode is shown in Figure 8(c). The PMOS and NMOS used can work simultaneously within a certain voltage range. When M1 and M2 are working, they can be equivalent to a closed switch and a resistor in series. The negative feedback regulation characteristics of the loop will adjust the active resistor M p1The resistance value makes By design size, ensuring that the resistance values ​​of M1 and M2 can be considered equal within the error range, then R PMOS1 =R NMOS2 , so we can get V out1 =2V IN1 .

[0153] 3.M1 works, M2 doesn't work

[0154] V IN1 Input low level (voltage is not equal to 0, the level is considered to be 0), the working principle of this mode is shown in Figure 8 (d). When M2 is not working, it is equivalent to an open switch. When M1 is working, it is equivalent to a closed switch and a resistor in series. At this time, V fb1 =V out1 , the high gain characteristic of the error amplifier EA will adjust the active resistor M p1 resistance value, so that the output V out1 Can be equal to the input V IN1 , that is, V is obtained through negative feedback regulation of the circuit out1 =V IN1 .

[0155] 2. NMOS+PMOS

[0156] The gate of M3 is connected to V G，NMOS3 Voltage, the gate of M4 is connected to V G，PMOS4 The source of M3 and M4 are connected, and depletion-type MOS devices are used. The inverting input of the operational amplifier is connected to V IN2 Voltage, set V G，NMOS3 =V G，PMOS4 =V IN2 , the circuit has three configurable operating modes (as shown in Figure 9(a)).

[0157] 1.M3 works, M4 doesn't work

[0158] V IN2 Input high level, the working principle of this mode is shown in Figure 9(b). When M4 is not working, it is equivalent to an open switch. When M3 is working, it is equivalent to a closed switch and a resistor in series. At this time, V fb2 =V out2 , the high gain characteristic of the error amplifier EA will adjust the active resistor M p2 resistance value, so that the output V out2 Can be equal to the input V IN2 , that is, V is obtained through negative feedback regulation of the circuit out2 =V IN2 .

[0159] 2.M3 work, M4 work

[0160] V IN2 Input intermediate level, the working principle of this mode is shown in Figure 9 (c). Although NMOS can work simultaneously with PMOS within a certain voltage range, when M3 and M4 are working, they can be equivalent to a closed switch in series with a resistor. The negative feedback regulation characteristics of the loop will adjust the active resistor M p2 The resistance value makes By design size, ensuring that the resistance values ​​of M3 and M4 can be considered equal within the error range, then R PMOS4 =R NMOS3 , so we can get V out2 =2V IN2 .

[0161] 3.M3 does not work, M4 does

[0162] V IN2 Input low level, the working principle of this mode is shown in Figure 9 (d). When M3 is not working, it is equivalent to an open switch. When M4 is working, it is equivalent to a closed switch and a resistor in series. At this time, V fb2 = 0, the high gain characteristic of the error operational amplifier EA will reduce the active resistance M p2 resistance value, so that the output V out2 is strongly pulled up to the supply voltage V DD That is, V is obtained through negative feedback regulation of the circuit. out2 =V DD .

[0163] In one embodiment, the analog circuit component device types include NMOS and PMOS;

[0164] Determining the target analog input signal type according to the analog circuit component type and the analog circuit working mode includes: determining the level signals corresponding to the input signal and output signal of the analog circuit according to the analog circuit component type and the analog circuit working mode; determining the target analog input signal type according to the corresponding level signals.

[0165] First, it is necessary to understand how the various components in the analog circuit (such as resistors, capacitors, inductors, transistors, etc.) affect the transmission and transformation of signals. This includes understanding the electrical characteristics of the device, such as the voltage-current relationship, frequency response, etc. Next, according to the topology of the circuit and the working mode of the device, analyze how the input signal passes through the various parts of the circuit and how these parts process the signal (such as amplification, attenuation, filtering, etc.). In this process, special attention should be paid to the level change of the signal, that is, the voltage or current level of the signal in the circuit. Through the above analysis, the level signal range of the input signal and output signal of the analog circuit in the circuit can be determined. This usually involves parameters such as the amplitude, DC bias, and AC component of the signal. After determining the level signals of the input and output signals, the next step is to determine the type of the target analog input signal based on these level signals.

[0166] Let’s continue with the above NMOS and PMOS examples. In the above analysis, the output is V DD The working mode will significantly affect the classification and is not considered. Therefore, we add the characterization analysis and select V IN1 Input mid-level and V IN2 The input intermediate level is respectively used as V IN1 The high level upper limit and V IN2 The lower limit of the low level.

[0167] V out1 and V out2 Then connect the voltage to current circuit, design a reasonable resistance value, and achieve the current addition effect by connecting the circuit in parallel. The final voltage output can be based on V IN1 and V IN2 The logic signal value is simplified and the result is shown in Table 1.

[0168] Table 1 Classification of circuit working modes

[0169]

[0170] Analysis shows that

[0171] V IN1，l <V IN1，h , V IN2，l <V IN2，h

[0172] Since V IN1，l <V low1 <V high1 <V IN1，h and V IN2，l <V low2 <V high2 <V IN2，h , affected by the threshold setting, further analysis shows:

[0173] V IN1，l <V IN2，l <<V IN1，h <V IN2，h

[0174] According to the working modes listed in the table, we can get:

[0175] V IN1，l +2V IN2，l <V IN1，l +V IN2，h <2V IN1，h +2V IN2，l <2V IN1，h +V IN2，h

[0176] There is a positive proportional mapping relationship between the overall output of the module and the output of the submodule. Multiply each term in the inequality by the mapping coefficient defined by the subsequent module, and the output relationship is as follows:

[0177] V out，ll <V out.lh <V out，hl <V out，hh

[0178] At this point, the two different sets of analog input signals can be fully classified, and after the access of different excitation functions, they can be compressed to the required number of classifications, completing the initial training effect of the neural network, and have the possibility of being applied to the reasoning process while running.

[0179] Based on the above processing, the following analysis is made on the activation function type.

[0180] The classification circuit can realize full classification of multiple input signals. In order to facilitate signal transmission, calculation and use, the activation function is used to compress the existing results to achieve the classification effect. Taking the four-classification results as an example, the compressed classification display is shown in Table 2.

[0181] Table 2 Activation function compression classification mode

[0182]

[0183] Some classification methods are not shown in the effect, such as the classification method consisting of four categories, which does not require special activation function processing and completes the classification after the classification mode is completed.

[0184] Commonly used activation functions include Sigmoid, Tanh, ReLU, etc. In addition to functions that perform nonlinear transformations on input information, linear activation functions can also be used for processing.

[0185] The Sigmoid function expression is:

[0186]

[0187] The analytical expression of Tanh function is:

[0188]

[0189] The mathematical expression of the ReLU function is:

[0190] ReLU=max(0,x).

[0191] (1) The “4+0” and “3+1” mode classification can be completed by setting the threshold;

[0192] (2) The derivative of the S-shaped curve can be obtained as a parabolic function, which can be used to implement the "2+2" model classification;

[0193] (3) The S-curve can easily classify the input into the “1+2+1” pattern.

[0194] The Sigmoid function is a typical S-shaped curve. The Sigmoid approximation curve composed of four nonlinear curves is realized based on the VI nonlinear curve of the CMOS tube. Since the intermediate value part of the independent variable is not directly realized by linear expression, more accurate difference design can be obtained in practical applications, thereby improving the compression mapping accuracy of the activation function.

[0195] For each pair of CMOS connections, NMOS and PMOS take different gradient gate bias voltages, so that the circuit has two sections of change trends from OFF to saturation, showing an S-curve effect. As the input changes from negative to positive, NMOS and PMOS are turned on successively, and the output voltage changes due to the change of the equivalent resistance of the MOS tube, and four sections of continuous nonlinear Sigmoid approximate function curves are obtained, completing the post-processing of the classification circuit.

[0196] In one embodiment, before obtaining the spatial distribution and processing mode corresponding to the analog circuit design based on the trained neural network, the method further includes:

[0197] The transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network of the neural network circuit model verified by simulation are obtained; the negative feedback system is used to adjust the feedforward transmission to obtain the input signal relationship function IN(s) and the output signal relationship function OUT(s) of the neural network circuit model verified by simulation; based on the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function INN(s) and the output signal relationship function OUT(s), detect whether the neural network circuit model verified by simulation is qualified; if unqualified, return the activation function type corresponding to the analog circuit design based on the training data set and the circuit model indicators.

[0198] Before applying the neural network circuit model verified by simulation, it is also necessary to detect whether the neural network circuit model verified by simulation is qualified. Specifically, this detection process includes: judging whether the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function INN(s) and the output signal relationship function OUT(s) satisfy the output signal domain input signal relationship; wherein, the output signal domain input signal relationship is:

[0199]

[0200] Furthermore, a negative feedback system is used to adjust the feedforward transmission content. The transfer function of the feedforward transmission network is defined as H(s), and the transfer function of the feedback transmission network is defined as G(s). According to the signal feedback path, after the feedback network detects the output change ΔOUT(s), it passes through the inverting unit and is added to the input signal at the adder to obtain the error signal IN(s)-G(s)*OUT(s). Subsequently, the error is amplified by the feedforward path and the output is corrected so that the output signal returns to the expected value.

[0201] The output signal relationship is as follows:

[0202] OUT n+1 (s)=H(s)*[IN(s)-G(s)*OUT n (s)]

[0203] After the feedback system is stabilized, the relationship between the output signal and the input signal can be obtained as follows:

[0204]

[0205] If it is found that the output signal and the input signal in the neural network circuit model verified by simulation do not satisfy the above relationship, it is necessary to return to the step of designing the activation function type corresponding to the simulation circuit design based on the training data set and circuit model indicators, and restart the training.

[0206] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0207] Based on the same inventive concept, the embodiment of the present application also provides a neural network-based analog circuit design device for implementing the above-mentioned neural network-based analog circuit design method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above-mentioned method, so the specific limitations in one or more embodiments of the neural network-based analog circuit design device provided below can refer to the limitations of the neural network-based analog circuit design method above, and will not be repeated here.

[0208] In one embodiment, Fig.10 As shown, a neural network-based analog circuit design device is provided, comprising:

[0209] The data set acquisition module 100 is used to acquire a training data set for analog circuit design;

[0210] A type selection module 200 is used to design an activation function type corresponding to the analog circuit design based on the training data set and the circuit model index;

[0211] An identification module 300 is used to identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the neuron circuit module for the training data set based on the number of neurons;

[0212] A model building module 400 is used to perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution, and to build a neural network training circuit of a multi-level complex neuron group;

[0213] The model training module 500 is used to train the neural network training circuit of the multi-level complex neuron group using the training data set to obtain a neural network circuit model verified by simulation.

[0214] In one embodiment, the data set acquisition module 100 is further used to acquire required data and input voltage domain for analog circuit design; and perform data mapping according to the required data and input voltage domain to obtain a training data set.

[0215] In one of the embodiments, the type selection module 200 is also used to determine the types of components of the analog circuit and the working modes of different components of the analog circuit based on the training data set and circuit model indicators; determine the target analog input signal type according to the types of components of the analog circuit and the working mode of the analog circuit; and select the activation function type corresponding to the analog circuit design according to the target analog input signal type.

[0216] In one embodiment, the types of components of the analog circuit include NMOS and PMOS; the type selection module 200 is also used to determine the level signals corresponding to the input signals and output signals of the analog circuit according to the types of components of the analog circuit and the analog circuit working mode; and determine the target analog input signal type according to the corresponding level signals.

[0217] In one embodiment, the activation functions include Sigmoid and Tanh.

[0218] In one embodiment, the design module 600 is also used to obtain the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network of the neural network circuit model verified by simulation; adopt a negative feedback system to adjust the feedforward transmission to obtain the input signal relationship function IN(s) and the output signal relationship function OUT(s) of the neural network circuit model verified by simulation; based on the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), detect whether the neural network circuit model verified by simulation is qualified; if unqualified, the control type selection module 200 re-executes the activation function type corresponding to the analog circuit design based on the training data set and the circuit model indicators.

[0219] In one embodiment, the design module 600 is further used to determine whether the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s) satisfy the output signal domain input signal relationship; wherein the output signal domain input signal relationship is:

[0220]

[0221] Each module in the above-mentioned analog circuit design device based on neural network can be implemented in whole or in part by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0222] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig.11 As shown. The computer device includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store preset data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for analog circuit design based on a neural network is implemented.

[0223] Those skilled in the art will understand that Fig.11 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0224] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above-mentioned neural network-based analog circuit design method when executing the computer program.

[0225] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned analog circuit design method based on neural network is implemented.

[0226] In one embodiment, a computer program product is provided, including a computer program, which implements the above-mentioned neural network-based analog circuit design method when executed by a processor.

[0227] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited thereto.

[0228] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0229] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for designing analog circuits based on a neural network, characterized in that: The method comprises: Obtain training data sets for analog circuit design; Based on the training data set and the circuit model index, design an activation function type corresponding to the analog circuit design; Identifying the number of neurons corresponding to the initial neural network, and determining the processing mode and spatial distribution of the training data set by the neuron circuit module based on the number of neurons; Perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution to construct a neural network training circuit of a multi-layer complex neuron group; The training data set is used to train the neural network training circuit of the multi-level complex neuron group to obtain a neural network circuit model verified by simulation.

2. The method according to claim 1, characterized in that The obtaining of a training data set for analog circuit design comprises: Obtain the required data and input voltage domain for analog circuit design; Data mapping is performed according to the required data and the input voltage domain to obtain a training data set.

3. The method according to claim 1, characterized in that The activation function type corresponding to the analog circuit design based on the training data set and the circuit model index includes: Based on the training data set and the circuit model indicators, determining the types of components of the analog circuit and the working modes of different components of the analog circuit; Determine the target analog input signal type according to the analog circuit component type and the analog circuit operation mode; According to the target analog input signal type, an activation function type corresponding to the analog circuit design is selected.

4. The method according to claim 3, characterized in that The analog circuit component types include NMOS and PMOS; Determining the target analog input signal type according to the analog circuit component type and the analog circuit operation mode includes: Determine the level signals corresponding to the input signals and output signals of the analog circuit according to the types of components of the analog circuit and the working mode of the analog circuit; The target analog input signal type is determined according to the corresponding level signal.

5. The method according to claim 1, characterized in that The activation functions include Sigmoid and Tanh.

6. The method according to claim 1, characterized in that Before obtaining the spatial distribution and processing mode corresponding to the analog circuit design based on the trained neural network, the method further includes: Obtaining the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network of the neural network circuit model verified by simulation; Adopting a negative feedback system to adjust the feedforward transmission mode, the input signal relationship function IN(s) and the output signal relationship function OUT(s) of the neural network circuit model verified by simulation are obtained; Based on the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), detecting whether the neural network circuit model verified by simulation is qualified; If it fails, the activation function type corresponding to the analog circuit design is designed based on the training data set and the circuit model index.

7. The method according to claim 6, characterized in that The transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, as well as the input signal relationship function IN(s) and the output signal relationship function OUT(s), detecting whether the neural network circuit model verified by simulation is qualified includes: Determine whether the transfer function H(s) of the feedforward transmission network and the transfer function G(s) of the feedback transmission network, and the input signal relationship function INN(s) and the output signal relationship function OUT(s) satisfy the output signal domain input signal relationship; wherein the output signal domain input signal relationship is:

8. A neural network-based analog circuit design device, characterized in that: The device comprises: A data set acquisition module, used to acquire a training data set for analog circuit design; A type selection module, used to design an activation function type corresponding to the analog circuit design based on the training data set and the circuit model indicator; An identification module, used to identify the number of neurons corresponding to the initial neural network, and determine the processing mode and spatial distribution of the training data set by the neuron circuit module based on the number of neurons; A model building module, used to perform analog circuit design according to the activation function type and the determined processing mode and spatial distribution, and to build a neural network training circuit of a multi-level complex neuron group; The model training module is used to train the neural network training circuit of the multi-level complex neuron group using the training data set to obtain a neural network circuit model verified by simulation.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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