Memory module related to signal integrity of clock

Abstract

The invention relates to a memory module related to signal integrity of a clock. A memory module includes a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock by delaying a divided clock generated from the external clock by a clock delay interval, the internal clock being transmitted to a memory chip. The clock driver adjusts a clock delay interval by comparing a phase of the divided clock with a phase of a feedback divided clock generated from the internal clock.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2023-0093434, filed on July 18, 2023, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to memory modules, and more specifically to memory modules related to clock signal integrity. Background Technology

[0004] Typically, a memory module comprises multiple memory chips mounted on a substrate. Each memory chip within the memory module performs various internal operations by receiving clock, command, and address information from a memory controller. When clock, command, and address information is applied from the memory controller to the memory chip, signal integrity (SI) must be ensured. Specifically, as the operating speed of memory modules increases, ensuring the signal integrity of clocks applied at high frequencies becomes even more critical. Summary of the Invention

[0005] In one embodiment, a memory module may include a clock driver configured to receive an external clock via a module pin and to generate an internal clock by delaying a clock delay interval using a divided clock generated from the external clock, the internal clock being transmitted to the memory chip. In one embodiment, the clock driver may adjust the clock delay interval by comparing the phase of the divided clock with the phase of a feedback divided clock generated from the internal clock.

[0006] In one embodiment, a memory module may include a clock driver configured to receive an external clock via a module pin and to generate an internal clock by delaying a clock delay interval using a divided clock generated from the external clock, the internal clock being transmitted to the memory chip. In one embodiment, the clock driver may adjust the clock delay interval by comparing the phase of an external buffer clock generated from the external clock with the phase of a feedback buffer clock generated from the internal clock.

[0007] In one embodiment, a memory module may include a clock driver configured to receive an external clock via a module pin and to generate an internal clock by delaying a divided clock generated from the external clock by a clock delay interval, the internal clock being transmitted to a memory chip. In one embodiment, the clock driver may include: a first phase detection circuit configured to generate a first delay control signal by comparing the phase of a divided clock with the phase of a feedback divided clock; a first clock delay circuit configured to generate a first selected delay divided clock by delaying the divided clock by the first clock delay interval, the first clock delay interval being set based on the first delay control signal and a drive control signal; a second phase detection circuit configured to generate a second delay control signal by comparing the phase of the divided clock with the phase of the feedback divided clock; and a second clock delay circuit configured to generate a second selected delay divided clock by delaying the divided clock by the second clock delay interval, the second clock delay interval being set based on the second delay control signal and the drive control signal.

[0008] In one embodiment, a memory module may include a clock driver configured to receive an external clock via a module pin and to generate an internal clock by delaying a divided clock generated from the external clock by a clock delay interval, the internal clock being transmitted to a memory chip. In one embodiment, the clock driver may include: a phase detection circuit configured to generate a delay control signal by comparing the phase of a divided clock with the phase of a feedback divided clock; a first clock delay circuit configured to generate a first selected delay divided clock by delaying the divided clock by a first clock delay interval, the first clock delay interval being set based on the delay control signal and a drive control signal; and a second clock delay circuit configured to generate a second selected delay divided clock by delaying the divided clock by a second clock delay interval, the second clock delay interval being set based on the delay control signal and the drive control signal.

[0009] In one embodiment, a memory module may include a clock driver configured to receive an external clock via a module pin and configured to generate an internal clock by delaying an external buffer clock generated from the external clock by a clock delay interval, the internal clock being transmitted to the memory chip. In one embodiment, the clock driver may adjust the clock delay interval by comparing the phase of the external buffer clock with the phase of a feedback buffer clock generated from the internal clock. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating the construction of a memory module according to an example of this disclosure.

[0011] Figure 2This is a block diagram illustrating the construction of a clock driver according to an example of this disclosure.

[0012] Figure 3 This is a block diagram illustrating the construction of a clock delay circuit according to an example of this disclosure.

[0013] Figure 4 This is a block diagram illustrating the construction of a delay-divided clock generation circuit according to an example of this disclosure.

[0014] Figures 5 to 9 This is a diagram illustrating the operation of a delay-divided clock generation circuit according to an example of this disclosure.

[0015] Figure 10 This is a circuit diagram of a delay-division clock drive circuit according to an example of this disclosure.

[0016] Figures 11 to 13 It is a waveform used to describe the operation of a delay-division clock drive circuit according to an example of this disclosure.

[0017] Figure 14 This is a block diagram illustrating the construction of a clock delay circuit according to another example of this disclosure.

[0018] Figure 15 This is a block diagram illustrating the construction of a clock driver according to another example of this disclosure.

[0019] Figure 16 This is a block diagram illustrating the construction of a clock driver according to yet another example of this disclosure.

[0020] Figure 17 This is a block diagram illustrating the construction of a clock driver according to yet another example of this disclosure.

[0021] Figure 18 This is a block diagram illustrating the construction of a clock driver according to yet another example of this disclosure.

[0022] Figure 19 This is a block diagram illustrating the construction of a memory system according to an example of this disclosure.

[0023] Figure 20 This is a block diagram illustrating the construction of an electronic system according to an example of this disclosure.

[0024] Figure 21 This is a block diagram illustrating the construction of an electronic system according to another example of this disclosure. Detailed Implementation

[0025] In the following description of embodiments, the term "preset" indicates that the value of a parameter is predetermined when it is used in a process or algorithm. According to one embodiment, the value of a parameter may be set at the start of the process or algorithm or during the execution of the process or algorithm.

[0026] Terms such as "first" and "second" used to distinguish between various components are not limited to any particular component. For example, a first component can be referred to as a second component, and vice versa.

[0027] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that these components may be directly coupled or connected to each other, or coupled or connected to each other through another component inserted between them. In contrast, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or connected to each other without any other component inserted between them.

[0028] "Logic high" and "logic low" are used to describe the logic level of a signal. A signal with a "logic high" is different from a signal with a "logic low". For example, when a signal with a first voltage corresponds to a signal with a "logic high", a signal with a second voltage can correspond to a signal with a "logic low". According to one embodiment, a "logic high" can be set to a voltage higher than a "logic low". According to one embodiment, the logic level of a signal can be set to different logic levels or opposite logic levels. For example, in some embodiments, a signal with a logic high can be set to a logic low, and in some embodiments, a signal with a logic low can be set to a logic high.

[0029] A "logic bit set" can refer to the combination of logic levels of the bits included in a signal. The logic bit set of a signal can be set differently when the logic level of each bit included in the signal changes. For example, if two bits are included in a signal, the logic bit set of the signal can be set to the first logic bit set when the logic levels of the two bits included in the signal are "logic low" and "logic high," and the logic bit set of the signal can be set to the second logic bit set when the logic levels of the two bits included in the signal are "logic low" and "logic high."

[0030] The present disclosure will be described in more detail below by way of examples. The examples are for illustrative purposes only, and the scope of the present disclosure is not limited by the examples.

[0031] Figure 1 This is a block diagram illustrating the construction of a memory module 1 according to an example of this disclosure. Figure 1As shown, memory module 1 may include clock driver (CLK DRV) 11, module pins 13, clock lines 15_1 to 15_4 and memory chips (MC) 171_1 to 171_16.

[0032] Clock driver 11 can receive signals from the memory controller via module pin 13. Figure 19 The external clock ECLK is applied (61) in the clock driver 11. The clock driver 11 can delay the frequency division clock generated from the external clock ECLK. Figure 2 The internal clock ICLK is generated by comparing the frequency divider (DCLK) with the memory chips 171_1 to 171_16. Figure 2 The phase of DCLK and the feedback divider clock generated from the internal clock ICLK (in the clock) Figure 2 The phase of the FDCLK in the clock driver 11 can be adjusted by the frequency division clock (FDCLK). Figure 2 The clock delay interval (DCLK) is delayed. Clock driver 11 can ensure the signal integrity of the internal clock ICLK by: when jitter occurs in the internal clock ICLK due to voltage and temperature changes, by using a frequency-divided clock (DCLK) to... Figure 2 The phase of DCLK in the clock and the feedback divider clock ( Figure 2 The comparison between the phases of FDCLK in the clock is used to adjust the frequency division clock (FDCLK). Figure 2 The DCLK in the clock is delayed by a clock delay interval to remove jitter that occurs in the internal clock ICLK.

[0033] Clock driver 11 can transmit internal clock ICLK to memory chips 171_1 to 171_16 via clock lines 15_1 to 15_4. Clock lines 15_1 to 15_4 may include a first clock line 15_1, a second clock line 15_2, a third clock line 15_3, and a fourth clock line 15_4. Memory chips 171_1 to 171_16 may include first memory chip groups 171_1, 171_2, 171_3, and 171_4; second memory chip groups 171_5, 171_6, 171_7, and 171_8; third memory chip groups 171_9, 171_10, 171_11, and 171_12; and fourth memory chip groups 171_13, 171_14, 171_15, and 171_16. Clock driver 11 can transmit its internal clock ICLK to first memory chipsets 171_1, 171_2, 171_3, and 171_4 via a first clock line 15_1. Clock driver 11 can transmit its internal clock ICLK to second memory chipsets 171_5, 171_6, 171_7, and 171_8 via a second clock line 15_2. Clock driver 11 can transmit its internal clock ICLK to third memory chipsets 171_9, 171_10, 171_11, and 171_12 via a third clock line 15_3. Clock driver 11 can transmit its internal clock ICLK to fourth memory chipsets 171_13, 171_14, 171_15, and 171_16 via a fourth clock line 15_4.

[0034] Figure 2 This is a block diagram illustrating the construction of a clock driver 11A according to an example of a clock driver 11. (See diagram for example.) Figure 2 As shown, the clock driver 11A may include external clock pads (ECLK PAD) 111_1 and 111_2, clock buffer (BUF) 113, frequency divider clock generation circuit (DCLK GEN) 115, phase detection circuit (PD) 117, clock delay circuit (DL) 119, clock transmission circuit (TX) 121_1 to 121_4, feedback buffer (FBUF) 123, feedback frequency divider clock generation circuit (FDCLK GEN) 125, and internal clock pads (ICLK PAD) 127_1 to 127_4.

[0035] Clock driver 11A can receive clock signals from the memory controller via external clock pads 111_1 and 111_2. Figure 1961) External clocks ECLK1 and ECLK2 are applied. External clocks ECLK1 and ECLK2 may include a first external clock ECLK1 and a second external clock ECLK2. The first external clock ECLK1 can be received through external clock pad 111_1. The second external clock ECLK2 can be received through external clock pad 111_2. The phase of the first external clock ECLK1 and the phase of the second external clock ECLK2 may be out of phase with respect to each other, but this is only one embodiment, and this disclosure is not limited to this embodiment.

[0036] Clock buffer 113 can be connected to external clock pads 111_1 and 111_2, and can receive a first external clock ECLK1 and a second external clock ECLK2 from external clock pads 111_1 and 111_2. Clock buffer 113 can generate an external buffer clock EBCLK based on the first external clock ECLK1 and the second external clock ECLK2. Clock buffer 113 can be implemented to generate the external buffer clock EBCLK by differentially amplifying the first external clock ECLK1 and the second external clock ECLK2, but this is only one embodiment, and this disclosure is not limited to this embodiment.

[0037] The frequency divider clock generation circuit 115 can be connected to the clock buffer 113 and can receive an external buffer clock EBCLK from the clock buffer 113. The frequency divider clock generation circuit 115 can generate a frequency divider clock DCLK based on the external buffer clock EBCLK. The frequency divider clock DCLK can be generated as a "2N" division signal of the external buffer clock EBCLK. The frequency divider clock DCLK can be set to have a period that is "2N" times the period of the external buffer clock EBCLK. In this case, "N" can be set to a natural number. The frequency divider clock DCLK can include multiple frequency divider clocks. According to one embodiment, the difference between the phases of the frequency divider clocks included in the frequency divider clock DCLK and the number of frequency divider clocks can be set differently.

[0038] Phase detection circuit 117 can be connected to frequency divider clock generation circuit 115 and feedback frequency divider clock generation circuit 125, and can receive frequency divider clock DCLK from frequency divider clock generation circuit 115 and feedback frequency divider clock FDCLK from feedback frequency divider clock generation circuit 125. Phase detection circuit 117 can generate delay control signal SFT based on frequency divider clock DCLK and feedback frequency divider clock FDCLK. By comparing the phase of frequency divider clock DCLK and the phase of feedback frequency divider clock FDCLK, phase detection circuit 117 can generate delay control signal SFT for adjusting the clock delay interval of clock delay circuit 119. According to one embodiment, delay control signal SFT can be implemented with one bit or more bits. According to one embodiment, the logic level of delay control signal SFT for adjusting the clock delay interval of clock delay circuit 119, or a set of logic bits included in delay control signal SFT, can be set differently. For example, when the phase of the divided clock DCLK is faster than the phase of the feedback divided clock FDCLK, the phase detection circuit 117 can generate a delay control signal SFT, the logic level or set of logic bits of which is set to increase the clock delay interval. As another example, when the phase of the divided clock DCLK is slower than the phase of the feedback divided clock FDCLK, the phase detection circuit 117 can generate a delay control signal SFT, the logic level or set of logic bits of which is set to decrease the clock delay interval. As yet another example, when the phase of the divided clock DCLK is the same as the phase of the feedback divided clock FDCLK, the phase detection circuit 117 can generate a delay control signal SFT, the logic level or set of logic bits of which is set to maintain the clock delay interval.

[0039] Clock delay circuit 119 can be connected to phase detection circuit 117 and can receive delay control signal SFT from phase detection circuit 117. Clock delay circuit 119 can generate a selected delayed clock SDCLKd by delaying the divided clock DCLK by a clock delay interval, and set the clock delay interval based on delay control signal SFT and drive control signals DCNT1 and DCNT2. Clock delay circuit 119 can generate a first delayed clock by delaying the divided clock DCLK by a first sub-delay interval based on delay control signal SFT. Figure 3 (DCLKd1 in the example). Clock delay circuit 119 may include unit delay units, each having a unit delay interval. Figure 4The clock delay circuit 119 can generate a second delayed clock (UD1(1) to UD1(16)) by delaying the clock delay interval based on the logic level or set of logic bits of the delay control signal SFT. For example, when the delay control signal SFT for increasing the clock delay interval is generated when the first sub-delay interval has been set to seven times the unit delay interval, the first sub-delay interval can be adjusted to become eight times the unit delay interval. As another example, when the delay control signal SFT for decreasing the clock delay interval is generated when the first sub-delay interval has been set to seven times the unit delay interval, the first sub-delay interval can be adjusted to become six times the unit delay interval. The clock delay circuit 119 can generate a second delayed clock by delaying the divided clock DCLK by a second sub-delay interval based on the delay control signal SFT. Figure 3 (DCLKd2 in the example). Clock delay circuit 119 may include unit delay units, each having a unit delay interval. Figure 4 The second sub-delay interval can be adjusted based on the logic level or set of logic bits of the delay control signal SFT. For example, when the delay control signal SFT for increasing the clock delay interval is generated in a state where the second sub-delay interval has been set to eight times the unit delay interval, the second sub-delay interval can be set to nine times the unit delay interval. As another example, when the delay control signal SFT for decreasing the clock delay interval is generated in a state where the second sub-delay interval has been set to eight times the unit delay interval, the second sub-delay interval can be set to seven times the unit delay interval. Preferably, the second sub-delay interval is set to be greater than the first sub-delay interval. In this embodiment, the second sub-delay interval has been set to be a unit delay interval larger than the first sub-delay interval, but this is only one embodiment, and this disclosure is not limited to this embodiment. The clock delay circuit 119 can adjust the clock delay interval to the interval between the first sub-delay interval and the second sub-delay interval based on the drive control signals DCNT1 and DCNT2. The drive control signals DCNT1 and DCNT2 may include the first drive control signal DCNT1 and the second drive control signal DCNT2. The first drive control signal DCNT1 and the second drive control signal DCNT2 can be generated within the memory module 1, or can be applied from outside the memory module 1, for example, from the memory controller. Figure 19 The clock delay circuit 119 can be applied based on the first delay divided clock (61) or a test device (not shown). Figure 3 The clock delay circuit 119 can be based on a second delay clock (SDCLKd1), which drives the selected delayed clock SDCLKd by a first drive power set by the first drive control signal DCNT1. Figure 3The first drive control signal DCNT1 and the second drive control signal DCNT2 can each include multiple bits. The drive power used to drive the selected delay-divided clock SDCLKd is driven by a second drive power set by the second drive control signal DCNT2.

[0040] Clock transmission circuits 121_1 to 121_4 can be connected to clock delay circuit 119 and can receive a selected delay divider clock SDCLKd from clock delay circuit 119. Clock transmission circuits 121_1 to 121_4 can generate internal clocks ICLK1 and ICLK2 based on the selected delay divider clock SDCLKd. Clock transmission circuits 121_1 to 121_4 may include a first clock transmission circuit 121_1, a second clock transmission circuit 121_2, a third clock transmission circuit 121_3, and a fourth clock transmission circuit 121_4. Internal clock pads 127_1 to 127_4 may include a first internal clock pad 127_1, a second internal clock pad 127_2, a third internal clock pad 127_3, and a fourth internal clock pad 127_4. Internal clocks ICLK1 and ICLK2 may include a first internal clock ICLK1 and a second internal clock ICLK2. The first clock transmission circuit 121_1 can generate a first internal clock ICLK1 from the selected delay-divided clock SDCLKd and output the first internal clock ICLK1 to the first internal clock pad 127_1. The first clock transmission circuit 121_1 can be implemented to generate the first internal clock ICLK1 with the same phase as the selected delay-divided clock SDCLKd. The second clock transmission circuit 121_2 can generate a second internal clock ICLK2 from the selected delay-divided clock SDCLKd and output the second internal clock ICLK2 to the second internal clock pad 127_2. The second clock transmission circuit 121_2 can be implemented to generate the second internal clock ICLK2 with a phase opposite to that of the selected delay-divided clock SDCLKd. The third clock transmission circuit 121_3 can generate the first internal clock ICLK1 from the selected delay-divided clock SDCLKd and output the first internal clock ICLK1 to the third internal clock pad 127_3. The third clock transmission circuit 121_3 can be implemented to generate a first internal clock ICLK1 having the same phase as the selected delay divider clock SDCLKd. The fourth clock transmission circuit 121_4 can generate a second internal clock ICLK2 from the selected delay divider clock SDCLKd and output the second internal clock ICLK2 to the fourth internal clock pad 127_4. The fourth clock transmission circuit 121_4 can be implemented to generate a second internal clock ICLK2 having a phase opposite to that of the selected delay divider clock SDCLKd. According to one embodiment, the first clock transmission circuit 121_1 and the third clock transmission circuit 121_3 can each be implemented to generate the first internal clock ICLK1 based on the selected delay divider clock SDCLKd, which has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2.According to one embodiment, the second clock transmission circuit 121_2 and the fourth clock transmission circuit 121_4 can each be implemented to generate a second internal clock ICLK2 based on a selected delay divider clock SDCLKd, the second internal clock ICLK2 being set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2.

[0041] Feedback buffer 123 can be connected to the first clock transmission circuit 121_1 and the second clock transmission circuit 121_2, and can receive a first internal clock ICLK1 from the first clock transmission circuit 121_1 and a second internal clock ICLK2 from the second clock transmission circuit 121_2. Feedback buffer 123 can generate a feedback buffer clock FBCLK based on the first internal clock ICLK1 and the second internal clock ICLK2. Feedback buffer 123 can be implemented to generate the feedback buffer clock FBCLK by differentially amplifying the first internal clock ICLK1 and the second internal clock ICLK2; however, this is only one embodiment, and this disclosure is not limited to this embodiment. Feedback buffer 123 can be implemented in the same way as clock buffer 113.

[0042] The feedback clock generation circuit 125 can be connected to the feedback buffer 123 and can receive the feedback buffer clock FBCLK from the feedback buffer 123. The feedback clock generation circuit 125 can generate a feedback clock FDCLK based on the feedback buffer clock FBCLK. The feedback clock FDCLK can be generated as a "2N" division signal of the feedback buffer clock FBCLK. The feedback clock FDCLK can be set to have a period that is "2N" times the period of the feedback buffer clock FBCLK. In this case, "N" can be set to a natural number. The feedback clock FDCLK can include multiple divided clocks. According to one embodiment, the difference between the phases of the divided clocks included in the feedback clock FDCLK and the number of divided clocks can be set differently. The feedback clock generation circuit 125 can be implemented identically to the clock generation circuit 115. The feedback clock generation circuit 125 can be connected to the phase detection circuit 117 and can transmit the feedback clock FDCLK to the phase detection circuit 117.

[0043] Figure 3 This is a block diagram illustrating the construction of a clock delay circuit 119A according to an example of a clock delay circuit 119. (See diagram for example.) Figure 3 As shown, the clock delay circuit 119A may include a first delay-divided clock generation circuit (DCLKd1GEN) 131_1, a second delay-divided clock generation circuit (DCLKd2GEN) 131_2, and a delay-divided clock drive circuit (DCLKd DRV) 133.

[0044] The first delay-divided clock generation circuit 131_1 can generate a first delay-divided clock DCLKd1 by delaying the divided clock DCLK by a first sub-delay interval based on the delay control signal SFT. The first delay-divided clock generation circuit 131_1 may include unit delay units, each with a unit delay interval. Figure 4 The first delayed clock generation circuit 131_1 can generate the first delayed clock DCLKd1 by delaying the first sub-delay interval of the divided clock DCLK by UD1(1) to UD1(16)). The first sub-delay interval can be set as an initial delay interval and adjusted based on the delay control signal SFT. For example, when the delay control signal SFT for increasing the clock delay interval is generated with the initial delay interval of the first sub-delay interval already set to seven times the unit delay interval, the first delayed clock generation circuit 131_1 can generate the first delayed clock DCLKd1 by adjusting the first sub-delay interval of the divided clock DCLK to eight times the unit delay interval. As another example, when the delay control signal SFT for decreasing the clock delay interval is generated with the initial delay interval of the first sub-delay interval already set to seven times the unit delay interval, the first delayed clock generation circuit 131_1 can generate the first delayed clock DCLKd1 by adjusting the first sub-delay interval of the divided clock DCLK to six times the unit delay interval.

[0045] The second delay-divided clock generation circuit 131_2 can generate a second delay-divided clock DCLKd2 by delaying the divided clock DCLK by a second sub-delay interval based on the delay control signal SFT. The second delay-divided clock generation circuit 131_2 may include unit delay units, each with a unit delay interval. Figure 4The second delayed clock frequency divider circuit 131_2 can generate the second delayed clock frequency divider clock DCLKd2 by delaying the divided clock DCLK by a second sub-delay interval. The second sub-delay interval can be set to the initial delay interval and adjusted based on the delay control signal SFT. For example, when the delay control signal SFT for increasing the clock delay interval is generated with the initial delay interval of the second sub-delay interval already set to eight times the unit delay interval, the second delayed clock frequency divider clock generation circuit 131_2 can generate the second delayed clock frequency divider clock DCLKd2 by adjusting the second sub-delay interval of the divided clock DCLK to nine times the unit delay interval. As another example, when the delay control signal SFT for decreasing the clock delay interval is generated with the initial delay interval of the second sub-delay interval already set to eight times the unit delay interval, the second delayed clock frequency divider clock generation circuit 131_2 can generate the second delayed clock frequency divider clock DCLKd2 by adjusting the second sub-delay interval of the divided clock DCLK to seven times the unit delay interval.

[0046] The delay-divided clock driving circuit 133 can be connected to the first delay-divided clock generation circuit 131_1 and the second delay-divided clock generation circuit 131_2. It can receive a first delayed-divided clock DCLKd1 from the first delayed-divided clock generation circuit 131_1 and a second delayed-divided clock DCLKd2 from the second delayed-divided clock generation circuit 131_2. The delay-divided clock driving circuit 133 can receive the first delayed-divided clock DCLKd1 and can drive the selected delayed-divided clock SDCLKd using a first drive power set by the first drive control signal DCNT1. The delay-divided clock driving circuit 133 can receive the second delayed-divided clock DCLKd2 and can drive the selected delayed-divided clock SDCLKd using a second drive power set by the second drive control signal DCNT2.

[0047] Figure 4 This is a block diagram illustrating the construction of a first delay-divided clock generation circuit 131_1A and a second delay-divided clock generation circuit 131_2A according to examples of a first delay-divided clock generation circuit 131_1 and a second delay-divided clock generation circuit 131_2.

[0048] The first delay-divided clock generation circuit 131_1A may include unit delayers UD1(1) to UD1(16), each unit delayer having a unit delay interval. The first delay-divided clock generation circuit 131_1A can generate a first delayed clock DCLKd1 by delaying the divided clock DCLK by a first sub-delay interval based on the delay control signal SFT. The first delay-divided clock generation circuit 131_1A can generate a first delayed clock DCLKd1 by delaying the divided clock DCLK by a first sub-delay interval that has been set to an initial delay interval. For example, when the initial delay interval of the first sub-delay interval has been set to seven times the unit delay interval, the first delay-divided clock generation circuit 131_1A can generate a first delayed clock DCLKd1 by delaying the divided clock DCLK via unit delayers UD1(1) to UD1(7). The first delay-divided clock generation circuit 131_1A can generate a first delayed clock DCLKd1 by delaying the divided clock DCLK by a first sub-delay interval adjusted based on the delay control signal SFT. For example, when a delay control signal SFT for increasing the clock delay interval is generated with the initial delay interval of the first sub-delay interval already set to seven times the unit delay interval, the first delay divider clock generation circuit 131_1A can generate the first delay divider clock DCLKd1 by delaying the divider clock DCLK via unit delayers UD1(1) to UD1(8). As another example, when a delay control signal SFT for decreasing the clock delay interval is generated with the initial delay interval of the first sub-delay interval already set to seven times the unit delay interval, the first delay divider clock generation circuit 131_1A can generate the first delay divider clock DCLKd1 by delaying the divider clock DCLK via unit delayers UD1(1) to UD1(6). The first delay divider clock generation circuit 131_1A can generate a minimum limit exceedance signal d_MIN, which is activated when the first sub-delay interval cannot be adjusted based on the delay control signal SFT. For example, the first delay divider clock generation circuit 131_1A can generate a minimum limit exceedance signal d_MIN, which is activated when a delay control signal SFT for reducing the clock delay interval is generated in a state where the first sub-delay interval has been set to twice the unit delay interval.

[0049] The second delay-divided clock generation circuit 131_2A may include unit delayers UD2(1) to UD2(16), each unit delayer having a unit delay interval. The second delay-divided clock generation circuit 131_2A can generate a second delayed clock DCLKd2 by delaying the divided clock DCLK by a second sub-delay interval based on the delay control signal SFT. The second delay-divided clock generation circuit 131_2A can also generate a second delayed clock DCLKd2 by delaying the divided clock DCLK by a second sub-delay interval that has been set to the initial delay interval. For example, when the initial delay interval of the second sub-delay interval has been set to eight times the unit delay interval, the second delay-divided clock generation circuit 131_2A can generate a second delayed clock DCLKd2 by delaying the divided clock DCLK via unit delayers UD2(1) to UD2(8). The second delay-divided clock generation circuit 131_2A can also generate a second delayed clock DCLKd2 by delaying the divided clock DCLK by a second sub-delay interval adjusted based on the delay control signal SFT. For example, when a delay control signal SFT for increasing the clock delay interval is generated with the initial delay interval of the second sub-delay interval already set to eight times the unit delay interval, the second delay divider clock generation circuit 131_2A can generate the second delay divider clock DCLKd2 by delaying the divider clock DCLK via unit delayers UD2(1) to UD2(9). As another example, when a delay control signal SFT for decreasing the clock delay interval is generated with the initial delay interval of the second sub-delay interval already set to eight times the unit delay interval, the second delay divider clock generation circuit 131_2A can generate the second delay divider clock DCLKd2 by delaying the divider clock DCLK via unit delayers UD2(1) to UD2(7). The second delay divider clock generation circuit 131_2A can generate a maximum limit exceedance signal d_MAX, which is activated when the second sub-delay interval cannot be adjusted based on the delay control signal SFT. For example, the second delay divider clock generation circuit 131_2A can generate a maximum limit exceedance signal d_MAX, which is activated when a delay control signal SFT for increasing the clock delay interval is generated in a state where the second sub-delay interval has been set to 16 times the unit delay interval.

[0050] Figures 5 to 9 This is a diagram illustrating the operation of a first delay-divided clock generation circuit 131_1A and a second delay-divided clock generation circuit 131_2A according to an example of this disclosure.

[0051] like Figure 5As shown, with the initial delay interval of the first sub-delay interval set to seven times the unit delay interval and the initial delay interval of the second sub-delay interval set to eight times the unit delay interval, the first delay-divided clock generation circuit 131_1A can generate the first delay-divided clock DCLKd1 by delaying and dividing the clock DCLK via seven unit delay units 7UD. The second delay-divided clock generation circuit 131_2A can generate the second delay-divided clock DCLKd2 by delaying and dividing the clock DCLK via eight unit delay units 8UD.

[0052] like Figure 5 and Figure 6 As shown, with the initial delay interval of the first sub-delay interval set to seven times the unit delay interval and the initial delay interval of the second sub-delay interval set to eight times the unit delay interval, when a delay control signal SFT with a logic low level "L" is generated to reduce the clock delay interval, the first delay divider clock generation circuit 131_1A can generate the first delay divider clock DCLKd1 via six unit delay units 6UD, and the second delay divider clock generation circuit 131_2A can generate the second delay divider clock DCLKd2 via seven unit delay units 7UD.

[0053] like Figure 5 and Figure 7 As shown, with the initial delay interval of the first sub-delay interval already set to seven times the unit delay interval and the initial delay interval of the second sub-delay interval already set to eight times the unit delay interval, when a delay control signal SFT with a logic high level "H" is generated to increase the clock delay interval, the first delay divider clock generation circuit 131_1A can generate the first delay divider clock DCLKd1 via eight unit delay units 8UD, and the second delay divider clock generation circuit 131_2A can generate the second delay divider clock DCLKd2 via nine unit delay units 9UD.

[0054] like Figure 8 As shown, when the first sub-delay interval has been set to one time the unit delay interval and the second sub-delay interval has been set to twice the unit delay interval, when a delay control signal SFT with a logic low level "L" is generated to reduce the clock delay interval, the first delay divider clock generation circuit 131_1A can generate a minimum limit exceeding the signal d_MIN that is activated as a logic high level "H", because the first sub-delay interval can no longer be reduced.

[0055] like Figure 9As shown, when the first sub-delay interval has been set to 15 times the unit delay interval and the second sub-delay interval has been set to 16 times the unit delay interval, when a delay control signal SFT with a logic high level "H" is generated to increase the clock delay interval, the second delay divider clock generation circuit 131_2A can generate a maximum limit of being activated as a logic high level "H" exceeding the signal d_MAX, because the second sub-delay interval can no longer be increased.

[0056] Figure 10 This is a circuit diagram of a delay-divided clock drive circuit 133A, as an example of a delay-divided clock drive circuit 133. (See diagram for example.) Figure 10 As shown, the delay-division clock drive circuit 133A may include a first clock drive circuit 141, a second clock drive circuit 143, and an output buffer 145.

[0057] The first clock driving circuit 141 can receive a first delayed frequency divider clock DCLKd1 and can drive node nd11 by a first driving power set by the first driving control signal DCNT1<1:L> and the first inverting driving control signal DCNT1B<1:L>. The first inverting driving control signal DCNT1B<1:L> can be generated by inverting the first driving control signal DCNT1<1:L>. The first driving power of the first clock driving circuit 141 can be adjusted based on the set of logic bits of the first driving control signal DCNT1<1:L> and the first inverting driving control signal DCNT1B<1:L>. As the number of logic high levels included in the set of logic bits of the first driving control signal DCNT1<1:L> and the number of logic high levels included in the set of logic bits of the first inverting driving control signal DCNT1B<1:L> increase, the first driving power of the first clock driving circuit 141 can be set to a large value.

[0058] The second clock drive circuit 143 can receive the second delayed frequency divider clock DCLKd2 and can drive node nd11 by a second drive power set by the second drive control signal DCNT2<1:L> and the second inverted drive control signal DCNT2B<1:L>. The second inverted drive control signal DCNT2B<1:L> can be generated by inverting the second drive control signal DCNT2<1:L>. The second drive power of the second clock drive circuit 143 can be adjusted based on the set of logic bits of the second drive control signal DCNT2<1:L> and the second inverted drive control signal DCNT2B<1:L>. As the number of logic high levels included in the set of logic bits of the second drive control signal DCNT2<1:L> and the number of logic high levels included in the set of logic bits of the second inverted drive control signal DCNT2B<1:L> increase, the second drive power of the second clock drive circuit 143 can be set to a large value.

[0059] Output buffer 145 can generate a selected delay-divided clock SDCLKd by inverting and buffering the signal at node nd11. As the first drive power of the first clock drive circuit 141 is set to a larger value and the second drive power of the second clock drive circuit 143 is set to a smaller value, the level transition timing of the selected delay-divided clock SDCLKd can be generated more similarly to the level transition timing of the first delay-divided clock DCLKd1 compared to the level transition timing of the second delay-divided clock DCLKd2. Furthermore, as the second drive power of the second clock drive circuit 143 is set to a larger value and the first drive power of the first clock drive circuit 141 is set to a smaller value, the level transition timing of the selected delay-divided clock SDCLKd can be generated more similarly to the level transition timing of the second delay-divided clock DCLKd2 compared to the level transition timing of the first delay-divided clock DCLKd1.

[0060] The clock delay circuit 119 can generate a selected delay divider clock SDCLKd by delaying the divided clock DCLK by a clock delay interval that has already been set between the first sub-delay interval and the second sub-delay interval. In this case, as the first drive power of the first clock drive circuit 141 is set to be larger and the second drive power of the second clock drive circuit 143 is set to be smaller, the clock delay interval can be set similarly to the first sub-delay interval. Furthermore, as the second drive power of the second clock drive circuit 143 is set to be larger and the first drive power of the first clock drive circuit 141 is set to be smaller, the clock delay interval can be set similarly to the second sub-delay interval.

[0061] Figures 11 to 13 This is a waveform used to describe the operation of the delay-division clock drive circuit 133A.

[0062] like Figure 11 As shown, with the first drive power of the first clock drive circuit 141 being set to a larger value and the second drive power of the second clock drive circuit 143 being set to a smaller value, the level transition timing of the selected delay clock SDCLKd can be generated similarly to the level transition timing of the first delay clock DCLKd1, compared to the level transition timing of the second delay clock DCLKd2. Therefore, the clock delay interval of the clock delay circuit 119 to which the divider clock DCLK is delayed can be set similarly to the first sub-delay interval.

[0063] like Figure 12 As shown, with the second drive power of the second clock drive circuit 143 set to a larger value and the first drive power of the first clock drive circuit 141 set to a smaller value, the level transition timing of the selected delay clock SDCLKd can be generated similarly to the level transition timing of the second delay clock DCLKd2, compared to the level transition timing of the first delay clock DCLKd1. Therefore, the clock delay interval of the clock delay circuit 119 for the delay clock DCLK can be set similarly to the second sub-delay interval.

[0064] like Figure 13 As shown, when the first driving power of the first clock driving circuit 141 and the second driving power of the second clock driving circuit 143 are set equally, the level transition timing of the selected delayed frequency divider clock SDCLKd can be set at the midpoint between the level transition timing of the first delayed frequency divider clock DCLKd1 and the level transition timing of the second delayed frequency divider clock DCLKd2. Therefore, the clock delay interval of the clock delay circuit 119 of the delayed frequency divider clock DCLK can be set to the midpoint interval between the first sub-delay interval and the second sub-delay interval.

[0065] Figure 14 This is a block diagram illustrating the construction of clock delay circuit 119B, according to another example of clock delay circuit 119. (See diagram for example.) Figure 14 As shown, the clock delay circuit 119B may include a delay-divided clock generation circuit (DCLKd GEN) 151 and a delay-divided clock drive circuit (DCLKd DRV) 153.

[0066] Based on the delay control signal SFT, the delay-divided clock generation circuit 151 can generate a first delayed clock DCLKd1 by delaying the divided clock DCLK by a first sub-delay interval, and generate a second delayed clock DCLKd2 by delaying the divided clock DCLK by a second sub-delay interval. The delay-divided clock generation circuit 151 may include unit delayers, each with a unit delay interval, and can generate the first delayed clock DCLKd1 by delaying the divided clock DCLK by a first sub-delay interval, and the second delayed clock DCLKd2 by delaying the divided clock DCLK by a second sub-delay interval. The first and second sub-delay intervals can each be set as initial delay intervals and can be adjusted based on the delay control signal SFT. For example, when a delay control signal SFT for increasing the clock delay interval is generated under the condition that the initial delay interval of the first sub-delay interval has been set to seven times the unit delay interval and the initial delay interval of the second sub-delay interval has been set to eight times the unit delay interval, the delay divider clock generation circuit 151 can generate a first delay divider clock DCLKd1 by adjusting the first sub-delay interval, which has been adjusted to eight times the unit delay interval, and can generate a second delay divider clock DCLKd2 by adjusting the second sub-delay interval, which has been adjusted to nine times the unit delay interval. As another example, when a delay control signal SFT for reducing the clock delay interval is generated under the condition that the initial delay interval of the first sub-delay interval has been set to seven times the unit delay interval and the initial delay interval of the second sub-delay interval has been set to eight times the unit delay interval, the delay divider clock generation circuit 151 can generate a first delay divider clock DCLKd1 by adjusting the delay of the divider clock DCLK to six times the unit delay interval of the first sub-delay interval, and can generate a second delay divider clock DCLKd2 by adjusting the delay of the divider clock DCLK to seven times the unit delay interval of the second sub-delay interval.

[0067] The delay-divided clock driving circuit 153 can be connected to the delay-divided clock generation circuit 151, and can receive a first delayed-divided clock DCLKd1 and a second delayed-divided clock DCLKd2 from the delay-divided clock generation circuit 151. The delay-divided clock driving circuit 153 can receive the first delayed-divided clock DCLKd1, and can drive the selected delayed-divided clock SDCLKd by a first drive power set by a first drive control signal DCNT1. The delay-divided clock driving circuit 153 can receive the second delayed-divided clock DCLKd2, and can drive the selected delayed-divided clock SDCLKd by a second drive power set by a second drive control signal DCNT2.

[0068] Figure 15 This is a block diagram illustrating the construction of a clock driver 11B according to another example of a clock driver 11. (See diagram for example.) Figure 15 As shown, the clock driver 11B may include external clock pads (ECLK PAD) 211_1 and 211_2, clock buffer (BUF) 213, frequency divider clock generation circuit (DCLK GEN) 215, phase detection circuit (PD) 217, clock delay circuit (DL) 219, clock transmission circuit (TX) 221_1 to 221_4, feedback buffer (FBUF) 223, and internal clock pads (ICLKPAD) 227_1 to 227_4.

[0069] Clock driver 11B can receive clock signals from the memory controller via external clock pads 211_1 and 211_2. Figure 19 The first external clock ECLK1 and the second external clock ECLK2 are applied in 61). The first external clock ECLK1 can be received through external clock pad 211_1. The second external clock ECLK2 can be received through external clock pad 211_2.

[0070] Clock buffer 213 can be connected to external clock pads 211_1 and 211_2, and can receive a first external clock ECLK1 and a second external clock ECLK2 from external clock pads 211_1 and 211_2. Clock buffer 213 can generate an external buffer clock EBCLK based on the first external clock ECLK1 and the second external clock ECLK2.

[0071] The frequency divider clock generation circuit 215 can be connected to the clock buffer 213 and can receive the external buffer clock EBCLK from the clock buffer 213. The frequency divider clock generation circuit 215 can generate the frequency divider clock DCLK based on the external buffer clock EBCLK.

[0072] Phase detection circuit 217 can be connected to clock buffer 213 and feedback buffer 223, and can receive external buffer clock EBCLK from clock buffer 213 and feedback buffer clock FBCLK from feedback buffer 223. Phase detection circuit 217 can generate delay control signal SFT based on external buffer clock EBCLK and feedback buffer clock FBCLK. By comparing the phase of external buffer clock EBCLK and the phase of feedback buffer clock FBCLK, phase detection circuit 217 can generate delay control signal SFT for adjusting the clock delay interval of clock delay circuit 219.

[0073] The clock delay circuit 219 can be connected to the phase detection circuit 217 and can receive the delay control signal SFT from the phase detection circuit 217. The clock delay circuit 219 can generate a selected delay divided clock SDCLKd by delaying the divided clock DCLK by a clock delay interval, and set the clock delay interval based on the delay control signal SFT and the drive control signals DCNT1 and DCNT2.

[0074] The first clock transmission circuit 221_1, the second clock transmission circuit 221_2, the third clock transmission circuit 221_3, and the fourth clock transmission circuit 221_4 can be connected to the clock delay circuit 219 and can receive the selected delay divided clock SDCLKd from the clock delay circuit 219. The first clock transmission circuit 221_1, the second clock transmission circuit 221_2, the third clock transmission circuit 221_3, and the fourth clock transmission circuit 221_4 can generate a first internal clock ICLK1 and a second internal clock ICLK2 based on the selected delay divided clock SDCLKd. The first clock transmission circuit 221_1 can generate the first internal clock ICLK1 with the same phase as the selected delay divided clock SDCLKd and can output the first internal clock ICLK1 to the first internal clock pad 227_1. The second clock transmission circuit 221_2 can generate the second internal clock ICLK2 with a phase opposite to the selected delay divided clock SDCLKd and can output the second internal clock ICLK2 to the second internal clock pad 227_2. The third clock transmission circuit 221_3 can generate a first internal clock ICLK1 with the same phase as the selected delay divider clock SDCLKd, and can output the first internal clock ICLK1 to the third internal clock pad 227_3. The fourth clock transmission circuit 221_4 can generate a second internal clock ICLK2 with a phase opposite to that of the selected delay divider clock SDCLKd, and can output the second internal clock ICLK2 to the fourth internal clock pad 227_4. According to one embodiment, the first clock transmission circuit 221_1 and the third clock transmission circuit 221_3 can each be implemented as follows: based on the selected delay divider clock SDCLKd, generating a first internal clock ICLK1 that has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2. According to one embodiment, the second clock transmission circuit 221_2 and the fourth clock transmission circuit 221_4 can each be implemented as generating a second internal clock ICLK2 that has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2, based on the selected delay divider clock SDCLKd.

[0075] Feedback buffer 223 can be connected to the first clock transmission circuit 221_1 and the second clock transmission circuit 221_2, and can receive a first internal clock ICLK1 from the first clock transmission circuit 221_1 and a second internal clock ICLK2 from the second clock transmission circuit 221_2. Feedback buffer 223 can generate a feedback buffer clock FBCLK based on the first internal clock ICLK1 and the second internal clock ICLK2. Feedback buffer 223 can be implemented in the same way as clock buffer 213.

[0076] Figure 16 This is a block diagram illustrating the construction of a clock driver 11C according to yet another example of a clock driver 11. (See diagram for example.) Figure 16 As shown, the clock driver 11C may include external clock pads (ECLK PAD) 311_1 and 311_2, clock buffer (BUF) 313, frequency divider clock generation circuit (DCLK GEN) 315, first phase detection circuit (PD1) 317_1, first clock delay circuit (DL1) 319_1, second phase detection circuit (PD2) 317_2, second clock delay circuit (DL2) 319_2, clock transmission circuit (TX) 321_1 to 321_4, feedback buffer (FBUF) 323, feedback frequency divider clock generation circuit (FDCLK GEN) 325, and internal clock pads (ICLK PAD) 327_1 to 327_4.

[0077] Clock driver 11C can receive clock signals from the memory controller via external clock pads 311_1 and 311_2. Figure 19 The first external clock ECLK1 and the second external clock ECLK2 are applied in 61). The first external clock ECLK1 can be received through external clock pad 311_1. The second external clock ECLK2 can be received through external clock pad 311_2.

[0078] Clock buffer 313 can be connected to external clock pads 311_1 and 311_2, and can receive a first external clock ECLK1 and a second external clock ECLK2 from external clock pads 311_1 and 311_2. Clock buffer 313 can generate an external buffer clock EBCLK based on the first external clock ECLK1 and the second external clock ECLK2.

[0079] The frequency divider clock generation circuit 315 can be connected to the clock buffer 313 and can receive the external buffer clock EBCLK from the clock buffer 313. The frequency divider clock generation circuit 315 can generate the frequency divider clock DCLK based on the external buffer clock EBCLK.

[0080] The first phase detection circuit 317_1 can be connected to the frequency divider clock generation circuit 315 and the feedback frequency divider clock generation circuit 325, and can receive the frequency divider clock DCLK from the frequency divider clock generation circuit 315 and the feedback frequency divider clock FDCLK from the feedback frequency divider clock generation circuit 325. The first phase detection circuit 317_1 can generate a first delay control signal SFT1 based on the frequency divider clock DCLK and the feedback frequency divider clock FDCLK. The first phase detection circuit 317_1 can generate the first delay control signal SFT1 for adjusting the clock delay interval of the first clock delay circuit 319_1 by comparing the phase of the frequency divider clock DCLK and the phase of the feedback frequency divider clock FDCLK.

[0081] The first clock delay circuit 319_1 can be connected to the first phase detection circuit 317_1 and can receive the first delay control signal SFT1 from the first phase detection circuit 317_1. The clock delay circuit 319_1 can generate a first selected delay divided clock SDCLKd1 by delaying the divided clock DCLK by a first clock delay interval, and set the first clock delay interval based on the first delay control signal SFT1 and the drive control signals DCNT1 and DCNT2.

[0082] The second phase detection circuit 317_2 can be connected to the frequency divider clock generation circuit 315 and the feedback frequency divider clock generation circuit 325, and can receive the frequency divider clock DCLK from the frequency divider clock generation circuit 315 and the feedback frequency divider clock FDCLK from the feedback frequency divider clock generation circuit 325. The second phase detection circuit 317_2 can generate a second delay control signal SFT2 based on the frequency divider clock DCLK and the feedback frequency divider clock FDCLK. The second phase detection circuit 317_2 can generate the second delay control signal SFT2 for adjusting the clock delay interval of the second clock delay circuit 319_2 by comparing the phase of the frequency divider clock DCLK and the phase of the feedback frequency divider clock FDCLK.

[0083] The second clock delay circuit 319_2 can be connected to the second phase detection circuit 317_2, and can receive the second delay control signal SFT2 from the second phase detection circuit 317_2. The second clock delay circuit 319_2 can generate a second selected delay divided clock SDCLKd2 by delaying the divided clock DCLK by a second clock delay interval, and set the second clock delay interval based on the second delay control signal SFT2 and the drive control signals DCNT1 and DCNT2.

[0084] The first clock transmission circuit 321_1 and the second clock transmission circuit 321_2 can be connected to the first clock delay circuit 319_1 and can receive a first selected delay divider clock SDCLKd1 from the first clock delay circuit 319_1. The first clock transmission circuit 321_1 and the second clock transmission circuit 321_2 can generate a first internal clock ICLK1 and a second internal clock ICLK2 based on the first selected delay divider clock SDCLKd1. The first clock transmission circuit 321_1 can generate a first internal clock ICLK1 with the same phase as the first selected delay divider clock SDCLKd1 and can output the first internal clock ICLK1 to the first internal clock pad 327_1. The second clock transmission circuit 321_2 can generate a second internal clock ICLK2 with a phase opposite to the first selected delay divider clock SDCLKd1 and can output the second internal clock ICLK2 to the second internal clock pad 327_2. According to one embodiment, the first clock transmission circuit 321_1 can be implemented as follows: based on a first selected delay divided clock SDCLKd1, it generates a first internal clock ICLK1 that has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2. According to one embodiment, the second clock transmission circuit 321_2 can be implemented as follows: based on the first selected delay divided clock SDCLKd1, it generates a second internal clock ICLK2 that has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2.

[0085] The third clock transmission circuit 321_3 and the fourth clock transmission circuit 321_4 can be connected to the second clock delay circuit 319_2 and can receive the second selected delay divided clock SDCLKd2 from the second clock delay circuit 319_2. The third clock transmission circuit 321_3 and the fourth clock transmission circuit 321_4 can generate a first internal clock ICLK1 and a second internal clock ICLK2 based on the second selected delay divided clock SDCLKd2. The third clock transmission circuit 321_3 can generate the first internal clock ICLK1 with the same phase as the second selected delay divided clock SDCLKd2 and can output the first internal clock ICLK1 to the third internal clock pad 327_3. The fourth clock transmission circuit 321_4 can generate the second internal clock ICLK2 with a phase opposite to the second selected delay divided clock SDCLKd2 and can output the second internal clock ICLK2 to the fourth internal clock pad 327_4. According to one embodiment, the third clock transmission circuit 321_3 can be implemented as follows: based on the second selected delay divided clock SDCLKd2, it generates a first internal clock ICLK1 that has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2. According to one embodiment, the fourth clock transmission circuit 321_4 can be implemented as follows: based on the second selected delay divided clock SDCLKd2, it generates a second internal clock ICLK2 that has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2.

[0086] The feedback buffer 323 can be connected to the first clock transmission circuit 321_1 and the second clock transmission circuit 321_2, and can receive a first internal clock ICLK1 from the first clock transmission circuit 321_1 and a second internal clock ICLK2 from the second clock transmission circuit 321_2. The feedback buffer 323 can generate a feedback buffer clock FBCLK based on the first internal clock ICLK1 and the second internal clock ICLK2.

[0087] The feedback divider clock generation circuit 325 can be connected to the feedback buffer 323 and can receive the feedback buffer clock FBCLK from the feedback buffer 323. The feedback divider clock generation circuit 325 can generate the feedback divider clock FDCLK based on the feedback buffer clock FBCLK.

[0088] Figure 17 This is a block diagram illustrating the construction of a clock driver 11D according to yet another example of a clock driver 11. (See diagram for example.) Figure 17As shown, the clock driver 11D may include external clock pads (ECLK PAD) 411_1 and 411_2, clock buffer (BUF) 413, frequency divider clock generation circuit (DCLK GEN) 415, phase detection circuit (PD) 417_1, first clock delay circuit (DL1) 419_1, second clock delay circuit (DL2) 419_2, clock transmission circuit (TX) 421_1 to 421_4, feedback buffer (FBUF) 423, feedback frequency divider clock generation circuit (FDCLK GEN) 425, and internal clock pads (ICLK PAD) 427_1 to 427_4.

[0089] Clock driver 11D can receive clock signals from the memory controller via external clock pads 411_1 and 411_2. Figure 19 The first external clock ECLK1 and the second external clock ECLK2 are applied in 61). The first external clock ECLK1 can be received through external clock pad 411_1. The second external clock ECLK2 can be received through external clock pad 411_2.

[0090] Clock buffer 413 can be connected to external clock pads 411_1 and 411_2, and can receive a first external clock ECLK1 and a second external clock ECLK2 from external clock pads 411_1 and 411_2. Clock buffer 413 can generate an external buffer clock EBCLK based on the first external clock ECLK1 and the second external clock ECLK2.

[0091] The frequency divider clock generation circuit 415 can be connected to the clock buffer 413 and can receive the external buffer clock EBCLK from the clock buffer 413. The frequency divider clock generation circuit 415 can generate the frequency divider clock DCLK based on the external buffer clock EBCLK.

[0092] Phase detection circuit 417 can be connected to frequency divider clock generation circuit 415 and feedback frequency divider clock generation circuit 425, and can receive frequency divider clock DCLK from frequency divider clock generation circuit 415 and feedback frequency divider clock FDCLK from feedback frequency divider clock generation circuit 425. Phase detection circuit 417 can generate delay control signal SFT based on frequency divider clock DCLK and feedback frequency divider clock FDCLK. Phase detection circuit 417 can generate delay control signal SFT for adjusting the clock delay interval of first clock delay circuit 419_1 by comparing the phase of frequency divider clock DCLK and the phase of feedback frequency divider clock FDCLK.

[0093] The first clock delay circuit 419_1 can be connected to the phase detection circuit 417 and can receive the delay control signal SFT from the phase detection circuit 417. The first clock delay circuit 419_1 can generate a first selected delay divided clock SDCLKd1 by delaying the divided clock DCLK by a first clock delay interval, and set the first clock delay interval based on the delay control signal SFT and the drive control signals DCNT1 and DCNT2.

[0094] The second clock delay circuit 419_2 can be connected to the phase detection circuit 417 and can receive the delay control signal SFT from the phase detection circuit 417. The second clock delay circuit 419_2 can generate a second selected delay divided clock SDCLKd2 by delaying the divided clock DCLK by a second clock delay interval, and set the second clock delay interval based on the delay control signal SFT and the drive control signals DCNT1 and DCNT2.

[0095] The first clock transmission circuit 421_1 and the second clock transmission circuit 421_2 can be connected to the first clock delay circuit 419_1 and can receive the first selected delay divider clock SDCLKd1 from the first clock delay circuit 419_1. The first clock transmission circuit 421_1 and the second clock transmission circuit 421_2 can generate a first internal clock ICLK1 and a second internal clock ICLK2 based on the first selected delay divider clock SDCLKd1. The first clock transmission circuit 421_1 can generate the first internal clock ICLK1 with the same phase as the first selected delay divider clock SDCLKd1 and can output the first internal clock ICLK1 to the first internal clock pad 427_1. The second clock transmission circuit 421_2 can generate the second internal clock ICLK2 with a phase opposite to the first selected delay divider clock SDCLKd1 and can output the second internal clock ICLK2 to the second internal clock pad 427_2. According to one embodiment, the first clock transmission circuit 421_1 can be implemented as follows: based on a first selected delay divided clock SDCLKd1, it generates a first internal clock ICLK1 that has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2. According to one embodiment, the second clock transmission circuit 421_2 can be implemented as follows: based on the first selected delay divided clock SDCLKd1, it generates a second internal clock ICLK2 that has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2.

[0096] The third clock transmission circuit 421_3 and the fourth clock transmission circuit 421_4 can be connected to the second clock delay circuit 419_2 and can receive the second selected delay divider clock SDCLKd2 from the second clock delay circuit 419_2. The third clock transmission circuit 421_3 and the fourth clock transmission circuit 421_4 can generate a first internal clock ICLK1 and a second internal clock ICLK2 based on the second selected delay divider clock SDCLKd2. The third clock transmission circuit 421_3 can generate the first internal clock ICLK1 with the same phase as the second selected delay divider clock SDCLKd2 and can output the first internal clock ICLK1 to the third internal clock pad 427_3. The fourth clock transmission circuit 421_4 can generate the second internal clock ICLK2 with a phase opposite to the second selected delay divider clock SDCLKd2 and can output the second internal clock ICLK2 to the fourth internal clock pad 427_4. According to one embodiment, the third clock transmission circuit 421_3 can be implemented to generate a first internal clock ICLK1, which has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2, based on the second selected delay divided clock SDCLKd2. According to one embodiment, the fourth clock transmission circuit 421_4 can be implemented to generate a second internal clock ICLK2, which has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2, based on the second selected delay divided clock SDCLKd2.

[0097] The feedback buffer 423 can be connected to the first clock transmission circuit 421_1 and the second clock transmission circuit 421_2, and can receive a first internal clock ICLK1 from the first clock transmission circuit 421_1 and a second internal clock ICLK2 from the second clock transmission circuit 421_2. The feedback buffer 423 can generate a feedback buffer clock FBCLK based on the first internal clock ICLK1 and the second internal clock ICLK2.

[0098] The feedback divider clock generation circuit 425 can be connected to the feedback buffer 423 and can receive the feedback buffer clock FBCLK from the feedback buffer 423. The feedback divider clock generation circuit 425 can generate the feedback divider clock FDCLK based on the feedback buffer clock FBCLK.

[0099] Figure 18 This is a block diagram illustrating the construction of a clock driver 11E according to an example of a clock driver 11. For example... Figure 18As shown, the clock driver 11E may include external clock pads (ECLK PAD) 511_1 and 511_2, clock buffer (BUF) 513, phase detection circuit (PD) 517, clock delay circuit (DL) 519, clock transmission circuit (TX) 521_1 to 521_4, feedback buffer (FBUF) 523, and internal clock pads (ICLK PAD) 527_1 to 527_4.

[0100] Clock driver 11E can receive clock signals from the memory controller via external clock pads 511_1 and 511_2. Figure 19 The first external clock ECLK1 and the second external clock ECLK2 are applied in 61). The first external clock ECLK1 can be received through external clock pad 511_1. The second external clock ECLK2 can be received through external clock pad 511_2.

[0101] Clock buffer 513 can be connected to external clock pads 511_1 and 511_2, and can receive a first external clock ECLK1 and a second external clock ECLK2 from external clock pads 511_1 and 511_2. Clock buffer 513 can generate an external buffer clock EBCLK based on the first external clock ECLK1 and the second external clock ECLK2.

[0102] Phase detection circuit 517 can be connected to clock buffer 513 and feedback buffer 523, and can receive external buffer clock EBCLK from clock buffer 513 and feedback buffer clock FBCLK from feedback buffer 523. Phase detection circuit 517 can generate delay control signal SFT based on external buffer clock EBCLK and feedback buffer clock FBCLK. Phase detection circuit 517 can generate delay control signal SFT for adjusting the clock delay interval of clock delay circuit 519 by comparing the phase of external buffer clock EBCLK and the phase of feedback buffer clock FBCLK.

[0103] The clock delay circuit 519 can be connected to the phase detection circuit 517 and can receive the delay control signal SFT from the phase detection circuit 517. The clock delay circuit 519 can generate a selected delay divider clock SDCLKd by delaying the external buffer clock EBCLK by the clock delay interval set based on the delay control signal SFT and the drive control signals DCNT1 and DCNT2.

[0104] The first clock transmission circuit 521_1, the second clock transmission circuit 521_2, the third clock transmission circuit 521_3, and the fourth clock transmission circuit 521_4 can be connected to the clock delay circuit 519 and can receive the selected delay divider clock SDCLKd from the clock delay circuit 519. The first clock transmission circuit 521_1, the second clock transmission circuit 521_2, the third clock transmission circuit 521_3, and the fourth clock transmission circuit 521_4 can generate internal clocks ICLK1 and ICLK2 based on the selected delay divider clock SDCLKd. The first clock transmission circuit 521_1 can generate a first internal clock ICLK1 with the same phase as the selected delay divider clock SDCLKd and can output the first internal clock ICLK1 to the first internal clock pad 527_1. The second clock transmission circuit 521_2 can generate a second internal clock ICLK2 with a phase opposite to the selected delay divider clock SDCLKd and can output the second internal clock ICLK2 to the second internal clock pad 527_2. The third clock transmission circuit 521_3 can generate a first internal clock ICLK1 with the same phase as the selected delay divider clock SDCLKd, and can output the first internal clock ICLK1 to the third internal clock pad 527_3. The fourth clock transmission circuit 521_4 can generate a second internal clock ICLK2 with a phase opposite to that of the selected delay divider clock SDCLKd, and can output the second internal clock ICLK2 to the fourth internal clock pad 527_4. According to one embodiment, the first clock transmission circuit 521_1 and the third clock transmission circuit 521_3 can each be implemented as follows: generating a first internal clock ICLK1, which has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2, based on the selected delay divider clock SDCLKd. According to one embodiment, the second clock transmission circuit 521_2 and the fourth clock transmission circuit 521_4 can each be implemented to generate a second internal clock ICLK2 that has been set to have the same frequency as each of the first external clock ECLK1 and the second external clock ECLK2, based on the selected delay divider clock SDCLKd.

[0105] The feedback buffer 523 can be connected to the first clock transmission circuit 521_1 and the second clock transmission circuit 521_2, and can receive a first internal clock ICLK1 from the first clock transmission circuit 521_1 and a second internal clock ICLK2 from the second clock transmission circuit 521_2. The feedback buffer 523 can generate a feedback buffer clock FBCLK based on the first internal clock ICLK1 and the second internal clock ICLK2.

[0106] Figure 19This is a block diagram illustrating the construction of a memory system 6 according to an example of this disclosure. Figure 19 As shown, the memory system 6 may include a memory controller 61 and a memory module 63.

[0107] The memory controller 61 can supply an external clock ECLK, a chip select signal CS, and a command address CA to the memory module 63. The memory module 63 can be connected to the memory controller 61 and can receive the external clock ECLK, chip select signal CS, and command address CA from the memory controller 61. The memory module 63 may include a clock driver (CLK_DRV) 631 and memory chips (MC) 633_1 to 633_L. It can be connected to... Figure 1 The clock driver 11 and memory chips 171_1 to 171_16 shown in the figure implement the clock driver 631 and memory chips 633_1 to 633_L included in the memory module 63 in the same way, and therefore detailed descriptions and operations of the clock driver 631 and memory chips 633_1 to 633_L are omitted.

[0108] refer to Figure 1 The memory module 1 described and the reference Figure 19 The described memory system 6 can be applied to electronic systems, including memory systems, graphics systems, computing systems, and mobile systems. For example, see reference... Figure 20 An electronic system 1000 according to an embodiment of the present disclosure may include a data storage unit 1001, a memory controller 1002, a buffer memory 1003, and an input and output (I / O) interface 1004.

[0109] Based on control signals from memory controller 1002, data storage unit 1001 can store data (not shown) applied by memory controller 1002, read stored data (not shown), and output read data to memory controller 1002. Data storage unit 1001 may include non-volatile memory capable of continuously storing data without data loss even when power is interrupted. Non-volatile memory may be implemented as flash memory (e.g., NOR flash memory or NAND flash memory), phase-change random access memory (PRAM), resistive random access memory (RRAM), spin-torque random access memory (STTRAM), or magnetic random access memory (MRAM).

[0110] The memory controller 1002 can decode instructions applied by external devices (or host devices) through the I / O interface 1004, and can control the input and output of data to and from the data storage unit 1001 and the buffer memory 1003 based on the decoding results. Figure 20In this context, memory controller 1002 is indicated as a block, but memory controller 1002 may include separately constructed controllers: a controller for controlling data storage unit 1001, and a controller for controlling buffer memory 1003, which is volatile memory. Memory controller 1002 may include reference... Figure 19 The memory controller 61 is described.

[0111] Buffer memory 1003 can store data to be processed by memory controller 1002, i.e., data input to and output from data storage unit 1001 (not shown). Based on control signals from memory controller 1002, buffer memory 1003 can store data applied by memory controller 1002 (not shown). Buffer memory 1003 may include references. Figure 1 The memory module 1 described and the reference Figure 19 The memory module 63 is described. The buffer memory 1003 can read data already stored in the buffer memory 1003 and can output the read data to the memory controller 1002. The buffer memory 1003 may include volatile memory, such as dynamic random access memory (DRAM), mobile DRAM, and static random access memory (SRAM).

[0112] I / O interface 1004 provides a physical connection between memory controller 1002 and external devices (or a host), enabling memory controller 1002 to receive control signals for inputting data to and outputting data from external devices, and to exchange data with external devices. I / O interface 1004 may include one of various interface protocols, such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, and IDE.

[0113] Electronic system 1000 can be used as an auxiliary storage device or external storage device for a host device. Electronic system 1000 may include solid-state drives (SSDs), universal serial bus (USB) memory, secure digital cards (SD cards), mini secure digital cards (mSD cards), micro SD cards, secure digital high-capacity (SDHC) cards, memory stick cards, smart media (SM) cards, multimedia cards (MMC) cards, embedded MMC (eMMC) cards, and compact flash memory (CF) cards.

[0114] Figure 21 This is a block diagram illustrating the construction of an electronic system 2000 according to another embodiment of the present disclosure. Figure 21 As shown, the electronic system 2000 may include a host 2100 and a semiconductor system 2200.

[0115] The host 2100 and the semiconductor system 2200 can transmit signals to each other using an interface protocol. The interface protocol used between the host 2100 and the semiconductor system 2200 may include Multimedia Card (MMC), Enhanced Small Panel Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), and Universal Serial Bus (USB).

[0116] Semiconductor system 2200 may include controller 2300 and semiconductor device 2400 (1:K). Controller 2300 may include reference... Figure 19 The memory controller 61 is described. Semiconductor devices 2400 (1:K) may each include references. Figure 1 The memory module 1 described and the reference Figure 19 The memory module 63 is described. The semiconductor device 2400 (1:K) can each be implemented as one of the following: dynamic random access memory (DRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM).

[0117] Embodiments of this disclosure have been described to date. Those skilled in the art to which this disclosure pertains will understand that this disclosure can be implemented in modified forms without departing from its inherent characteristics. Therefore, the disclosed embodiments should be considered from a descriptive rather than a restrictive viewpoint. The scope of this disclosure is described in the claims, not in the foregoing description, and all differences within their equivalents should be construed as being included in this disclosure.

Claims

1. A memory module, comprising: a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock by delaying a divided clock generated from the external clock by a clock delay interval, the internal clock being transmitted to the memory chip, The clock driver adjusts the clock delay interval by comparing the phase of the divided clock with the phase of a feedback divided clock generated from the internal clock.

2. The memory module of claim 1, wherein: The clock driver generates the divided clock based on the external clock, The divided clock is set to have a period of "2N" times the period of the external clock, and "N" is set to a natural number. 3 . The memory module of claim 1 , wherein the clock driver comprises a phase detection circuit configured to generate a delay control signal by comparing a phase of the divided clock and a phase of the feedback divided clock.

4. The memory module of claim 3 , wherein the phase detection circuit compares the phase of the divided clock and the phase of the feedback divided clock and generates the delay control signal having a logic level determined based on a result of the comparison, or generates the delay control signal including bits whose logic bit set is determined based on the result of the comparison.

5. The memory module of claim 3, further comprising a clock delay circuit configured to generate a selected delayed divided clock by delaying the divided clock by the clock delay interval set based on the delay control signal and the drive control signal.

6. The memory module of claim 5, wherein the clock delay circuit comprises: a first delayed divided-clock generating circuit configured to generate a first delayed divided-clock by delaying the divided-clock by a first sub-delay interval based on the delay control signal; a second delayed frequency-divided clock generating circuit configured to generate a second delayed frequency-divided clock by delaying the frequency-divided clock by a second sub-delay interval based on the delay control signal; as well as The delayed frequency-divided clock driving circuit is configured to drive the selected delayed frequency-divided clock based on the driving control signal. 7 . The memory module of claim 6 , wherein each of the first delayed frequency-divided clock generating circuit and the second delayed frequency-divided clock generating circuit comprises a plurality of unit delayers each having a unit delay interval.

8. The memory module of claim 6, wherein an initial delay interval of the second sub-delay interval set in the second delayed frequency-divided clock generating circuit is set to be greater than an initial delay interval of the first sub-delay interval set in the first delayed frequency-divided clock generating circuit.

9. The memory module of claim 6, wherein the delayed divided clock driving circuit drives the selected delayed divided clock so that the clock delay interval is set to an interval between the first sub-delay interval and the second sub-delay interval.

10. The memory module of claim 6, wherein: The driving control signal includes a first driving control signal and a second driving control signal, The delayed frequency-divided clock driving circuit comprises: a first clock driving circuit configured to receive the first delayed frequency-divided clock and configured to drive the selected delayed frequency-divided clock by a first driving power set by the first driving control signal; and The second clock driving circuit is configured to receive the second delayed frequency-divided clock and to drive the selected delayed frequency-divided clock by a second driving power set by the second driving control signal.

11. The memory module of claim 5, further comprising a clock transmission circuit, wherein the clock transmission circuit is configured to generate the internal clock based on the selected delayed divided clock, and is configured to output the internal clock to an internal clock pad to transmit the internal clock to the memory chip.

12. The memory module of claim 5, wherein the clock delay circuit comprises: a delayed divided-clock generating circuit configured to generate a first delayed divided-clock by delaying the divided-clock by a first sub-delay interval based on the delay control signal, and configured to generate a second delayed divided-clock by delaying the divided-clock by a second sub-delay interval based on the delay control signal; as well as The delayed frequency-divided clock driving circuit is configured to drive the selected delayed frequency-divided clock based on the driving control signal.

13. The memory module of claim 12, wherein the delayed divided-frequency clock generating circuit comprises a plurality of unit delayers, each of the plurality of unit delayers having a unit delay interval.

14. A memory module, comprising: a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock by delaying a divided clock generated from the external clock by a clock delay interval, the internal clock being transmitted to the memory chip, The clock driver adjusts the clock delay interval by comparing a phase of an external buffered clock generated from the external clock and a phase of a feedback buffered clock generated from the internal clock.

15. The memory module of claim 14, wherein the clock driver comprises: a clock buffer configured to generate the external buffered clock by buffering the external clock; as well as A feedback buffer is configured to generate the feedback buffer clock by buffering the internal clock. 16 . The memory module of claim 15 , wherein the clock driver comprises a phase detection circuit configured to generate a delay control signal by comparing a phase of the external buffer clock and a phase of the feedback buffer clock.

17. The memory module of claim 16, further comprising a clock delay circuit configured to generate a selectively delayed divided clock by delaying the divided clock by the clock delay interval set based on the delay control signal and the driving control signal.

18. A memory module, comprising: a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock by delaying a divided clock generated from the external clock by a clock delay interval, the internal clock being transmitted to the memory chip, The clock driver comprises: a first phase detection circuit configured to generate a first delay control signal by comparing the phase of the divided clock and the phase of the feedback divided clock; a first clock delay circuit configured to generate a first selected delayed frequency-divided clock by delaying the frequency-divided clock by a first clock delay interval, the first clock delay interval being set based on the first delay control signal and a drive control signal; a second phase detection circuit configured to generate a second delay control signal by comparing the phase of the divided clock and the phase of the feedback divided clock; and The second clock delay circuit is configured to generate a second selectively delayed frequency-divided clock by delaying the frequency-divided clock by a second clock delay interval, wherein the second clock delay interval is set based on the second delay control signal and the driving control signal.

19. A memory module comprising: a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock by delaying a divided clock generated from the external clock by a clock delay interval, the internal clock being transmitted to the memory chip, The clock driver comprises: a phase detection circuit configured to generate a delay control signal by comparing the phase of the divided clock and the phase of the feedback divided clock; a first clock delay circuit configured to generate a first selected delayed frequency-divided clock by delaying the frequency-divided clock by a first clock delay interval, the first clock delay interval being set based on the delay control signal and the drive control signal; and The second clock delay circuit is configured to generate a second selectively delayed frequency-divided clock by delaying the frequency-divided clock by a second clock delay interval, wherein the second clock delay interval is set based on the delay control signal and the drive control signal.

20. A memory module, comprising: a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock by delaying an external buffered clock generated from the external clock by a clock delay interval, the internal clock being transmitted to the memory chip, The clock driver adjusts the clock delay interval by comparing a phase of the external buffered clock with a phase of a feedback buffered clock generated from the internal clock.

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