Memory circuit and operating method thereof

Abstract

The embodiment of the invention discloses a memory circuit and an operating method thereof. A memory circuit includes a memory array including a plurality of non-volatile memory cells, where the non-volatile memory cells are arranged along a plurality of access lines, the plurality of access lines extending in a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in a lateral direction. The memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite the first side. When each non-volatile memory cell is configured to be programmed by at least a first current and a second current, the first current and the second current flow through the first path and the second path, respectively. The first path includes at least a portion on the first side and the second path includes at least a portion on the second side.

Description

Technical Field

[0001] Embodiments of the present application relate to memory circuits and methods of operating the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, the increase in integration density comes from the repeated reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array comprising a plurality of nonvolatile memory cells, wherein the nonvolatile memory cells are arranged along a plurality of access lines, and the plurality of access lines extend in a lateral direction; a first access circuit physically disposed on a first side of the memory array in the lateral direction; and a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side; wherein, when each nonvolatile memory cell is configured to be programmed by at least a first current and a second current, the first current and the second current flow through a first path and a second path, respectively, and wherein the first path includes at least a portion on the first side, and the second path includes at least a portion on the second side.

[0004] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: a plurality of nonvolatile memory cells arranged above a plurality of bit lines extending in a lateral direction; a first access circuit physically disposed on a first side of the nonvolatile memory cell in the lateral direction, wherein the first access circuit comprises a first subcircuit and a second subcircuit; and a second access circuit physically disposed on a second side of the nonvolatile memory cell in the lateral direction, the second side being opposite to the first side, wherein the second access circuit comprises a third subcircuit and a fourth subcircuit; wherein the first subcircuit is configured to couple a programming voltage to a corresponding one of the plurality of nonvolatile memory cells, and when a first logic state is programmed to the corresponding nonvolatile memory cell, the second subcircuit and the fourth subcircuit are both configured to supplement a conduction path from the programming voltage to ground; and wherein the second subcircuit is configured to couple a programming voltage to the corresponding nonvolatile memory cell, and when a second logic state is programmed to the corresponding nonvolatile memory cell, the first subcircuit and the third subcircuit are both configured to supplement another conduction path from the programming voltage to ground.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, comprising: activating (i) a first access circuit physically disposed on a first side of a nonvolatile memory cell; (ii) a second access circuit physically disposed on the first side of the nonvolatile memory cell; and (iii) a third access circuit physically disposed on the second side of the nonvolatile memory cell; providing a voltage to the nonvolatile memory cell; conducting a first current flowing through a first conduction path, the first conduction path extending from the voltage, passing through the first access circuit, the nonvolatile memory cell, and the second access circuit, and reaching ground; and conducting a second current flowing through a second conduction path, the second conduction path extending from a programming voltage, passing through the first access circuit, the nonvolatile memory cell, and the third access circuit, and reaching ground. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of a memory device according to some embodiments is shown.

[0008] Figure 2 A schematic diagram of a memory cell of a memory device according to some embodiments is shown.

[0009] Figure 3 According to some embodiments Figure 1 An example schematic diagram of a portion of a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0010] Figure 4 According to some embodiments Figure 1 Another example schematic diagram of a portion of a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0011] Figure 5 According to some embodiments Figure 1 00147] Still another example schematic diagram of a portion of a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0012] Figure 6 According to some embodiments Figure 1 00147] Still another example schematic diagram of a portion of a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0013] Figure 7 According to some embodiments Figure 1 00147] Still another example schematic diagram of a portion of a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0014] Figure 8 According to some embodiments Figure 1 00147] Still another example schematic diagram of a portion of a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0015] Fig. 9 According to some embodiments Figure 1 00147] Still another example schematic diagram of a portion of a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0016] Fig.10 According to some embodiments Figure 1 00147] Still another example schematic diagram of a portion of a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0017] Fig.11 According to some embodiments Figure 1 00147] Still another example schematic diagram of a portion of a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0018] Fig.12 A method for operating according to some embodiments is shown. Figure 1 Example waveforms of multiple control signals for a memory device including multiple access circuits physically disposed on opposite sides of a memory array.

[0019] Fig.13 An example flow chart of a method of operating a memory device including a plurality of access circuits physically disposed on opposite sides of a memory array is shown according to some embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0022] Many modern electronic devices contain memory devices. Memory devices generally include volatile memory devices or nonvolatile memory devices. Nonvolatile memory devices can retain their stored data in the absence of power, while volatile memory devices lose their data storage content when power is removed. Magnetoresistive random access memory (MRAM) devices are a promising candidate for the next generation of nonvolatile electronic memory devices due to their superiority over current electronic memory devices. Compared to current nonvolatile memory devices (such as flash random access memory devices), MRAM devices are generally faster and have better endurance. Compared to current volatile memory devices (such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices), MRAM devices generally have similar performance and density, but lower power consumption.

[0023] Typically, an MRAM device includes a plurality of MRAM cells formed into a memory array. The MRAM cell may include a magnetic tunnel junction (MTJ) arranged between conductive electrodes (e.g., an upper electrode and a lower electrode). The MTJ may include a pinned layer separated from a free layer by a tunnel barrier layer. The magnetic orientation of the pinned layer is static (i.e., fixed), and the magnetic orientation of the free layer may be switched between a parallel configuration and an anti-parallel configuration relative to the magnetic orientation of the pinned layer. The parallel configuration provides a low resistance state that stores the data digitally as a first data state (e.g., a logical "1"). The anti-parallel configuration provides a high resistance state that stores the data digitally as a second data state (e.g., a logical "0").

[0024] Each MRAM cell of the memory array can be programmed through its own upper electrode and lower electrode. In addition, in order to achieve different data states, a programming voltage can be applied to the MRAM cell by a corresponding bit line connected to the upper electrode when the lower electrode is coupled to ground or by a corresponding source line connected to the lower electrode when the upper electrode is coupled to ground. Therefore, the current can be conducted through the MRAM cell in opposite directions. For example, a first current can flow through a first path extending from a bit line, passing through the MRAM cell, and reaching a source line to write a first data state; a second current can flow through a second path extending from a source line, passing through the MRAM cell, and reaching a bit line to write a second data state. Such a programming voltage is typically provided or delivered by a driver circuit that is operably coupled to the memory array and physically disposed next to the memory array, and the resulting current is typically flowed to ground by a pull-down circuit that is also operably coupled to the memory array and physically disposed next to the memory array.

[0025] In the prior art, the driver circuit and the pull-down circuit are usually formed on the same side of the memory array. As the size of the memory array becomes larger (for example, as the number of word lines increases / the length of the bit line increases), the MRAM cells formed farther away from the driver circuit and the pull-down circuit are usually affected by insufficient programming voltage, which is mainly due to the increase in the voltage (IR) drop along the extended bit line. To this end, some technologies have proposed placing the driver circuit and the pull-down circuit on opposite sides of the memory array. In other words, regardless of the direction of current flow, the programming voltage is applied to one side of the memory array (through the driver circuit), and the resulting current flows to the ground on the other side of the memory array (through the pull-down circuit). However, the electrodes of each MRAM cell are usually coupled to or formed as metal lines. As the size of the technology node is increasingly reduced, the size of these metal lines is also reduced accordingly. Therefore, the metal line (or the corresponding write path) may present a higher resistance, which causes the voltage drop problem to remain unsolved. Therefore, the existing MRAM devices are not completely satisfactory in some aspects.

[0026] The present disclosure provides various embodiments of a memory device or circuit including a memory array, wherein one or more driver circuits and one or more pull-down circuits are physically formed on the same side of a memory array having a plurality of memory cells. In one aspect of the present disclosure, the memory device includes a driver circuit disposed on a first side of the memory array, and two pull-down circuits disposed on a first side and a second side of the memory array, respectively. In another aspect of the present disclosure, the memory device includes two driver circuits disposed on a first side and a second side of the memory array, respectively, and a pull-down circuit disposed on a first side or a second side of the memory array. In another aspect of the present disclosure, the memory device includes two driver circuits disposed on a first side and a second side of the memory array, respectively, and two pull-down circuits disposed on a first side and a second side of the memory array, respectively. Therefore, each memory cell of the memory array can be programmed by at least a first current and a second current, and the two currents can flow in different directions, respectively. Therefore, the equivalent resistance of a conductive (e.g., programming or reading) path on any memory cell can be significantly reduced, which can advantageously increase the write / read margin of the disclosed memory device.

[0027] Figure 1 1 shows a block diagram of a memory device 100 according to various embodiments of the present disclosure. Figure 1 In the illustrated embodiment, memory device 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuitry 108, and control logic circuitry 110. Figure 1 Although not shown in FIG. 1 , all components of the memory device 100 may be coupled to each other and to the control logic circuit 110. Figure 1 In the illustrated embodiment, each component is shown as a separate block for clarity of illustration, but in some other embodiments. Figure 1 Some or all of the components shown in can be integrated together. For example, memory array 102 can include embedded I / O circuits (eg, 108).

[0028] The memory array 102 is a hardware component that stores data. In various embodiments, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other storage units) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R M Each row extends in a first direction (eg, X direction), and a plurality of columns C1, C2, C3, ... N, each column extends in a second direction (e.g., Y direction). Each row and each column may include one or more conductive (e.g., metal) structures used as access lines. Each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and may be operated according to a voltage or current through the corresponding conductive structure of the column and row. For example, each row may include one or more corresponding word lines (WL), and each column may include one or more corresponding bit lines (BL) and one or more source lines (SL).

[0029] In some embodiments, each memory cell 103 is implemented as an MRAM cell, details of which will be described in detail in Figure 2 However, it should be understood that the memory array 102 may include any of a variety of other non-volatile memory cells, such as spin transfer torque random access memory (STT-RAM) cells, ferroelectric random access memory (FeRAM) cells, resistive random access memory (RRAM) cells, phase change random access memory (PCRAM) cells, etc., while remaining within the scope of the embodiments of the present disclosure.

[0030] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., WL) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert a conductive structure (e.g., BL and source line SL) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each memory cell 103 asserted by the row decoder 104 and the column decoder 106. The control logic circuit 110 is a hardware component that can control the coupled components (e.g., 102 to 108).

[0031] It should be understood that Figure 1 The arrangement of components shown in is for illustration purposes only and does not limit the physical layout of these components. For example, although I / O circuit 108 is shown as being arranged on a first side of memory array 102, according to various embodiments of the present disclosure, I / O circuit 108 may include multiple subcomponents or subcircuits (e.g., one or more driver circuits, one or more pull-down circuits) that are physically arranged on different sides of memory array 102. In addition, these subcomponents may be physically disposed between column decoder 106 and memory array 102. In some embodiments, driver circuits and pull-down circuits may sometimes be referred to as access circuits.

[0032] Figure 2 A schematic diagram of an MRAM cell 200 according to various embodiments of the present disclosure is shown. The MRAM cell 200 may be Figure 1Implementation of the memory cell 103. The MRAM cell 200 includes magnetic storage elements such as an MTJ device 210 and a switching device 220. In the present disclosure, the MTJ device 210 may sometimes be referred to as a memory cell. The MTJ device 210 includes a fixed layer or pinned layer 212, a tunneling barrier layer or insulator layer 214, and a free layer 216. The magnetization of the free layer 216 can rotate freely to point in one of two directions. For the fixed layer 212, an antiferromagnetic layer can be used to fix or pin its magnetization in a specific direction. The insulator layer 214 is sandwiched between the free layer 216 and the fixed layer 212. The free layer 216 is connected to a bit line (BL) 230, which provides a voltage to the free layer during a read or write operation. The fixed layer 212 is connected to the drain of the switching device 220.

[0033] The switching device 220 is configured to read from or write to the MTJ device 210. Example embodiments of the switching device 220 include a metal oxide semiconductor (MOS) transistor, a MOS diode, and / or a bipolar transistor. The gate of the switching device 220 is connected to a word line (WL) 240, which can activate the memory cell for a read or write operation. In some other embodiments, the WL 240 may include a read WL and a write WL, wherein the read WL is activated for a read operation and the write WL is activated for a write operation. The source of the switching device 220 is connected to a source line (SL) 250, which can drive the fixed layer 212 with a voltage in a read or write operation when the WL 240 is activated. The SL 250 may include a common source line (CSL), which may be connected to a plurality of memory cells (e.g., 103) that are connected to the same WL 240. A controller (eg, control logic circuit 110) may provide a turn-on voltage (eg, V DD or V CC ).

[0034] The data in the MTJ device 210 is represented by the magnetization direction of the free layer 216 relative to the fixed layer 212. For example, when the magnetizations of the free layer 216 and the fixed layer 212 are programmed to be parallel ("P") and the magnetic moments have the same polarity, the MTJ device 210 may present a low resistance. When the magnetizations of the free layer 216 and the fixed layer 212 are programmed to be antiparallel ("AP") and the magnetic moments have opposite polarities, the MTJ device 210 may present a high resistance. During a read operation of the MRAM cell 200, current may flow from the SL 250 to the BL 230. When the resistance of the MTJ device 210 is low or the magnetizations of the free layer 216 and the fixed layer 212 are parallel, the current flowing through the MRAM cell 200 may be high (sometimes referred to as a logic 0 state). When the resistance of the MTJ device 210 is high or the magnetizations of the free layer 216 and the fixed layer 212 are antiparallel, the current flowing through the MRAM cell 200 may be low (sometimes referred to as a logic 1 state).

[0035] The current flowing out of BL 230 may be provided to a sense amplifier, which may compare the sense amplifier with a reference current from a reference cell. The reference cell may have a resistance that is an average of two different states of the MTJ device 210. For example, the resistance of the reference cell may be set to an average of a parallel state and an antiparallel state. The sense amplifier may then compare the current output of the MTJ device 210 with the current output of the reference cell. If the current output of the MTJ device 210 is less than the reference cell, it means that the resistance in the MTJ device 210 is high, and a logic 1 state is read from the MTJ device 210. If the current output of the MTJ device 210 is greater than the reference cell, it means that the resistance in the MTJ device 210 is low, and a logic 0 state is read from the MTJ device 210.

[0036] Figure 3 Some embodiments of the present disclosure are shown Figure 1 3. An example schematic diagram 300 of a portion of a memory device 100 (hereinafter referred to as "memory device 300") is shown. As a brief overview, the memory device 300 includes a driver circuit and a first pull-down circuit disposed on a first side of a memory array 102, and a second pull-down circuit disposed on an opposite second side of the memory array 102. The memory array 102 is shown as an MRAM cell 200 ( Figure 2 ) of a memory cell (e.g., 103A). In some embodiments, the driver circuit and the pull-down circuit can be part of the I / O circuit 108. For illustration purposes, Figure 3 The memory device 300 is simplified, therefore, it should be understood that Figure 3 Can be omitted Figure 1 some components of .

[0037] As shown, the memory device 300 includes a driver circuit 310, a first pull-down circuit 320, and a second pull-down circuit 330. According to some embodiments, the driver circuit 310 and the first pull-down circuit 320 are physically disposed (or otherwise formed) on a first side of the memory array 102, for example, along the Y direction, and the second pull-down circuit 330 is physically disposed, for example, along the Y direction, on a second side of the memory array 101. In addition, the driver circuit 310 includes sub-circuits 310A and 310B; the first pull-down circuit 320 includes sub-circuits 320A and 320B; and the second pull-down circuit 330 includes sub-circuits 330A and 330B.

[0038] In some embodiments, subcircuit 310A of driver circuit 310 includes two p-type transistors 312 and 314 connected in series with each other; subcircuit 310B of driver circuit 310 includes a p-type transistor 313; subcircuit 320A of first pull-down circuit 320 includes two n-type transistors 322 and 324 connected in series with each other; subcircuit 320B of first pull-down circuit 320 includes an n-type transistor 324; subcircuit 330A of second pull-down circuit 330 includes two n-type transistors 332 and 334 connected in series with each other; subcircuit 330B of second pull-down circuit 330 includes an n-type transistor 334. The sub-circuits 310A and 310B of the driver circuit 310 are each configured to selectively couple a programming voltage (e.g., VBL) to the memory cell 103A via BL or SL, while the sub-circuits 320A and 320B of the first pull-down circuit 320 and the sub-circuits 330A and 330B of the second pull-down circuit 330 are each configured to selectively couple the memory cell 103A to ground via BL or SL.

[0039] The p-type transistors 312 to 313 of the driver circuit 310 are gated (e.g., activated) by corresponding control signals to couple the programming voltage to the memory cell 103A. For example, the p-type transistors 312 to 313 can each be turned on in response to the corresponding control signal being asserted as a logic low state. The n-type transistors 322 to 324 of the first pull-down circuit 320 are gated (e.g., activated) by corresponding control signals to ground the memory cell 103A. Similarly, the n-type transistors 332 to 334 of the second pull-down circuit 330 are gated (e.g., activated) by corresponding control signals to ground the memory cell 103A. For example, the n-type transistors 322 to 324 and 332 to 334 can each be turned on in response to the corresponding control signal being asserted as a logic high state. In some embodiments, the respective logic states of these control signals can be configured based on the logic state to be programmed into the memory cell 103A.

[0040] In some embodiments, subcircuits 310A and 310B of driver circuit 310 may be activated alternately (e.g., transistors 312 and 314 are turned on simultaneously, and transistor 313 is turned off) to couple a programming voltage to memory cell 103A; subcircuits 320A and 320B of first pull-down circuit 320 may be activated alternately (e.g., transistors 322 and 324 are turned off simultaneously, and transistor 324 is turned on) to ground memory cell 103A; and subcircuits 330A and 330B of second pull-down circuit 330 may be activated alternately (e.g., transistors 332 and 334 are turned on simultaneously, and transistor 334 is turned off) to ground memory cell 103A.

[0041] For example, to program a logic 0 into memory cell 103A (from the AP state to the P state), subcircuits 310A, 320B, and 330B are activated, while subcircuits 310B, 320A, and 330A are deactivated. Thus, the programming voltage may be coupled to memory cell 103A via BL (and subcircuit 310A), and memory cell 103A may be coupled to ground via SL (via subcircuits 320B and 330B, respectively). Equivalently, two conduction paths 351 and 353 may flow through memory cell 103A. Conduction path 351 extends from subcircuit 310A, through memory cell 103A and subcircuit 320B, and to ground; conduction path 353 extends from subcircuit 310A, through memory cell 103A and subcircuit 330B, and to ground. In other words, conductive path 351 extends from a first side of memory array 102 to memory array 102 , while conductive path 353 extends from a first side of memory array 102 to a second side of memory array 102 .

[0042] In another example, to program a logic 1 into memory cell 103A (from a P state to an AP state), subcircuits 310B, 320A, and 330A are activated, while subcircuits 310A, 320B, and 330B are deactivated. Thus, a programming voltage may be coupled to memory cell 103A via SL (and subcircuit 310B), and memory cell 103A may be coupled to ground via BL (via subcircuits 320A and 330A, respectively). Equivalently, two conduction paths 371 and 373 may flow through memory cell 103A. Conduction path 371 extends from subcircuit 310B, through memory cell 103A and subcircuit 320A, and to ground; conduction path 373 extends from subcircuit 310B, through memory cell 103A and subcircuit 330A, and to ground. In other words, conductive path 371 extends from a first side of memory array 102 to a first side of memory array 102 , while conductive path 373 extends from a first side of memory array 102 to a second side of memory array 102 .

[0043] Figure 4 Some embodiments of the present disclosure are shown Figure 1 Another example schematic diagram 400 of a portion of a memory device 100 (hereinafter referred to as "memory device 400") is shown in FIG. As a brief overview, the memory device 400 includes a first driver circuit disposed on a first side of a memory array 102, and a second driver circuit and a pull-down circuit disposed on an opposite second side of the memory array 102. The memory array 102 is shown as an MRAM cell 200 ( Figure 2 ) of a memory cell (e.g., 103A). In some embodiments, the driver circuit and the pull-down circuit can be part of the I / O circuit 108. For illustration purposes, Figure 4 The memory device 400 is simplified, therefore, it should be understood that Figure 4 Can be omitted Figure 1 some components of .

[0044] As shown, the memory device 400 includes a first driver circuit 410, a second driver circuit 420, and a pull-down circuit 430. According to some embodiments, the first driver circuit 410 is physically disposed (or otherwise formed) on a first side of the memory array 102, for example, along the Y direction, and the second driver circuit 420 and the pull-down circuit 430 are physically disposed, for example, along the Y direction, on a second side of the memory array 101. In addition, the first driver circuit 410 includes sub-circuits 410A and 410B; the second driver circuit 420 includes sub-circuits 420A and 420B; and the pull-down circuit 430 includes sub-circuits 430A and 430B.

[0045] In some embodiments, the sub-circuit 410A of the first driver circuit 410 includes two p-type transistors 412 and 414 connected in series with each other; the sub-circuit 410B of the first driver circuit 410 includes a p-type transistor 416; the sub-circuit 420A of the second driver circuit 420 includes two p-type transistors 422 and 424 connected in series with each other; the sub-circuit 420B of the second driver circuit 420 includes a p-type transistor 426; the sub-circuit 430A of the pull-down circuit 430 includes two n-type transistors 432 and 434 connected in series with each other; the sub-circuit 430B of the pull-down circuit 430 includes an n-type transistor 436. Sub-circuits 410A and 410B of the first driver circuit 410 and sub-circuits 420A and 420B of the second driver circuit 420 are both configured to selectively couple a programming voltage (e.g., VBL) to the memory cell 103A via BL or SL, and sub-circuits 430A and 430B of the pull-down circuit 430 are both configured to selectively couple the memory cell 103A to ground via BL or SL.

[0046] The p-type transistors 412 to 416 of the first driver circuit 410 are gated (e.g., activated) by corresponding control signals to couple the programming voltage to the memory cell 103A. Similarly, the p-type transistors 422 to 426 of the second driver circuit 420 are gated (e.g., activated) by corresponding control signals to couple the programming voltage to the memory cell 103A. For example, the p-type transistors 412 to 416 and 422 to 426 can each be turned on in response to the corresponding control signal being asserted as a logic low state. The n-type transistors 432 to 436 of the pull-down circuit 430 are gated (e.g., activated) by corresponding control signals to ground the memory cell 103A. For example, the n-type transistors 432 to 436 can each be turned on in response to the corresponding control signal being asserted as a logic high state. In some embodiments, the respective logic states of these control signals can be configured based on the logic state to be programmed into the memory cell 103A.

[0047] In some embodiments, sub-circuit 410A and sub-circuit 410B of the first driver circuit 410 can be alternately activated to couple the programming voltage to the memory cell 103A; sub-circuit 420A and sub-circuit 420B of the second driver circuit 420 can be alternately activated to couple the programming voltage to the memory cell 103A; and sub-circuit 430A and sub-circuit 430B of the pull-down circuit 430 can be alternately activated to ground the memory cell 103A.

[0048] For example, to program a logic 0 into memory cell 103A (from the AP state to the P state), subcircuits 410A, 420A, and 430B are activated, while subcircuits 410B, 420B, and 430A are deactivated. Thus, the programming voltage may be coupled to memory cell 103A via BL (and subcircuits 410A and 420A), and memory cell 103A may be coupled to ground via SL (and subcircuit 430B). Equivalently, two conduction paths 451 and 453 may flow through memory cell 103A. Conduction path 451 extends from subcircuit 410A, through memory cell 103A and subcircuit 430B, and to ground; conduction path 453 extends from subcircuit 420A, through memory cell 103A and subcircuit 430B, and to ground. In other words, conductive path 451 extends from a first side of memory array 102 to a second side of memory array 102 , while conductive path 453 extends from a second side of memory array 102 to a second side of memory array 102 .

[0049] In another example, to program a logic 1 into memory cell 103A (from a P state to an AP state), subcircuits 410B, 420B, and 430A are activated, while subcircuits 410A, 420A, and 430B are deactivated. Thus, a programming voltage may be coupled to memory cell 103A via SL (and respective subcircuits 410B and 420B), and memory cell 103A may be coupled to ground via BL (and subcircuit 430A). Equivalently, two conduction paths 471 and 473 may flow through memory cell 103A. Conductive path 471 extends from subcircuit 410B, through memory cell 103A and subcircuit 430A, and to ground; conductive path 473 extends from subcircuit 420B, through memory cell 103A and subcircuit 430A, and to ground. In other words, conductive path 471 extends from a first side of memory array 102 to a second side of memory array 102 , while conductive path 473 extends from a second side of memory array 102 to a second side of memory array 102 .

[0050] Figure 5 Some embodiments of the present disclosure are shown Figure 1 1 is another example schematic diagram 500 of a portion of a memory device 100 (hereinafter referred to as "memory device 500"). As a brief overview, the memory device 500 includes a first driver circuit and a pull-down circuit disposed on a first side of a memory array 102, and a second driver circuit disposed on an opposite second side of the memory array 102. The memory array 102 is shown as an MRAM cell 200 ( Figure 2 ) of a memory cell (e.g., 103A). In some embodiments, the driver circuit and the pull-down circuit can be part of the I / O circuit 108. For illustration purposes, Figure 5 The memory device 500 is simplified, therefore, it should be understood that Figure 5 Can be omitted Figure 1 some components of .

[0051] As shown, the memory device 500 includes a first driver circuit 510, a second driver circuit 520, and a pull-down circuit 530. According to some embodiments, the first driver circuit 510 and the pull-down circuit 530 are physically disposed (or otherwise formed) on a first side of the memory array 102, for example, along the Y direction, and the second driver circuit 520 is physically disposed, for example, along the Y direction, on a second side of the memory array 101. In addition, the first driver circuit 510 includes sub-circuits 510A and 510B; the second driver circuit 520 includes sub-circuits 520A and 520B; and the pull-down circuit 530 includes sub-circuits 530A and 530B.

[0052] In some embodiments, sub-circuit 510A of the first driver circuit 510 includes two p-type transistors 512 and 514 connected in series with each other; sub-circuit 510B of the first driver circuit 510 includes a p-type transistor 516; sub-circuit 520A of the second driver circuit 520 includes two p-type transistors 522 and 524 connected in series with each other; sub-circuit 520B of the second driver circuit 520 includes a p-type transistor 526; sub-circuit 530A of the pull-down circuit 530 includes two n-type transistors 532 and 534 connected in series with each other; sub-circuit 530B of the pull-down circuit 530 includes an n-type transistor 536. Sub-circuits 510A and 510B of the first driver circuit 510 and sub-circuits 520A and 520B of the second driver circuit 520 are both configured to selectively couple a programming voltage (e.g., VBL) to the memory cell 103A via BL or SL, and sub-circuits 530A and 530B of the pull-down circuit 530 are both configured to selectively couple the memory cell 103A to ground via BL or SL.

[0053] The p-type transistors 512 to 516 of the first driver circuit 510 are gated (e.g., activated) by corresponding control signals to couple the programming voltage to the memory cell 103A. Similarly, the p-type transistors 522 to 526 of the second driver circuit 520 are gated (e.g., activated) by corresponding control signals to couple the programming voltage to the memory cell 103A. For example, the p-type transistors 512 to 516 and 522 to 526 can each be turned on in response to the corresponding control signal being asserted as a logic low state. The n-type transistors 532 to 536 of the pull-down circuit 530 are gated (e.g., activated) by corresponding control signals to ground the memory cell 103A. For example, the n-type transistors 532 to 536 can each be turned on in response to the corresponding control signal being asserted as a logic high state. In some embodiments, the respective logic states of these control signals can be configured based on the logic state to be programmed into the memory cell 103A.

[0054] In some embodiments, sub-circuit 510A and sub-circuit 510B of the first driver circuit 510 can be alternately activated to couple the programming voltage to the memory cell 103A; sub-circuit 520A and sub-circuit 520B of the second driver circuit 520 can be alternately activated to couple the programming voltage to the memory cell 103A; and sub-circuit 530A and sub-circuit 530B of the pull-down circuit 530 can be alternately activated to ground the memory cell 103A.

[0055] For example, to program a logic 0 into memory cell 103A (from the AP state to the P state), subcircuits 510A, 520A, and 530B are activated, while subcircuits 510B, 520B, and 530A are deactivated. Thus, the programming voltage may be coupled to memory cell 103A via BL (and subcircuits 510A and 520A), and memory cell 103A may be coupled to ground via SL (and subcircuit 530B). Equivalently, two conduction paths 551 and 553 may flow through memory cell 103A. Conduction path 551 extends from subcircuit 510A, passes through memory cell 103A and subcircuit 530B, and reaches ground; conduction path 553 extends from subcircuit 520A, passes through memory cell 103A and subcircuit 530B, and reaches ground. In other words, conductive path 551 extends from a first side of memory array 102 to a first side of memory array 102 , while conductive path 553 extends from a second side of memory array 102 to a first side of memory array 102 .

[0056] In another example, to program a logic 1 into memory cell 103A (from a P state to an AP state), subcircuits 510B, 520B, and 530A are activated, while subcircuits 510A, 520A, and 530B are deactivated. Thus, a programming voltage may be coupled to memory cell 103A via SL (and subcircuits 510B and 520B), and memory cell 103A may be coupled to ground via BL (and subcircuit 530A). Equivalently, two conduction paths 571 and 573 may flow through memory cell 103A. Conduction path 571 extends from subcircuit 510B, through memory cell 103A and subcircuit 530A, and to ground; conduction path 573 extends from subcircuit 520B, through memory cell 103A and subcircuit 530A, and to ground. In other words, conductive path 571 extends from a first side of memory array 102 to a first side of memory array 102 , while conductive path 573 extends from a second side of memory array 102 to a first side of memory array 102 .

[0057] Figure 6 Some embodiments of the present disclosure are shown Figure 1 6. As a brief overview, the memory device 600 includes a first driver circuit and a first pull-down circuit disposed on a first side of the memory array 102, and a second driver circuit and a second pull-down circuit disposed on an opposite second side of the memory array 102. The memory array 102 is shown as an MRAM cell 200 ( Figure 2) of a memory cell (e.g., 103A). In some embodiments, the driver circuit and the pull-down circuit can be part of the I / O circuit 108. For illustration purposes, Figure 6 The memory device 600 is simplified, therefore, it should be understood that Figure 6 Can be omitted Figure 1 some components of .

[0058] As shown, the memory device 600 includes a first driver circuit 610, a second driver circuit 620, a first pull-down circuit 630, and a second pull-down circuit 640. According to some embodiments, the first driver circuit 610 and the first pull-down circuit 630 are physically disposed (or otherwise formed) on a first side of the memory array 102, for example, along the Y direction, and the second driver circuit 620 and the second pull-down circuit 640 are physically disposed, for example, along the Y direction, on a second side of the memory array 102. In addition, the first driver circuit 610 includes sub-circuits 610A and 610B; the second driver circuit 620 includes sub-circuits 620A and 620B; the first pull-down circuit 630 includes sub-circuits 630A and 630B; and the second pull-down circuit 640 includes sub-circuits 640A and 640B.

[0059] In some embodiments, the sub-circuit 610A of the first driver circuit 610 includes two p-type transistors 612 and 614 connected in series with each other; the sub-circuit 610B of the first driver circuit 610 includes a p-type transistor 616; the sub-circuit 620A of the second driver circuit 620 includes two p-type transistors 622 and 624 connected in series with each other; the sub-circuit 620B of the second driver circuit 620 includes a p-type transistor 626; the sub-circuit 630A of the first pull-down circuit 630 includes two n-type transistors 632 and 634 connected in series with each other; the sub-circuit 630B of the pull-down circuit 630 includes an n-type transistor 636; the sub-circuit 640A of the second pull-down circuit 640 includes two n-type transistors 642 and 644 connected in series with each other; the sub-circuit 640B of the second pull-down circuit 640 includes an n-type transistor 646. Sub-circuits 610A and 610B of the first driver circuit 610 and sub-circuits 620A and 620B of the second driver circuit 620 are both configured to selectively couple a programming voltage (e.g., VBL) to the memory cell 103A via BL or SL, while sub-circuits 630A and 630B of the pull-down circuit 630 and sub-circuits 640A and 640B of the pull-down circuit 640 are both configured to selectively couple the memory cell 103A to ground via BL or SL.

[0060] The p-type transistors 612 to 616 of the first driver circuit 610 are gated (e.g., activated) by corresponding control signals to couple the programming voltage to the memory cell 103A. Similarly, the p-type transistors 622 to 626 of the second driver circuit 620 are gated (e.g., activated) by corresponding control signals to couple the programming voltage to the memory cell 103A. For example, the p-type transistors 612 to 616 and 622 to 626 can each be turned on in response to the corresponding control signal being asserted to a logic low state. The n-type transistors 632 to 636 of the first pull-down circuit 630 are gated (e.g., activated) by corresponding control signals to ground the memory cell 103A. Similarly, the n-type transistors 642 to 646 of the second pull-down circuit 640 are gated (e.g., activated) by corresponding control signals to ground the memory cell 103A. For example, n-type transistors 632-636 and 642-646 may each be turned on in response to a corresponding control signal being asserted to a logic high state. In some embodiments, the respective logic states of these control signals may be configured based on the logic state to be programmed into memory cell 103A.

[0061] In some embodiments, subcircuit 610A and subcircuit 610B of the first driver circuit 610 can be alternately activated to couple the programming voltage to the memory cell 103A; subcircuit 620A and subcircuit 620B of the second driver circuit 620 can be alternately activated to couple the programming voltage to the memory cell 103A; subcircuit 630A and subcircuit 630B of the first pull-down circuit 630 can be alternately activated to ground the memory cell 103A; and subcircuit 640A and subcircuit 640B of the second pull-down circuit 640 can be alternately activated to ground the memory cell 103A.

[0062] For example, to program a logic 0 into memory cell 103A (from the AP state to the P state), subcircuits 610A, 620A, 630B, and 640B are activated, while subcircuits 610B, 620B, 630A, and 640A are deactivated. Thus, a programming voltage may be coupled to memory cell 103A via BL (and subcircuits 610A and 620A, respectively), and memory cell 103A may be coupled to ground via SL (and subcircuits 630B and 640B, respectively). Equivalently, two conduction paths 651 and 653 may flow through memory cell 103A. Conduction path 651 extends from subcircuit 610A, through memory cell 103A and subcircuit 630B, and to ground; conduction path 653 extends from subcircuit 620A, through memory cell 103A and subcircuit 640B, and to ground. In other words, conductive path 651 extends from a first side of memory array 102 to a first side of memory array 102 , while conductive path 653 extends from a second side of memory array 102 to a second side of memory array 102 .

[0063] In another example, to program a logic 1 into memory cell 103A (from a P state to an AP state), subcircuits 610B, 620B, 630A, and 640A are activated, while subcircuits 610A, 620A, 630B, and 640B are deactivated. Thus, a programming voltage may be coupled to memory cell 103A via SL (and subcircuits 610B and 620B, respectively), and memory cell 103A may be coupled to ground via BL (and subcircuits 630A and 640A, respectively). Equivalently, two conduction paths 671 and 673 may flow through memory cell 103A. Conduction path 671 extends from subcircuit 610B, through memory cell 103A and subcircuit 630A, and to ground; conduction path 673 extends from subcircuit 620B, through memory cell 103A and subcircuit 640A, and to ground. In other words, conductive path 671 extends from a first side of memory array 102 to a first side of memory array 102 , while conductive path 673 extends from a second side of memory array 102 to a second side of memory array 102 .

[0064] Figure 7 Some embodiments of the present disclosure are shown Figure 1 700 is another example schematic diagram of a portion of the memory device 100 (hereinafter referred to as "memory device 700"). The memory device 700 is similar to the memory device 400 ( Figure 4), for example, including a first driver circuit 410 disposed on a first side of the memory array 102, and a second driver circuit 420 and a pull-down circuit 430 disposed on a second side of the memory array 102, except that the transistors of each of the sub-circuits 410A, 420A, and 430A can be activated by different control signals. Therefore, the following discussion of the memory device 700 will focus on the differences.

[0065] For subcircuit 410A, transistor 412 is gated by control signal MX1, while transistor 414 is gated by control signal S1B; for subcircuit 410B, transistor 416 is gated by control signal S1. Similarly, transistors 422 and 424 of subcircuit 420A are gated by control signals S1B and MX1, respectively, while transistor 426 of subcircuit 420B is gated by control signal S1; transistors 432 and 434 of subcircuit 430A are gated by control signals S1B and MX1, respectively, while transistor 436 of subcircuit 430B is gated by control signal S1. In some embodiments, the logic state of signal MX1 can be configured based on determining that a group of columns of memory cells are to be programmed / read, and the logic state of signal S1 / S1B can be configured based on determining that a certain memory cell is to be programmed / read. Therefore, signal MX1 and signal S1 / S1B can have different pulse widths, respectively. For example, the pulse width of signal MX1 is wider than the pulse width of signal S1 / S1B. In addition, the control signals S1 and S1B are logically opposite to each other. Therefore, sub-circuits of any one of the first driver circuit 410, the second driver circuit 420, and the pull-down circuit 430 may be activated alternately.

[0066] use Figure 7 As a representative example, signal MX1 may be pulled to a logic low state and then signal S1B may be pulled to a logic state where signal S1 is pulled to a logic high state. In some other embodiments, signal MX1 and signal S1B may be pulled down simultaneously. Thus, subcircuits 410A, 420A, and 430B may be activated, while subcircuits 410B, 420B, and 430A may be deactivated. Thus, subcircuits 410A and 420A may each couple a programming voltage (VBL) to memory cell 103A, and subcircuit 430B may couple memory cell 103A to ground, thereby writing a logic 0 to memory cell 103A.

[0067] Figure 8 Some embodiments of the present disclosure are shown Figure 1 800 is another example schematic diagram of a portion of the memory device 100 (hereinafter referred to as "memory device 800"). The memory device 800 is similar to the memory device 500 ( Figure 5), for example, including a first driver circuit 510 and a pull-down circuit 530 disposed on a first side of the memory array 102, and a second driver circuit 520 disposed on a second side of the memory array 102, except that the transistors of each of the sub-circuits 510A, 520A, and 530A can be activated by different control signals. Therefore, the following discussion of the memory device 800 will focus on the differences.

[0068] For subcircuit 510A, transistor 512 is gated by control signal MX1, while transistor 514 is gated by control signal S1B; for subcircuit 510B, transistor 516 is gated by control signal S1. Similarly, transistors 522 and 524 of subcircuit 520A are gated by control signals S1B and MX1, respectively, while transistor 526 of subcircuit 520B is gated by control signal S1; transistors 532 and 534 of subcircuit 530A are gated by control signals MX1 and S1B, respectively, while transistor 536 of subcircuit 530B is gated by control signal S1. In some embodiments, the logic state of signal MX1 can be configured based on determining that a group of columns of memory cells are to be programmed / read, and the logic state of signal S1 / S1B can be configured based on determining that a certain memory cell is to be programmed / read. Therefore, signal MX1 and signal S1 / S1B can have different pulse widths, respectively. For example, the pulse width of signal MX1 is wider than the pulse width of signal S1 / S1B. In addition, the control signals S1 and S1B are logically opposite to each other. Therefore, sub-circuits of any one of the first driver circuit 510, the second driver circuit 520, and the pull-down circuit 530 may be activated alternately.

[0069] use Figure 8 As a representative example, signal MX1 may be pulled to a logic low state and then signal S1B may be pulled to a logic state where signal S1 is pulled to a logic high state. In some other embodiments, signal MX1 and signal S1B may be pulled down simultaneously. Thus, subcircuits 510A, 520A, and 530B may be activated, while subcircuits 510B, 520B, and 530A may be deactivated. Thus, subcircuits 510A and 520A may each couple a programming voltage (VBL) to memory cell 103A, and subcircuit 530B may couple memory cell 103A to ground, thereby writing a logic 0 to memory cell 103A.

[0070] Fig. 9 Some embodiments of the present disclosure are shown Figure 1 900 is another example schematic diagram of a portion of a memory device 100 (hereinafter referred to as a "memory device 900"). The memory device 900 is similar to the memory device 600 ( Figure 6), for example, including a first driver circuit 610 and a first pull-down circuit 630 disposed on a first side of the memory array 102, and a second driver circuit 620 and a second pull-down circuit 640 disposed on a second side of the memory array 102, except that the transistors of each of the sub-circuits 610A, 620A, 630A, and 640A can be activated by different control signals. Therefore, the following discussion of the memory device 900 will focus on the differences.

[0071] For subcircuit 610A, transistor 612 is selected by control signal MX1, while transistor 614 is selected by control signal S1B; for subcircuit 610B, transistor 616 is selected by control signal S1. Similarly, transistors 622 and 624 of subcircuit 620A are selected by control signals S1B and MX1, respectively, while transistor 626 of subcircuit 620B is selected by control signal S1; transistors 632 and 634 of subcircuit 630A are selected by control signals MX1 and S1B, respectively, while transistor 636 of subcircuit 630B is selected by control signal S1; transistors 642 and 644 of subcircuit 640A are selected by control signals S1B and MX1, respectively, while transistor 646 of subcircuit 640B is selected by control signal S1. In some embodiments, the logic state of the signal MX1 can be configured based on determining that a group of columns of memory cells are to be programmed / read, and the logic state of the signal S1 / S1B can be configured based on determining that a certain memory cell is to be programmed / read. Therefore, the signal MX1 and the signal S1 / S1B can have different pulse widths, respectively. For example, the pulse width of the signal MX1 is wider than the pulse width of the signal S1 / S1B. In addition, the control signals S1 and S1B are logically opposite to each other. Therefore, the sub-circuit of any one of the first driver circuit 610, the second driver circuit 620, the first pull-down circuit 630, and the second pull-down circuit 640 can be activated alternately.

[0072] use Fig. 9 As a representative example, signal MX1 may be pulled to a logic low state and then signal S1B may be pulled to a logic state where signal S1 is pulled to a logic high state. In some other embodiments, signal MX1 and signal S1B may be pulled down simultaneously. Thus, subcircuits 610A, 620A, 630B, and 640B may be activated, while subcircuits 610B, 620B, 630A, and 640A may be deactivated. Thus, subcircuits 610A and 620A may respectively couple a programming voltage (VBL) to memory cell 103A, and subcircuits 630B and 640B may respectively couple memory cell 103A to ground, thereby writing a logic 0 to memory cell 103A.

[0073] Fig.10 Some embodiments of the present disclosure are shown Figure 1 1000 (hereinafter referred to as "memory device 1000"). The memory device 1000 is similar to the memory device 900 ( Fig. 9 ), for example, including a first driver circuit 610 and a first pull-down circuit 630 disposed at a first side of the memory array 102 and controlled by a signal MX1 / S1B / S1, and a second driver circuit 620 and a second pull-down circuit 640 disposed at a second side of the memory array 102 and controlled by a signal MX1 / S1B / S, except that the memory device 1000 further includes sub-circuits 1010 and 1020 to further reduce the on-resistance. Therefore, the following discussion of the memory device 1000 will focus on the differences.

[0074] As shown, subcircuits 1010 and 1020 are physically disposed on the same side of memory array 102 as subcircuits 610A-B and 630A-B (i.e., a first side along the Y direction). It should be understood that subcircuits 1010 and 1020 may be disposed on a second side of memory array 102 (i.e., the same side as subcircuits 620A-B and 640A-B) while remaining within the scope of the present disclosure. In addition, subcircuit 1010 includes p-type transistors 1012 and 1014 that are respectively selected by signals MX1 and S1B; subcircuit 1020 includes n-type transistors 1022 and 1024 that are respectively selected by signals MX1 and S1B. In some embodiments, subcircuit 1010 is configured to couple a programming voltage (VBL) to memory cell 103A; subcircuit 1020 is configured to ground memory cell 103A. In some embodiments, subcircuit 1010 can be activated simultaneously with subcircuits 610A, 620A, 630B, and 640B, and thus, at least one additional conductive path can be formed to extend through memory cell 103A (e.g., starting from subcircuit 1010, through memory cell 103A and subcircuit 630B, and reaching ground).

[0075] Fig.11 Some embodiments of the present disclosure are shown Figure 1 100 (hereinafter referred to as "memory device 1100"). The memory device 1100 is similar to the memory device 1000 ( Fig.10), for example, including a first driver circuit 610 and a first pull-down circuit 630 controlled by a signal MX1 / S1B / S1, a second driver circuit 620 and a second pull-down circuit 640 controlled by a signal MX1 / S1B / S1, except that the memory device 1000 also includes sub-circuits 1010 and 1020 to further reduce the on-resistance. Therefore, the following discussion of the memory device 1000 will focus on the differences. As shown, the additional sub-circuits 1010 and 1020 can be physically disposed on a third side of the memory array. For example, the sub-circuits 1010 and 1020 can be disposed on one side of the memory array 102 along the X direction.

[0076] Fig.12 The waveforms of the above-mentioned signals S1, S1B and MX1 according to some embodiments of the present disclosure are shown. For example, the corresponding waveforms of the signals S1, S1B and MX1 when writing logic 0 and writing logic 1 to the corresponding memory cell (e.g., 103A) are shown respectively. When writing logic 0, the signal MX1 can be pulled low, and then the signal S1 is pulled high (the logic inversion signal S1B is pulled low). When writing logic 1, the signal MX1 can be pulled high, and then the signal S1 is pulled low (while the logic inversion signal S1B is pulled high).

[0077] Fig.13 A flow chart of an example method 1300 for operating a memory device including access circuits physically disposed on opposite sides of a memory array according to some embodiments is shown. For example, at least some operations of method 1300 may be performed to write / read a memory cell (e.g., 103A) based on at least two conduction paths. Therefore, in the following discussion of method 1300, the above may be reused. Figure 1-Figure 12 Reference numerals used in the method 1300 are provided. It should be noted that the method 1300 is merely an example and is not intended to limit the present disclosure. Therefore, it is understood that Fig.13 Additional operations may be provided before, during, and after method 1300. And some other operations may only be briefly described here.

[0078] Method 1300 begins with operation 1310, in which a plurality of access circuits physically disposed on opposite sides of a memory array are activated. In some embodiments, the memory array (e.g., 102) includes a plurality of memory cells (e.g., MRAM cells 103) arranged in a plurality of columns and a plurality of rows. Along each column, a subset of the memory cells are coupled to each other through bit lines and source lines, each of which may extend in the Y direction; and along each row, another subset of the memory cells are coupled to each other through word lines, which may extend in the X direction.

[0079] In one aspect of the present disclosure (e.g., Figure 3In a memory device 300 of the present disclosure, a first access circuit (e.g., 310) is physically disposed on a first side of a memory array 102 along a Y direction, a second access circuit (e.g., 320) is physically disposed on a first side of the memory array 102 along a Y direction, and a third access circuit (e.g., 330) is physically disposed on a second side of the memory array 102 along a Y direction. In another aspect of the present disclosure (e.g., Figure 4 In a memory device 400 of the present disclosure, a first access circuit (e.g., 410) is physically disposed on a first side of a memory array 102, a second access circuit (e.g., 420) is physically disposed on a second side of the memory array 102, and a third access circuit (e.g., 430) is physically disposed on a second side of the memory array 102. In another aspect of the present disclosure (e.g., Figure 5 In a memory device 500 of the present disclosure, a first access circuit (e.g., 510) is physically disposed on a first side of a memory array 102, a second access circuit (e.g., 520) is physically disposed on a second side of the memory array 102, and a third access circuit (e.g., 530) is physically disposed on the first side of the memory array 102. In another aspect of the present disclosure (e.g., Figure 6 In the memory device 600, a first access circuit (e.g., 610) is physically disposed on a first side of a memory array 102, a second access circuit (e.g., 620) is physically disposed on a second side of the memory array 102, a third access circuit (e.g., 630) is physically disposed on the first side of the memory array 102, and a fourth access circuit (e.g., 640) is physically disposed on the second side of the memory array 102.

[0080] In order to access (e.g., program, read) the memory array, multiple access circuits can be activated. Specifically, each access circuit can include two sub-circuits that can be activated alternately based on the logic state to be programmed into the corresponding memory cell. Since at least two access circuits are arranged on opposite sides of the memory array 102, each memory cell in the memory array 102 can be programmed / read through at least two conduction paths, which can advantageously reduce the equivalent resistance along the conduction path. In the following discussion of method 1300, the memory device 300 ( Figure 3 ) is used as a representative example. When a logic 0 is written, the sub-circuit 310A of the access circuit 310, the sub-circuit 320B of the access circuit 320, and the sub-circuit 330B of the access circuit 330 are activated, and the other sub-circuit (310B, 320A, 330A) of each access circuit is deactivated. When a logic 1 is written, the sub-circuit 310B of the access circuit 310, the sub-circuit 320A of the access circuit 320, and the sub-circuit 330A of the access circuit 330 are activated, and the other sub-circuit (310A, 320B, 330B) of each access circuit is deactivated.

[0081] Method 1300 proceeds to operation 1320, where a voltage is provided to the memory cell. Continuing with the same example above, when the memory cell is selected for programming, the voltage may be a programming voltage (VBL). Based on the logic state to be programmed, different subcircuits of the access circuit may be activated to couple the programming voltage to the memory cell. When subcircuits 310A, 320B, and 330B are activated (e.g., to write a logic 0 to the memory cell), the programming voltage may be coupled to the memory cell through its corresponding bit line. When subcircuits 310B, 320A, and 330A are activated (e.g., to write a logic 1 to the memory cell), the programming voltage may be coupled to the memory cell through its corresponding source line.

[0082] Method 1300 proceeds to operation 1330, in which a first current is conducted to flow through the memory cell, and operation 1340, in which a second current is conducted to flow through the memory cell. In some embodiments, operations 1330 and 1340 may be performed simultaneously. Still using the same example described above (when writing a logic 0 to the memory cell), subcircuits 310A, 320B, and 330B are activated. Thus, a first conduction path (e.g., 351) extending from subcircuit 310A through memory cell 103A and subcircuit 320B and reaching ground, and a second conduction path (e.g., 353) extending from subcircuit 310A through memory cell 103A and subcircuit 330B and reaching ground may be formed. When writing a logic 1 to the memory cell, subcircuits 310B, 320A, and 330A are activated. Thus, a first conductive path (eg, 371) extending from subcircuit 310B through memory cell 103A and subcircuit 320A to ground and a second conductive path (eg, 373) extending from subcircuit 310B through memory cell 103A and subcircuit 330A to ground may be formed.

[0083] In one aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a memory array, the memory array includes a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines, and the plurality of access lines extend in a lateral direction. The memory circuit includes a first access circuit, the first access circuit is physically arranged on a first side of the memory array in a lateral direction. The memory circuit includes a second access circuit, the second access circuit is physically arranged on a second side of the memory array in a lateral direction, and the second side is opposite to the first side. When each non-volatile memory cell is configured to be programmed by at least a first current and a second current, the first current and the second current flow through a first path and a second path, respectively. The first path includes at least a portion on the first side, and the second path includes at least a portion on the second side.

[0084] In some embodiments, each nonvolatile memory cell includes a magnetic tunnel junction element.

[0085] In some embodiments, the first access circuit includes a first subcircuit and a second subcircuit, and the second access circuit includes a third subcircuit, and wherein the first subcircuit and the second subcircuit are operable to form part of a first path, and the first subcircuit and the third subcircuit are operable to form part of a second path.

[0086] In some embodiments, the first subcircuit is configured to couple a programming voltage to a corresponding one of the nonvolatile memory cells through a corresponding one of the access lines, and the second subcircuit and the third subcircuit are configured to couple the first path and the second path to ground, respectively.

[0087] In some embodiments, the first access circuit includes a first subcircuit and the second access circuit includes a second subcircuit and a third subcircuit, and wherein the first subcircuit and the third subcircuit are operable to form part of a first path and the second subcircuit and the third subcircuit are operable to form part of a second path.

[0088] In some embodiments, the first subcircuit and the second subcircuit are each configured to couple a programming voltage to a corresponding one of the nonvolatile memory cells through a corresponding one of the access lines, and the third subcircuit is configured to couple the first path and the second path to ground.

[0089] In some embodiments, the first access circuit includes a first subcircuit and a second subcircuit, and the second access circuit includes a third subcircuit, and wherein the first subcircuit and the second subcircuit are operable to form part of a first path, and the third subcircuit and the second subcircuit are operable to form part of a second path.

[0090] In some embodiments, the first subcircuit and the third subcircuit are each configured to couple a programming voltage to a corresponding one of the nonvolatile memory cells through a corresponding one of the access lines, and the second subcircuit is configured to couple the first path and the second path to ground.

[0091] In some embodiments, the first access circuit includes a first subcircuit and a second subcircuit, and the second access circuit includes a third subcircuit and a fourth subcircuit, and wherein the first subcircuit and the second subcircuit are operable to form part of a first path, and the third subcircuit and the fourth subcircuit are operable to form part of a second path.

[0092] In some embodiments, the first sub-circuit and the third sub-circuit are each configured to couple a programming voltage to a corresponding one of the non-volatile memory cells through a corresponding one of the access lines, and the second sub-circuit and the fourth sub-circuit are configured to couple the first path and the second path to ground, respectively.

[0093] In some embodiments, the first path and the second path both extend from the first side or the second side, both extend through a corresponding one of the nonvolatile memory cells, and then diverge toward the first side and the second side, respectively.

[0094] In some embodiments, the first path and the second path extend from the first side and the second side, respectively, each extend through a corresponding one of the nonvolatile memory cells, and then each extend toward the first side or the second side.

[0095] In some embodiments, the first current and the second current have the same direction, and the directions are configured to determine a logic state programmed into a corresponding one of the non-volatile memory cells.

[0096] In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a plurality of non-volatile memory cells arranged above a plurality of bit lines extending in a lateral direction. The memory circuit includes: a first access circuit physically disposed on a first side of the non-volatile memory cell in the lateral direction, wherein the first access circuit includes a first subcircuit and a second subcircuit. The memory circuit includes: a second access circuit physically disposed on a second side of the non-volatile memory cell in the lateral direction, the second side being opposite to the first side, wherein the second access circuit includes a third subcircuit and a fourth subcircuit. The first subcircuit is configured to couple a programming voltage to a corresponding one of the plurality of non-volatile memory cells, and when a first logic state is programmed to the corresponding non-volatile memory cell, the second subcircuit and the fourth subcircuit are both configured to supplement a conduction path from the programming voltage to ground. The second subcircuit is configured to couple a programming voltage to the corresponding non-volatile memory cell, and when a second logic state is programmed to the corresponding non-volatile memory cell, the first subcircuit and the third subcircuit are both configured to supplement another conduction path from the programming voltage to ground.

[0097] In some embodiments, each of the nonvolatile memory cells includes a magnetic tunnel junction element.

[0098] In some embodiments, the first sub-circuit and the second sub-circuit each include one or more first switches coupled between a corresponding one of the bit lines and a corresponding non-volatile memory cell.

[0099] In some embodiments, the first sub-circuit and the second sub-circuit each include one or more second switches coupled between the corresponding non-volatile memory cell and ground.

[0100] In some embodiments, the third sub-circuit and the fourth sub-circuit each include one or more third switches coupled between the corresponding non-volatile memory cell and ground.

[0101] In another aspect of the present disclosure, a method for operating a memory circuit is disclosed. The method includes: activating (i) a first access circuit physically disposed on a first side of a nonvolatile memory cell; (ii) a second access circuit physically disposed on a first side of the nonvolatile memory cell; and (iii) a third access circuit physically disposed on a second side of the nonvolatile memory cell. The method includes providing a voltage to the nonvolatile memory cell. The method includes: conducting a first current flowing through a first conduction path, the first conduction path extending from a voltage, passing through a first access circuit, a nonvolatile memory cell, and a second access circuit, and reaching ground. The method includes: conducting a second current flowing through a second conduction path, the second conduction path extending from a programming voltage, passing through a first access circuit, a nonvolatile memory cell, and a third access circuit, and reaching ground.

[0102] In some embodiments, the non-volatile memory cell includes a magnetic tunnel junction element.

[0103] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of a value (e.g., +10%, ±20%, or ±30% of a value).

[0104] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory circuit, comprising: A memory array comprising a plurality of nonvolatile memory cells, wherein the nonvolatile memory cells are arranged along a plurality of access lines extending in a lateral direction; a first access circuit physically disposed on a first side of the memory array in the lateral direction; and a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side; Wherein, when each of the nonvolatile memory cells is configured to be programmed by at least a first current and a second current, the first current and the second current flow through a first path and a second path, respectively, and wherein the first path includes at least a portion on the first side and the second path includes at least a portion on the second side.

2. The memory circuit according to claim 1, wherein: The first access circuit includes a first subcircuit and a second subcircuit, and the second access circuit includes a third subcircuit, and wherein the first subcircuit and the second subcircuit are operably formed as part of the first path, and the first subcircuit and the third subcircuit are operably formed as part of the second path.

3. The memory circuit according to claim 2, wherein: The first subcircuit is configured to couple a programming voltage to a corresponding one of the nonvolatile memory cells through a corresponding one of the access lines, and the second and third subcircuits are configured to couple the first and second paths to ground, respectively.

4. The memory circuit according to claim 1, wherein: The first access circuit includes a first subcircuit and the second access circuit includes a second subcircuit and a third subcircuit, and wherein the first subcircuit and the third subcircuit are operably formed as part of the first path and the second subcircuit and the third subcircuit are operably formed as part of the second path.

5. The memory circuit according to claim 1, wherein: The first access circuit includes a first subcircuit and a second subcircuit, and the second access circuit includes a third subcircuit, and wherein the first subcircuit and the second subcircuit are operable to form part of the first path, and the third subcircuit and the second subcircuit are operable to form part of the second path.

6. The memory circuit according to claim 5, wherein: The first subcircuit and the third subcircuit are each configured to couple a programming voltage to a corresponding one of the nonvolatile memory cells through a corresponding one of the access lines, and the second subcircuit is configured to couple the first path and the second path to ground.

7. The memory circuit according to claim 1, wherein: The first access circuit includes a first subcircuit and a second subcircuit, and the second access circuit includes a third subcircuit and a fourth subcircuit, and wherein the first subcircuit and the second subcircuit are operable to form part of the first path, and the third subcircuit and the fourth subcircuit are operable to form part of the second path.

8. The memory circuit according to claim 1, wherein: The first current and the second current have the same direction, and the directions are configured to determine a logic state programmed into a corresponding one of the nonvolatile memory cells.

9. A memory circuit comprising: a plurality of nonvolatile memory cells arranged above a plurality of bit lines extending in a lateral direction; a first access circuit physically disposed on a first side of the nonvolatile memory cell in a lateral direction, wherein the first access circuit includes a first sub-circuit and a second sub-circuit; and a second access circuit physically disposed on a second side of the nonvolatile memory cell in the lateral direction, the second side being opposite to the first side, wherein the second access circuit includes a third sub-circuit and a fourth sub-circuit; wherein the first subcircuit is configured to couple a programming voltage to a corresponding one of the plurality of nonvolatile memory cells, and when programming a first logic state to the corresponding nonvolatile memory cell, the second subcircuit and the fourth subcircuit are both configured to supplement a conduction path from the programming voltage to ground; and The second sub-circuit is configured to couple the programming voltage to the corresponding non-volatile memory cell, and when programming the second logic state to the corresponding non-volatile memory cell, the first sub-circuit and the third sub-circuit are both configured to supplement another conduction path from the programming voltage to ground.

10. A method for operating a memory circuit, comprising: activating (i) a first access circuit physically disposed on a first side of the nonvolatile memory cell; (ii) a second access circuit physically disposed on the first side of the nonvolatile memory cell; and (iii) a third access circuit physically disposed on the second side of the nonvolatile memory cell; providing a voltage to the nonvolatile memory cell; conducting a first current through a first conduction path extending from the voltage, through the first access circuit, the nonvolatile memory cell, and the second access circuit, and to ground; as well as A second current is conducted through a second conduction path extending from the programming voltage, through the first access circuit, the nonvolatile memory cell, and the third access circuit, and to ground.

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