Preparation method of chip packaging structure and chip packaging structure

Abstract

The embodiment of the invention provides a preparation method of a chip packaging structure and the chip packaging structure. The chip packaging structure comprises a first chip, a second protection layer, a second chip, a third protection layer, a first conductive connection structure, a second conductive connection structure and a polyimide layer, the second protection layer is located on one side, close to the second chip, of the first chip, the third protection layer is located on one side, away from the first chip, of the second chip, and the polyimide layer is formed on the side wall of the first chip; the first conductive connection structure is arranged in the first opening, the second chip is electrically connected with the first chip through the first conductive connection structure, the second conductive connection structure is arranged at the second opening, the third protection layer exposes part of the second conductive connection structure, and the first chip outputs or receives an electric signal through the second conductive connection structure. The prepared chip packaging structure is small in overall size and high in integration level.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology and related technical fields, and in particular to a preparation method for a chip packaging structure and a chip packaging structure. Background Art

[0002] Wafer Level Chip Scale Packaging (WLCSP) is a wafer-level chip packaging method. This latest technology is to package and test the entire wafer first, and then cut it into individual IC particles. Therefore, the volume after packaging is equivalent to the original size of the IC bare crystal.

[0003] In traditional CSP packaging, only the original chip is encapsulated with plastic, and the chip is electrically connected to the PCB circuit board through the bonding pad. The integration is relatively low, and the overall volume of the prepared chip is large. In addition, since the prepared semiconductor chip is the original plastic encapsulation, the cutting path between two adjacent chips is wide, and the number of chips accommodated on a thin sheet is small. Summary of the invention

[0004] The embodiments described herein provide a method for preparing a chip packaging structure and a chip packaging structure with a high degree of integration.

[0005] In a first aspect, according to the present disclosure, a method for preparing a chip packaging structure is provided, comprising:

[0006] Forming a second protective layer on a wafer having a plurality of first chips, wherein the second protective layer includes a first opening and a second opening;

[0007] After forming a first conductive connection structure in the first opening of the second protective layer, flip-chip connecting the second chip to the first chip on the wafer through the first conductive connection structure;

[0008] forming a second conductive connection structure at a second opening position of the second protective layer;

[0009] forming a third protective layer on the second conductive connection structure and the second chip on a side away from the second protective layer;

[0010] Cutting the wafer from a side of the wafer away from the second protective layer at a position between two adjacent first chips to form a scribe line, and spraying polyimide on the scribe line to form a polyimide layer on a surface of the scribe line;

[0011] Processing the third protective layer so that a portion of the second conductive connection structure is exposed outside the third protective layer;

[0012] The positions of the cutting paths are cut again to obtain a plurality of separated chip packaging structures.

[0013] In some embodiments of the present disclosure, forming a second conductive connection structure at the second opening position of the second protective layer includes:

[0014] Forming a mask layer on a side of the second protective layer away from the wafer, wherein the mask layer comprises a third opening, and a vertical projection of the third opening on the wafer covers a vertical projection of the second opening on the wafer;

[0015] After forming a second conductive connection structure at the second opening position of the second protection layer, the mask layer is removed.

[0016] In some embodiments of the present disclosure, the wafer is cut from a side of the wafer away from the second protective layer at a position between two adjacent first chips to form a scribe line, and polyimide is sprayed on the scribe line. Before a polyimide layer is formed on a surface of the scribe line, the method further includes:

[0017] Performing a thinning process on the wafer at a side of the wafer away from the second protective layer;

[0018] A first protective layer is formed on a side of the wafer away from the second protective layer.

[0019] In some embodiments of the present disclosure, before forming the first protective layer on the side of the wafer away from the second protective layer, the method further includes:

[0020] A metal layer is formed on a side of the wafer away from the second protective layer.

[0021] In some embodiments of the present disclosure, the materials of the first protective layer and the third protective layer are epoxy resin, the material of the second protective layer is polyimide, and the second conductive connection structure is a solder ball.

[0022] In some embodiments of the present disclosure, before processing the third protective layer so that part of the second conductive connection structure is exposed outside the third protective layer, the method further includes:

[0023] Disposing a support layer on a side of the wafer away from the second protective layer;

[0024] After the positions of the cutting paths are cut again to obtain a plurality of separated chip packaging structures, the method further comprises:

[0025] The prepared chip packaging structure is separated from the supporting layer.

[0026] In a second aspect, according to the present disclosure, there is provided a chip packaging structure, comprising: sequentially stacking a first chip, a second protective layer, a second chip and a third protective layer, and a first conductive connection structure, a second conductive connection structure and a polyimide layer;

[0027] The second protective layer is located on a side of the first chip close to the second chip, the third protective layer is located on a side of the second chip away from the first chip, and the polyimide layer is formed on a side wall of the first chip;

[0028] The second protective layer includes a first opening and a second opening, the first conductive connection structure is arranged in the first opening, the second chip is flip-chip connected to the first chip through the first conductive connection structure, the second conductive connection structure is arranged at the second opening, the third protective layer exposes a portion of the second conductive connection structure, and the first chip outputs or receives electrical signals through the second conductive connection structure.

[0029] In some embodiments of the present disclosure, the thickness of the third protection layer is H1, the thickness of the second chip is H2, and the thickness of the second conductive connection structure is H3, then H1, H2 and H3 satisfy: H2

[0030] The thickness of the third protective layer satisfies:

[0031] In some embodiments of the present disclosure, a first protective layer and a metal layer are further included. The metal layer is located on a side of the first chip away from the second chip, and the first protective layer is located on a side of the metal layer away from the first chip.

[0032] In some embodiments of the present disclosure, the materials of the first protective layer and the third protective layer are epoxy resin, the material of the second protective layer is polyimide, and the second conductive connection structure is a solder ball.

[0033] ​The chip packaging structure preparation method and chip packaging structure provided by the embodiment of the present disclosure include a first chip, a second protective layer, a second chip and a third protective layer stacked in sequence, as well as a first conductive connection structure, a second conductive connection structure and a polyimide layer. The second chip is electrically connected to an external PCB circuit board through the first conductive connection structure, the first chip and the second conductive connection structure to achieve output or reception of electrical signals. Compared with the prior art in which one chip is used to achieve reception or output of electrical signals of different functional modules, the chip packaging structure prepared by the embodiment of the present disclosure has a higher degree of integration. In addition, after the first protective layer and the first chip are cut to form a cutting path, the surface of the cutting path is A polyimide layer is formed on the surface. Based on the properties of the polyimide layer material, the particles of polyimide are relatively small, and the thickness of the prepared polyimide layer is relatively thin. Therefore, in the process of preparing and forming the cutting path, the width of the formed cutting path is relatively narrow. Compared with the prior art, in the process of preparing and forming the chip packaging structure, the cutting path can only form a plastic packaging material. Since the plastic packaging material is an epoxy resin material, the particles of the epoxy resin material are generally larger, and the thickness of the formed epoxy resin is thicker. Therefore, the width of the formed cutting path is wider. In the preparation method of the chip packaging structure provided in the embodiment of the present disclosure, the cutting path between two adjacent first chips is narrower. Therefore, the number of chips that can be accommodated on a wafer will be more than that of the prior art.

[0034] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0036] Figure 1 is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present disclosure;

[0037] Figure 2 is a structural schematic diagram of another chip packaging structure provided by an embodiment of the present disclosure;

[0038] Figure 3 It is a schematic flow chart of a method for preparing a chip packaging structure provided by an embodiment of the present disclosure;

[0039] Figures 4A-4K is a process schematic diagram of a method for preparing a chip packaging structure provided by an embodiment of the present disclosure;

[0040] Figures 5A-5D It is a process schematic diagram of a method for preparing a chip packaging structure provided in an embodiment of the present disclosure.

[0041] Among them, 10, first protective layer; 20, first chip; 21, wafer; 30, second protective layer; 40, second chip; 50, third protective layer; 60, first conductive connection structure; 70, second conductive connection structure; 31, first opening; 32, second opening; 80, metal layer.

[0042] In the drawings, reference numerals with the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0045] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] The term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0047] Furthermore, in all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0048] In the description of the present application, unless otherwise specified, "plurality" means more than two (including two), and similarly, "multiple groups" means more than two groups (including two).

[0049] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0050] Based on the problems existing in the prior art, the present disclosure provides a chip packaging structure. Figure 1 is a schematic diagram of the structure of the chip packaging structure provided by the embodiment of the present disclosure, such as Figure 1 As shown, the chip packaging structure includes: a first chip 20, a second protective layer 30, a second chip 40 and a third protective layer 50 are stacked in sequence, as well as a first conductive connection structure 60, a second conductive connection structure 70 and a polyimide layer 90; the second protective layer 30 is located on the side of the first chip 20 close to the second chip 40, the third protective layer 50 is located on the side of the second chip 40 away from the first chip 20, and the polyimide layer 90 is formed on the side wall of the first chip 20; the second protective layer 30 includes a first opening 31 and a second opening 32, the first conductive connection structure 60 is arranged in the first opening 31, the second chip 40 is flip-chip connected to the first chip 20 through the first conductive connection structure 60, the second conductive connection structure 70 is arranged at the second opening 32, the third protective layer 50 exposes a portion of the second conductive connection structure 70, and the first chip 20 outputs or receives electrical signals through the second conductive connection structure 70.

[0051] In a specific embodiment, in combination with Figure 1 In the embodiment of the present disclosure, the prepared chip packaging structure includes a first chip 20 and a second chip 40, wherein the first chip 20 is a WLCSP chip, and the second chip 40 is a flip chip. The second chip 40 serves as the main control chip in the chip packaging structure provided by the embodiment of the present disclosure. The control logics of different functional modules in the first chip 20 are integrated on the second chip 40, and the first chip 20 is controlled by the second chip 40 to receive or output electrical signals. Specifically, the second chip is electrically connected to an external PCB circuit board through the first conductive connection structure, the first chip, and the second conductive connection structure to achieve output or reception of electrical signals. Compared with the prior art in which one chip is used to achieve reception or output of electrical signals of different functional modules, the chip packaging structure provided by the embodiment of the present disclosure has a higher degree of integration.

[0052] In a specific implementation manner, in the embodiment of the present disclosure, based on the specific structure of the chip packaging structure obtained in the preparation process, Figure 1 As shown, by setting a chip packaging structure including a first chip 20 and a second chip 40, the second chip 40 is flip-chip connected to the first chip 20 through a first conductive connection structure 60 of a first opening 31, the second chip 40 is smaller in size than the first chip 20, and the first chip 20 is electrically connected to an external PCB circuit board through a second conductive connection structure 70 of a second opening 32, the first chip 20 receives an electrical signal transmitted by the PCB circuit board through the second conductive connection structure 70 and sends it to the second chip 40 through the first conductive connection structure 60, or the second chip 40 outputs an electrical signal to the first chip 20 through the first conductive connection structure 60, and the first chip 20 transmits the electrical signal output by the second chip 40 to the PCB circuit board through the second conductive connection structure 70.

[0053] In addition, in the process of preparing the chip packaging structure, after cutting at the cutting position of two adjacent chip packaging structures on one side of the first protective layer through a cutting process, a polyimide layer 90 is formed on the side wall of the cut first chip 20 through a spraying or other process to prevent the side wall of the cut first chip 20 from directly contacting the outside world.

[0054] In a specific implementation, the second protection layer 30 is located on a side of the first chip 20 close to the second chip 40 , and the second protection layer 30 serves as an insulation between the first chip 20 and the second chip 40 .

[0055] In a specific implementation, the third protective layer 50 is disposed on the side of the second chip 30 away from the first chip 20 . On the one hand, the third protective layer 50 is also the plastic packaging frame of the chip packaging structure. On the other hand, the second chip 40 can be protected based on the third protective layer 50 .

[0056] In a specific implementation, a portion of the second conductive connection structure 70 is exposed by providing the third protective layer 50 , thereby achieving electrical connection between the exposed portion of the second conductive connection structure 70 and an external PCB circuit board.

[0057] The chip packaging structure provided by the embodiment of the present disclosure is provided with a first chip, a second protective layer, a second chip and a third protective layer, and a first conductive connection structure and a second conductive connection structure, which are sequentially stacked in the chip packaging structure. The second chip is electrically connected to an external PCB circuit board through the first conductive connection structure, the first chip and the second conductive connection structure to achieve output or reception of electrical signals. Compared with the prior art in which one chip is used to achieve reception or output of electrical signals of different functional modules, the chip packaging structure prepared by the embodiment of the present disclosure has a higher degree of integration. In addition, after the first chip is cut to form a cutting path, a polyimide layer is prepared on the side surface of the cutting path. Based on the properties of the polyimide layer material, the particles of polyimide are relatively small, and the thickness of the prepared polyimide layer is relatively thin. Therefore, in the process of preparing and forming the cutting path, the width of the formed cutting path is relatively narrow. Compared with the prior art, in the process of preparing and forming the chip packaging structure, the cutting path can only form a plastic packaging material. Since the plastic packaging material is an epoxy resin material, the particles of the epoxy resin material are generally larger, and the thickness of the formed epoxy resin is thicker. Therefore, the width of the formed cutting path is wider. In the chip packaging structure provided in the embodiment of the present disclosure, the cutting path between two adjacent first chips is narrower. Therefore, the number of chips that can be accommodated on a chip will be more compared with the prior art.

[0058] In a specific embodiment, the thickness of the third protection layer 50 is H1, the thickness of the second chip 40 is H2, and the thickness of the second conductive connection structure 70 is H3, then H1, H2 and H3 satisfy: H2

[0059] Combination Figure 1 If the thickness of the third protection layer 50 is H1, the thickness of the second chip 40 is H2, and the thickness of the second conductive connection structure 70 is H3, H1, H2, and H3 need to be set to satisfy: H2

[0060] As a preferred embodiment, the thickness of the third protective layer 50 satisfies:

[0061] In a specific embodiment, after the second conductive connection structure 70 is prepared, a third protective layer 50 is first formed on the side of the second chip 40 away from the first chip 20, and the third protective layer 50 completely covers the second conductive connection structure 70 and the second chip 40. Then, the third protective layer 50 is processed by a chemical process so that the third protective layer 50 exposes a portion of the second conductive connection structure 70 and covers the second chip 40.

[0062] ​​In a specific embodiment, the third protective layer 50 is processed by a chemical process so that the third protective layer 50 exposes a portion of the second conductive connection structure and covers the second chip. When the third protective layer 50 is ground based on the chemical process so that the thickness of the remaining third protective layer is greater than or equal to one third of the thickness of the second conductive connection structure and less than or equal to one half of the second conductive connection structure, the processing of the third protective layer is stopped.

[0063] In a specific embodiment, the second conductive connection structure 70 includes a spherical structure.

[0064] The vertical projection of the spherical second conductive connection structure 70 on the first chip 20 covers the vertical projection of the second opening 32 on the first chip 20 .

[0065] Specifically, the second conductive connection structure is a solder ball.

[0066] Specifically, in the embodiment of the present disclosure, after the second chip 40 is flipped onto the first chip 20, a second conductive connection structure 70 is formed at the position of the second opening 32 by setting a mask plate, so that the second conductive connection structure 70 is electrically connected to the first chip 20 at the position of the second opening 32. The second conductive connection structure 70 serves as a transmission conductor for receiving or outputting electrical signals, and the thickness of the second conductive connection structure 70 needs to be greater than the thickness of the third protective layer 50.

[0067] As a preferred embodiment, in the process of preparing the second conductive connection structure 70, a mask plate including a circular opening at the position of the second opening 32 is selected. Therefore, the second conductive connection structure 70 formed at the position of the second opening 32 is spherical. After the second conductive connection structure 70 is formed and the mask plate is removed, the spherical second conductive connection structure 70 will undergo a certain amount of backflow, thereby completely filling the second opening 32, thereby improving the conductive connection performance between the second conductive connection structure 70 and the first chip 20.

[0068] During the preparation process of forming the spherical second conductive connection structure 70, the spherical second conductive connection structure 70 will undergo a certain amount of reflow. Therefore, the circular opening included in the second opening position of the mask plate is selected to be larger than the second opening, that is, the vertical projection of the spherical conductive connection structure 70 on the first chip 20 covers the vertical projection of the second opening 32 on the first chip 20.

[0069] In a specific implementation, the second chip is electrically connected to the first chip via the first conductive connection structure in the first opening, that is, the second chip and the first chip are electrically connected via the Bonding Pad, and the Bonding Pad is also the first conductive connection structure.

[0070] Based on the above embodiments, Figure 2is a schematic diagram of another chip packaging structure provided by an embodiment of the present disclosure, such as Figure 2 As shown, the chip packaging structure further includes a first protection layer 10 and a metal layer 80 . The metal layer 80 is located on a side of the first chip 20 away from the second chip 40 , and the first protection layer 10 is located on a side of the metal layer 80 away from the first chip 20 .

[0071] For details, see Figure 2 By disposing a metal layer 80 between the first protection layer 10 and the first chip 20 , the metal layer acts as a heat-conducting layer to dissipate the heat generated by the first chip 20 .

[0072] In addition, the first protection layer 10 is disposed on a side of the metal layer 80 away from the first chip 20 . The first protection layer 10 is used to prevent the surface of the metal layer 80 from directly contacting the outside and thus damaging the first chip 20 .

[0073] In a specific embodiment, the first protective layer 10, the second protective layer 30 and the third protective layer 50 are all insulating materials. In addition, the first protective layer 10 serves as a packaging structure for the first chip 20 away from the second chip 40, and the third protective layer 50 serves as a packaging structure for the second chip 40 away from the first chip 20.

[0074] It should be noted that, in the above embodiment, the materials of the first protective layer and the third protective layer have larger particles and higher hardness than the material of the second protective layer.

[0075] Furthermore, in the above embodiment, the materials of the first protective layer and the third protective layer are epoxy resin, and the material of the second protective layer is polyimide.

[0076] Based on the above embodiments, the present disclosure also provides a method for preparing a chip packaging structure. Figure 3 is a schematic diagram of a process for preparing a chip packaging structure provided by an embodiment of the present disclosure, Figure 4A-Figure 4I The process for preparing the chip packaging structure provided in the embodiment of the present disclosure is combined with Figure 3 and Figure 4A-Figure 4I , the preparation method of the chip packaging structure includes:

[0077] S110 , forming a second protection layer on a wafer having a plurality of first chips.

[0078] The second protective layer includes a first opening and a second opening.

[0079] In a specific embodiment, in combination with Figure 4AFirst, a second protective layer 30 is formed on a wafer 21 having a plurality of first chips 20, and then a first opening 31 and a second opening 32 are formed on the second protective layer 30 by masking and other processes, wherein the first opening 31 is located at a position where the first chip 20 and the second chip 40 are electrically connected through a bonding pad, and the second opening 32 is located at a position where the first chip 20 is electrically connected to an external PCB circuit board.

[0080] S120 , after forming a first conductive connection structure in the first opening of the second protective layer, flip-chip connect the second chip to the first chip on the wafer through the first conductive connection structure.

[0081] After forming the first opening 31 and the second opening 32 on the second protective layer 30, Figure 4B As shown, firstly, a second metal layer 301 (the material of the second metal layer is copper) is formed on the second protective layer 30, and the second metal layer 301 includes an opening at a position corresponding to the first opening 31, and then solder paste is brushed at the position corresponding to the first opening, as shown in FIG. Figure 4C As shown, the first conductive connection structure 60 is formed in the first opening 31, and then the second metal layer 301 is removed. Figure 4D shown.

[0082] After the first conductive connection structure 60 is formed in the first opening 31, the second chip 40 is flip-chip connected to the first conductive connection structure 60. Figure 4E shown.

[0083] S130 , forming a second conductive connection structure at a second opening position of the second protective layer.

[0084] In a specific embodiment, forming a second conductive connection structure at the second opening position of the second protective layer includes: preparing a mask layer on the side of the second protective layer away from the wafer, wherein the mask layer includes a third opening, and the vertical projection of the third opening on the wafer covers the vertical projection of the second opening on the wafer; after forming the second conductive connection structure at the second opening position of the second protective layer, removing the mask layer.

[0085] Specifically, Figure 4F As shown, the mask layer formed on the side of the second protective layer 30 away from the wafer 21 can be a ball-leaking net, and the material of the ball-leaking net is a metal material. After the ball-leaking net is prepared, a spherical second conductive connection structure 70 is formed at the opening of the ball-leaking net, and then the ball-leaking net is removed. After the ball-leaking net is removed, the spherical second conductive connection structure 70 will have a certain amount of backflow, thereby completely filling the second opening 32, thereby improving the conductive connection performance between the second conductive connection structure 70 and the first chip 20, such as Figure 4J .

[0086] S140 , forming a third protection layer on a side of the second conductive connection structure and the second chip away from the second protection layer.

[0087] After the second conductive connection structure 70 is formed, the third protective layer 50 is formed. Figure 4H The formed third protection layer 50 completely covers the second conductive connection structure 70 and the second chip 40 .

[0088] S150, cutting the wafer from a side of the wafer away from the second protective layer at a position between two adjacent first chips to form a cutting line, and spraying polyimide on the cutting line to form a polyimide layer on a surface of the cutting line.

[0089] In the preparation of Figure 4H After the structure shown in the figure, the whole wafer is first turned over by a turning process, that is, the side of the first chip away from the second chip faces upward, and then the wafer 21 is cut to form a cutting path at the position between two adjacent first chips by a cutting process, and a polyimide layer is formed on the surface of the cutting path by a process such as spraying, such as Fig. 4I .

[0090] Specifically, at a position between two adjacent first chips, in a process of cutting the wafer to form a cutting street, the wafer is cut by a laser cutting process.

[0091] S160, processing the third protective layer so that part of the second conductive connection structure is exposed outside the third protective layer.

[0092] In the preparation of Fig. 4I After the structure shown in the figure, the whole wafer is flipped again by a flipping process, that is, the third protective layer side faces upward. Since the second conductive connection structure is electrically connected to the external PCB circuit board, the third protective layer 50 can be processed by a process such as chemical grinding, so that the third protective layer 50 exposes a part of the second conductive connection structure 70, as shown in the figure. Figure 4G , the prepared chip packaging structure is electrically connected to the external PCB circuit board through the second conductive connection structure 70.

[0093] S170, cutting the positions of the cutting paths again to obtain a plurality of separated chip packaging structures.

[0094] Finally, by cutting again at the cutting path position of two adjacent first chips on the side of the third protective layer 50 away from the second protective layer 30, a plurality of separated chip packaging structures are obtained, such as Figure 4K .

[0095] In a specific embodiment, the position of the cutting line is cut again at a position between two adjacent first chips on a side of the third protective layer away from the second protective layer to obtain a chip packaging structure. In the process, the position of the cutting line is cut again using a physical cutting process, and after the position of the cutting line is cut again, the entire second chip is cleaned through a cleaning process to obtain a chip packaging structure.

[0096] It should be noted that in the above embodiment, in the process of cutting the wafer to form a cutting path from the side of the wafer away from the second protective layer, at the position between two adjacent first chips, based on the laser cutting process, it is inevitable to cut the second protective layer, but in the process of forming a polyimide layer on the surface of the cutting path (the formed polyimide layer is made of the same material as the second protective layer), a polyimide layer will also be formed on the second protective layer in the cutting path. Therefore, when the position of the cutting path is cut again to obtain a plurality of phase-separated chip packaging structures, the third protective layer and the polyimide layer need to be cut again.

[0097] The method for preparing a chip packaging structure provided by an embodiment of the present disclosure comprises a first chip, a second protective layer, a second chip and a third protective layer stacked in sequence, and a first conductive connection structure, a second conductive connection structure and a polyimide layer. The second chip is electrically connected to an external PCB circuit board through the first conductive connection structure, the first chip and the second conductive connection structure to achieve output or reception of electrical signals. Compared with the prior art in which one chip is used to achieve reception or output of electrical signals of different functional modules, the chip packaging structure prepared by the embodiment of the present disclosure has a higher degree of integration. In addition, after the first chip is cut to form a cutting path, a polyimide layer is prepared on the surface of the cutting path. The imide layer, based on the properties of the polyimide layer material, the particles of polyimide are relatively small, and the thickness of the prepared polyimide layer is relatively thin. Therefore, in the process of preparing and forming the cutting path, the width of the formed cutting path is relatively narrow. Compared with the prior art, in the process of preparing and forming the chip packaging structure, the cutting path can only form a plastic packaging material. Since the plastic packaging material is an epoxy resin material, the particles of the epoxy resin material are generally larger, and the thickness of the formed epoxy resin is thicker. Therefore, the width of the formed cutting path is wider. In the preparation method of the chip packaging structure provided in the embodiment of the present disclosure, the cutting path between two adjacent first chips is narrower. Therefore, the number of chips that can be accommodated on a chip will be more compared with the prior art.

[0098] Based on the above embodiment, before executing step S150, the method further includes: thinning the wafer on the side of the wafer away from the second protective layer; and preparing a first protective layer on the side of the wafer away from the second protective layer.

[0099] Specifically, the wafer 21 is first thinned on the side of the wafer 21 away from the second protective layer 30 to reduce the overall volume of the chip packaging structure finally manufactured, and then a first protective layer 10 is prepared to protect the wafer 21 to avoid scratches on the wafer 21. Figure 5A At this time, during the execution of step S150, the first protective layer and the wafer are cut from the side of the wafer away from the second protective layer at a position between two adjacent first chips to form a cutting path, and polyimide is sprayed on the cutting path to form a polyimide layer on the surface of the cutting path.

[0100] In addition, in the above embodiment, before forming the first protective layer on the side of the wafer away from the second protective layer, the process further includes: forming a metal layer on the side of the wafer away from the second protective layer.

[0101] A metal layer 80 is formed on the side of the wafer 21 away from the second protective layer 30. The metal layer 80 serves as a heat dissipation layer of the chip packaging structure. Figure 5B and 5C As shown, after the metal layer is prepared, step S150-step S170 are executed. At this time, in the process of executing step S150, on the side of the wafer away from the second protective layer, at the position between two adjacent first chips, the first protective layer, the metal layer and the wafer are cut to form a cutting path, and polyimide is sprayed on the cutting path to form a polyimide layer on the surface of the cutting path.

[0102] Through the above steps, the chip packaging structure formed is a six-sided WICSP chip packaging structure.

[0103] On the basis of the above embodiment, before executing step S160, it further includes: preparing a support layer on a side of the wafer away from the second protective layer.

[0104] When the wafer is cut to form a cutting path at a position between two adjacent first chips from the side of the wafer away from the second protective layer, and polyimide is sprayed on the cutting path, and a polyimide layer is formed on the surface of the cutting path, a support layer 90 is first prepared on the side of the wafer 21 away from the second protective layer. The support layer 90 is a transparent adhesive, and the support layer 90 is bonded to the uncut first chip to avoid deformation of the chip packaging structure to be cut. Figure 5D As shown, after the support layer 90 is prepared and formed, step S160 to step S170 are performed.

[0105] Specifically, the material of the support layer is a polymer synthetic material.

[0106] In a specific implementation, before executing step S160 , a support layer is prepared on a side of the wafer away from the second protective layer. At this time, after executing step S170 , the prepared chip packaging structure is separated from the support layer.

[0107] Specifically, the chip packaging structure formed by cutting is sucked off from the support layer by a suction nozzle to obtain the final chip packaging structure.

[0108] On the basis of the above embodiments, an embodiment of the present disclosure further provides an electronic device. The electronic device includes a chip packaging structure according to an embodiment of the present disclosure. The electronic device is, for example, an automotive electronic product or an intelligent terminal device, such as a tablet computer, a smart phone, etc.

[0109] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0110] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0111] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0112] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a chip packaging structure, characterized in that: include: Forming a second protective layer on a wafer having a plurality of first chips, wherein the second protective layer includes a first opening and a second opening; After forming a first conductive connection structure in the first opening of the second protective layer, flip-chip connecting the second chip to the first chip on the wafer through the first conductive connection structure; forming a second conductive connection structure at a second opening position of the second protective layer; forming a third protective layer on the second conductive connection structure and the second chip on a side away from the second protective layer; Cutting the wafer from a side of the wafer away from the second protective layer at a position between two adjacent first chips to form a scribe line, and spraying polyimide on the scribe line to form a polyimide layer on a surface of the scribe line; Processing the third protective layer so that a portion of the second conductive connection structure is exposed outside the third protective layer; The positions of the cutting paths are cut again to obtain a plurality of separated chip packaging structures.

2. The method according to claim 1, characterized in that The forming of a second conductive connection structure at the second opening position of the second protective layer comprises: Forming a mask layer on a side of the second protective layer away from the wafer, wherein the mask layer comprises a third opening, and a vertical projection of the third opening on the wafer covers a vertical projection of the second opening on the wafer; After forming a second conductive connection structure at the second opening position of the second protection layer, the mask layer is removed.

3. The method according to claim 1, characterized in that The method further comprises: cutting the wafer from a side of the wafer away from the second protective layer at a position between two adjacent first chips to form a cutting path, and spraying polyimide on the cutting path. Before a polyimide layer is formed on a surface of the cutting path, the method further comprises: Performing a thinning process on the wafer at a side of the wafer away from the second protective layer; A first protective layer is formed on a side of the wafer away from the second protective layer.

4. The method according to claim 3, characterized in that Before forming the first protective layer on the side of the wafer away from the second protective layer, the method further includes: A metal layer is formed on a side of the wafer away from the second protective layer.

5. The method according to claim 3, characterized in that: The materials of the first protective layer and the third protective layer are epoxy resin, the material of the second protective layer is polyimide, and the second conductive connection structure is a solder ball.

6. The method according to claim 1, characterized in that Before the third protective layer is processed so that part of the second conductive connection structure is exposed outside the third protective layer, the method further includes: Disposing a support layer on a side of the wafer away from the second protective layer; After the positions of the cutting paths are cut again to obtain a plurality of separated chip packaging structures, the method further comprises: The prepared chip packaging structure is separated from the supporting layer.

7. A chip packaging structure, characterized in that: include: A first chip, a second protective layer, a second chip and a third protective layer, a first conductive connection structure, a second conductive connection structure and a polyimide layer are sequentially stacked; The second protective layer is located on a side of the first chip close to the second chip, the third protective layer is located on a side of the second chip away from the first chip, and the polyimide layer is formed on a side wall of the first chip; The second protective layer includes a first opening and a second opening, the first conductive connection structure is arranged in the first opening, the second chip is flip-chip connected to the first chip through the first conductive connection structure, the second conductive connection structure is arranged at the second opening, the third protective layer exposes a portion of the second conductive connection structure, and the first chip outputs or receives electrical signals through the second conductive connection structure.

8. The chip packaging structure according to claim 7, characterized in that: The thickness of the third protective layer is H1, the thickness of the second chip is H2, and the thickness of the second conductive connection structure is H3, then H1, H2 and H3 satisfy: H2 <H1<H3; The thickness of the third protective layer satisfies:

9. The chip packaging structure according to claim 7, characterized in that: It also includes a first protection layer and a metal layer. The metal layer is located on a side of the first chip away from the second chip, and the first protection layer is located on a side of the metal layer away from the first chip.

10. The chip packaging structure according to claim 9, characterized in that: The materials of the first protective layer and the third protective layer are epoxy resin, the material of the second protective layer is polyimide, and the second conductive connection structure is a solder ball.

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