Manufacturing method of metal interconnection line and semiconductor device
By cleaning and oxidizing metal interconnect lines in the semiconductor manufacturing process, the problem of post-metal layer corrosion defects is solved, and product quality and production efficiency are improved.
Patent Information
- Application Number
- CN202310898594.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-20
- Publication Date
- 2025-01-21
AI Technical Summary
In the existing semiconductor manufacturing process, metal interconnects are prone to metal-level corrosion defects, resulting in a decline in product quality.
Remove the polymer generated by the metal layer etching, and then oxidize the metal interconnect line to form a dense oxidation layer to prevent chloride and fluorine ion reactions.
Effectively prevent the occurrence of corrosion defects after metal levels, and improves the reliability and production efficiency of semiconductor devices.
Smart Images
Figure CN119340271A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a metal interconnection line, and also to a semiconductor device. Background Art
[0002] Metal interconnection technology is widely used in semiconductor manufacturing. For some products, metal interconnection lines will have metal layer corrosion defects (Metal Corrosion Defect). The consequences of this defect are serious and should be avoided as much as possible. Summary of the invention
[0003] Based on this, it is necessary to provide a method for manufacturing a metal interconnection line that can prevent corrosion defects after forming a metal layer.
[0004] A method for manufacturing a metal interconnection line comprises: etching a metal layer on a first main surface of a wafer to form a metal interconnection line; cleaning the metal interconnection line; and oxidizing the cleaned metal interconnection line.
[0005] The above-mentioned method for manufacturing metal interconnects removes the polymer generated by etching the metal layer through cleaning treatment, and then oxidizes the surface of the metal interconnects, using the oxide layer to prevent chloride ions, fluorine ions, etc. in the environment from reacting with the metal interconnects to form corrosion defects in the metal layer. By cleaning first and then oxidizing, it is possible to avoid the polymer generated in the metal layer etching step from hindering the oxidation process, and provide a sufficient process window for production efficiency.
[0006] In one embodiment, after the step of oxidizing the cleaned metal interconnects, the step further includes: attaching a protective film to the first main surface; thinning the second main surface of the wafer; and arranging the first main surface and the second main surface relative to each other.
[0007] In one embodiment, the time from the completion of the oxidation treatment of the cleaned metal interconnection line to the start of the thinning treatment of the second main surface of the wafer is less than or equal to 180 hours.
[0008] In one of the embodiments, the cleaning time of the step of cleaning the metal interconnection line is 1500-2000 seconds.
[0009] In one embodiment, the material of the metal interconnection line includes aluminum.
[0010] In one embodiment, the material of the metal interconnection line includes aluminum-copper alloy.
[0011] In one embodiment, the step of oxidizing the cleaned metal interconnection lines forms aluminum oxide on the surface of the metal interconnection lines.
[0012] In one embodiment, the step of oxidizing the cleaned metal interconnects is to introduce nitrogen and oxygen into a reaction chamber of a plasma ashing device for 30 to 70 seconds.
[0013] In one embodiment, the gas pressure in the reaction chamber during the oxidation process is 800 mTorr to 1200 mTorr.
[0014] In one embodiment, the power of the plasma ashing equipment during the oxidation process is 2000 to 3000 watts.
[0015] In one of the embodiments, during the oxidation treatment process, the oxygen flow rate introduced into the reaction chamber is 1000 to 4000 sccm, and the nitrogen flow rate introduced into the reaction chamber is 100 to 400 sccm.
[0016] In one embodiment, the step of etching the metal layer on the first main surface of the wafer to form metal interconnects is performed by dry etching, and the reaction gas of the dry etching includes a gas containing chlorine elements and a compound containing carbon elements and hydrogen elements.
[0017] In one embodiment, the dry etching reaction gas includes BCl 3 .
[0018] In one of the embodiments, after the step of etching the metal layer on the first main surface of the wafer to form metal interconnections and before the step of cleaning the metal interconnections, a step of removing the photoresist is also included.
[0019] In one embodiment, the step of removing the photoresist is to use a plasma ashing device to remove the photoresist.
[0020] In one embodiment, after the step of oxidizing the cleaned metal interconnects and before the step of applying a protective film to the first main surface, a step of heat treating the wafer is also included.
[0021] In one embodiment, the heat treatment includes annealing.
[0022] In one embodiment, before the step of heat treatment and after the step of oxidizing the cleaned metal interconnects, a step of defect inspection on the wafer is also included.
[0023] In one embodiment, after the step of heat treatment and before the step of applying a protective film to the first main surface, a step of performing electrical testing on the wafer is also included.
[0024] It is also necessary to protect a semiconductor device including a metal interconnection line, wherein the semiconductor device is manufactured using the method for manufacturing the metal interconnection line described in any of the aforementioned embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.
[0026] Figure 1a is a schematic diagram of etching a metal layer on a dielectric layer 1 to form a metal interconnection line 2. Figure 1b is a schematic diagram of the metal interconnect line 2 being exposed to an environment containing F and Cl. Figure 1c is a schematic diagram of a corrosion defect 3 after a metal interconnect line 2 forms a metal layer;
[0027] Figure 2 is a flow chart of a method for manufacturing a metal interconnect line in one embodiment of the present application;
[0028] Figure 3a is a schematic diagram of forming a metal interconnection line 2 after photolithography and etching of a metal layer on a dielectric layer 1 in an embodiment of the present application, Figure 3b is a schematic diagram of an oxidation treatment of a metal interconnection line 2 in an embodiment of the present application, Figure 3c is a schematic diagram of forming a metal oxide layer 4 on the surface of the metal interconnection line 2 after the metal interconnection line 2 is oxidized in one embodiment of the present application;
[0029] Figure 4 is a graph showing the relationship between K and post-metal layer corrosion defects in some embodiments of the present application;
[0030] Figure 5 is a flow chart of a method for manufacturing a metal interconnection line in another embodiment of the present application;
[0031] Figure 6 This is a defect improvement trend chart of corrosion defects after metal layering. DETAILED DESCRIPTION
[0032] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.
[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0034] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
[0035] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0036] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0037] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.
[0038] In semiconductor technology, dry etching of metal layers to form metal interconnects, taking copper-aluminum alloy as an example, the main component of the etching gas is BCl3, and the byproducts of etching are mainly AlCl3 and BCl x etc., and fluorine-containing byproducts will also be generated; the reaction gas may also include CH4, CHF3, etc., and the reaction can refer to the following reaction formula:
[0039] BCl3→BCl x
[0040] BCl x +Cl → BCl y
[0041] CHF3, CH4 → C a H b
[0042] Among them C a H bIt is a polymer that can be deposited on the sidewalls of the metal to prevent the etching gas from etching laterally. After etching, the photoresist needs to be removed, and then the byproducts containing F and Cl are removed by wet cleaning to prevent the polymers of the byproducts from corroding Al. The reaction of the byproducts containing Cl and aluminum can be referred to the following reaction formula:
[0043] 2Al+3Cl2→2AlCl3
[0044] AlCl3+H2O→Al(OH)3+HCl
[0045] HCl+Al→AlCl3
[0046] Figure 1a Schematic diagram of etching the metal layer on the dielectric layer 1 to form the metal interconnection line 2. After the aforementioned wet cleaning is completed, if the metal interconnection line 2 is exposed to an environment containing F and Cl, such as Figure 1b As shown, byproducts containing F and Cl will also be produced and react with metals (refer to the previous reaction formula) to form metal layer corrosion defects 3 (Metal Corrosion Defect), refer to Figure 1c .
[0047] In order to avoid the generation of post-metal layer corrosion defects, the present application proposes a novel method for manufacturing metal interconnects, in which the metal interconnects are oxidized after wet cleaning to form a densely structured oxide layer on the surface of the metal interconnects as a protective layer, which can prevent F and Cl ions in the environment from reacting with the metal to form post-metal layer corrosion defects.
[0048] Figure 2 : is a flow chart of a method for manufacturing a metal interconnect line in an embodiment of the present application, comprising the following steps:
[0049] S210, etching the metal layer on the front side of the wafer to form metal interconnection lines.
[0050] Reference Figure 3a The metal layer on the dielectric layer 1 forms a metal interconnection line 2 after photolithography and etching. In one embodiment of the present application, the material of the metal layer includes aluminum; further, the material of the metal layer is an aluminum-copper alloy.
[0051] In one embodiment of the present application, step S210 adopts a dry etching process. In one embodiment of the present application, the reaction gas of the dry etching includes a gas containing chlorine elements and a compound containing carbon elements and hydrogen elements. The gas containing chlorine elements may include BCl3, and the compound containing carbon elements and hydrogen elements may include CH4, CHF3, etc. Among them, BCl3 is used to form plasma, and the plasma bombards the metal layer for etching; CH4, CHF3, etc. can react with photoresist to generate polymers deposited on the side walls of the metal to prevent the etching gas from etching laterally.
[0052] After the etching is completed, the photoresist needs to be removed. In one embodiment of the present application, the photoresist is removed by dry stripping, that is, a plasma ashing device (plasma stripper) is used to remove the photoresist.
[0053] In one embodiment of the present application, the dielectric layer 1 is an intermetallic dielectric (IMD).
[0054] S220, cleaning the metal interconnection lines.
[0055] The purpose of cleaning includes washing away the byproducts containing F and Cl formed in step S210 to prevent the polymer of the byproducts from corroding Al in the metal interconnection line 2. In one embodiment of the present application, the wafer is placed in an organic solvent containing hydroxylamine for cleaning.
[0056] S230, performing oxidation treatment on the metal interconnection line.
[0057] Figure 3b is a schematic diagram of an oxidation treatment of a metal interconnection line 2 in an embodiment of the present application, Figure 3c Schematic diagram of forming a metal oxide layer 4 on the surface of the metal interconnection line 2 after oxidation treatment of the metal interconnection line 2 in one embodiment of the present application. Through the oxidation treatment, a dense metal oxide layer 4 is formed on the surface of the cleaned metal interconnection line 2 as a protective layer, which can prevent chloride ions, fluorine ions, etc. in the environment from reacting with the metal interconnection line 2 to form corrosion defects after the metal layer.
[0058] On the other hand, polymers generated by CH4, CHF3, etc. will hinder the metal oxidation in step S220. Therefore, these polymers are washed away in step S220 before the oxidation in step S230 to avoid the polymers hindering the oxidation in step S220, so that the metal oxide can be generated more fully and better protect the metal.
[0059] In the above-mentioned method for manufacturing metal interconnects, after the polymer generated by etching the metal layer in step S210 is removed by cleaning in step S220, the surface of the metal interconnects is oxidized in step S230, and the oxide layer is used to prevent chloride ions, fluorine ions, etc. in the environment from reacting with the metal interconnects 2 to form corrosion defects in the metal layer. By cleaning first and then oxidizing, it is possible to avoid the polymer formed in step S210 from hindering the oxidation process.
[0060] According to the above, in order to obtain a better oxidation effect, the polymer needs to be removed by step S220. Therefore, in order to ensure the removal effect of the polymer, the cleaning time can be extended. In one embodiment of the present application, the cleaning time of step S220 is 1500-2000 seconds.
[0061] In one embodiment of the present application, after step S230, a step of applying a protective film to the front side of the wafer is further included. After applying the protective film, the back side of the wafer is thinned.
[0062] In one embodiment of the present application, the time from the completion of step S230 to the start of the backside thinning process on the wafer is less than or equal to 180 hours. The longer the waiting time (hereinafter referred to as K), the greater the risk of the metal interconnect 2 being exposed to the air and corroded by F, Cl plasma. Figure 4 is a graph showing the relationship between K and post-metal layer corrosion defects in some embodiments of the present application. Figure 4 The horizontal axis is K, and the vertical axis is the number of post-metal corrosion defects of the tested wafer. It can be seen that when K is controlled within 180 hours, the number of defects is 0, and the process safety window is further expanded.
[0063] In one embodiment of the present application, after step S230 and before attaching a protective film to the front side of the wafer, a step of heat treating the wafer is also included. In one embodiment of the present application, the heat treatment is annealing.
[0064] Since the semiconductor production process is closely linked and continuous, the waiting time (Q-time) between processes is very important for production efficiency. In order to ensure production efficiency and yield, the processing time of each process step and the interval time between each process step must be strictly controlled. In one embodiment of the present application, the waiting time from step S210 metal dry etching to step S220 wet cleaning is 4 hours, and the waiting time from step S220 wet cleaning to annealing is 24 hours. Therefore, step S220 is performed first and then step S230. Compared with performing step S230 first and then step S220, the production scheduling flexibility time can be greatly improved, sufficient process windows are provided for production efficiency, and product defects can be further reduced.
[0065] In one embodiment of the present application, the oxidation treatment of step S230 is performed using a plasma ashing device, that is, a dry degumming device for removing the photoresist layer formed during etching in step S210 can be used. Specifically, nitrogen and oxygen can be introduced into the reaction chamber of the plasma ashing device for 30 to 70 seconds, and the flow ratio of the nitrogen and oxygen introduced can be 1:10. In one embodiment of the present application, the gas pressure in the reaction chamber during the oxidation treatment is 800 mTorr to 1200 mTorr. In one embodiment of the present application, the oxygen flow rate introduced into the reaction chamber during the oxidation treatment is 1000 to 4000 sccm, and the nitrogen flow rate introduced is 100 to 400 sccm.
[0066] Figure 5 : is a flow chart of a method for manufacturing a metal interconnect line in another embodiment of the present application, comprising the following steps:
[0067] S410, etching the metal layer on the front side of the wafer to form metal interconnection lines.
[0068] In one embodiment of the present application, the material of the metal interconnection line is aluminum-copper alloy.
[0069] In one embodiment of the present application, step S210 adopts a dry etching process. In one embodiment of the present application, the reaction gas of the dry etching includes a gas containing chlorine elements and a compound containing carbon elements and hydrogen elements. The gas containing chlorine elements may include BCl3, and the compound containing carbon elements and hydrogen elements may include CH4, CHF3, etc. Among them, BCl3 is used to form plasma, and the plasma bombards the metal layer for etching; CH4, CHF3, etc. can react with photoresist to generate polymers deposited on the side walls of the metal to prevent the etching gas from etching laterally.
[0070] S412, removing the photoresist.
[0071] In one embodiment of the present application, the photoresist is removed by dry stripping, that is, a plasma ashing device is used to remove the photoresist.
[0072] S420, cleaning the metal interconnection lines.
[0073] The purpose of cleaning includes washing away the byproducts containing F and Cl formed in step S210 to prevent the polymers of the byproducts from corroding Al in the metal interconnects. In one embodiment of the present application, the wafer formed with the metal interconnects is placed in an organic solvent containing hydroxylamine for cleaning.
[0074] In order to achieve a better oxide layer protection effect in the subsequent step S430, the polymer attached to the sidewall of the metal interconnection line generated by CH4, CHF3, etc. needs to be removed more cleanly through the cleaning in step S420, so the polymer can be removed more cleanly by increasing the cleaning time. In one embodiment of the present application, the cleaning time is 1500-2000 seconds.
[0075] S430, performing oxidation treatment on the metal interconnection line.
[0076] Through oxidation treatment, a dense metal oxide layer is formed on the surface of the cleaned metal interconnect as a protective layer, which can prevent chloride ions, fluorine ions, etc. in the environment from reacting with the metal interconnect to form corrosion defects after the metal layer. In one embodiment of the present application, after the surface of the metal interconnect is oxidized, the main component of the oxide layer is aluminum oxide.
[0077] In one embodiment of the present application, the oxidation treatment is performed using a plasma ashing device, and the dry degumming device used in step S412 can be used. In one embodiment of the present application, the process parameters of the oxidation treatment are shown in the following table:
[0078]
[0079] Table 1
[0080] S440, defect inspection.
[0081] A defect monitoring device may be used to perform defect inspection on the wafer after step S430 is completed, which may be an inline particle defect monitor or an offline particle defect QC monitor.
[0082] S450, annealed.
[0083] The wafer is thermally annealed.
[0084] S460, electrical test.
[0085] In one embodiment of the present application, the electrical parameters of the test device may be Idsat (saturation current), Vt (threshold voltage), breakdown voltage, etc.
[0086] S470, attaching a protective film to the front side of the wafer.
[0087] Before thinning the front side of the wafer, a protective film may be attached to the front side of the wafer to protect the front side of the wafer.
[0088] S480, thinning the back side of the wafer.
[0089] The time from the completion of step S430 to the start of step S480 is less than or equal to 180 hours to reduce the risk of corrosion defects after the metal layer is formed.
[0090] Figure 6 This is a defect improvement trend diagram of post-metal layer corrosion defects, in which the horizontal axis is the wafer number and the vertical axis is the number of post-metal layer corrosion defects in the corresponding wafer. The solution of removing the polymer produced by metal layer etching by the cleaning process of the present application and then oxidizing the surface of the metal interconnection line, supplemented by controlling the waiting time from the completion of step S430 to the start of step S480 within 180 hours, can control the number of post-metal layer corrosion defects to less than one.
[0091] The present application accordingly claims protection for a semiconductor device including a metal interconnection line, wherein the semiconductor device is manufactured using the method for manufacturing the metal interconnection line described in any of the aforementioned embodiments.
[0092] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0093] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0094] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0095] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A method for manufacturing a metal interconnection line, comprising: Etching the metal layer on the first main surface of the wafer to form metal interconnection lines; Cleaning the metal interconnection line; The cleaned metal interconnection lines are subjected to oxidation treatment.
2. The method for manufacturing a metal interconnection line according to claim 1, characterized in that: After the step of oxidizing the cleaned metal interconnection line, the step further includes: Applying a protective film to the first main surface; The second main surface of the wafer is thinned; the first main surface and the second main surface are arranged opposite to each other.
3. The method for manufacturing a metal interconnection line according to claim 2, characterized in that: The time from the completion of the step of oxidizing the cleaned metal interconnection line to the start of the thinning process on the second main surface of the wafer is less than or equal to 180 hours.
4. The method for manufacturing a metal interconnection line according to claim 1, characterized in that: The material of the metal interconnection line includes aluminum.
5. The method for manufacturing a metal interconnection line according to claim 4, characterized in that: The material of the metal interconnection line includes aluminum-copper alloy.
6. The method for manufacturing a metal interconnection line according to claim 1, characterized in that: The step of oxidizing the cleaned metal interconnection line is to introduce nitrogen and oxygen into the reaction chamber of the plasma ashing equipment for 30 to 70 seconds.
7. The method for manufacturing a metal interconnection line according to claim 1, characterized in that: The step of etching the metal layer on the first main surface of the wafer to form metal interconnection lines is performed by dry etching, and the reaction gas of the dry etching includes a gas containing chlorine elements and a compound containing carbon elements and hydrogen elements.
8. The method for manufacturing a metal interconnection line according to claim 2, characterized in that: After the step of oxidizing the cleaned metal interconnection line and before the step of applying a protective film to the first main surface, the method further includes a step of heat treating the wafer.
9. The method for manufacturing a metal interconnection line according to claim 3, characterized in that: Before the step of heat treatment and after the step of oxidizing the cleaned metal interconnects, a step of inspecting the wafer for defects is also included; and / or After the step of heat treatment and before the step of applying a protective film to the first main surface, the method further includes the step of performing electrical testing on the wafer.
10. A semiconductor device comprising a metal interconnection line, characterized in that: The semiconductor device is manufactured by using the method for manufacturing a metal interconnection line according to any one of claims 1 to 9.