Electronic device

Abstract

An electronic device is provided. The electronic device includes a first electronic component, a plurality of second electronic components, and a plurality of conductive elements. The plurality of second electronic components is disposed below the first electronic components. The plurality of conductive elements electrically connect the first electronic component to the plurality of second electronic components. The plurality of conductive elements do not vertically overlap the plurality of second electronic components.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly, to an electronic device integrating a plurality of electronic components. Background Art

[0002] Recently, three-dimensional (3D) stacking technology and 2.5D stacking technology are being developed to integrate electronic components with different functions. However, conventional 3D and 2.5D stacking technologies face multiple problems. For example, electronic components stacked by 3D technology have a relatively large thickness; 2.5D stacking technology has process challenges that need to be overcome, such as alignment between solder balls and interposers that is sensitive to warping. This alignment problem makes it difficult to optimize process conditions. In order to solve the above problems, a new electronic device is needed. Summary of the invention

[0003] According to some arrangements of the present disclosure, an electronic device includes a first electronic component, a plurality of second electronic components, and a plurality of conductive elements. The plurality of second electronic components are disposed below the first electronic component. The plurality of conductive elements electrically connect the first electronic component to the plurality of second electronic components. The plurality of conductive elements do not vertically overlap with the plurality of second electronic components.

[0004] According to some arrangements of the present disclosure, an electronic device includes a first electronic component, a plurality of second electronic components, and a first circuit layer. The plurality of second electronic components are disposed below the first electronic component. The first circuit layer is disposed below the plurality of second electronic components. The first electronic component is electrically connected to the plurality of second electronic components through the first circuit layer.

[0005] According to some arrangements of the present disclosure, an electronic device includes a first electronic component and a second electronic component. The second electronic component is disposed below the first electronic component and is separated from the first electronic component by an adhesive layer. The electronic device provides an electrical path that passes through the first electronic component and the second electronic component but not through the adhesive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that for clarity, various features may not be drawn to scale.

[0007] Figure 1 is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0008] Figure 2 is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0009] Figure 3is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0010] Figure 4 is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0011] Figure 5 is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0012] Figure 6 is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0013] Figure 7 is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0014] Figure 8 is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0015] Fig. 9 is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0016] Fig.10 is a cross-sectional view of an electronic device according to some arrangements of the present disclosure.

[0017] Fig.11A One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0018] Fig. 11B One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0019] Fig. 11C One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0020] Fig.11D One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0021] Fig.11E One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0022] Fig.11F One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0023] Fig.11G One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0024] Fig.11H One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0025] Fig. 12A One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0026] Fig. 12B One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0027] Fig. 12C One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0028] Fig.12D One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0029] Fig.12E One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0030] Fig.12F One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0031] Figure 12G One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0032] Fig.13A One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0033] Fig. 13B One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0034] Fig. 13C One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0035] Fig.13D One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0036] Fig.13E One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0037] Fig.13FOne or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0038] Figure 13G One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0039] Fig.13H One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0040] Fig.14A One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0041] Fig. 14B One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0042] Fig. 14C One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0043] Fig.14D One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0044] Fig.14E One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0045] Fig.14F One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0046] Figure 14G One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0047] Fig.15A One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0048] Fig. 15B One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0049] Fig. 15C One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0050] Fig.15D One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0051] Fig.15E One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0052] Fig.16A One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0053] Fig. 16B One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0054] Fig. 16C One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0055] Fig.16D One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0056] Fig.16E One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0057] Fig.16F One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0058] Figure 16G One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0059] Fig.16H One or more stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0060] Common reference numerals are used throughout the drawings and detailed description to refer to the same or similar components. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0061] The following disclosure provides many different arrangements or examples of different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be restrictive. In the present disclosure, in the following description, mentioning that a first feature is formed or arranged above or on a second feature may include an arrangement in which the first and second features are formed or arranged directly in contact, and may also include an arrangement in which one or more additional features may be formed or arranged between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. The same reference numerals and / or letters refer to the same or similar parts. This repetition is for the purpose of simplification and clarity, and does not specify the relationship between various arrangements and / or configurations per se.

[0062] The following is a detailed discussion of the arrangements of the present disclosure. However, it should be appreciated that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific arrangements discussed are merely illustrative and do not limit the scope of the present disclosure.

[0063] Figure 1 1 is a cross-sectional view of an electronic device 1a according to some arrangements of the present disclosure. In some arrangements, the electronic device 1a may include an electronic component 10, a redistribution structure 12, an electronic component 14-1, an electronic component 14-2, an electronic component 14-3, a circuit layer 16, an encapsulant 18, at least one conductive element 20, an electrical connector 22, and a heat dissipating element 24.

[0064] The electronic component 10 may include an active component. Active components may include semiconductor dies or chips, such as logic dies (e.g., application-specific IC (ASIC), application processor (AP), system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, sensor die, micro-electro-mechanical-system (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front-end (AFE) die), or other active components. The electronic component 10 may include a surface 10s1, a surface 10s2, and a surface 10s3. The surface 10s1 (or the lower surface) may serve as an active surface through which a signal (e.g., a data signal, a power signal, etc.) passes. The surface 10s2 (or the upper surface) may be opposite to the surface 10s1 and may serve as a passive surface, which may also be referred to as a backside surface. The surface 10s3 (or the side) may extend between the surfaces 10s1 and 10s2. In some arrangements, the electronic component 10 may include a semiconductor substrate, which may include silicon, germanium or other suitable materials, such as gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide. The IC may be formed in the semiconductor substrate of the electronic component 10. In some arrangements, the IC may be formed adjacent to the surface 10s1 of the electronic component 10. In addition, the electronic component 10 may include a plurality of terminals (not shown) for electrical connection, such as conductive pads, on the surface 10s1 of the electronic component 10. The electronic component 10 may include a circuit layer 10a within which one or more ICs are disposed. In some arrangements, the circuit layer 10a may be disposed adjacent to the surface 10s1.Under this condition, the surface 10s1 may be referred to as an active surface, and the surface 10s2 may be referred to as a passive surface. In other arrangements, the circuit layer 10a may be disposed adjacent to the surface 10s2. Under this condition, the surface 10s2 may be referred to as an active surface, and the surface 10s1 may be referred to as a passive surface.

[0065] In some arrangements, the redistribution structure 12 may be disposed on or below the surface 10s1 of the electronic component 10. The redistribution structure 12 may include at least one conductive trace and / or conductive via embedded in the dielectric layer. The redistribution structure 12 may include a fan-in structure. In some arrangements, the redistribution structure 12 may be electrically connected to the electronic component 10. The redistribution structure 12 may include a surface 12s1, a surface 12s2, and a surface 12s3. The surface 12s1 (or the lower surface) may be spaced apart from the electronic component 10. The surface 12s2 (or the upper surface) may be opposite to the surface 12s1. The surface 12s3 (or the side) may extend between the surfaces 12s1 and 12s2. A plurality of terminals (not shown) such as conductive pads may be disposed above the surface 12s2 and / or below the surface 12s1. In some arrangements, the redistribution structure 12 may be considered as a part of the electronic component 10.

[0066] In some arrangements, the electronic components 14-1, 14-2, and 14-3 may be disposed on or below the surface 12s1 of the redistribution structure 12. The electronic components 14-1, 14-2, and 14-3 may include active components, such as memory dies (e.g., DRAM dies, SRAM dies, etc.), power management dies (e.g., PMIC dies), or other active components. Each of the electronic components 14-1, 14-2, and 14-3 may include an active surface, a passive surface, and a side. For example, the electronic component 14-1 may include a surface 14-1s1, a surface 14-1s2, and a surface 14-1s3. The surface 14-1s1 (or lower surface) may serve as an active surface through which a signal (e.g., a data signal, a power signal, etc.) passes. In some embodiments, each of the electronic components 14-1, 14-2, and 14-3 may include an active circuit area 14a. The active circuit area 14a of the electronic component 14-1 may be disposed adjacent to the surface 14-1s1. The surface 14-1s2 (or upper surface) may be opposite to the surface 14-1s1 and may act as a passive surface, which may also be referred to as a backside surface. The surface 14-1s3 (or side) may extend between the surfaces 14-1s1 and 14-1s2. In some arrangements, each of the electronic components 14-1, 14-2, and 14-3 may include different functions. For example, each of the electronic components 14-1, 14-2, and 14-3 may include different ICs. In some arrangements, each of the electronic components 14-1, 14-2, and 14-3 may be electrically connected to or communicate with the electronic component 10. In some arrangements, electronic component 10 may be a CPU, SoC, or other IC that may control electronic components 14-1, 14-2, and 14-3; electronic components 14-1, 14-2, and 14-3 may include memory dies, PMIC dies, or other dies.

[0067] Each of the electronic components 14-1, 14-2, and 14-3 may include a terminal 141 and an adhesive layer 142. The terminal 141 may be disposed, for example, on or below the surface 14-1s1 of the electronic component 14-1. Each of the terminals 141 may include, for example, a conductive column or other suitable element. Each of the terminals 141 may include a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. The adhesive layer 142 may be disposed, for example, above the surface 14-1s2 of the electronic component 14-1. The adhesive layer 142 may be configured to attach the electronic components 14-1, 14-2, and 14-3 to the redistribution structure 12.

[0068] In some arrangements, the circuit layer 16 may be disposed on or below the electronic components 14-1, 14-2, and 14-3. In some arrangements, the surface 14-1s1 of the electronic component 14-1 may face the circuit layer 16. In some arrangements, the circuit layer 16 may include a fan-out structure. In some arrangements, the circuit layer 16 may include a redistribution structure. The circuit layer 16 may include at least one conductive trace and / or conductive via embedded in the dielectric layer. In some arrangements, the circuit layer 16 may be electrically connected to the redistribution structure 12. In some arrangements, the circuit layer 16 may be electrically connected to the electronic components 14-1, 14-2, and 14-3. In some arrangements, the electronic components 14-1, 14-2, and 14-3 may be electrically connected to the circuit layer 16 through a non-solder joint. For example, no soldering material such as tin or its derivatives is formed or disposed between the electronic component 14-1 and the circuit layer 16. Circuit layer 16 may include surface 16s1, surface 16s2, and surface 16s3. Surface 16s2 (or upper surface) may be opposite to surface 16s1 (or lower surface). Surface 16s3 (or side surface) may extend between surfaces 16s1 and 16s2. A plurality of terminals (not shown) such as conductive pads may be disposed above surface 16s2 and / or below surface 16s1.

[0069] In some arrangements, the encapsulant 18 may be disposed between the redistribution structure 12 and the circuit layer 16. In some arrangements, the encapsulant 18 may encapsulate the electronic components 14-1, 14-2, and 14-3. In some arrangements, the encapsulant 18 may encapsulate the terminal 141. The encapsulant 18 may cover the surface 14-1s1 of the electronic component 14-1. The encapsulant 18 may cover the surface 14-1s3 of the electronic component 14-1. The encapsulant 18 may be disposed between the conductive layer 16c within the circuit layer 16 and the electronic component 14-1 (or 14-2 or 14-3). The encapsulant 18 may contact the adhesive layer 142. The encapsulant 18 may include an insulating or dielectric material. For example, the encapsulant 18 may include a molding material. In some arrangements, the encapsulant 18 may be made of a molding material, which may include, for example, a phenolic-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers, such as powdered SiO2, may also be included. Encapsulant 18 may include surface 18s1, surface 18s2, and surface 18s3. Surface 18s1 (or lower surface) may face or contact circuit layer 16. Surface 18s2 (or upper surface) may face or contact redistribution structure 12. Surface 18s3 may extend between surfaces 18s1 and 18s2. In some arrangements, surface 18s3 of encapsulant 18 may be substantially aligned with surface 16s3 of circuit layer 16. In some arrangements, surface 18s3 of encapsulant 18 may be substantially aligned with surface 12s3 of redistribution structure 12. In some arrangements, surface 18s3 of encapsulant 18 may be substantially aligned with surface 10s3 of electronic component 10.

[0070] In some arrangements, the conductive element 20 may be disposed on or above the circuit layer 16. In some arrangements, the conductive element 20 may penetrate the encapsulation 18. In some arrangements, some of the conductive elements 20 may be disposed between or among the electronic components 14-1, 14-2, and 14-3. In some arrangements, the conductive element 20 may be electrically connected to the electronic component 10 (or the redistribution structure 12) through a non-welding head. In some arrangements, the conductive element 20 may extend between the surfaces 18s1 and 18s2 of the encapsulation 18. In some arrangements, the conductive element 20 may extend across the surface 14-1s3 of the electronic component 14-1. In some arrangements, the conductive element 20 may be electrically connected to the redistribution structure 12. In some arrangements, the conductive element 20 may be electrically connected to the circuit layer 16. In some arrangements, the conductive element 20 may be electrically connected to the electronic components 14-1, 14-2, and / or 14-3 through the circuit layer 16. For example, the conductive layer 16c within the circuit layer 16 may extend from the lower surface of the electronic component 14-1 (or to the lower surface of the terminal of the electronic component 14-1) to the lower surface of one of the conductive elements 20 to electrically connect the electronic component 14-1 and the conductive element 20. The conductive element 20 may surround the electronic components 14-1, 14-2, and / or 14-3. In some arrangements, the conductive element 20 may not overlap vertically with the electronic components 14-1, 14-2, and / or 14-3. In some arrangements, each of the electronic components 14-1, 14-2, and 14-3 may communicate with each other through the redistribution structure 12 and the circuit layer 16 and the conductive element 20. In some arrangements, the surface 20s1 (or lower surface) of the conductive element 20 may be substantially aligned with the surface 141s1 (or lower surface) of the terminal 141. The conductive element 20 may include, for example, a conductive column or other suitable element. The conductive element 20 may include a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta) or other suitable materials.

[0071] The electrical connector 22 may be disposed on or below the surface 16s1 of the circuit layer 16. The electrical connector 22 may be configured to electrically connect the electronic device 1a to another device (not shown). In some arrangements, the electrical connector 22 may include solder balls, such as controlled collapse chip connection (C4) bumps, ball grid arrays (BGA), land grid arrays (LGA), etc. In some arrangements, the electrical connector 22 may include a solder material, which may include an alloy of gold and tin solder or an alloy of silver and tin solder or other suitable materials.

[0072] In some arrangements, the heat dissipation element 24 may be disposed on or above the surface 10s2 of the electronic component 10. The heat dissipation element 24 may cover the electronic component 10. In some arrangements, the heat dissipation element 24 may be configured to dissipate the heat from the electronic component 10. The heat dissipation element 24 may also include a thermal interface material. In some arrangements, the heat dissipation element 24 may be replaced by a heat sink, which includes a plurality of protrusions protruding from the base portion. In some arrangements, the heat dissipation element 24 may include but is not limited to a solid metal block or an electrical insulator coated with a metal film. In some arrangements, the heat dissipation element 24 may have one or more conductive layers. For example, the heat dissipation element 24 may include copper (Cu), aluminum (Al), gold (Au), nickel (Ni) and / or other suitable layers. The heat dissipation element 24 may also include aluminum oxide (Al2O3), aluminum nitride (AlN) or a silicon nitride (SiN) plate coated with copper. In some arrangements, the heat dissipation element 24 may include a lower layer serving as a thermally conductive layer with a larger thickness and an upper layer serving as a protective layer with a smaller thickness. In some arrangements, the size (eg, width or surface area) of the heat dissipation element 24 may be equal to or greater than the size of the electronic component 10. The material of the heat dissipation element 24 may be different from the material of the electronic component 10.

[0073] In a comparative electronic device, three-dimensional stacking (3D stacking) technology is used to integrate electronic components with different functions. In a 3D stacked electronic device, electronic components are stacked in three or more levels, which increases the overall thickness of the electronic device. In another comparative electronic device, a 2.5D stacking technology utilizes an interposer (e.g., a silicon interposer) containing multiple through silicon vias (TSVs) to integrate electronic components with different functions. Under this condition, the electronic component is electrically connected to the interposer by a solder ball. This technology involves the alignment accuracy between the solder ball and the TSV, which is sensitive to the warping of the intermediate structure. In this arrangement, some circuits are integrated in the electronic component 10, and the electronic component can communicate with electronic components 14-1, 14-2 and 14-3 with different functions. The electronic component 10 can be electrically connected to the circuit layer 16 by a non-welding head. In addition, the signal path (or electrical path) between the electronic component 10 and the electronic component 14-1, 14-2 and 14-3 does not have a solder joint. For example, the signal path may pass through the surface 10s1 of the electronic component 10, the redistribution structure 12, the conductive element 20, the circuit layer 16, and the active surface (e.g., 14-1s1) of the electronic component 14-1 (or 14-2 or 14-3). The signal path does not pass through the adhesive layer 142. During the manufacture of the electronic device 1a, the alignment problem between the solder ball and the TSV can be ignored. In addition, in this arrangement, the silicon interposer can be omitted. Therefore, the thickness of the electronic device 1a can be reduced. In this disclosure, the signal path (or electrical path) can refer to a virtual path through which the current passes or to a physical structure through which the current passes.

[0074] Figure 2FIG. 1 is a cross-sectional view of an electronic device 1b according to some arrangements of the present disclosure. The electronic device 1b may be similar to Figure 1 The electronic device 1a is shown, and the differences between them are described below.

[0075] The electronic device 1b may include electronic components 14-1', 14-2', and 14-3'. In some arrangements, the electronic components 14-1', 14-2', and 14-3' may be disposed on or below the surface 10s1 of the electronic component 10. In some arrangements, the electronic components 14-1', 14-2', and 14-3' may be disposed on or below the surface 12s1 of the redistribution structure 12. The electronic components 14-1', 14-2', and 14-3' may include active components, such as memory dies (e.g., DRAM dies, SRAM dies, etc.), power management dies (e.g., PMIC dies), RF dies, sensor dies, MEMS dies, signal processing dies (e.g., DSP dies), front-end dies (e.g., AFE dies), or other active components. Each of the electronic components 14-1', 14-2', and 14-3' may include an active surface, a passive surface, and a side. For example, the electronic component 14-1' may include a surface 14-1's1, a surface 14-1's2, and a surface 14-1's3. The surface 14-1's1 (or the lower surface) may act as a passive surface, which may also be referred to as a backside surface. The surface 14-1's2 (or the upper surface) may be opposite to the surface 14-1's1 and act as an active surface through which a signal (e.g., a data signal, a power signal, etc.) passes. The surface 14-1's3 (or the side) may extend between the surfaces 14-1's1 and 14-1's2. In some arrangements, each of the electronic components 14-1', 14-2', and 14-3' may include different functions. For example, each of the electronic components 14-1', 14-2', and 14-3' may include different ICs. In some arrangements, each of the electronic components 14-1', 14-2', and 14-3' may be electrically connected to or communicate with the electronic component 10.

[0076] Each of the electronic components 14-1', 14-2' and 14-3' may include a terminal 141'. In some arrangements, the terminal 141' may be disposed, for example, on or above the surface 14-1's2 of the electronic component 14-1'. The terminal 141' may include a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta) or other applicable materials. In this arrangement, the redistribution structure 12 may include a first circuit for electrically connecting the electronic components 14-1', 14-2' and / or 14-3', and a second circuit for electrically connecting the conductive element 20. In some arrangements, the first circuit and the second circuit may have different sizes. In some arrangements, the line width / line spacing (L / S) of the first circuit may be different from the L / S of the second circuit. In some arrangements, the first circuit and the second circuit may have different densities (e.g., the number of conductive elements per unit area). In some arrangements, the density of the second circuit may be greater than the density of the first circuit. For example, the density of conductive layers, conductive traces, conductive pads, and / or conductive vias of the second circuit may be greater than the density of conductive layers, conductive traces, conductive pads, and / or conductive vias of the first circuit.

[0077] Figure 3 FIG. 1 is a cross-sectional view of an electronic device 1c according to some arrangements of the present disclosure. The electronic device 1c may be similar to Figure 1 The electronic device 1a is shown, and the differences between them are described below.

[0078] In some arrangements, the surface 10s3 of the electronic component 10 may be covered by the encapsulant 18. In some arrangements, the width of the electronic component 10 along a direction substantially orthogonal to the normal direction of the surface 10s1 may be different from the width of the encapsulant 18. In some arrangements, the surface 10s3 of the electronic component 10 may have an offset relative to the surface 18s3 of the encapsulant 18. In some arrangements, the surface 10s3 of the electronic component 10 may have an offset relative to the surface 16s3 of the circuit layer 16. In some arrangements, the encapsulant 18 may be in contact with the heat dissipation element 24.

[0079] In some arrangements, the surface 12s3 of the redistribution structure 12 may be covered by the encapsulant 18. In some arrangements, the surface 12s3 of the redistribution structure 12 may have an offset relative to the surface 18s3 of the encapsulant 18. In some arrangements, the surface 12s3 of the redistribution structure 12 may have an offset relative to the surface 16s3 of the circuit layer 16. In some arrangements, the width of the redistribution structure 12 may be different from the width of the circuit layer 16. The surface 10s3 of the electronic component 10 is encapsulated by the encapsulant 18, which in turn prevents the electronic component 10 from being damaged by the surrounding environment.

[0080] Figure 4FIG. 1 is a cross-sectional view of an electronic device 1d according to some arrangements of the present disclosure. The electronic device 1d may be similar to Figure 1 The electronic device 1a is shown, and the differences between them are described below.

[0081] In some arrangements, the electronic device 1d may include a circuit layer 26. In some arrangements, the circuit layer 26 may be disposed on or above the electronic component 10. In some arrangements, the circuit layer 26 may include a fan-out structure. In some arrangements, the circuit layer 26 may include a redistribution structure. The circuit layer 26 may include at least one conductive trace and / or conductive via embedded in the dielectric layer. In some arrangements, the circuit layer 26 may be electrically connected to the electronic component 10. In some arrangements, the circuit layer 26 may be electrically connected to the electronic components 14-1, 14-2, and 14-3. The circuit layer 26 may be configured to electrically connect the electronic device 1d to an external device (not shown). The circuit layer 26 may include a surface 26s1, a surface 26s2, and a surface 26s3. The surface 26s1 (or lower surface) may face or contact the electronic component 10. The surface 26s2 (or upper surface) may be opposite to the surface 26s1. The surface 26s3 (or side) may extend between the surfaces 26s1 and 26s2. A plurality of terminals (not shown), such as conductive pads, may be disposed on or above surface 26s2 and / or below surface 26s1. In some arrangements, surface 26s3 of circuit layer 26 may be substantially aligned with surface 10s3 of electronic component 10. In some arrangements, surface 26s3 of circuit layer 26 may be substantially aligned with surface 12s3 of redistribution structure 12. In some arrangements, surface 26s3 of circuit layer 26 may be substantially aligned with surface 16s3 of circuit layer 16.

[0082] In some arrangements, the electronic component 10 may include one or more through-holes 28. Each of the through-holes 28 may extend between the surfaces 10s1 and 10s2. In some arrangements, the through-holes 28 may electrically connect the redistribution structure 12 and the circuit layer 26. The through-holes 28 may be configured to connect components disposed above the electronic component 10. The components may include, for example, heat dissipation elements, packaging structures, and / or integrated circuits. In some arrangements, the through-holes 28 may overlap vertically with at least one of the electronic components 14-1 to 14-3. The through-holes 28 may include, for example, through-silicon vias (TSVs) or other suitable elements.

[0083] Figure 5 FIG. 1 is a cross-sectional view of an electronic device 1e according to some arrangements of the present disclosure. The electronic device 1e may be similar to Figure 4 The electronic device 1d is shown, and the differences between them are described below.

[0084] In some arrangements, the surface 10s3 of the electronic component 10 may be covered by the encapsulant 18. In some arrangements, the width of the electronic component 10 may be different from the width of the circuit layer 26. In some arrangements, the surface 10s3 of the electronic component 10 may have an offset relative to the surface 26s3 of the circuit layer 26. In some arrangements, the encapsulant 18 may contact the surface 26s1 of the circuit layer 26. In some arrangements, the encapsulant 18 may contact the dielectric layer, the trace, or both of the circuit layer 26. Therefore, the mold locking effect may be enhanced, thereby enhancing the reliability of the electronic device 1e. The surface 10s3 of the electronic component 10 is encapsulated by the encapsulant 18, which in turn prevents the electronic component 10 from being damaged by the surrounding environment. The encapsulant 18 may contact the surface 12s3 of the redistribution structure 12. For example, the encapsulant 18 may contact the side of the dielectric material of the redistribution structure 12.

[0085] Figure 6 is a cross-sectional view of an electronic device 1f according to some arrangements of the present disclosure.

[0086] In some arrangements, the electronic device 1f may include a device 31 and a packaging structure 40. In some arrangements, the structure of the device 31 may be similar to that of Figure 5 The structures of the electronic devices 1e shown are the same or similar.

[0087] In some arrangements, package structure 40 may be disposed on or over surface 26s2 of circuit layer 26. In some arrangements, package structure 40 may include carrier 41, electrical connector 42, electronic component 43, wire 44, and encapsulant 45.

[0088] The carrier 41 may be disposed above the circuit layer 26. The carrier 41 may be formed as a printed circuit board (PCB) comprising a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some arrangements, the carrier 41 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polymer materials such as polyimide. In some arrangements, the carrier 41 may have a surface 41s1 and a surface 41s2. The surface 41s1 (or the lower surface) may face the device 31. The surface 41s2 (or the upper surface) may be opposite to the surface 41s1. The carrier 41 may include one or more conductive pads (not shown) close to, adjacent to, embedded in, and / or exposed by the surface 41s1 and / or the surface 41s2 of the carrier 41. The carrier 41 may include a solder resist (not shown) on the surface 41 s 1 and / or the surface 41 s 2 of the carrier 41 to fully expose the conductive pads or expose at least a portion of the conductive pads for electrical connection.

[0089] The electrical connector 42 may be disposed on or below the surface 41s1 of the carrier 41. The electrical connector 42 may be configured to electrically connect the device 31 and the carrier 41. In some arrangements, the electrical connector 42 may include solder balls, such as controlled collapse chip connection (C4) bumps, ball grid arrays (BGA), land grid arrays (LGA), etc. In some arrangements, the electrical connector 42 may include a solder material, which may include an alloy of gold and tin solder or an alloy of silver and tin solder or other suitable materials.

[0090] The electronic component 43 may be disposed on or above the surface 41s2 of the carrier 41. The electronic component 43 may be electrically connected to the electronic component 10. The electronic component 43 may include active components, such as a logic die (e.g., ASIC, AP, SoC, CPU, GPU, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), an RF die, a sensor die, a MEMS die, a signal processing die (e.g., DSP die), a front-end die (e.g., AFE die), or other active components. The electronic component 43 may include a surface 43s1 and a surface 43s2. The surface 43s1 (or the lower surface) may act as a passive surface, which may also be referred to as a backside surface. The surface 43s2 (or the upper surface) may be opposite to the surface 43s1 and act as an active surface through which a signal (e.g., a data signal, a power signal, etc.) passes. The electronic component 43 may be attached to the carrier 41 by an adhesive (not labeled). The electronic component 43 may include one or more conductive pads proximate to, adjacent to, embedded in, and / or exposed by the surface 43s2.

[0091] The wires 44 may be configured to electrically connect the carrier 41 and the electronic component 43. Each of the wires 44 may have one end connected to the surface 41s2 of the carrier 41 and the other end connected to the surface 43s2 of the electronic component 43. Figure 6 The electronic component 43 is shown to be electrically connected to the carrier 41 through wires 44, but the electronic component 43 may be electrically connected to the carrier 41 through other techniques such as flip chip bonding techniques.

[0092] The encapsulant 45 may be disposed on or above the surface 41s2 of the carrier 41. In some arrangements, the encapsulant 45 may encapsulate the electronic component 43. In some arrangements, the encapsulant 45 may encapsulate the wire 44. In some arrangements, a portion of the surface 41s2 of the carrier 41 may be exposed by the encapsulant 45. The encapsulant 45 may include an insulating or dielectric material. For example, the encapsulant 45 may include a molding material. In some arrangements, the encapsulant 45 may be made of a molding material, which may include, for example, a phenolic-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. A suitable filler, such as powdered SiO2, may also be included.

[0093] Figure 7 is a cross-sectional view of an electronic device 1g according to some arrangements of the present disclosure.

[0094] In some arrangements, the electronic device 1g may include a device 32, an electronic component 51, and at least one passive component 52. In some arrangements, the structure of the device 32 may be similar to that of Figure 5 The structures of the electronic devices 1e shown are the same or similar.

[0095] In some arrangements, the electronic component 51 may be disposed on or above the device 32. The electronic component 51 may be disposed on or above the surface 26s2 of the circuit layer 26. The electronic component 51 may be electrically connected to the electronic component 10. The electronic component 51 may include active components, such as a logic die (e.g., ASIC, AP, SoC, CPU, GPU, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), an RF die, a sensor die, a MEMS die, a signal processing die (e.g., DSP die), a front-end die (e.g., AFE die), or other active components. The electronic component 51 may include a surface 51s1 and a surface 51s2. The surface 51s1 (or the lower surface) may face the device 32 and act as an active surface through which a signal (e.g., a data signal, a power signal, etc.) passes. The surface 51s2 (or the upper surface) may be opposite to the surface 51s1 and may act as a passive surface, which may also be referred to as a backside surface. The electronic component 51 may include one or more conductive pads (not shown) proximate to, adjacent to, embedded in, and / or exposed by the surface 51 s 1 .

[0096] Passive component 52 may be placed on or above device 32. Passive component 52 may be placed on or above surface 26s2 of circuit layer 26. Passive component 52 may be electrically connected to electronic component 10. Passive component 52 may be electrically connected to electronic component 51. In some arrangements, passive component 52 may be configured to regulate signals (e.g., power signals) transmitted to electronic components 10, 14-1, 14-2, 14-3 and / or 51. For example, electronic component 51 may be configured to stabilize the voltage of the signal. In some arrangements, passive component 52 may include capacitors, inductors, resistors, filters, or combinations of such components. In some arrangements, passive component 52 may include capacitors, such as deep trench capacitors (DTC), multi-layer ceramic capacitors (MLCC), or other capacitors that may be configured to filter high frequency signals and / or low frequency signals.

[0097] Figure 8 is a cross-sectional view of an electronic device 1h according to some arrangements of the present disclosure.

[0098] In some arrangements, the electronic device 1h may include a device 33 and an antenna package 60. In some arrangements, the device 33 may be similar to Figure 4 The electronic device 1d is shown, and the circuit layer 26 may be omitted from the device 33. In other arrangements, the device 33 may be the same as the electronic device 1d.

[0099] The antenna package 60 may be disposed on or over the device 33. The antenna package 60 may include an antenna 61, an electronic component 62, and an encapsulant 63.

[0100] Antenna 61 may be disposed on or above device 33. In some arrangements, antenna 61 may be configured to radiate and / or receive electromagnetic signals, such as RF signals. For example, antenna 61 may be configured to operate at a frequency between about 10 GHz and about 40 GHz (e.g., 10 GHz, 20 GHz, 30 GHz, or 40 GHz). In some arrangements, antenna 61 may be configured to operate at a frequency between about 30 GHz and about 300 GHz. In some arrangements, antenna 61 may be configured to operate at a frequency between about 300 GHz and about 10 THz. In some arrangements, antenna 61 may support fifth generation (5G) communications, such as lower than 6 GHz bands and / or millimeter (mm) wave bands. For example, antenna 61 may incorporate both lower than 6 GHz antennas and millimeter wave antennas. In some arrangements, antenna 61 may support communications exceeding 5G or 6G, such as terahertz (THz) bands. Antenna 61 may include multiple circuit patterns (not labeled) configured to determine or control the frequency of RF signals. The circuit pattern may be disposed within a dielectric structure (not labeled). A redistribution structure (not shown) may be embedded within the dielectric structure for providing electrical connections (eg, providing a feeding signal).

[0101] In some arrangements, the electronic component 62 may be placed on or above the antenna 61. The electronic component 62 may be electrically connected to the antenna 61. In some arrangements, the electronic component 62 may include an RFIC or other suitable components. The electronic component 62 may have a surface 62s1 and a surface 62s2. The surface 62s1 (or the lower surface) may face the antenna 61 and act as an active surface through which a signal (e.g., a data signal, a power signal, etc.) passes. The surface 62s2 (or the upper surface) may be opposite to the surface 62s1 and may act as a passive surface, which may also be referred to as a backside surface. The electronic component 62 may include one or more conductive pads (not shown) that are close to, adjacent to, embedded in, and / or exposed by the surface 62s1. The electronic component 62 may be electrically connected to the antenna 61 by an electrical connector (not labeled) such as a solder ball.

[0102] In some arrangements, the encapsulant 63 may be disposed on or above the antenna 61. In some arrangements, the encapsulant 63 may encapsulate the electronic component 62. The encapsulant 63 may include an insulating or dielectric material. For example, the encapsulant 63 may include a molding material. In some arrangements, the encapsulant 63 may be made of a molding material, which may include, for example, a phenolic-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. A suitable filler may also be included, such as powdered SiO2.

[0103] In some arrangements, the electronic device 1h may include a shielding layer 64. In some arrangements, the shielding layer 64 may cover the surface 10s2 of the electronic component 10. In some arrangements, the shielding layer 64 may cover the surface 10s3 of the electronic component 10. In some arrangements, the shielding layer 64 may cover the surface 18s3 of the encapsulation 18. In some arrangements, the shielding layer 64 may cover the surface 16s3 of the circuit layer 16. In some arrangements, the shielding layer 64 may include a portion (not labeled) between the electronic component 10 and the antenna 61 of the antenna package 60. In some arrangements, the shielding layer 64 may be configured to shield the electronic component 10 (or the electronic components 14-1, 14-2 and 14-3) from electromagnetic waves from the antenna package 60. Therefore, the electronic component 10 may not be affected by electromagnetic interference (EMI). The shielding layer 64 may include a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials.

[0104] In some arrangements, the device 33 may include a ground structure 65. The ground structure 65 may be electrically connected to ground. In some arrangements, the ground structure 65 may be electrically connected to the shielding layer 64. The ground structure 65 may be disposed within the electronic component 10, the redistribution structure 12, and the enclosure 18. For example, the ground structure 65 may be located at a peripheral region of the electronic component 10, the redistribution structure 12, and the enclosure 18. In some arrangements, the ground structure 65 may be closer to the surface 10s3 of the electronic component 10 than the through-hole 28. In some arrangements, the ground structure 65 may surround the through-hole 28. In some arrangements, the ground structure 65 may be closer to the surface 18s3 of the enclosure 18 than the conductive element 20. In some arrangements, the ground structure 65 may surround the conductive element 20.

[0105] Fig. 9 is a cross-sectional view of an electronic device 1i according to some arrangements of the present disclosure.

[0106] In some arrangements, the electronic device 1i may include the device 34 and the antenna device 70. In some arrangements, the device 34 may be similar to Figure 4 Electronic device 1d is shown, and circuit layer 26 may be omitted from device 34. In other arrangements, device 34 may be identical to electronic device 1d.

[0107] The antenna device 70 may be disposed on or above the device 34. The antenna device 70 may include a ground structure 29, an antenna 71, and an electronic component 75.

[0108] The ground structure 29 may be electrically connected to the ground. The ground structure 29 may be disposed within the electronic component 10, the redistribution structure 12, and the encapsulation 18. For example, the ground structure 29 may be located at a peripheral region of the electronic component 10, the redistribution structure 12, and the encapsulation 18. In some arrangements, the ground structure 29 may be closer to the surface 10s3 of the electronic component 10 than the through-hole 28. In some arrangements, the ground structure 29 may surround the through-hole 28. In some arrangements, the ground structure 29 may be closer to the surface 18s3 of the encapsulation 18 than the conductive element 20. In some arrangements, the ground structure 29 may surround the conductive element 20.

[0109] Antenna 71 may be placed on or above device 34. In some arrangements, antenna 71 may be configured to radiate and / or receive electromagnetic signals, such as RF signals. For example, antenna 71 may be configured to operate at a frequency between about 10 GHz and about 40 GHz (e.g., 10 GHz, 20 GHz, 30 GHz, or 40 GHz). In some arrangements, antenna 61 may be configured to operate at a frequency between about 30 GHz and about 300 GHz. In some arrangements, antenna 71 may be configured to operate at a frequency between about 300 GHz and about 10 THz. In some arrangements, antenna 71 may support fifth generation (5G) communications, such as lower than 6 GHz bands and / or millimeter (mm) wave bands. For example, antenna 71 may incorporate lower than 6 GHz antennas and millimeter wave antennas. In some arrangements, antenna 71 may support communications exceeding 5G or 6G, such as terahertz (THz) bands.

[0110] Antenna 71 may include circuit pattern 711, dielectric structure 712, and circuit pattern 713. Circuit pattern 711 may be disposed on or over surface 10s2 of electronic component 10. Circuit pattern 711 may be electrically connected to ground structure 29.

[0111] The dielectric structure 712 may be disposed between the circuit patterns 711 and 713. The dielectric structure 712 may include a dielectric material such as polyimide or other suitable material.

[0112] The circuit pattern 713 may be disposed on or over the circuit pattern 711. The arrangement of the circuit patterns 711 and 713 may be configured to determine or control the frequency of the RF signal.

[0113] The dielectric structure 72 may be disposed on or over the dielectric structure 712. The dielectric structure 72 may cover the circuit pattern 713. The dielectric structure 72 may include one or more dielectric layers. The dielectric structure 72 may include a dielectric material, such as polyimide or other suitable materials.

[0114] The shielding layer 73 may be disposed on or above the upper surface (not labeled) of the dielectric structure 72 and the side (not labeled) of the dielectric structure 72. In some arrangements, the shielding layer 73 may cover the surface 10s3 of the electronic component 10. In some arrangements, the shielding layer 73 may cover the surface 18s3 of the encapsulation 18. In some arrangements, the shielding layer 73 may cover the surface 16s3 of the circuit layer 16. In some arrangements, the shielding layer 73 may be configured to shield the electronic component 10 (or the electronic components 14-1, 14-2 and 14-3) from the electromagnetic waves from the antenna 71. The shielding layer 73 may include a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. In some arrangements, the shielding layer 73 may be electrically connected to the circuit pattern 711 of the antenna 71. In some arrangements, the shielding layer 73 may be electrically connected to the ground. In some arrangements, the shielding layer 73 may be configured to serve as a reference ground for the antenna 71.

[0115] Dielectric structure 74 may be disposed on or over shielding layer 73. Dielectric structure 74 may cover shielding layer 73. Dielectric structure 74 may cover dielectric structure 72. Dielectric structure 74 may include a dielectric material, such as polyimide or other suitable material.

[0116] In some arrangements, the electronic component 75 may be disposed on or above the antenna 71. The electronic component 75 may be electrically connected to the antenna 71. For example, the electronic component 75 may be electrically connected to the antenna 71 through an electrical connector 75e, a conductive layer 75u, and a conductive via 71v. The electrical connector 75e may include, for example, a solder material. The conductive layer 75u may serve as an under-bump metallization (UBM). The conductive via 71v may be disposed between the circuit pattern 711 and the conductive layer 75u. In some arrangements, the electronic component 75 may include an RFIC or other suitable components. The electronic component 75 may have a surface 75s1, a surface 75s2, and a surface 75s3. The surface 75s1 (or lower surface) may face the antenna 71 and serve as an active surface through which a signal (e.g., a data signal, a power signal, etc.) passes. The surface 75s2 (or upper surface) may be opposite to the surface 75s1 and may serve as a passive surface, which may also be referred to as a backside surface. Surface 75s3 may extend between surfaces 75s1 and 75s2. Electronic component 75 may include one or more conductive pads (not shown) proximate to, adjacent to, embedded in, and / or exposed by surface 75s1. Electronic component 75 may be electrically connected to antenna 71 via an electrical connector (not labeled) such as a solder ball.

[0117] In some arrangements, a redistribution structure (not labeled) may electrically connect the electronic component 75 and the device 34. The redistribution structure may be disposed within or adjacent to the dielectric structure 72. The redistribution structure may be surrounded by the antenna 71.

[0118] Filler 76 may be disposed on or over dielectric structure 72. Filler 76 may encapsulate an electrical connector (e.g., solder ball) between antenna 71 and electronic component 75. Filler 76 may include, for example, an underfill or other suitable component. Filler 76 may cover electrical connector 75e and conductive layer 75u.

[0119] The shielding layer 77 may be disposed on or above the filler 76. In some arrangements, the shielding layer 77 may cover the surface 75s2 of the electronic component 75. In some arrangements, the shielding layer 77 may cover the surface 75s3 of the electronic component 75. In some arrangements, the shielding layer 77 may be configured to shield the electronic component 75 from EMI. The shielding layer 77 may include a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials.

[0120] The protective layer 78 may be disposed on or over the filler 76. The protective layer 78 may cover the shielding layer 77 to protect the shielding layer 77 from damage by the environment. The protective layer 78 may include a dielectric material such as polyimide, a phenolic compound or material, or other suitable materials.

[0121] Fig.10 1 is a cross-sectional view of an electronic device 1j according to some arrangements of the present disclosure. The electronic device 1j may include a device 35, a device 36, and a device 37. In some arrangements, the device 35 may be connected to the device 37. Figure 5 The electronic device 1e shown is the same or similar. In some arrangements, the device 36 may be used with Figure 4 The electronic device 1d shown is the same or similar. In some arrangements, the device 37 may be used with Figure 3 The electronic device 1c shown is the same or similar. Device 35 may be electrically connected to devices 36 and 37. Devices 35, 36 and 37 may be stacked vertically.

[0122] FIG. 11A to FIG. 11H Various stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0123] refer to Fig.11A, a substrate 10' may be provided. The substrate 10' may include, for example, a wafer. The substrate 10' may include a plurality of units (not labeled), each of which may correspond to a die. After performing a singulation technique, the substrate 10' may be sawn into a plurality of dies. The substrate 10' may include a surface 10's1 and a surface 10's2 opposite to the surface 10's1. A plurality of ICs (not shown) may be formed adjacent to the surface 10's1 of the substrate 10'. A redistribution structure 12 may be formed on the surface 10's1 of the substrate 10'.

[0124] refer to Fig. 11B , at least one conductive element 20 may be formed below the surface 12s1 of the redistribution structure 12. In some arrangements, a photosensitive material (not shown) may be formed above the redistribution structure 12. The photosensitive material may be patterned, for example, by photolithography techniques, to form at least one opening penetrating the photosensitive material. Next, a seed layer may be formed within the opening and on the redistribution structure 12, and then a conductive material may be formed on the seed layer to produce the conductive element 20.

[0125] refer to Fig. 11C , electronic components 14-1, 14-2, 14-3, 14-4, 14-5, and 14-6 may be mounted below the surface 12s1 of the redistribution structure 12. Each of the electronic components 14-4, 14-5, and 14-6 may be the same as or similar to the electronic component 14-1.

[0126] refer to Fig.11D , the encapsulant 18 may be formed below the surface 12s1 of the redistribution structure 12 to cover the electronic components 14 - 1 to 14 - 6 and the conductive elements 20 .

[0127] refer to Fig.11E , the surface 18s1 of the encapsulant 18 may be grinded. In some arrangements, the terminals 141 may be grinded. In some arrangements, the conductive element 20 may be grinded. Thus, the terminals 141 of the electronic components 14-1 to 14-6 may be exposed by the surface 18s1 of the encapsulant 18. The conductive element 20 (e.g., the lower surface of the conductive element 20) may be exposed by the surface 18s1 of the encapsulant 18.

[0128] refer to Fig.11F , the circuit layer 16 may be formed below the surface 18s1 of the encapsulant 18 to electrically connect the conductive element 20 .

[0129] refer to Fig.11G The heat dissipation element 24 may be formed on the surface 10 ′ s 2 of the substrate 10 ′. For example, one or more metal materials may be plated on the surface 10 ′ s 2 of the substrate 10 ′ to form the heat dissipation element 24 .

[0130] refer to Fig.11H, the electrical connector 22 may be formed below the surface 18s1 of the encapsulant 18. Next, a singulation technique may be performed on the substrate 10'. The electronic components 14-1 to 14-3 and the electronic components 14-4 to 14-6 may be integrated on the corresponding electronic component 10. Thus, a plurality of electronic devices may be produced, such as Figure 1 The electronic device 1a is shown.

[0131] FIG. 12A to FIG. 12G Various stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown. Fig. 12A Depicted in Fig.11A The stage following the stage depicted in .

[0132] refer to Fig. 12A , at least one conductive element 20 may be formed below the surface 12s1 of the redistribution structure 12. The substrate 10' may be sawn to form the electronic component 10. The surface 10s2 of the electronic component 10 may be attached to a carrier 81. The carrier 81 may include a silicon carrier, a glass carrier, a ceramic carrier, or other suitable carriers. The release film 82 may be configured to attach the electronic component 10 to the carrier 81. The groove 10r may be formed above the carrier 81.

[0133] refer to Fig. 12B , the electronic components 14 - 1 , 14 - 2 , 14 - 3 , 14 - 4 , 14 - 5 , and 14 - 6 may be mounted below the surface 12 s 1 of the redistribution structure 12 of the corresponding electronic component 10 .

[0134] refer to Fig. 12C , an encapsulant 18 may be formed under the surface 12s1 of the redistribution structure 12 to cover the electronic components 14-1 to 14-6 and the conductive element 20. The encapsulant 18 may fill the groove 10r.

[0135] refer to Fig.12D , the surface 18s1 of the encapsulant 18 may be polished. Therefore, the terminals 141 of the electronic components 14-1 to 14-6 may be exposed by the surface 18s1 of the encapsulant 18. The conductive element 20 (eg, the lower surface of the conductive element 20) may be exposed by the surface 18s1 of the encapsulant 18.

[0136] refer to Fig.12E , the circuit layer 16 may be formed below the surface 18s1 of the encapsulant 18 to electrically connect the conductive element 20 .

[0137] refer to Fig.12F The heat dissipation element 24 may be formed on the surface 10s2 of the electronic component 10. For example, one or more metal materials may be plated on the surface 10s2 of the electronic component 10 to form the heat dissipation element 24. The carrier 81 and the release film 82 may be removed.

[0138] refer to Figure 12G , the electrical connector 22 may be formed below the surface 18s1 of the encapsulant 18. Next, a singulation technique may be performed on the recess 10r. Thus, a plurality of electronic devices may be produced, such as Figure 3 The electronic device 1c is shown.

[0139] FIG. 13A to FIG. 13H Various stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown.

[0140] refer to Fig.13A , a substrate 10' may be provided. The substrate 10' may include, for example, a wafer. The substrate 10' may include a plurality of units (not labeled), each of which may correspond to a die. After performing the singulation technique, the substrate 10' may be sawn into a plurality of dies. The substrate 10' may include a surface 10's1 and a surface 10's2 opposite to the surface 10's1. A plurality of ICs (not shown) may be formed adjacent to the surface 10's1 of the substrate 10'. At least one through-hole 28 may be formed in the substrate 10' and extend between the surfaces 10's1 and 10's2. A redistribution structure 12 may be formed on the surface 10's1 of the substrate 10' and electrically connected to the through-hole 28.

[0141] refer to Fig. 13B , at least one conductive element 20 may be formed below the surface 12s1 of the redistribution structure 12 .

[0142] refer to Fig. 13C , electronic components 14-1, 14-2, 14-3, 14-4, 14-5, and 14-6 may be mounted below the surface 12s1 of the redistribution structure 12. Each of the electronic components 14-4, 14-5, and 14-6 may be the same as or similar to the electronic component 14-1.

[0143] refer to Fig.13D , the encapsulant 18 may be formed below the surface 12s1 of the redistribution structure 12 to cover the electronic components 14 - 1 to 14 - 6 and the conductive elements 20 .

[0144] refer to Fig.13E , the surface 18s1 of the encapsulant 18 may be polished. Therefore, the terminals 141 of the electronic components 14-1 to 14-6 may be exposed by the surface 18s1 of the encapsulant 18. The conductive element 20 (eg, the lower surface of the conductive element 20) may be exposed by the surface 18s1 of the encapsulant 18.

[0145] refer to Fig.13F , the circuit layer 16 may be formed below the surface 18s1 of the encapsulant 18 to electrically connect the conductive element 20 .

[0146] refer to Figure 13G, a circuit layer 26 may be formed over the surface 10 ′ s 2 of the substrate 10 ′ and electrically connected to the through-via 28 .

[0147] refer to Fig.13H , the electrical connector 22 may be formed below the surface 18s1 of the encapsulant 18. Next, a singulation technique may be performed. Thus, a plurality of electronic devices may be produced, such as Figure 4 The electronic device 1d is shown.

[0148] FIG. 14A to FIG. 14G Various stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown. Fig.14A Depicted in Fig.13A The stage following the stage depicted in .

[0149] refer to Fig.14A , at least one conductive element 20 may be formed below the surface 12s1 of the redistribution structure 12 and electrically connected to the through-hole 28. The substrate 10' may be sawn to form the electronic component 10. The electronic component 10 may be attached to a carrier 83. The carrier 83 may include a silicon carrier, a glass carrier, a ceramic carrier, or other suitable carriers. A release film 84 may be configured to attach the electronic component 10 to the carrier 83. A groove 10r may be formed above the carrier 83.

[0150] refer to Fig. 14B , the electronic components 14-1, 14-2, 14-3, 14-4, 14-5, and 14-6 may be mounted below the surface 12s1 of the redistribution structure 12. The electronic components 14-1 to 14-3 and the electronic components 14-4 to 14-6 may be separated by the groove 10r.

[0151] refer to Fig. 14C , an encapsulant 18 may be formed under the surface 12s1 of the redistribution structure 12 to cover the electronic components 14-1 to 14-6 and the conductive element 20. The encapsulant 18 may fill the groove 10r.

[0152] refer to Fig.14D , the surface 18s1 of the encapsulant 18 may be polished. Therefore, the terminals 141 of the electronic components 14-1 to 14-6 may be exposed by the surface 18s1 of the encapsulant 18. The conductive element 20 (eg, the lower surface of the conductive element 20) may be exposed by the surface 18s1 of the encapsulant 18.

[0153] refer to Fig.14E , the circuit layer 16 may be formed below the surface 18s1 of the encapsulant 18 to electrically connect the conductive element 20 .

[0154] refer to Fig.14F , the circuit layer 26 may be formed over the surface 10s2 of the electronic component 10 and electrically connected to the through-hole 28. The carrier 83 and the release film 84 may be removed.

[0155] refer to Figure 14G , the electrical connector 22 may be formed below the surface 18s1 of the encapsulant 18. Next, a singulation technique may be performed on the recess 10r. Thus, a plurality of electronic devices may be produced, such as Figure 5 The electronic device 1e is shown.

[0156] FIG. 15A to FIG. 15E Various stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown. Fig.15A Depicted in Fig.13F The stage following the stage depicted in .

[0157] refer to Fig.15A , a singulation technique may be performed on the substrate 10' to separate the plurality of electronic components 10. Next, the circuit layer 16 may be attached to the carrier 85. In this arrangement, a ground structure 65 may be formed within the electronic components 10, the redistribution structure 12, and the encapsulant 18.

[0158] refer to Fig. 15B , a shielding layer 64 may be formed to cover the surface 10s2 of the electronic component 10. The shielding layer 64 may cover the surface 10s3 of the electronic component 10 and the surface 18s3 of the encapsulant 18. The shielding layer 64 may be formed by, for example, a sputtering technique or other suitable techniques.

[0159] refer to Fig. 15C , the shielding layer 64 may be patterned to expose the through-hole 28 (eg, the upper surface of the through-hole 28 ).

[0160] refer to Fig.15D , the carrier 85 can be removed.

[0161] refer to Fig.15E , the antenna package 60 can be mounted above the surface 10s2 of the electronic component 10. Therefore, an electronic device such as Figure 8 The electronic device 1h is shown.

[0162] FIG. 16A to FIG. 16H Various stages of an example of a method for manufacturing an electronic device according to some arrangements of the present disclosure are shown. Fig.16A Depicted in Fig.13F The stage following the stage depicted in .

[0163] refer to Fig.16A , a singulation technique may be performed on the substrate 10 ′ to separate the plurality of electronic components 10 .

[0164] refer to Fig. 16B , the circuit pattern 711 may be formed over the surface 10s2 of the electronic component 10 .

[0165] refer to Fig. 16C , a dielectric structure 712 may be formed to cover the circuit pattern 711. A circuit pattern 713 may be formed over the dielectric structure 712. An antenna 71 may be defined.

[0166] refer to Fig.16D , a dielectric structure 72 may be formed to cover the dielectric structure 712 .

[0167] refer to Fig.16E , the circuit layer 16 may be attached to the carrier 86. The shielding layer 73 may be formed to cover the dielectric structure 72 and the surface 10s3 of the electronic component 10 and the surface 18s3 of the encapsulant 18. The mask 79 may be formed on the shielding layer 73. The mask 79 may be patterned to expose a portion of the shielding layer 73.

[0168] refer to Fig.16F , shielding layer 73 may be patterned. Portions of shielding layer 73 exposed by mask 79 may be removed. Portions of dielectric structure 72 may be exposed. Mask 79 may be removed.

[0169] refer to Figure 16G , a dielectric structure 74 may be formed to cover the shielding layer 73 .

[0170] refer to Fig.16H , the electronic component 75, the filler 76, the shielding layer 77 and the protective layer 78 may be formed over the antenna 71. Thus, an electronic device such as Fig. 9 The electronic device 1i is shown.

[0171] Unless otherwise specified, spatial descriptions such as "above", "below", "upward", "left", "right", "downward", "top", "bottom", "vertical", "horizontal", "side", "above", "lower", "upper", "above", "below", etc. are indicated relative to the orientation shown in the figure. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the arrangements disclosed herein are not deviated by such arrangements.

[0172] As used herein, the term "vertical" is used to refer to an upward and downward direction, while the term "horizontal" refers to a direction transverse to the vertical direction.

[0173] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and explain small variations. When used in conjunction with an event or circumstance, the terms may refer to situations where the event or circumstance clearly occurs as well as situations where the event or circumstance is very close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation of less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value may be considered to be "substantially" the same as or equal to the second numerical value. For example, "substantially" vertical may refer to an angular variation range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0174] Two surfaces are considered to be coplanar or substantially coplanar if the displacement between them is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm. A surface is considered to be substantially flat if the displacement between the highest point and the lowest point of the surface is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm.

[0175] As used herein, the singular terms "a," "an," and "the" may include plural references unless the context clearly dictates otherwise.

[0176] As used herein, the terms "conductive", "electrically conductive" and "conductivity" refer to the ability to carry an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m (e.g., at least 10 5 S / m or at least 10 6 S / m). The conductivity of a material can sometimes change with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0177] In addition, amounts, ratios and other numerical values ​​are sometimes presented herein in a range format. It should be understood that such a range format is used for convenience and brevity, and should be flexibly construed to include not only the values ​​explicitly specified as range limits, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly specified.

[0178] Although the disclosure has been described and illustrated with reference to the specific arrangement of the disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes and equivalents may be made without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in the disclosure and the actual equipment. The disclosure may have other arrangements that are not specifically described. The description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to make specific situations, materials, material compositions, methods or processes suitable for the goals, spirit and scope of the disclosure. All such modifications are expected to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations on the disclosure.

Claims

1. An electronic device, comprising: a first electronic component; a plurality of second electronic components disposed below the first electronic components; as well as A plurality of conductive elements electrically connect the first electronic component to the plurality of second electronic components, wherein the plurality of conductive elements do not vertically overlap the plurality of second electronic components.

2. The electronic device according to claim 1, further comprising: An encapsulant encapsulates a side surface of the first electronic component. 3 . The electronic device according to claim 2 , wherein the encapsulant encapsulates the plurality of second electronic components and the plurality of conductive elements. 4 . The electronic device according to claim 3 , wherein at least one of the plurality of second electronic components has a passive surface facing the first electronic component and an active surface opposite to the passive surface, and the encapsulant covers the active surface. 5 . The electronic device of claim 1 , wherein the first electronic component includes a through-hole configured to connect a component disposed above the first electronic component.

6. The electronic device according to claim 5, further comprising: Shielding layer, The component includes an integrated circuit, and the shielding layer is disposed between the first electronic component and the integrated circuit to block electromagnetic interference.

7. The electronic device according to claim 5, further comprising: Conductive layer, Wherein the component includes an antenna disposed between the first electronic component and the conductive layer, the conductive layer being configured to serve as a reference ground for the antenna. The electronic device according to claim 5 , wherein the through hole overlaps with at least one of the plurality of second electronic components.

9. The electronic device according to claim 1, further comprising: A redistribution structure is disposed below the plurality of second electronic components, wherein the plurality of conductive elements are electrically connected to the plurality of second electronic components through the redistribution structure.

10. The electronic device according to claim 1, further comprising: A heat dissipation element is disposed above the first electronic component.

11. An electronic device comprising: a first electronic component; a plurality of second electronic components disposed below the first electronic components; as well as a first circuit layer disposed below the plurality of second electronic components, The first electronic component is electrically connected to the plurality of second electronic components through the first circuit layer. 12 . The electronic device of claim 11 , wherein the plurality of second electronic components do not vertically overlap each other.

13. The electronic device according to claim 11, further comprising: an encapsulation encapsulating the plurality of second electronic components; as well as A conductive element penetrates the encapsulant and electrically connects the first circuit layer and the first electronic component.

14. The electronic device of claim 13, wherein an upper surface of the encapsulant is substantially aligned with a passive surface of the first electronic component.

15. The electronic device according to claim 11, further comprising: A shielding layer covers the first electronic component and exposes a portion of an upper surface of the first electronic component. 16 . The electronic device of claim 15 , wherein the first electronic component comprises a first conductive via electrically connected to the shielding layer and a second conductive via exposed by the upper surface of the first electronic component. The electronic device according to claim 16 , wherein the shielding layer covers a side surface of the first electronic component.

18. An electronic device comprising: a first electronic component; as well as a second electronic component disposed below the first electronic component and spaced apart from the first electronic component by an adhesive layer, The electronic device provides an electrical path through the first electronic component and the second electronic component without passing through the adhesive layer.

19. The electronic device according to claim 18, further comprising: a plurality of conductive elements disposed below the first electronic component and adjacent to the second electronic component, wherein the electrical path passes through at least one of the plurality of conductive elements; as well as A conductive layer extends from a lower surface of the second electronic component to a lower surface of the at least one of the plurality of conductive elements.

20. The electronic device according to claim 19, further comprising: An encapsulant covers the second electronic component and is disposed between the conductive layer and the second electronic component, wherein the encapsulant contacts the adhesive layer.

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