A clock-modulated charge pump circuit

Abstract

This invention discloses a clock-modulated charge pump circuit, comprising a reference voltage module, an LDO module, a charge pump module, a feedback network module, a voltage-controlled current source, and a clock module. The reference voltage module provides a precise reference voltage VREF. The LDO module generates a first voltage VIN_CP based on the input reference voltage VREF. The charge pump module generates a second voltage VCP from the first voltage VIN_CP, a first clock CLKP, and a second clock CLKN. The feedback network module generates a third voltage Vc based on the second voltage VCP. The voltage-controlled current source generates a bias voltage Vbias based on the third voltage Vc. The clock module generates complementary first clock CLKP and second clock CLKN based on the bias voltage Vbias. This invention has a wide load drive capability and can adjust the clock frequency according to the load, improving the efficiency of the charge pump.

Description

Technical Field

[0001] The invention relates to a charge pump circuit, in particular to a clock-modulated charge pump circuit, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] A charge pump is a basic circuit widely used in various integrated circuits and integrated systems. It is essentially a DC-DC converter that uses capacitors as energy storage elements and controls the charging and discharging of capacitors through switching elements to achieve the function of boosting or lowering voltage. It has a series of advantages such as the ability to output high voltage, high conversion efficiency, and low static power consumption. It plays an increasingly important role in modern electronic devices.

[0003] Modern charge pumps are basically developed from Dickson structure charge pumps. In order to solve the problem of charge pump performance degradation caused by body effect and Vth of Dickson structure charge pumps, charge pumps with Bootstrap structure and charge transfer charge pump (CTS) were developed. In order to further improve the driving ability and efficiency of charge pumps, double structure charge pumps were developed. The Latch structure is shown in Figure 8. Due to the simple driving clock and small number of devices required, it has the advantages of double structure continuous drive load and is widely used in modern electronic systems. However, from the perspective of its structure, it is an open-loop structure, which means that it has no ability to detect the output signal. Therefore, in actual design, in order to meet the extremely rare working conditions, In order to meet the load conditions at the output end, it is often necessary to make more hardware or power consumption redundancy under normal working conditions during design, which increases the hardware cost. FIG9 is a commonly used charge pump structure with feedback modulation. When the load at the output end increases, the voltage at the input end of the charge pump is increased by feedback, thereby increasing the amount of charge pumped into the charge pump in each cycle to meet the requirements for improving the charge pump driving capability. The output voltage of the charge pump is based on the input voltage and the high-level clock voltage. The input voltage range is often limited to a smaller range. Therefore, due to the limitation of the system operating voltage, the load range that can be driven by this LDO modulated charge pump is still relatively small. For some application scenarios with a large load variation range, a new charge pump structure is needed to achieve the design requirements at a limited hardware cost.

[0004] Therefore, the traditional open-loop charge pump is suitable for driving fixed loads. When the load variation range is large, in order to meet the driving requirements of the maximum load, it is necessary to increase the pumping capacitor or increase the clock frequency to meet the maximum driving capability requirements. However, when the load is small, the open-loop charge pump still uses a relatively large pumping capacitor or clock frequency, which will result in power consumption and area waste and low efficiency under small load conditions. The charge pump using LDO modulation can adaptively adjust the input voltage of the charge pump according to the output voltage value, and pump more charge in each clock cycle to achieve a wider range of driving capabilities. However, due to the limited output voltage variation range of the LDO, this also leads to a smaller input voltage variation range of the charge pump, so the load variation range it can drive is also smaller. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a clock-modulated charge pump circuit to improve the problem that the open-loop charge pump has weak driving capability and the LDO-modulated charge pump has a small range of load driving capability.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A clock-modulated charge pump circuit comprises a reference voltage module, an LDO module, a charge pump module, a feedback network module, a voltage-controlled current source and a clock module, wherein the reference voltage module is used to provide an accurate reference voltage VREF, the LDO module generates a first voltage VIN_CP based on the input reference voltage VREF, the charge pump module generates a second voltage VCP from the first voltage VIN_CP, a first clock CLKP and a second clock CLKN, the feedback network module generates a third voltage Vc based on the second voltage VCP, the voltage-controlled current source generates a bias voltage Vbias based on the third voltage Vc, and the clock module generates a complementary first clock CLKP and a second clock CLKN based on the bias voltage Vbias.

[0008] Further, the LDO module includes an operational amplifier OP1, a feedback resistor Rfb3 and a feedback resistor Rfb4, the non-inverting input terminal of the operational amplifier OP1 serves as the input terminal of the LDO module and is connected to the reference voltage VREF, the inverting input terminal of the operational amplifier OP1 is connected to one end of the feedback resistor Rfb3 and one end of the feedback resistor Rfb4, the output terminal of the operational amplifier OP1 is connected to the other end of the feedback resistor Rfb3 and serves as the output terminal of the LDO module to output the second voltage VCP, and the other end of the feedback resistor Rfb4 is grounded.

[0009] Further, the charge pump module includes an NMOS tube NM1, an NMOS tube NM2, a PMOS tube PM1, a PMOS tube PM2, a pump capacitor Cpump1 and a pump capacitor Cpump2; the source of the NMOS tube M1 is connected to the source of the NMOS tube NM2 and is connected to the first voltage VIN_CP as the input end of the charge pump module, the gate of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2, one end of the pump capacitor Cpump2, the gate of the PMOS tube PM1 and the drain of the PMOS tube PM2, the drain of the NMOS tube NM1 is connected to the gate of the NMOS tube NM2, one end of the pump capacitor Cpump1, the gate of the PMOS tube PM2 and the drain of the PMOS tube PM1, the source of the PMOS tube PM1 is connected to the source of the PMOS tube PM2 and is connected to the output end of the charge pump module to generate a second voltage VCP, the other end of the pump capacitor Cpump1 is connected to the second clock CLKN, and the other end of the pump capacitor Cpump2 is connected to the first clock CLKP.

[0010] Further, the feedback network module includes a feedback resistor Rfb1, a feedback resistor Rfb2, a feedback capacitor Cfb1, a feedback capacitor Cfb2 and an operational amplifier OP2, one end of the feedback capacitor Cfb1 is connected to one end of the feedback resistor Rfb1 and is connected to the second voltage VCP as an input end of the feedback network module, the other end of the feedback capacitor Cfb1 is connected to one end of the feedback capacitor Cfb2, the other end of the feedback resistor Rfb1, one end of the feedback resistor Rfb2 and the reverse input end of the operational amplifier OP2, the other end of the feedback capacitor Cfb2 and the other end of the feedback resistor Rfb2 are grounded, the positive input end of the operational amplifier OP2 is connected to the reference voltage VREF, and the output end of the operational amplifier OP2 serves as the output end of the feedback network module and generates a third voltage Vc.

[0011] Further, the voltage-controlled current source includes an operational amplifier OP3, an NMOS tube NM3, a PMOS tube PM3, a resistor Rs, resistors Rs1-Rsn and switches S1-Sn, the source of the PMOS tube PM3 is connected to the power supply VCC, the gate of the PMOS tube PM3 is connected to the drain of the PMOS tube PM3 and the drain of the NMOS tube NM3 and serves as the output end of the voltage-controlled current source to generate a bias voltage Vbias, the gate of the NMOS tube NM3 is connected to the output end of the operational amplifier OP3, the positive input end of the operational amplifier OP3 serves as the input end of the voltage-controlled current source and is connected to the third voltage Vc, the reverse input end of the operational amplifier OP3 is connected to the source of the NMOS tube NM3, one end of the resistor Rs, and one end of the switch S1-Sn, the other end of the switch S1-Sn is connected to one end of the resistor Rs1-Rsn in a one-to-one correspondence, the control end of the switch S1-Sn is connected to the control signal PROG_R, and the other end of the resistor Rs and the other end of the resistor Rs1-Rsn are grounded.

[0012] Further, the clock module comprises a PMOS tube PM4, a PMOS tube PM5, a PMOS tube PM6, a PMOS tube PM7, a PMOS tube PM8, an NMOS tube NM4, an NMOS tube NM5, an NMOS tube NM6, an NMOS tube NM7, an NMOS tube NM8 and a capacitor Cosc, a gate of the PMOS tube PM4 is connected to a gate of the PMOS tube PM5 and is connected to a bias voltage Vbias as an input end of the clock module, a source of the PMOS tube PM4, a source of the PMOS tube PM5, a source of the PMOS tube PM7 and a source of the PMOS tube PM8 are connected to a charge pump clock high level Vosc, a drain of the PMOS tube PM4 is connected to a drain of the NMOS tube NM4, a gate of the NMOS tube NM4 and a gate of the NMOS tube NM5, a source of the NMOS tube NM4 is connected to a The source of the NMOS tube NM5, one end of the capacitor Cosc, the source of the NMOS tube NM7 and the source of the NMOS tube NM8 are connected, the drain of the PMOS tube PM5 is connected to the source of the PMOS tube PM6, the gate of the PMOS tube PM6 is connected to the gate of the NMOS tube NM6, the drain of the PMOS tube PM8 and the drain of the NMOS tube NM8 are connected to generate the second clock CLKN, the drain of the PMOS tube PM6 is connected to the drain of the NMOS tube NM6, the other end of the capacitor Cosc, the gate of the PMOS tube PM7 and the gate of the NMOS tube NM7, the source of the NMOS tube NM6 is connected to the drain of the NMOS tube NM5, the drain of the PMOS tube PM7 is connected to the drain of the NMOS tube NM7, the gate of the PMOS tube PM8 and the gate of the NMOS tube NM8 are connected to generate the first clock CLKP.

[0013] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a clock-modulated charge pump circuit, which has a wider load driving capability and can adjust the clock frequency according to the load, thereby improving the efficiency of the charge pump. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of a clock modulated charge pump circuit of the present invention.

[0015] Figure 2 The invention discloses a circuit diagram of a clock-modulated charge pump circuit.

[0016] Figure 3 is a circuit diagram of the LDO module of the present invention.

[0017] Figure 4 is a circuit diagram of the charge pump module of the present invention.

[0018] Figure 5 It is a circuit diagram of the feedback network module of the present invention.

[0019] Figure 6 is a circuit diagram of a voltage-controlled current source of the present invention.

[0020] Figure 7 is a circuit diagram of a clock module of the present invention.

[0021] Figure 8 is a schematic diagram of an open-loop charge pump in the prior art.

[0022] Fig. 9 FIG. 4 is a schematic diagram of a charge pump modulated by an LDO in the prior art. DETAILED DESCRIPTION

[0023] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0024] like Figure 1 and Figure 2As shown, a clock-modulated charge pump circuit of the present invention comprises a reference voltage module 10, an LDO module 11, a charge pump module 12, a feedback network module 13, a voltage-controlled current source 14 and a clock module 15. The reference voltage module 10 is used to provide an accurate reference voltage VREF for the entire charge pump circuit. The reference voltage VREF is input into the LDO module, and the LDO module uses an operational amplifier OP1 and feedback resistors Rfb3 and Rfb4 to generate a first voltage VIN_CP based on the input reference voltage VREF, VIN_CP=(VREF*Rfb3) / (Rfb3+Rfb4). The charge pump module raises the first voltage VIN_CP to generate a second voltage VCP under the action of the charge pump module and the first clock CLKP and the second clock CLKN. In theory, the second voltage VCP at the output end of the charge pump=VIN_CP+Vosc, but since the actual charge pump will be loaded, the voltage will drop. The feedback network module samples the second voltage VCP output by the charge pump module to form a feedback voltage connected to the inverting input terminal of the operational amplifier OP2. By comparing the voltage difference between the feedback voltage value and the reference voltage value, a third voltage Vc is generated and sent to the voltage-controlled current source module for controlling the reference current of the current source module. The voltage-controlled current source makes the voltage of the node 141 equal to the voltage of the third voltage Vc under the action of the negative feedback network composed of the operational amplifier OP3 and the NMOS tube NM3. Under the action of the pull-down resistor Rs and the like, a bias current Ibias is formed. The bias current Ibias forms a bias voltage Vbias on the PMOS tube PM3 to provide a bias voltage for the current mirror of the OSC module. The clock module receives the bias voltage Vbias generated by the voltage-controlled current source and generates a complementary first clock CLKP and a second clock CLKN. The period of the first clock CLKP and the second clock CLKN is the loop delay.

[0025] like Figure 2 As shown, the LDO module includes an operational amplifier OP1, a feedback resistor Rfb3 and a feedback resistor Rfb4, the non-inverting input terminal of the operational amplifier OP1 serves as the input terminal of the LDO module and is connected to the reference voltage VREF, the inverting input terminal of the operational amplifier OP1 is connected to one end of the feedback resistor Rfb3 and one end of the feedback resistor Rfb4, the output terminal of the operational amplifier OP1 is connected to the other end of the feedback resistor Rfb3 and serves as the output terminal of the LDO module to output the second voltage VCP, and the other end of the feedback resistor Rfb4 is grounded.

[0026] like Figure 3As shown, the charge pump module includes an NMOS tube NM1, an NMOS tube NM2, a PMOS tube PM1, a PMOS tube PM2, a pump capacitor Cpump1 and a pump capacitor Cpump2; the source of the NMOS tube M1 is connected to the source of the NMOS tube NM2 and is connected to the first voltage VIN_CP as the input end of the charge pump module, the gate of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2, one end of the pump capacitor Cpump2, the gate of the PMOS tube PM1 and the drain of the PMOS tube PM2, the drain of the NMOS tube NM1 is connected to the gate of the NMOS tube NM2, one end of the pump capacitor Cpump1, the gate of the PMOS tube PM2 and the drain of the PMOS tube PM1, the source of the PMOS tube PM1 is connected to the source of the PMOS tube PM2 and is used as the output end of the charge pump module to generate the second voltage VCP, the other end of the pump capacitor Cpump1 is connected to the second clock CLKN, and the other end of the pump capacitor Cpump2 is connected to the first clock CLKP.

[0027] like Figure 4 As shown, the feedback network module includes a feedback resistor Rfb1, a feedback resistor Rfb2, a feedback capacitor Cfb1, a feedback capacitor Cfb2 and an operational amplifier OP2, one end of the feedback capacitor Cfb1 is connected to one end of the feedback resistor Rfb1 and is connected to the second voltage VCP as the input end of the feedback network module, the other end of the feedback capacitor Cfb1 is connected to one end of the feedback capacitor Cfb2, the other end of the feedback resistor Rfb1, one end of the feedback resistor Rfb2 and the reverse input end of the operational amplifier OP2, the other end of the feedback capacitor Cfb2 and the other end of the feedback resistor Rfb2 are grounded, the positive input end of the operational amplifier OP2 is connected to the reference voltage VREF, and the output end of the operational amplifier OP2 serves as the output end of the feedback network module and generates a third voltage Vc.

[0028] like Figure 5As shown, the voltage-controlled current source includes an operational amplifier OP3, an NMOS tube NM3, a PMOS tube PM3, a resistor Rs, resistors Rs1-Rsn and switches S1-Sn, the source of the PMOS tube PM3 is connected to the power supply VCC, the gate of the PMOS tube PM3 is connected to the drain of the PMOS tube PM3 and the drain of the NMOS tube NM3 and serves as the output end of the voltage-controlled current source to generate a bias voltage Vbias, the gate of the NMOS tube NM3 is connected to the output end of the operational amplifier OP3, the positive input end of the operational amplifier OP3 serves as the input end of the voltage-controlled current source and is connected to the third voltage Vc, the reverse input end of the operational amplifier OP3 is connected to the source of the NMOS tube NM3, one end of the resistor Rs, and one end of the switch S1-Sn, the other end of the switch S1-Sn is connected to one end of the resistor Rs1-Rsn in a one-to-one correspondence, the control end of the switch S1-Sn is connected to the control signal PROG_R, and the other end of the resistor Rs and the other end of the resistor Rs1-Rsn are grounded. The resistors Rs1 -Rsn and the switches S1 -Sn are optional and are used to adjust the actual equivalent resistance value Rs_total between the node 141 and BND.

[0029] like Figure 6As shown, the clock module includes PMOS tube PM4, PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, PMOS tube PM8, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, NMOS tube NM7, NMOS tube NM8 and capacitor Cosc, the gate of PMOS tube PM4 is connected to the gate of PMOS tube PM5 and is connected to the bias voltage Vbias as the input end of the clock module, the source of PMOS tube PM4, the source of PMOS tube PM5, the source of PMOS tube PM7 and the source of PMOS tube PM8 are connected to the charge pump clock high level Vosc, the drain of PMOS tube PM4 is connected to the drain of NMOS tube NM4, the gate of NMOS tube NM4 and the gate of NMOS tube NM5, the source of NMOS tube NM4 is connected to the gate of NMOS tube NM5, and the source of NMOS tube NM4 is connected to the gate of NMOS tube NM5. The source of the OS transistor NM5, one end of the capacitor Cosc, the source of the NMOS transistor NM7 and the source of the NMOS transistor NM8 are connected, the drain of the PMOS transistor PM5 is connected to the source of the PMOS transistor PM6, the gate of the PMOS transistor PM6 is connected to the gate of the NMOS transistor NM6, the drain of the PMOS transistor PM8 and the drain of the NMOS transistor NM8 are connected to generate the second clock CLKN, the drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM6, the other end of the capacitor Cosc, the gate of the PMOS transistor PM7 and the gate of the NMOS transistor NM7, the source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM5, the drain of the PMOS transistor PM7 is connected to the drain of the NMOS transistor NM7, the gate of the PMOS transistor PM8 and the gate of the NMOS transistor NM8 are connected to generate the first clock CLKP. The gates of PMOS tubes PM4 and PM5 are connected to the bias voltage Vbias output by the voltage-controlled current source, and the current generated by the voltage-controlled current source is copied to the clock module. NMOS tube NM4 is used to copy the current on PMOS tube PM4 to NMOS tube NM5. PMOS tube PM5, PMOS tube PM6, NMOS tube NM5, and NMOS tube NM6 form a current-limiting inverter to increase loop delay. PMOS tube PM7, NMOS tube NM7 and PMOS tube PM8, NMOS tube NM8 respectively form two-stage inverters to ensure that they can start oscillation.

[0030] Since the second and third stages use inverters, their current is large at the moment the inverter jumps, and the capacitors at the output ends of the second and third stages are only parasitic capacitors, so the corresponding delays of the second and third stages are very small. In the OSC with a lower clock frequency, the impact on the frequency of OSC is not significant. The delay of the loop is mainly determined by the current of the first-stage current mirror and the capacitance at the output end of the first stage.

[0031] When the load at the output end of the charge pump increases, the second voltage VCP output by the charge pump will decrease, which will cause the voltage of the feedback voltage Vfb in the feedback network module to decrease. The feedback voltage Vfb is the voltage at the reverse input end of the operational amplifier OP2. After the operation of the operational amplifier OP2, the third voltage Vc output by the feedback network module will increase. Under the action of the feedback loop formed by the operational amplifier OP3 and the NMOS tube NM3, the voltage of the node 141 will increase, which will increase the bias current Ibias generated by the voltage-controlled current source. The bias voltage Vbias in the voltage-controlled current source will copy the increased voltage to the clock module, thereby increasing the frequency of the clock and allowing the charge pump to pump more charge into the load end per unit time, thereby increasing the second voltage VCP output by the charge pump, thereby improving the driving capability of the charge pump.

[0032] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A clock modulated charge pump circuit, characterized in that: It comprises a reference voltage module, an LDO module, a charge pump module, a feedback network module, a voltage-controlled current source and a clock module, wherein the reference voltage module is used to provide an accurate reference voltage VREF, the LDO module generates a first voltage VIN_CP based on the input reference voltage VREF, the charge pump module generates a second voltage VCP based on the first voltage VIN_CP, a first clock CLKP and a second clock CLKN, the feedback network module generates a third voltage Vc based on the second voltage VCP, the voltage-controlled current source generates a bias voltage Vbias based on the third voltage Vc, and the clock module generates a complementary first clock CLKP and a second clock CLKN based on the bias voltage Vbias; The voltage-controlled current source comprises an operational amplifier OP3, an NMOS tube NM3, a PMOS tube PM3 and a resistor Rs, the source of the PMOS tube PM3 is connected to a power supply VCC, the gate of the PMOS tube PM3 is connected to the drain of the PMOS tube PM3 and the drain of the NMOS tube NM3 and serves as an output end of the voltage-controlled current source to generate a bias voltage Vbias, the gate of the NMOS tube NM3 is connected to the output end of the operational amplifier OP3, the positive input end of the operational amplifier OP3 serves as an input end of the voltage-controlled current source and is connected to a third voltage Vc, the negative input end of the operational amplifier OP3 is connected to the source of the NMOS tube NM3 and one end of the resistor Rs, and the other end of the resistor Rs is grounded; The clock module comprises a PMOS tube PM4, a PMOS tube PM5, a PMOS tube PM6, a PMOS tube PM7, a PMOS tube PM8, an NMOS tube NM4, an NMOS tube NM5, an NMOS tube NM6, an NMOS tube NM7, an NMOS tube NM8 and a capacitor Cosc, a gate of the PMOS tube PM4 is connected to a gate of the PMOS tube PM5 and is connected to a bias voltage Vbias as an input end of the clock module, a source of the PMOS tube PM4, a source of the PMOS tube PM5, a source of the PMOS tube PM7 and a source of the PMOS tube PM8 are connected to a power supply VCC, a drain of the PMOS tube PM4 is connected to a drain of the NMOS tube NM4, a gate of the NMOS tube NM4 and a gate of the NMOS tube NM5, a source of the NMOS tube NM4 is connected to a gate of the NMOS tube NM5, and a source of the NMOS tube NM5 is connected to a gate of the NMOS tube NM6. The source of NMOS tube M5, one end of capacitor Cosc, the source of NMOS tube NM7 and the source of NMOS tube NM8 are connected, the drain of PMOS tube PM5 is connected to the source of PMOS tube PM6, the gate of PMOS tube PM6 is connected to the gate of NMOS tube NM6, the drain of PMOS tube PM8 and the drain of NMOS tube NM8 are connected to generate the second clock CLKN, the drain of PMOS tube PM6 is connected to the drain of NMOS tube NM6, the other end of capacitor Cosc, the gate of PMOS tube PM7 and the gate of NMOS tube NM7, the source of NMOS tube NM6 is connected to the drain of NMOS tube NM5, the drain of PMOS tube PM7 is connected to the drain of NMOS tube NM7, the gate of PMOS tube PM8 and the gate of NMOS tube NM8 are connected to generate the first clock CLKP.

2. The clock modulated charge pump circuit according to claim 1, characterized in that: The LDO module includes an operational amplifier OP1, a feedback resistor Rfb3 and a feedback resistor Rfb4, the non-inverting input terminal of the operational amplifier OP1 serves as the input terminal of the LDO module and is connected to the reference voltage VREF, the inverting input terminal of the operational amplifier OP1 is connected to one end of the feedback resistor Rfb3 and one end of the feedback resistor Rfb4, the output terminal of the operational amplifier OP1 is connected to the other end of the feedback resistor Rfb3 and serves as the output terminal of the LDO module to output the first voltage VIN_CP, and the other end of the feedback resistor Rfb4 is grounded.

3. The clock-modulated charge pump circuit according to claim 1, characterized in that: The charge pump module includes an NMOS tube NM1, an NMOS tube NM2, a PMOS tube PM1, a PMOS tube PM2, a pump capacitor Cpump1 and a pump capacitor Cpump2; the source of the NMOS tube M1 is connected to the source of the NMOS tube NM2 and is connected to the first voltage VIN_CP as the input end of the charge pump module, the gate of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2, one end of the pump capacitor Cpump2, the gate of the PMOS tube PM1 and the drain of the PMOS tube PM2, the drain of the NMOS tube NM1 is connected to the gate of the NMOS tube NM2, one end of the pump capacitor Cpump1, the gate of the PMOS tube PM2 and the drain of the PMOS tube PM1, the source of the PMOS tube PM1 is connected to the source of the PMOS tube PM2 and is connected to the output end of the charge pump module to generate a second voltage VCP, the other end of the pump capacitor Cpump1 is connected to the second clock CLKN, and the other end of the pump capacitor Cpump2 is connected to the first clock CLKP.

4. The clock-modulated charge pump circuit according to claim 1, characterized in that: The feedback network module includes a feedback resistor Rfb1, a feedback resistor Rfb2, a feedback capacitor Cfb1, a feedback capacitor Cfb2 and an operational amplifier OP2, one end of the feedback capacitor Cfb1 is connected to one end of the feedback resistor Rfb1 and is connected to the second voltage VCP as the input end of the feedback network module, the other end of the feedback capacitor Cfb1 is connected to one end of the feedback capacitor Cfb2, the other end of the feedback resistor Rfb1, one end of the feedback resistor Rfb2 and the reverse input end of the operational amplifier OP2, the other end of the feedback capacitor Cfb2 and the other end of the feedback resistor Rfb2 are grounded, the positive input end of the operational amplifier OP2 is connected to the reference voltage VREF, and the output end of the operational amplifier OP2 serves as the output end of the feedback network module and generates a third voltage Vc.

5. The clock-modulated charge pump circuit according to claim 1, characterized in that: The voltage-controlled current source further includes resistors Rs1-Rsn and switches S1-Sn, the inverting input end of the operational amplifier OP3 is connected to one end of the switch S1-Sn, the other end of the switch S1-Sn is connected to one end of the resistor Rs1-Rsn in a one-to-one correspondence, the control end of the switch S1-Sn is connected to the control signal PROG_R, and the other end of the resistor Rs1-Rsn is grounded.

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