Buck circuit for improving receiving current tolerance

Abstract

The invention belongs to the field of Buck circuits, and provides a Buck circuit for improving receiving current tolerance, and the Buck circuit comprises a summation amplifier which is used for adding the voltages of a feedback signal, a fixed power supply signal, a first triangular wave signal and a second triangular wave signal to obtain a sum signal; the positive phase input end of the comparator is connected with the sum signal, and the negative phase input end of the comparator is connected with a voltage loop compensation signal; the R end of the SR trigger is connected with the output end of the comparator, and the S end of the SR trigger is connected with a clock signal; the output end of the converter outputs Buck voltage; a voltage dividing unit; the operational amplifier outputs a voltage loop compensation signal; the slope compensator outputs a first triangular wave signal; the input end of the slope generator is connected with the Buck voltage, the output end of the slope generator outputs a second triangular wave signal, and the voltage slope of the second triangular wave signal is reversely correlated with the Buck voltage; according to the invention, the problems of overlarge ripple, unstable switching frequency and the like caused by overlarge output receiving current of the circuit in the prior art can be solved.

Description

Technical Field

[0001] The present invention relates to the field of Buck circuits, and in particular to a Buck circuit capable of improving receiving current tolerance. Background Art

[0002] The Current Mode Buck circuit is a control method for a DC-DC converter, which uses the current in the inductor as a control signal to adjust the output voltage. The Current Mode Buck circuit usually includes a converter, which is composed of a buffer, a PMOS PMOS tube MP, and an NMOS lower tube. In this Current Mode Buck circuit, if the output receiving current of the circuit is too large, the voltage of the voltage loop compensation signal drops too much, which will cause the PMOS PMOS tube MP of the buffer to fail to turn on normally and be in an unstable state, resulting in problems such as excessive output ripple and unstable switching frequency. Summary of the invention

[0003] In view of the above technical problems, the present invention provides a Buck circuit with improved receiving current tolerance to solve the problems in the prior art where the output receiving current of the circuit is too large, resulting in excessive ripple, unstable switching frequency, etc.

[0004] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0005] The present invention discloses a Buck circuit for improving receiving current tolerance, the circuit comprising:

[0006] A summing amplifier, the summing amplifier is used to add the voltages of the feedback signal, the fixed power supply signal, the first triangular wave signal, and the second triangular wave signal to obtain a sum signal;

[0007] A comparator, wherein a non-phase input terminal of the comparator is connected to the sum signal, and an inverting input terminal of the comparator is connected to the voltage loop compensation signal;

[0008] An SR trigger, wherein an R terminal of the SR trigger is connected to the output terminal of the comparator, and an S terminal of the SR trigger is connected to a clock signal;

[0009] A converter, the converter comprising a buffer, a PMOS tube, and an NMOS tube, an input end of which is connected to the Q end of the SR trigger, and an output end of which outputs a Buck voltage;

[0010] A voltage dividing unit, connected to the output end of the converter, for dividing the Buck voltage;

[0011] An operational amplifier, wherein the inverting input terminal of the operational amplifier is connected to the output terminal of the voltage divider unit, the non-inverting input terminal of the operational amplifier is connected to the reference signal, and the output terminal of the operational amplifier outputs the voltage loop compensation signal;

[0012] an inductor, wherein the inductor is arranged between the converter and the voltage dividing unit;

[0013] A capacitor, one end of which is connected between the inductor and the voltage dividing unit, and the other end of which is grounded;

[0014] A slope compensator, wherein an input terminal of the slope compensator is connected to a Q terminal of the SR trigger, and an output terminal of the slope compensator outputs the first triangular wave signal;

[0015] A slope generator, wherein an input terminal of the slope generator is connected to the Buck voltage, and an output terminal thereof outputs the second triangular wave signal, wherein a voltage slope of the second triangular wave signal is inversely correlated with a magnitude of the Buck voltage.

[0016] Furthermore, a radio frequency circuit is provided between the summing amplifier and the output end of the converter.

[0017] The technical solution disclosed in this disclosure has the following beneficial effects:

[0018] A second triangle wave signal with a slope adjusted with the Buck voltage is added to the voltage of the sum signal to increase the voltage of the voltage loop compensation signal and increase the tolerance of the Buck voltage when receiving current;

[0019] The voltage slope of the second triangular wave signal is inversely correlated with the size of the Buck voltage. When the Buck voltage is higher, the voltage slope of the added second triangular wave signal is slower, so as to avoid the voltage of the voltage loop compensation signal from rising too much and reaching the Buck voltage, thereby avoiding causing an abnormal Buck state. When the Buck voltage is lower, the voltage slope of the added second triangular wave signal is faster, so as to increase the voltage rise amplitude of the voltage loop compensation signal, thereby avoiding the problem that the Buck voltage receiving current tolerance is not significantly improved due to the short opening time of the PMOSPMOS tube MP and the insufficient voltage rise of the voltage loop compensation signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of a Buck circuit for improving receiving current tolerance in an embodiment of this specification;

[0021] Figure 2 Schematic diagram of voltages at various nodes when the Buck circuit in the embodiment of this specification is not provided with a slope generator;

[0022] Figure 3 The Buck voltage in the embodiment of this specification is Figure 2Schematic diagram of voltage at each node when multiple currents are drawn;

[0023] Figure 4 A schematic diagram of voltages of various nodes when the Buck voltage of the Buck circuit without a slope generator in the embodiment of this specification receives current;

[0024] Figure 5 A schematic diagram of voltages at each node when the Buck voltage of the Buck circuit in the embodiment of this specification receives current;

[0025] Figure 6 Schematic diagram of voltages at various nodes of the Buck circuit at different duty cycles in the embodiment of this specification;

[0026] Figure 7 The Buck circuit in the embodiment of this specification uses the Buck voltage to adjust the slope of the second triangular wave signal and the voltage of each node at different duty cycles;

[0027] Figure 8 is a circuit schematic diagram of a slope generator in an embodiment of this specification. DETAILED DESCRIPTION

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0029] like Figure 1-8As shown, the embodiment of the present specification provides a Buck circuit for improving the receiving current tolerance, and the circuit includes: a summing amplifier 1, the summing amplifier is used to add the voltages of the feedback signal VS, the fixed power supply signal VDC, the first triangular wave signal VM, and the second triangular wave signal VM2 to obtain a sum signal VSUM; a comparator CMP, the non-phase input terminal of the comparator CMP is connected to the sum signal VSUM, and the inverting input terminal thereof is connected to the voltage loop compensation signal VCOMP; an SR trigger 2, the R terminal of the SR trigger 2 is connected to the output terminal of the comparator CMP, and the S terminal thereof is connected to the clock signal CLK; a converter 3, the converter 3 includes a buffer MOS Buffer, PMOS tube MP, NMOS tube MN, whose input end is connected to the Q end of the SR trigger 2, and whose output end outputs the Buck voltage; a voltage divider unit 4, the voltage divider unit 4 is connected to the output end of the converter 3, and is used to divide the Buck voltage; an operational amplifier OP, the inverting input end of the operational amplifier OP is connected to the output end of the voltage divider unit, the non-inverting input end of the operational amplifier OP is connected to the reference signal VREF, and the output end outputs the voltage loop compensation signal VCOMP; an inductor L, the inductor L is arranged between the converter 3 and the voltage divider unit 4; one end of the capacitor C1 is connected between the inductor L and the voltage divider unit 4, and the other end of the capacitor C1 is grounded; a slope compensator 5, the input end of the slope compensator 5 is connected to the Q end of the SR trigger 2, and the output end outputs the first triangular wave signal VM; a slope generator 6, the input end of the slope generator 6 is connected to the Buck voltage, and the output end outputs the second triangular wave signal VM2, and the voltage slope of the second triangular wave signal VM2 is inversely correlated with the size of the Buck voltage.

[0030] A radio frequency circuit RF is provided between the summing amplifier 1 and the output end of the converter 3 .

[0031] Specifically, Figure 1 As shown, VO is the Buck voltage, which is divided by the resistors RF1 and RF2 of the voltage divider unit 4 to obtain the VFB voltage. In a stable working state, the VFB voltage is locked at the reference signal VREF through the action of the operational amplifier OP. The operational amplifier OP outputs a voltage loop compensation signal VCOMP, which is connected to the positive terminal of the comparator CMP and compared with the voltage of the sum signal VSUM.

[0032] The sum signal VSUM is the sum of the four voltages of the feedback signal VS, the fixed power signal VDC, the first triangular wave signal VM, and the second triangular wave signal VM2. The feedback signal VS is the voltage after the current IS of the inductor L is converted by the radio frequency circuit RF when the PMOS tube MP is turned on. The relationship between the feedback signal VS and the current IS of the inductor L can be expressed as follows:

[0033] VS = IS * RF;

[0034] The fixed power supply signal VDC is a constant voltage source, which is used to adjust the voltage of the sum signal VSUM. The first triangular wave signal VM is generated by a triangular wave voltage source for slope compensation, that is, generated by the slope compensator 5, which is an existing compensation mechanism added to improve the stability and dynamic response of the control loop. For example, since the rising and falling slopes of the inductor current will cause a delay in the control signal, if compensation is not performed, when the duty cycle exceeds 50%, the circuit may become unstable or even cause subharmonic oscillation.

[0035] It is assumed below that the slope generator 6 is not set, that is, there is no second triangular wave signal VM2. Figure 2 The voltage diagram of each node is shown in the figure, and its detailed operation is as follows:

[0036] a. When CLK rises (or falls and then reverses), the SR trigger output Q will be pulled high, turning on the PMOS tube MP, IS = IL, VS = IS * RF, and the first triangle wave signal VM starts to climb from 0V;

[0037] b. When the sum signal VSUM slowly rises until VSUM=VCOMP, the comparator CMP outputs a high level, and the output Q end of the SR trigger is a low level. At this time, the PMOS tube MP is turned off, the feedback signal VS and the first triangular wave signal VM are discharged to 0V, and the sum signal VSUM returns to the voltage of the fixed power supply signal VDC;

[0038] c. When the Buck circuit is in a stable state, VCOMP = VDC + VSH + VMH, where VSH = ILH * RF.

[0039] When the BUCK circuit outputs VO to provide current, the current IL of the inductor L will increase, thereby increasing the maximum voltage of the feedback signal VS and the sum signal VSUM, and the voltage loop compensation signal VCOMP will also increase. Figure 3 As shown, VO is Figure 2 Schematic diagram of the voltage of each node when more current is drawn. The voltages of VS, VSUM and VCOMP will rise by VSL, VSL=ΔIO*RF.

[0040] When the BUCK circuit outputs VO to receive current, the inductor current IL will decrease, which will cause the maximum values ​​of the feedback signal VS and the sum signal VSUM to decrease, and the VCOMP value will also decrease. Figure 4 Schematic diagram of the voltage at each node when VO receives current.

[0041] If the current received by the BUCK circuit output VO increases further, the VCOMP value will further decrease. If the VCOMP value drops below the fixed power signal VDC, because VSUM=VDC when the high side is closed, VSUM>VCOMP will be caused, making the R input of the SR trigger always high, the SR trigger is always in the reset state, and the output Q cannot be pulled high. If the Q of the SR trigger is always low, the PMOS tube MP of the buffer will not turn on, which will cause the Buck circuit to be in an unstable state, the output ripple will become larger, and the switching frequency will also be unstable.

[0042] Therefore, the second triangle wave signal VM2 is provided in the present embodiment, that is, a triangle wave voltage whose slope varies with VO is added. The second triangle wave signal VM2 can further increase the VSUM voltage, and also increase the VCOMP voltage, so that the VCOMP voltage is far away from the VDC voltage, so that the output can withstand a larger input current. Figure 5 This is a schematic diagram of the voltages of each node when current is poured into VO after VM2 is added, where VCOMP is raised by VM2H.

[0043] Since the turn-on time of the PMOS tube MP of the Buck circuit is related to the ratio of VIN and VO, the turn-on time of the PMOS tube MP can be expressed as: Td = VO / VIN.

[0044] When VIN is fixed and VO is higher, the PMOS tube MP is turned on for a longer time Td, and the voltage provided by the second triangle wave signal VM2 in VSUM will be higher. When VO is lower, the Td time is shorter, and the voltage provided by the second triangle wave signal VM2 will be lower. If the second triangle wave signal VM2 uses a triangle wave voltage with a fixed slope, when Td is longer, the VCOMP rise caused by the second triangle wave signal VM2 may be too much, causing the VCOMP value to reach VIN, resulting in an abnormal state of the Buck circuit. When Td is shorter, the VCOMP rise caused by the second triangle wave signal VM2 may be too little, resulting in the inability to improve the ability of the Buck circuit to output and absorb current. Figure 6 Schematic diagram of the voltage at each node of the circuit for different duty cycles.

[0045] This embodiment uses the method of detecting the VO voltage to adjust the slope of VM2 to improve the output absorption current of the Buck circuit. When VO is higher, because Td is longer, the slope of the second triangle wave signal VM2 is smaller, so that VCOMP does not rise too much. When VO is low, because Td is shorter, the slope of the second triangle wave signal VM2 is larger, so that VCOMP can rise to a sufficient height, thereby improving the output absorption current capability. Figure 7Schematic diagram of the voltages at each node of the circuit at different duty cycles Duty in order to use the VO voltage to adjust the slope of the second triangular wave signal VM2.

[0046] In another embodiment, if Figure 8 As shown in the figure, it is a way to detect the VO voltage and adjust the VM2 slope, that is, the circuit principle of the slope generator. Among them, the current I=(VIN–VO) / R, and the VM2 rising slope can be expressed as:

[0047] Slope_VM2=M*N*I / C=M*N*(VIN-VO) / (R*C);

[0048] It can be seen from the above formula that when VO is larger, the slope of Slope_VM2 is smaller, and when VO is smaller, the slope of Slope_VM2 is larger.

[0049] certainly, Figure 8 The circuit shown is only one method of realizing the adjustment of VM2 slope by detecting VO voltage. Any other method of adjusting VM2 slope by detecting VO voltage to raise VSUM and VCOMP voltages is protected by the present invention.

[0050] Beneficial effects:

[0051] The present invention adds a second triangular wave signal whose slope is adjusted with the Buck voltage at the voltage of the sum signal, thereby increasing the voltage of the voltage loop compensation signal and increasing the tolerance of the Buck voltage when receiving current;

[0052] The voltage slope of the second triangular wave signal is inversely correlated with the size of the Buck voltage. When the Buck voltage is higher, the voltage slope of the added second triangular wave signal is slower, so as to avoid the voltage of the voltage loop compensation signal from rising too much and reaching the Buck voltage, thereby avoiding causing an abnormal Buck state. When the Buck voltage is lower, the voltage slope of the added second triangular wave signal is faster, so as to increase the voltage rise amplitude of the voltage loop compensation signal, thereby avoiding the problem that the Buck voltage receiving current tolerance is not significantly improved due to the short opening time of the PMOSPMOS tube MP and the insufficient voltage rise of the voltage loop compensation signal.

[0053] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A Buck circuit for improving receiving current tolerance, characterized in that: The circuit is a current mode buck circuit, and the circuit comprises: A summing amplifier, the summing amplifier is used to add the voltages of the feedback signal, the fixed power supply signal, the first triangular wave signal, and the second triangular wave signal to obtain a sum signal; A comparator, wherein a non-phase input terminal of the comparator is connected to the sum signal, and an inverting input terminal of the comparator is connected to the voltage loop compensation signal; An SR trigger, wherein an R terminal of the SR trigger is connected to the output terminal of the comparator, and an S terminal of the SR trigger is connected to a clock signal; A converter, the converter comprising a buffer, a PMOS tube, and an NMOS tube, an input end of which is connected to the Q end of the SR trigger, and an output end of which outputs a Buck voltage; A voltage dividing unit, connected to the output end of the converter, for dividing the Buck voltage; An operational amplifier, wherein the inverting input terminal of the operational amplifier is connected to the output terminal of the voltage divider unit, the non-inverting input terminal of the operational amplifier is connected to the reference signal, and the output terminal of the operational amplifier outputs the voltage loop compensation signal; an inductor, wherein the inductor is arranged between the converter and the voltage dividing unit; A slope compensator, wherein an input terminal of the slope compensator is connected to a Q terminal of the SR trigger, and an output terminal of the slope compensator outputs the first triangular wave signal; A slope generator, wherein an input terminal of the slope generator is connected to the Buck voltage, and an output terminal of the slope generator outputs the second triangular wave signal, and a voltage slope of the second triangular wave signal is inversely correlated with a magnitude of the Buck voltage; A capacitor, one end of the capacitor is connected between the inductor and the voltage dividing unit, and the other end of the capacitor is grounded.

2. A Buck circuit for improving receiving current tolerance according to claim 1, characterized in that: A radio frequency circuit is arranged between the summing amplifier and the output end of the converter.

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