Semiconductor device for switching power supply and switching power supply device

Abstract

The invention provides a semiconductor device for a switching power supply and a switching power supply device. A semiconductor device for a switching power supply, which generates a drive signal for controlling the ON / OFF of a switching element connected in series to a primary winding of a transformer, is provided with: a resonance monitoring circuit for monitoring the resonance state of a secondary winding; a timer circuit that generates a period signal imparting a minimum switching period; a circuit that generates a turn-on signal based on the periodic signal and a signal from the resonance monitoring circuit; a cut-off circuit that detects that the current flowing through the switching element reaches a predetermined current value and outputs a cut-off signal; a circuit that generates an ON / OFF control signal on the basis of the output of the ON circuit and the OFF circuit; and a circuit for generating a first dither signal for imparting a fluctuation to the interval of the periodic signal and a second dither signal for imparting a fluctuation to the current value, wherein the first dither signal and the second dither signal have a predetermined phase difference.

Description

Technical Field

[0001] The present invention relates to a semiconductor device for a switching power supply (power supply control IC) and a switching power supply device, and in particular to a power supply control IC for controlling a switching element on the primary side of a DC power supply device having a voltage conversion transformer and a switching power supply device using the power supply control IC. Background Art

[0002] In the DC power supply device, there is an isolated switching power supply device composed of a diode bridge circuit for rectifying an AC power supply and a DC-DC converter for converting the DC voltage rectified by the circuit into a desired DC voltage. As an isolated switching power supply device, for example, the following switching power supply device is known: a switching element connected in series with the primary winding of a voltage conversion transformer is turned on and off by a PWM (pulse width modulation) control method or a quasi-resonance control method to control the current flowing through the primary winding, thereby controlling the voltage induced in the secondary winding.

[0003] PWM control and quasi-resonant control have advantages and disadvantages respectively. For example, although PWM control has the disadvantages of switching loss, large conduction noise, and slightly poor power efficiency, it has the advantage of being able to reduce the size of the transformer due to low noise and the ability to operate even in the current continuous mode, which can suppress the current peak of the transformer. On the other hand, quasi-resonant control has noise caused by valley jumping, and only operates in the current discontinuous mode, so there is a disadvantage that the size of components such as the transformer and output capacitor becomes larger, but soft switching (soft conduction) is performed at the valley of the zero current resonant voltage when it is turned on, so it has the advantages of low switching loss, low conduction noise, and good power efficiency.

[0004] Conventional isolated switching power supply devices that adopt a quasi-resonant control method are generally configured to operate only under quasi-resonant control (for example, Patent Document 1).

[0005] In order to take advantage of both advantages, the applicant has proposed an isolated switching power supply device that switches between PWM control and quasi-resonant control based on a feedback voltage from a secondary-side output voltage, and has previously filed patent applications (Patent Documents 2 and 3).

[0006] In addition, the invention of Patent Document 3 is made to solve the problem in the invention of Patent Document 2. Here, the problem in the invention of Patent Document 2 is that when applied to a power supply device having a function of switching the output voltage, when the output voltage is switched to a low voltage, the switching cycle changes greatly, thereby increasing the fluctuation of the output voltage or generating a sound.

[0007] Furthermore, the present applicant has developed a technique for adding jitter to a periodic pulse signal providing a switching cycle in order to reduce the peak of the spectrum of the conduction noise in the switching power supply device to which the invention of Patent Document 3 is applied.

[0008] However, when jitter is added to the periodic pulse signal providing the switching cycle, a sufficient effect of reducing the peak of the spectrum of the conducted noise can be obtained during PWM operation, but during quasi-resonant operation, such as Fig.14 As shown in (A), the switching cycles are concentrated on a specific cycle. Therefore, it is clear that there is a problem that the effect of reducing the peak of the spectrum of the conduction noise cannot be obtained or the reduction effect is quite limited.

[0009] Patent Document 1: Japanese Patent Application Publication No. 2014-124038

[0010] Patent Document 2: Japanese Patent Application Publication No. 2020-58196

[0011] Patent Document 3: Japanese Patent Application Publication No. 2021-103931 Summary of the invention

[0012] The present invention has been made with focus on the above-mentioned problems, and its object is to reduce the peak of the spectrum of the conducted noise in both the PWM operation and the quasi-resonant operation in an isolated switching power supply device that switches between PWM control and quasi-resonant control in normal operation.

[0013] Another object of the present invention is to provide a switching power supply semiconductor device and a switching power supply device capable of suppressing conducted noise emitted during execution of either PWM control or quasi-resonance control.

[0014] To achieve the above object, the present invention is a semiconductor device for a switching power supply, which generates a drive signal for controlling on and off a switching element connected in series with a primary winding of a voltage conversion transformer having an auxiliary winding.

[0015] The semiconductor device for a switching power supply comprises:

[0016] a resonance monitoring circuit that monitors a resonance state of the secondary winding of the transformer according to a voltage of the auxiliary winding;

[0017] a timer circuit that generates a periodic signal that specifies a switching period of the switching element;

[0018] a conduction circuit that outputs a conduction signal for turning on the switch element based on the periodic signal and the signal from the resonance monitoring circuit;

[0019] a cut-off circuit that detects when the current flowing through the switching element reaches a predetermined current value and outputs a cut-off signal for turning off the switching element; and

[0020] a jitter generating circuit, which generates a first jitter signal and a second jitter signal, wherein the first jitter signal is used to apply fluctuations to the interval of the periodic signal, and the second jitter signal is used to apply fluctuations to the predetermined current value of the cutoff signal output by the cutoff circuit,

[0021] The first jitter signal and the second jitter signal have a predetermined phase difference.

[0022] According to the above-mentioned structure, fluctuations can be given to the periodic signal that gives the minimum switching period, and fluctuations can be given to the turn-on timing of the switching element, so the peak of the spectrum of the conducted noise can be reduced. As a result, in a switching power supply device that can switch between PWM control and quasi-resonant control, the conducted noise emitted from the power supply device can be suppressed during either PWM operation or quasi-resonant operation.

[0023] According to the present invention, in an isolated switching power supply device that switches between PWM control and quasi-resonant control in normal operation, the peak of the spectrum of conducted noise can be reduced in both PWM operation and quasi-resonant operation, thereby achieving an effect of suppressing conducted noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a circuit configuration diagram showing one embodiment of a DC-DC converter as a DC power supply device that is effective to which the semiconductor device for a switching power supply of the present invention is applied.

[0025] Figure 2 It means in Figure 1 A functional block diagram of an embodiment of a semiconductor device for a switching power supply of the present invention provided on the primary side of a transformer in a DC-DC converter.

[0026] Figure 3 (A) is a circuit configuration diagram showing a specific example of a resonance start detection circuit constituting a semiconductor device for a switching power supply of an embodiment, and (B) is a circuit configuration diagram showing a specific example of a resonance phase detection circuit.

[0027] Figure 4 It is a circuit configuration diagram showing a specific example of a conduction circuit constituting the semiconductor device for a switching power supply of the embodiment.

[0028] Figure 5 It is a circuit configuration diagram showing a specific example of a minimum cycle timer circuit constituting a semiconductor device for a switching power supply according to an embodiment.

[0029] Figure 6(A) is a circuit structure diagram showing a specific example of a jitter circuit of a semiconductor device for a switching power supply constituting an embodiment, (B) is a circuit structure diagram showing a specific example of a data generation circuit constituting the jitter circuit, and (C) is a circuit structure diagram showing a specific example of a jitter conversion circuit constituting the jitter circuit.

[0030] Figure 7 It is a circuit configuration diagram showing a specific example of a cutoff circuit (current detection circuit) constituting the semiconductor device for a switching power supply of the embodiment.

[0031] Figure 8 (A) is a graph showing the relationship between the voltage of the FB terminal in the semiconductor device for the switching power supply of the embodiment and the timing time of the minimum cycle timer circuit, and (B) is a graph showing the relationship between the voltage of the FB terminal and the reference voltage which is the threshold value of Vcs of the cut-off circuit (current detection circuit).

[0032] Fig. 9 (A) is a timing diagram showing the changes in the intervals of the period jitter signal and the minimum period signal in the semiconductor device for the switching power supply of the embodiment, and (B) is a timing diagram showing the changes in the current jitter signal and the reference voltage of the cutoff circuit (current detection circuit).

[0033] Fig.10 This is a timing chart showing changes in signals of various components when a power supply control IC that generates only a periodic jitter signal using a jitter circuit operates in a PWM mode.

[0034] Fig.11 This is a timing chart showing signal changes in various parts when a power supply control IC that generates a period jitter signal and a current jitter signal using a jitter circuit operates in a PWM mode.

[0035] Fig.12 This is a timing chart showing changes in signals of various components when a power supply control IC that generates only a periodic jitter signal using a jitter circuit operates in a quasi-resonance mode.

[0036] Fig.13 This is a timing chart showing signal changes in various parts when a power supply control IC that generates a period jitter signal and a current jitter signal using a jitter circuit operates in a quasi-resonance mode.

[0037] Fig.14 (A) is a graph showing the variation of the switching period in a switching power supply device using a power supply control IC that provides only period jitter, and (B) is a graph showing the variation of the switching period in a switching power supply device using a power supply control IC that provides both period jitter and current jitter.

[0038] Fig.15This is a graph showing the spectral distribution of noise in a switching power supply device using the power supply control IC of the embodiment, with the vertical axis representing noise intensity and the horizontal axis representing frequency.

[0039] Fig.16 This is a graph showing the relationship between the phase difference between the period jitter and the current jitter and the spectrum peak in the switching power supply device using the power supply control IC of the embodiment. DETAILED DESCRIPTION

[0040] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0041] Figure 1 This is a circuit configuration diagram showing one embodiment of an isolated DC-DC converter as a DC power supply device to which the power supply control semiconductor device of the present invention is applied.

[0042] The insulated DC-DC converter of this embodiment has: a pair of voltage input terminals 11 for inputting a DC voltage; a transformer 12 for voltage conversion having a primary winding Np, a secondary winding Ns, and an auxiliary winding Nb; a switching transistor SW1 connected in series with the primary winding Np of the transformer 12; and a switching power supply semiconductor device (hereinafter referred to as a power supply control IC) 13 for turning on and off the switching transistor SW1. When constituting a switching power supply device (AC-DC converter), a diode bridge circuit and a smoothing capacitor for rectifying an AC voltage from an AC power supply are connected to the front stage of the input terminal 11.

[0043] In the present embodiment, the switching transistor SW1 is formed of an N-channel MOSFET (insulated gate field effect transistor) as a discrete component. The power supply control IC 13 is provided with an output terminal GATE of a gate drive signal for driving the gate of the transistor SW1.

[0044] In addition, in the DC-DC converter of the present embodiment, a rectifying and smoothing circuit is provided on the primary side of the transformer 12. The rectifying and smoothing circuit is composed of a rectifying diode D1 connected in series with the auxiliary winding Nb and a smoothing capacitor C1 connected between the cathode terminal of the diode D1 and the ground point GND, and the voltage rectified and smoothed by the rectifying and smoothing circuit is applied to the power supply voltage terminal VDD of the power supply control IC 13. In addition, the power supply control IC 13 is provided with an external terminal DMG, to which a voltage VDMG obtained by dividing the voltage induced by the auxiliary winding Nb by the resistors R1 and R2 is applied.

[0045] The power supply control IC 13 is provided with an external terminal FB connected to a phototransistor (light receiving element) PT that constitutes a photocoupler for transmitting an output detection signal on the secondary side to the primary side as a feedback voltage VFB.

[0046] The power supply control IC 13 is provided with an external terminal CS as a current detection terminal, to which a voltage Vcs converted from a current to a voltage by a current detection resistor Rs connected between a source terminal of the switching transistor SW1 and a ground point GND is input.

[0047] On the other hand, a rectifying diode D2 connected in series with the secondary winding Ns and a smoothing capacitor C2 connected between the cathode terminal of the diode D2 and the other terminal of the secondary winding Ns are provided on the secondary side of the transformer 12. The AC voltage induced in the secondary winding Ns by intermittently flowing current in the primary winding Np is rectified and smoothed, thereby generating and outputting a DC voltage Vout. The primary winding Np of the transformer 12 has opposite polarities to the secondary winding Ns, and is a flyback converter.

[0048] Moreover, a constant voltage control circuit (parallel regulator) 14 and a light emitting diode (light emitting element) PD are provided on the secondary side of the transformer 12, wherein the constant voltage control circuit 14 constitutes an output voltage detection circuit for detecting the output voltage Vout, and the light emitting diode PD constitutes a photocoupler for transmitting an output voltage detection signal corresponding to the detection voltage of the constant voltage control circuit 14 to the primary side.

[0049] In the light emitting diode PD, a current corresponding to the detection voltage flows through the constant voltage control circuit 14, and is transmitted to the primary side as a light signal having an intensity corresponding to the detection voltage. As a result, a current corresponding to the light intensity flows through the phototransistor PT, and is pulled up by the pull-up resistor ( Figure 2 Rp) etc. is converted into feedback voltage VFB for input.

[0050] The constant voltage control circuit 14 includes a bipolar transistor TR1 connected in series with a light emitting diode PD, resistors R3 and R4 for dividing the output voltage Vout on the secondary side, an error amplifier AMP0 for comparing the divided voltage with a reference voltage Vref0 to output a voltage corresponding to the potential difference, and a phase compensation circuit 14a, and is configured to apply the output voltage of the error amplifier AMP0 to the base terminal of the transistor TR1, so that a current corresponding to the output voltage Vout flows. In this embodiment, the higher the output voltage Vout on the secondary side, the more current flows through the light emitting diode PD, thereby the more current flows through the phototransistor PT, and the lower the voltage VFB of the external terminal FB of the power supply control IC13.

[0051] In addition, in the present embodiment, the rectifying diode D2 is used in the secondary side circuit, but a synchronous rectification method may be adopted in which the rectifying diode D2 is replaced with a switch.

[0052] Next, use Figure 2 to Figure 7 right Figure 1 The functional block structure of an embodiment of IC13 for primary-side power control in a power supply device and the function of each block are described.

[0053] The power supply control IC 13 of this embodiment is configured to be able to switch between an operation based on quasi-resonance control (hereinafter referred to as quasi-resonance mode) and an operation based on PWM control (hereinafter referred to as PWM mode). Figure 2 As shown, the power supply control IC 13 of this embodiment has: a resonance start detection circuit 31, which monitors the voltage VDMG of the external terminal DMG, detects the start of zero current resonance that starts just after the current of the secondary winding Ns of the transformer 12 becomes zero, and outputs a resonance start detection signal RSD; and a resonance phase detection circuit 32, which detects a predetermined phase of the zero current resonance and outputs a resonance phase detection signal RPD.

[0054] In addition, the power supply control IC 13 includes: a timer circuit 33, which generates a minimum cycle signal that provides a minimum switching cycle; and a conduction circuit 34, which receives the output signals of the above-mentioned resonance start detection circuit 31, the resonance phase detection circuit 32 and the timer circuit 33 as inputs, and generates a timing signal TON that turns on the switch element SW1.

[0055] The timer circuit 33 is configured to measure the time corresponding to the voltage VFB of the external terminal FB to which the feedback signal from the secondary side is input. In order to reduce the conduction noise emitted from the power supply in the PWM mode, a jitter circuit 35 is provided to give jitter to the interval of the minimum period signal generated by the timer circuit 33.

[0056] The power supply control IC 13 includes a cutoff circuit 36 ​​composed of a current detection circuit, which generates a timing signal for turning off the switch element SW1 by taking the voltage VFB of the external terminal FB and the voltage Vcs of the current detection terminal CS as inputs. The power supply control IC 13 includes a latch circuit 37 composed of an RS flip-flop or the like that takes the output signal TON of the conduction circuit 34 and the output signal TOFF of the cutoff circuit 36 ​​as inputs, and a drive circuit 38 that generates a gate drive signal for driving the switch element SW1 based on the gate control signal GCS output from the latch circuit 37 and outputs it from the external terminal GATE.

[0057] The gate control signal GCS is supplied to the timer circuit 33 as a signal for activating the timer circuit 33, and is supplied to the resonance start detection circuit 31 and the conduction circuit 34 as a signal for resetting the resonance start detection circuit 31 and the conduction circuit 34. In addition, the power supply control IC 13 is provided with an internal power supply circuit 39 composed of a voltage regulator such as a series regulator for supplying an operating voltage to each of the functional circuits.

[0058] Furthermore, in the power supply control IC 13 of the present embodiment, the jitter circuit 35 is provided with a function of generating a current jitter signal JTi for jittering the peak current of the switch element SW1 determined by the cutoff signal by changing the input voltage of the cutoff circuit 36. The current jitter signal JTi generated by the jitter circuit 35 is input to the cutoff circuit 36.

[0059] Next, specific examples and operations of the above-mentioned functional blocks 31 to 36 will be described.

[0060] For example, Figure 3 As shown in (A), the resonance start detection circuit 31 in the functional blocks 31 to 36 constituting the power supply control IC 13 is composed of a comparator (voltage comparison circuit) CMP1 and a D-type flip-flop FF1, wherein the comparator CMP1 compares the voltage VDMG of the external terminal DMG with a predetermined reference voltage VDMGREF1, and when VDMG is lower than VDMGREF1, the output changes to a high level, and the D-type flip-flop FF1 latches the data "1" according to the output of the comparator CMP1. Then, the output of the flip-flop is supplied to the conduction circuit 34 as a resonance start detection signal RSD.

[0061] On the other hand, the resonance phase detection circuit 32 is configured to detect a predetermined phase point (for example, 180°) from the zero current resonance starting point to output a resonance phase detection signal RPD. Figure 3 As shown in (B), it can be composed of a comparator CMP2, which compares the voltage VDMG of the external terminal DMG with a predetermined reference voltage VDMGREF2, and changes the output to a high level when VDMG is lower than VDMGREF2. Here, VDMGREF1 and VDMGREF2 are set to have a relationship of VDMGREF1 ≥ VDMGREF2.

[0062] The resonance start detection circuit 31 and the resonance phase detection circuit 32 are circuits provided to detect the timing of turning on the switch element SW1 in the quasi-resonance mode. Therefore, it is also possible to configure the circuit to monitor and detect the drain voltage VD of the switch element SW1. However, the drain voltage VD of SW1 may exceed 500V depending on the specifications of the power supply device. Even if the voltage is divided, the loss and components will increase, and the zero current resonance start point ( Fig.13 The voltage at the timing t2) also depends on the input voltage. Therefore, in this embodiment, an external terminal DMG is provided and its voltage VDMG is monitored, wherein the external terminal DMG inputs a voltage obtained by dividing the voltage appearing in the auxiliary winding Nb of the transformer 12 by the resistors R1 and R2.

[0063] like Figure 4 As shown, the conduction circuit 34 includes: an AND gate G1, which receives the minimum period signal MPS from the timer circuit 33 and the detection signal RSD from the resonance start detection circuit 31 as inputs; and a D-type flip-flop FF2, whose data terminal is input with the output of the AND gate G1. In addition, the conduction circuit 34 includes: an AND gate G2, which receives the minimum period signal MPS from the timer circuit 33 and a signal obtained by inverting the detection signal RSD from the resonance start detection circuit 31 through an inverter INV1 as inputs; and an OR gate G3, which receives the output signal of the AND gate G2 and the output signal of the D-type flip-flop FF2 as inputs. The output of the OR gate G3 is output as a conduction signal TON.

[0064] The D-type flip-flop FF2 is configured to take in the output of the AND gate G1 in synchronization with the rise of the resonance phase detection signal RPD from the resonance phase detection circuit 32. The D-type flip-flop FF2 is configured to be cleared by an inverted signal of the gate control signal GCS output from the latch circuit 37 by the inverter INV2.

[0065] like Figure 5 As shown, the timer circuit 33 includes an AND gate G4, which receives as input the gate control signal GCS output from the latch circuit 37 and a signal obtained by delaying and inverting the control signal GCS through a delay circuit DLY composed of a series inverter. In addition, the AND gate 33 includes a variable current source VCS1 that flows a current corresponding to the voltage VFB of the external terminal FB, a capacitor C3 that is charged by the current from the current source VCS1, and a discharge switching transistor SW2 for discharging the charge of the capacitor C3, and the output of the AND gate G4 is applied to the gate terminal of the switching transistor SW2.

[0066] The timer circuit 33 further includes: a comparator CMP3 that compares the charging voltage of the capacitor C3 with a predetermined reference voltage Vref3; and a second variable current source VCS2 that is connected in parallel with the variable current source VCS1. The second variable current source VCS2 is configured to increase or decrease the current flowing therethrough according to the periodic jitter signal JTp from the jitter circuit 35. In addition, the timer circuit 33 may also be a digital timer circuit that performs a timing operation according to a clock signal.

[0067] exist Figure 5 In the timer circuit 33, when the gate control signal GCS changes from a low level to a high level, the output of the AND gate G4 changes to a high level in a predetermined time (delay time of the delay circuit DLY), so that the switch transistor SW2 is turned on and the charge of the capacitor C3 is discharged. In addition, when the gate control signal GCS changes to a low level and the switch transistor SW2 is turned off, the charging of the capacitor C3 begins. When a predetermined time determined by the capacitance value of the capacitor C3 and the current values ​​of the variable current sources VCS1 and VCS2 has passed, the charging voltage of the capacitor C3 reaches Vref3, and the output of the comparator CMP3 changes from a low level to a high level. As a result, a minimum period signal MPS having a period corresponding to the voltage VFB is output from the period timer circuit 33, and jitter (fluctuation) is given to the interval of the minimum period signal MPS according to the period jitter signal JTp input at this time.

[0068] The timer circuit 33 in this embodiment is set so that the higher the voltage VFB of the external terminal FB is (the larger the load on the secondary side is), the larger the current of the variable current source VCS1 is, the shorter the timing is, and the shorter the interval tMIN of the minimum period signal MPS is. Figure 8 (A) shows an example of setting the interval tMIN of the minimum period signal MPS and the voltage VFB of the FB terminal. Fig. 9 (A) shows the variation of the period jitter signal JTp and the interval tMIN of the minimum period signal MPS changed by the period jitter signal JTp.

[0069] By the way, in this embodiment, the period of the above-mentioned minimum period signal MPS is used as the switching period in the PWM mode (current continuous mode), and is also used as the detection period of the zero current resonance phase in the quasi-resonance mode (current discontinuous mode). Therefore, in the switching power supply device using the power supply control IC13 of this embodiment, the switching period is determined according to the interval of the minimum period signal MPS output from the timer circuit 33 (the timing time of the timer circuit 33), and in the PWM mode, the reciprocal of the interval of the minimum period signal MPS becomes the switching frequency. In the quasi-resonance mode, the reciprocal of (the timing time of the minimum period signal MPS + the detection delay time until the rise of the next phase detection signal) becomes the switching frequency.

[0070] Figure 6 (A) shows a specific circuit structure example of the dither circuit 35. Figure 6 As shown in (A), the jitter circuit 35 has: a data generating circuit 51, which generates first data FDT; a jitter conversion circuit 52A, which generates a periodic jitter signal JTp based on the first data FDT generated by the data generating circuit 51; an adding circuit 53, which adds a predetermined addition value (fixed value) ADT to the first data FDT to generate a second data SDT; and a jitter conversion circuit 52B, which generates a current jitter signal JTi based on the second data SDT generated by the adding circuit 53.

[0071] like Figure 6 As shown in (B), the data generation circuit 51 is composed of a counter circuit CNT formed by cascading counter flip-flops T-FF0 to T-FF3, and a clock generator CG that generates a clock signal CLK for operating the counter circuit. The counter circuit CNT performs coefficient operation according to the clock signal CLK, and repeatedly outputs an increasing (+1) value. In addition, the number of stages of the counter circuit CNT is not limited to the 4 stages shown in the figure, and can be set arbitrarily. The period of the clock signal CLK that operates the counter circuit CNT is set so that the period of the generated first data has a sufficiently long period (a period of one hundred to several hundred times) compared to the switching period of the switching element SW1.

[0072] On the other hand, Figure 6As shown in (C), the jitter conversion circuits 52A and 52B have inverters IV1 to IV3 and multiplexers MPX1 to MPX3. The inverters IV1 to IV3 invert the outputs Q0 to Q2 of the counter flip-flops T-FF0 to FF2. The multiplexers MPX1 to MPX3 receive the outputs Q0 to Q2 of the flip-flops T-FF0 to T-FF2 and their inversion signals as inputs, select one of the signals and output it. Furthermore, the output Q3 of the final stage flip-flop T-FF3 of the counter circuit CNT is applied to the control terminal of the multiplexers MPX1 to MPX3.

[0073] Thus, the jitter conversion circuits 52A and 52B operate as the following circuits: while the output Q3 is at a low level, the increasing (+1) value supplied from the counter circuit is directly output; when the output Q3 changes to a high level, the data (ascending data) consisting of the increasing (+1) value supplied from the counter circuit CNT is converted into data (descending data) consisting of decrementing (-1) values ​​and output.

[0074] As a result, the outputs of the jitter conversion circuits 52A and 52B can be regarded as data that repeatedly increases and decreases, that is, a pseudo-triangular wave signal with a predetermined period. Fig. 9 As shown in (B), the pseudo triangular wave signal (JTi) output from the jitter conversion circuit 52B becomes a signal having a phase difference corresponding to the addition data ADT with respect to the pseudo triangular wave signal (JTp) output from the jitter conversion circuit 52A. Therefore, the addition data ADT is information (phase shift signal) indicating the phase shift amount, and the addition circuit 53 can be regarded as a phase shift circuit.

[0075] In addition, in the jitter circuit of this embodiment, the period jitter signal JTp is generated based on the first data FDT, and the current jitter signal JTi is generated based on the second data SDT obtained by adding a predetermined addition value ADT to the first data FDT, but the period jitter signal JTp and the current jitter signal JTi can also be opposite.

[0076] Figure 7 FIG. 2 shows a specific circuit configuration example of the cutoff circuit 36 ​​composed of a current detection circuit. Figure 7 As shown, the cut-off circuit 36 ​​includes: a voltage divider circuit, which is composed of a resistor R5 and a variable resistor R6 connected in series between the external terminal FB and the ground point, and divides the voltage VFB of the terminal FB; and a comparator CMP4, which uses the voltage divided by the resistors R5 and R6 as a threshold voltage VREF to determine the voltage Vcs of the external terminal CS. When the voltage Vcs of the external terminal CS exceeds VREF, the output of the comparator CMP4 changes from a low level to a high level. The output is supplied to the latch circuit 37 as a cut-off signal TOFF, and the switch element SW1 is turned off.

[0077] Furthermore, in the power supply control IC 13 of the present embodiment, the resistance value of the variable resistor R6 of the cutoff circuit 36 ​​changes according to the current jitter signal JTi output from the jitter circuit 35. As a result, the timing of the signal TOFF output from the cutoff circuit 36 ​​fluctuates, and jitter is given to the cutoff signal of the switch element SW1. Furthermore, at the timing when the switch element SW1 is cut off, the drain current of SW1 becomes a peak current. Therefore, when jitter is given to the cutoff signal TOFF as described above, the peak current changes. That is, the current jitter signal JTi is used as a signal that gives jitter (fluctuation) to the peak current of the drain current of SW1.

[0078] exist Figure 8 (B) shows an example of setting the voltage VFB of the terminal FB and the threshold voltage VREF of the comparator CMP3 of the cutoff circuit (current detection circuit) 36. In this embodiment, the resistance value of the variable resistor R6 is changed in proportion to the voltage VFB of the terminal FB, as shown in FIG. Figure 8 As shown in (B), the threshold voltage VREF is set to change linearly with respect to the voltage VFB.

[0079] Fig. 9 (B) shows the current jitter signal JTi and the change of the threshold voltage VREF changed by the signal. Fig. 9 As can be seen from (B), the period and phase of the current jitter signal JTi are the same as the threshold voltage VREF. Fig. 9 (A) and Fig. 9 As can be seen from the comparison of (B), the current jitter signal JTi has a predetermined phase difference PD with respect to the period jitter signal JTp. The phase difference PD is composed of Figure 6 The added data ADT is provided by the adding circuit 52 of the jitter circuit 35 shown above. Although not shown in the figure, in the case of only period jitter, the variation of the interval tMIN of the minimum period signal MPS is similar to Fig. 9 is the same as (A), but since no current jitter is given, the threshold voltage VREF does not change but remains fixed.

[0080] Next, use Figure 10 to Figure 13 The characteristics of the operation of the power supply control IC 13 of this embodiment having the above-described structure will be described.

[0081] in, Fig.10 FIG. 1 is a timing chart showing the operation of the power supply control IC in the PWM mode in which only the periodic jitter signal JTp is generated by the jitter circuit 35. Fig.11 The timing chart is shown when the power supply control IC 13 of the present embodiment generates the period jitter signal JTp and the current jitter signal JTi by the jitter circuit 35 and operates in the PWM mode.

[0082] exist Fig.10 and Fig.11 In the example, the switching period without period jitter and current jitter is set to tSW, and the current jitter ( Fig.10 The switching period of the switch with only period jitter is set to tSWJ, and the switch with both period jitter and current jitter is set to Fig.11 ) is set to tSWJ', the interval of the minimum period signal MPS is set to tMIN, and the time changed due to the period jitter is set to Δt.

[0083] Therefore, when there is no period jitter or current jitter, tSW = tMIN. In addition, when there is only period jitter, tSWJ = tMIN + Δt, and when there is both period jitter and current jitter, tSWJ' = tMIN + Δt. It can be seen that in PWM mode, the switching cycle dispersion effect caused by jitter can be obtained in the case of only period jitter and in the case of both period jitter and current jitter.

[0084] In addition, Fig.12 FIG. 2 shows a timing chart of a power supply control IC that generates only a periodic jitter signal JTp through a jitter circuit 35 and operates in a quasi-resonance mode. Fig.13 2 is a timing chart showing when the power supply control IC 13 of the present embodiment, in which the period jitter signal JTp and the current jitter signal JTi are generated by the jitter circuit 35, operates in the quasi-resonance mode.

[0085] exist Fig.12 In the case of only period jitter, the switching period tSW becomes the next phase detection timing tZ2 until the interval tMIN of the minimum period signal MPS. Therefore, when the timing of the conduction of the switching element SW1 is set to the reference time 0, the zero current resonance start time is set to t2, the zero current resonance period is set to tZP, and the added amount of period jitter is set to Δt, and the switching period when the period jitter is effective is set to tSWJ, tSW and tSWJ are determined by the following formula:

[0086] tSW(N)=t2+(N+X)*tZP

[0087] tSWJ(NJ)=t2+(NJ+X)*tZP

[0088] In addition, here, N and NJ are natural numbers, and X is a constant greater than or equal to 0 and less than 1.

[0089] In addition, the relationship between tSW and tMIN, and the relationship between tSWJ and tMIN+Δt are expressed by the following equations:

[0090] tSW(N-1)<tMIN≤tSW(N)

[0091] tSWJ(NJ-1)<tMIN+Δt≤tSWJ(NJ)

[0092] Among them, when Δt converges to the range of tSW(N-1)<tMIN+Δt≤tSW(N), the switching period is tSWJ(NJ)=tSW(N), and the switching period is the same regardless of whether there is period jitter. Therefore, in the case of only period jitter, the dispersion effect of the switching period caused by period jitter cannot be obtained in the quasi-resonant mode.

[0093] On the other hand, Fig.13 With periodic jitter and current jitter, when the power supply control IC operates in quasi-resonance mode, the reference voltage of the current detection circuit for detecting the cut-off timing is set to VREF, the added amount of current jitter is set to ΔV, the timing of switch conduction is set to the reference time 0, the cut-off time is set to t1', and the zero current resonance start time is set to t2'. Thus,

[0094] t1'=t1*(1+ΔV / VREF)

[0095] t2'=t2*(1+ΔV / VREF)

[0096] In addition, the switching cycle tSW′ is a value determined by the next phase detection timing tZ2′ of the interval tMIN of the minimum cycle signal MPS.

[0097] Here, if the switching period when both the cycle jitter and the current jitter occur is tSWJ', tSW and tSWJ' are determined by the following equations.

[0098] tSW(N)=t2+(N+X)*tZP

[0099] tSWJ'(NJ')=t2'+(NJ'+X)*tZP

[0100] =t2*(1+ΔV / VREF)+(NJ'+X)*tZP

[0101] In addition, N and NJ are natural numbers, and X is a constant greater than or equal to 0 and less than 1.

[0102] Therefore, the difference between the switching period with and without jitter is:

[0103] tSWJ'(NJ')-tSW(N)=t2+(N+X)*tZP-t2*(1+ΔV / VREF)+(NJ'+X)*tZP

[0104] =t2*ΔV / VREF+(N-NJ')*tZP

[0105] Even if N=NJ' is assumed, a switching cycle variation of t2*ΔV / VREF will occur. Therefore, even in the presence of cycle jitter and current jitter, the switching cycle dispersion effect can be obtained in the quasi-resonant mode.

[0106] exist Fig.14 In (A), a graph showing the change in the switching cycle in a switching power supply device using a power supply control IC that only provides period jitter is shown, with the horizontal axis being the feedback voltage VFB and the vertical axis being the ratio of the switching cycle when jitter is effective to that when jitter is ineffective tsw' / tsw. Fig.14 (B) shows a graph showing the variation of the switching cycle in a switching power supply device using a power supply control IC that provides cycle jitter and current jitter, with the horizontal axis representing the feedback voltage VFB and the vertical axis representing the ratio tsw' / tsw of the switching cycle when jitter is valid and when jitter is invalid.

[0107] If you compare Fig.14 In the graphs (A) and (B), in the quasi-resonant operation area, in the case of only periodic jitter in (A), the switching period is concentrated on discrete specific 3-point periods, and thus the peak of the spectrum of the conducted noise becomes higher. The reason why the switching period is concentrated on discrete specific periods is that in the quasi-resonant operation, if the resonance period is set to tZP, the resonance period Tr of the zero current resonance becomes "Tr = tZP × (0.5 + N)" (N is an integer).

[0108] In contrast, Fig.14 In the case of period jitter and current jitter in (B), although the switching period is concentrated in a specific period range in quasi-resonant operation, it can also be seen that the switching period is dispersed around a specific period. In this way, the switching period dispersion in quasi-resonant operation is due to the time t2 ( Fig.13 ) varies according to the current jitter. As a result, Fig.14 (B) In the case of period jitter and current jitter, under quasi-resonant operation, with Fig.14 Compared with the case of only period jitter in (A), a good noise reduction effect can be obtained.

[0109] exist Fig.15 A graph is shown in which the horizontal axis is the frequency and the vertical axis is the noise intensity. Fig.15 In the figure, the dotted line represents the spectrum of the noise intensity when only the period jitter occurs, and the solid line represents the spectrum of the noise intensity when the period jitter and current jitter occur. Fig.15It can be seen that the case of period jitter and current jitter (solid line) has a lower peak than the case of period jitter alone (dashed line), and a good noise reduction effect can be obtained.

[0110] Furthermore, the inventors have found that in a switching power supply device using the power supply control IC of the above-described embodiment, Fig.16 As shown in Figure 1, the spectrum peaks vary depending on the phase difference between the period jitter and the current jitter. Fig.16 In the example of the graph of , the spectrum peak at a phase difference of -45 degrees is the smallest compared to the spectrum peak at a phase difference of 0 degrees, and the effect of noise spectrum dispersion can be expected.

[0111] However, the magnitude relationship of the spectrum peak with respect to the phase difference also changes depending on the structure of the switching power supply device, the input voltage, the output voltage, and the magnitude of the output current. Therefore, it is most effective from the perspective of reducing noise if the phase shift amount is set to match the conditions under which the conducted noise is to be reduced, that is, the phase shift amount is set in a manner that minimizes the spectrum peak under the condition that becomes the bottleneck of the spectrum peak of the conducted noise. For example, after determining the conditions other than the phase difference, the phase difference that minimizes the spectrum peak under the conditions may be found to set the added data (added value) in the jitter circuit 35.

[0112] The invention made by the inventors is specifically described above based on the embodiments, but the present invention is not limited to the above embodiments. For example, in the above embodiments, the voltage of the auxiliary winding is divided by the resistors R1 and R2 as external elements and input to the external terminal DMG, but the voltage of the auxiliary winding may be directly input to the external terminal DMG, or the voltage divided by the resistor element provided in the power control IC or the voltage divided by the resistor element provided in the power control IC and the external resistor element may be input to the external terminal DMG.

[0113] In addition, in the above-mentioned embodiment, the switching transistor SW1 and the current sensing resistor Rs are set as components different from the power supply control IC13, but the switching transistor SW1 can also be taken into the power supply control IC13 to form a semiconductor integrated circuit (the current sensing resistor Rs is an external component), or the switching transistor SW1 and the current sensing resistor Rs can be taken into the power supply control IC13. In addition, instead of providing the current sensing resistor Rs to generate and detect the voltage Vcs, it can also be configured to detect the magnitude of the drain current based on the drain voltage of the internal switching transistor SW1.

[0114] Description of Reference Numerals

[0115] 12…transformer, 13…semiconductor device for switching power supply (IC for power supply control), 14…constant voltage control circuit, 31…resonance start detection circuit, 32…resonance phase detection circuit, 33…timer circuit, 34…conduction circuit, 35…jitter circuit, 36…cutoff circuit (current detection circuit), 37…latch circuit (gate control signal generation circuit), 38…drive circuit, 39…internal power supply circuit, 51…data generation circuit, 52A, 52B…jitter conversion circuit, 53…addition circuit (phase shift circuit).

Claims

1. A semiconductor device for a switching power supply, which generates a drive signal for controlling on and off a switching element connected in series with a primary winding of a voltage conversion transformer having an auxiliary winding, It is characterized in that The semiconductor device for a switching power supply comprises: a resonance monitoring circuit that monitors a resonance state of the secondary winding of the transformer according to a voltage of the auxiliary winding; a timer circuit that generates a periodic signal that specifies a switching period of the switching element; a conduction circuit that outputs a conduction signal for turning on the switch element based on the periodic signal and the signal from the resonance monitoring circuit; a cut-off circuit for detecting that the current flowing through the switch element reaches a predetermined current value and outputting a cut-off signal for turning off the switch element; as well as a jitter generating circuit, which generates a first jitter signal and a second jitter signal, wherein the first jitter signal is used to give fluctuations to the interval of the periodic signal, and the second jitter signal is used to give fluctuations to the predetermined current value of the cutoff signal output by the cutoff circuit, The first jitter signal and the second jitter signal have a predetermined phase difference.

2. The semiconductor device for a switching power supply according to claim 1, wherein: The jitter generating circuit comprises: a data generating circuit for generating first data which becomes a basis of the first dithering signal; a first jitter signal generating circuit, which generates the first jitter signal according to the first data; as well as a second jitter signal generating circuit, which generates the second jitter signal by performing a phase shift on the first jitter signal, The periods of the first jitter signal and the second jitter signal are longer than the switching period of the switching element. The timer circuit imparts fluctuations to the interval of the periodic signal based on the first jitter signal output from the first jitter signal generating circuit. The cutoff circuit imparts fluctuation to the cutoff signal based on the second dither signal output from the second dither signal generating circuit.

3. The semiconductor device for a switching power supply according to claim 1, wherein: The jitter generating circuit comprises: a counter circuit that generates first data that becomes a basis for the first wobble signal; an adding circuit for adding a predetermined addition value to the first data to generate second data which is a basis of the second dithering signal; A first data conversion circuit converts the first data, which is ascending order data, into descending order data, and outputs ascending order followed by descending order data; as well as a second data conversion circuit, which converts the second data, which is ascending order data, into descending order data, and outputs ascending order followed by descending order data; The timer circuit imparts fluctuations to the periodic signal according to data output from the first data conversion circuit. The cutoff circuit is configured to impart fluctuations to the cutoff signal based on data output from the second data conversion circuit.

4. The semiconductor device for a switching power supply according to claim 3, wherein: The added value is set so as to minimize the peak of the frequency spectrum of the conduction noise emitted from the power supply device.

5. The semiconductor device for a switching power supply according to claim 1, wherein: The switching power supply semiconductor device includes a third external terminal to which the voltage induced in the auxiliary winding or a voltage proportional to the voltage is input. The resonance monitoring circuit has: a resonance start detection circuit that detects, based on the voltage of the third external terminal, that zero current resonance that starts immediately after the current of the secondary winding of the transformer becomes zero after the switching element is turned off, and outputs a resonance start detection signal; as well as a resonance phase detection circuit that detects a predetermined phase of the zero current resonance based on the voltage of the third external terminal to output a resonance phase detection signal, The conduction circuit generates the conduction signal based on the periodic signal, the resonance start detection signal, and the resonance phase detection signal when the periodic signal is received before the resonance start detection signal is received or when the next resonance phase detection signal rises after the periodic signal is received.

6. The semiconductor device for a switching power supply according to claim 5, wherein: The semiconductor device for a switching power supply comprises: a first external terminal to which a feedback voltage corresponding to a voltage output from a secondary side of the transformer is input; and a second external terminal to which a voltage proportional to the current flowing through the switching element is input, The cutoff circuit detects that the current flowing through the switching element reaches a predetermined current value based on the voltage of the first external terminal and the voltage of the second external terminal. The second jitter signal imparts fluctuations to the predetermined current value by varying a voltage derived from a voltage of the second external terminal.

7. The semiconductor device for a switching power supply according to claim 6, wherein: The switching power supply semiconductor device includes a voltage dividing circuit having a fixed resistor and a variable resistor connected in series between the first external terminal and a reference potential point, and divides the voltage of the first external terminal. The cutoff circuit compares the voltage divided by the voltage dividing circuit with the voltage of the second external terminal to detect that the current flowing through the switching element reaches a predetermined current value. The second jitter signal varies the resistance value of the variable resistor to change the divided voltage of the voltage divider circuit, thereby imparting fluctuations to the predetermined current value.

8. A switching power supply device, characterized in that: have: The semiconductor device for a switching power supply according to any one of claims 1 to 7; A transformer including an auxiliary winding, wherein a voltage obtained by rectifying an AC voltage is applied to a primary winding; and a switching element connected to the primary winding, The switching power supply device is configured to output a predetermined voltage to a secondary winding side by controlling the switching element using the switching power supply semiconductor device.

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