Integrated oscillator and preparation method

Abstract

The invention provides an integrated oscillator and a preparation method, and relates to the technical field of oscillators. According to the invention, the conductive member is arranged in the substrate; a driving circuit structure is formed on the side face of the base body; the conductive part is electrically connected with the driving circuit structure; a bottom electrode layer, a piezoelectric layer and a top electrode layer are sequentially stacked on the substrate to form a beam structure; the bottom electrode layer and the top electrode layer are electrically connected with the conductive piece. The drive circuit structure and the beam structure are integrated on the two faces of the base body, the overall size of the oscillator is conveniently reduced, the drive circuit structure and the beam structure are electrically connected through the conductive piece in the base body, electric interconnection is achieved, the preparation steps are simplified, and compared with external welding, connection is more stable.

Description

Technical Field

[0001] The present application relates to the technical field of oscillators, and in particular to an integrated oscillator and a preparation method thereof. Background Art

[0002] Micro-Electro-Mechanical System (MEMS) is a technology that integrates micro-mechanical structures and electronic functions on a single chip. It has a wide range of applications, such as MEMS sensors and MEMS oscillators. Among them, MEMS oscillators use micro-mechanical resonators to generate high-precision time-frequency signals. MEMS oscillators can be divided into electrostatic drive and piezoelectric drive due to different resonant drive methods.

[0003] In the prior art, a piezoelectrically driven MEMS oscillator includes a MEMS resonator and a driving circuit. After the MEMS resonator and the driving circuit are packaged separately, they are integrated by stacking them up and down through packaging technology such as a Quad Flat No-leads Package (QFN).

[0004] However, the above structure is relatively large in size. Summary of the invention

[0005] The present application provides an integrated oscillator and a preparation method thereof, so as to solve the problem of large size of the existing oscillator structure.

[0006] In order to achieve the above purpose, the technical solution of this application is as follows:

[0007] On the one hand, the present application provides a method for preparing an integrated oscillator, comprising: setting a conductive member in a substrate; forming a driving circuit structure on the side of the substrate; the conductive member is electrically connected to the driving circuit structure; a bottom electrode layer, a piezoelectric layer and a top electrode layer are sequentially stacked on the substrate to form a beam structure; the bottom electrode layer and the top electrode layer are both electrically connected to the conductive member.

[0008] In one possible implementation, the preparation method provided in the embodiment of the present application, in which a bottom electrode layer, a piezoelectric layer and a top electrode layer are stacked in sequence on a substrate to form a beam structure, including: two connecting holes are set on the substrate to correspond to exposing one end of the conductive member away from the driving circuit structure, wherein two conductive members are set; a bottom electrode layer is set on the substrate in one connecting hole; a piezoelectric layer and a top electrode layer are stacked in sequence on the bottom electrode layer, the bottom electrode layer and the top electrode layer are both located on one side of the connecting hole, and the top electrode layer extends into another connecting hole to be connected to the conductive member.

[0009] In one possible implementation, the preparation method provided in an embodiment of the present application, two connection holes are set on the substrate, including: stacking a top silicon layer, a buried oxide layer and a substrate silicon in sequence to form a substrate; connection holes are set on the top silicon layer and the buried oxide layer, wherein the conductive member is located on the substrate silicon.

[0010] In one possible implementation, the preparation method provided in an embodiment of the present application comprises sequentially stacking a top silicon layer, a buried oxide layer and a substrate silicon to form a base, comprising: setting a buried oxide layer with a thickness of 1um to 5um on a top silicon layer with a thickness of 2um to 20um, and setting a substrate silicon with a thickness of 300um to 800um on the buried oxide layer, wherein a cavity is provided in the substrate silicon, the depth of the cavity is 2um to 5um, and the width and length of the cavity are both 400um to 500um.

[0011] In one possible implementation, the preparation method provided in the embodiment of the present application sets a conductive part in a substrate, including: setting a through hole in the substrate; setting a passivation layer on the surface of the substrate and the surface of the inner wall of the through hole, and the conductive part is set in the through hole.

[0012] In a possible implementation, the preparation method provided in the embodiment of the present application provides a through hole in a substrate, including: etching a through hole with a diameter of 10 um to 200 um using photolithography and DRIE processes.

[0013] In one possible implementation, the preparation method provided in the embodiment of the present application sets two connection holes on the substrate, including: etching the top silicon layer and the buried oxide layer in sequence through photolithography, DRIE, and RIE processes to form connection holes; the diameter of the connection hole is larger than the through hole.

[0014] In one possible implementation, the preparation method provided in the embodiment of the present application sequentially stacks a bottom electrode layer, a piezoelectric layer and a top electrode layer on a substrate to form a beam structure, including: depositing a piezoelectric electrode layer with a thickness of 500nm to 2000nm on a bottom electrode layer 310 with a thickness of 20nm to 100nm by a PVD process, and depositing a top electrode layer with a thickness of 20nm to 500nm on the piezoelectric electrode layer; patterning the bottom electrode layer by photolithography and corrosion processes, and sequentially patterning the piezoelectric electrode layer and the top electrode layer by photolithography, IBE and ICP etching processes; removing the top silicon layer by photolithography and DRIE dry etching processes, and etching to form a beam structure.

[0015] In one possible implementation, the preparation method provided in the embodiment of the present application forms a driving circuit structure on the side of the substrate, including: forming a driving circuit structure on the side of the substrate silicon of the substrate through a CMOS process, a 40nm to 180nm process, and passivating the side of the substrate silicon.

[0016] On the other hand, the present application also provides an integrated oscillator, which is prepared by the preparation method in any of the above embodiments, and includes: a substrate, a driving circuit structure and a beam structure; the driving circuit structure and the beam structure are respectively arranged on opposite sides of the substrate, and a conductive member is arranged in the substrate, and the driving circuit structure and the beam structure are electrically connected through the conductive member, one end of the beam structure is connected to the substrate, and the other end of the beam structure is suspended above the substrate.

[0017] The integrated oscillator and preparation method provided by the present application are as follows: a conductive member is arranged in a substrate; a driving circuit structure is formed on the side of the substrate; the conductive member is electrically connected to the driving circuit structure; a bottom electrode layer, a piezoelectric layer and a top electrode layer are sequentially stacked on the substrate to form a beam structure; and both the bottom electrode layer and the top electrode layer are electrically connected to the conductive member. By integrating the driving circuit structure and the beam structure on both sides of the substrate, it is convenient to reduce the overall size of the oscillator, and the driving circuit structure and the beam structure are electrically connected through the conductive member in the substrate to achieve electrical interconnection, simplify the preparation steps, and the connection is more stable than external welding. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of the structure of an integrated oscillator provided in an embodiment of the present application;

[0020] Figure 2 for Figure 1 A schematic diagram of the structure of the integrated oscillator from another perspective;

[0021] Figure 3 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 1 ;

[0022] Figure 4 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 2 ;

[0023] Figure 5 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 3 ;

[0024] Figure 6 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 4 ;

[0025] Figure 7 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 5 ;

[0026] Figure 8 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 6 ;

[0027] Fig. 9 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 7 ;

[0028] Fig.10 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 8 ;

[0029] Fig.11 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 9 ;

[0030] Fig.12 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 10 ;

[0031] Fig.13 for Figure 1 Structural diagram of the center beam structure;

[0032] Fig.14 for Figure 1 A schematic diagram of the structure of the driving circuit structure;

[0033] Fig.15 Flow chart of the method for preparing an integrated oscillator in an embodiment of the present application.

[0034] Description of reference numerals:

[0035] 100-matrix;

[0036] 110-conductive member;

[0037] 120- cavity;

[0038] 130-through hole;

[0039] 140-top silicon layer;

[0040] 150- buried oxygen layer;

[0041] 160-substrate silicon;

[0042] 170-passivation layer;

[0043] 200-driving circuit structure;

[0044] 210- electrical connector;

[0045] 300-beam structure;

[0046] 310- bottom electrode layer;

[0047] 320- piezoelectric layer;

[0048] 330 - top electrode layer.

[0049] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0050] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0051] It should be noted that in the description of the embodiments of the present application, terms such as "upper", "lower", "inside" and "outside" indicating orientation or positional relationships are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of description, and do not indicate or imply that the device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the embodiments of the present application.

[0052] In addition, it should be noted that the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0053] In this application, unless otherwise clearly specified and limited, the terms "installation", "connection", "fixation" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0054] The full name of CMOS process is Complementary Metal-Oxide-Semiconductor (CMOS) process, which is a semiconductor manufacturing technology used to manufacture integrated circuits.

[0055] PECVD deposition stands for Plasma-Enhanced Chemical Vapor Deposition, which is a process used to deposit thin films on substrates.

[0056] The PVD (Physical Vapor Deposition) process is a thin film deposition technology used to deposit thin films on solid surfaces.

[0057] IBE (ion beam mixing or ion beam doping) is a process that uses ion beam technology to dope or mix semiconductor materials.

[0058] The ICP dry method refers to a dry etching process using an inductively coupled plasma (ICP) technology.

[0059] RIE (Reactive Ion Etching) dry method is a process that uses reactive gas to react with the material surface in a plasma environment to achieve precise etching.

[0060] Micro-Electro-Mechanical System (MEMS) is a technology that integrates micro-mechanical structures and electronic functions on a single chip. It has a wide range of applications, such as MEMS sensors and MEMS oscillators. Among them, MEMS oscillators use micro-mechanical resonators to generate high-precision time-frequency signals. MEMS oscillators can be divided into electrostatic drive and piezoelectric drive due to different resonant drive methods.

[0061] In the prior art, a piezoelectrically driven MEMS oscillator includes a MEMS resonator and a driving circuit. After the MEMS resonator and the driving circuit are packaged separately, the two are integrated by stacking them up and down through packaging technology, such as a Quad Flat No-leads Package (QFN). However, the above structure is relatively large in size.

[0062] In view of this, the present application provides an integrated oscillator and a preparation method, including: a conductive member is arranged in a substrate; a driving circuit structure is formed on the side of the substrate; the conductive member is electrically connected to the driving circuit structure; a bottom electrode layer, a piezoelectric layer and a top electrode layer are stacked in sequence on the substrate to form a beam structure; the bottom electrode layer and the top electrode layer are both electrically connected to the conductive member. By integrating the driving circuit structure and the beam structure on both sides of the substrate, it is convenient to reduce the overall size of the oscillator, and the driving circuit structure and the beam structure are electrically connected through the conductive member in the substrate to achieve electrical interconnection, simplify the preparation steps, and the connection is more stable than external welding.

[0063] Combination Figures 1 to 15 The present application is described with specific embodiments. Figure 1 A schematic diagram of the structure of an integrated oscillator provided in an embodiment of the present application; Figure 2 for Figure 1 A schematic diagram of the structure of the integrated oscillator from another perspective; Figure 3 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 1 ; Figure 4 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 2 ; Figure 5 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 3 ; Figure 6 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 4 ; Figure 7 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 5 ; Figure 8 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 6 ; Fig. 9 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 7 ; Fig.10 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 8 ; Fig.11 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 9 ; Fig.12 for Figure 1 Schematic diagram of the structure during the preparation of the integrated oscillator Figure 10 ; Fig.13 for Figure 1 Structural diagram of the center beam structure; Fig.14 for Figure 1 Schematic diagram of the structure of the driving circuit.

[0064] On the one hand, the present application provides a method for preparing an integrated oscillator, including: S100, setting a conductive member 110 in a substrate 100; S200, forming a driving circuit structure 200 on a side of the substrate 100; S300, electrically connecting the conductive member 110 to the driving circuit structure 200; S400, sequentially stacking a bottom electrode layer 310, a piezoelectric layer 320 and a top electrode layer 330 on the substrate 100 to form a beam structure 300; the bottom electrode layer 310 and the top electrode layer 330 are both electrically connected to the conductive member 110.

[0065] The substrate 100 is a cavity-silicon-on-insulator wafer (C-SOI wafer). The structure of the substrate 100 is as follows: Figure 3 As shown, the substrate 100 includes a top silicon layer 140, a buried oxide layer 150 and a substrate silicon 160 which are stacked in sequence, and a cavity 120 is arranged in the substrate silicon 160. The present application does not limit the size and structure of the substrate 100. Exemplarily, a buried oxide layer 150 with a thickness of 1um to 5um is arranged on the top silicon layer 140 with a thickness of 2um to 20um, and a substrate silicon 160 with a thickness of 300um to 800um is arranged on the buried oxide layer 150, wherein a cavity 120 is arranged in the substrate silicon 160, the depth of the cavity 120 is 2um to 5um, and the width and length of the cavity 120 are both 400um to 500um. For example, the thickness of the substrate silicon 160 is 500, the thickness of the buried oxide layer 150 is 3um, the thickness of the top silicon layer 140 is 5um, the depth of the cavity 120 is 3um, and the width and length of the cavity 120 are both 500um.

[0066] To arrange the conductive member 110 in the substrate 100, it is necessary to first arrange the through hole 130 in the substrate 100, such as Figure 4 As shown, the through hole 130 is made by TSV technology on the substrate silicon 160, and the through hole 130 is etched by photolithography and DRIE process. The diameter of the through hole 130 is 10um to 200um. The etching is stopped when the buried oxide layer 150 is etched. The substrate silicon 160 of the substrate 100 is made of TSV technology. The through hole 130 is etched by photolithography and DRIE process. The diameter of the through hole 130 is 10um to 200um. When the buried oxide layer 150 is etched, the etching is stopped, thereby forming Figure 4 vias shown.

[0067] A passivation layer 170 is disposed on the surface of the substrate 100 and the surface of the inner wall of the through hole 130. That is, a SiO2 passivation layer 170 is formed by a thermal oxidation process, and the thickness is 0.1 um to 2 um. Figure 5 shown.

[0068] A passivation layer 170 is disposed on the surface of the substrate 100 and the inner wall of the through hole 130, and the conductive member 110 is disposed in the through hole 130. Specifically, an adhesion layer or a barrier layer is grown on the inner wall of the through hole 130 and the surface of the substrate silicon 160 by magnetron sputtering, and the sputtered metal is titanium (Ti), titanium tungsten (TiW) or titanium nitride (TiN), and the thickness is 0.1um to 1um, such as Figure 6 shown.

[0069] The conductive member 110 is made of copper (Cu), and the through hole 130 and the surface of the substrate silicon 160 are filled with copper by electroplating. Figure 7 shown.

[0070] The copper metal on the surface of the substrate silicon 160 is subjected to a CMP process to remove the copper on the surface. Figure 8 As shown in Figure 1. The CMP process refers to the Chemical Mechanical Polishing (CMP) process, which is used to remove materials or smooth the surface.

[0071] The driving circuit structure 200 is set on one side of the substrate 100 by CMOS process, that is, the ASIC driving circuit is made on the C-SOI wafer substrate surface, using CMOS process, 40-180nm process. The substrate surface is passivated, and silicon oxide or silicon nitride is deposited by PECVD, such as Fig. 9 shown.

[0072] The area corresponding to the through hole 130 of the top silicon layer 140 is photolithographically processed, and the top silicon layer 140 and the buried oxide layer 150 are sequentially etched by the DRIE process and the RIE process to form a connection hole 180, exposing the copper lead, that is, the end of the conductive member 110 away from the driving circuit structure 200. That is, the connection hole 180 is set on the top silicon layer 140 and the buried oxide layer 150, wherein the conductive member 110 is located in the through hole 130 of the substrate silicon 160, and the connection hole 180 is connected to the through hole 130, as shown in FIG. Fig.10 It should be noted that the diameter of the connecting hole 180 is larger than that of the through hole 130 .

[0073] Two connecting holes 180 are set on the substrate 100 to expose one end of the conductive member 110 away from the driving circuit structure 200, wherein two conductive members 110 are set; a bottom electrode layer 310 is set in one connecting hole 180 to the substrate 100; a piezoelectric layer 320 and a top electrode layer 330 are stacked in sequence on the bottom electrode layer 310, and the bottom electrode layer 310 and the top electrode layer 330 are both located on one side of the connecting hole 180, and the top electrode layer 330 extends to the other connecting hole 180 to be connected to the conductive member 110.

[0074] The bottom electrode of the MEMS part is made by metal deposition, and the metal molybdenum, gold or platinum is deposited by PVD process with a thickness of 20-100nm. The bottom electrode layer 310 is patterned by photolithography and etching process, and the beam structure 300 is interconnected with the input electrode of the driving circuit structure 200, such as Fig.11 shown.

[0075] Deposit a piezoelectric film using AlN or PZT using a PVD process with a deposition thickness of 500 to 2000 nm, and deposit a top electrode metal of molybdenum, gold or platinum with a thickness of 20 nm to 500 nm. Remove the top metal through photolithography and IBE metal dry etching process, and pattern the top electrode. On a bottom electrode layer 310 with a thickness of 20 nm to 100 nm. Deposit a piezoelectric electrode layer 320 with a thickness of 500 nm to 2000 nm through a PVD process, and deposit a top electrode layer 330 with a thickness of 20 nm to 500 nm on the piezoelectric electrode layer 320; pattern the bottom electrode layer 310 through photolithography and etching processes, pattern the piezoelectric electrode layer 320 through photolithography, IBE process and ICP etching process, and pattern the top electrode layer 330 through photolithography and IBE etching process; combine Fig.12 and Figure 2 shown.

[0076] The top silicon layer 140 is removed by photolithography and DRIE dry etching process, and the beam structure 300 is formed by etching. Finally, the buried oxide layer 150 is dry etched by RIE to release the beam structure 300. Figure 1 shown.

[0077] On the other hand, the present application also provides an integrated oscillator, which is prepared by the preparation method in any of the above embodiments, including: a substrate 100, a driving circuit structure 200 and a beam structure 300; the driving circuit structure 200 and the beam structure 300 are respectively arranged on opposite sides of the substrate 100, and a conductive member 110 is arranged in the substrate 100, and the driving circuit structure 200 and the beam structure 300 are electrically connected through the conductive member 110, one end of the beam structure 300 is connected to the substrate 100, and the other end of the beam structure 300 is suspended above the substrate 100.

[0078] Specifically, the substrate 100, the driving circuit structure 200 and the beam structure 300 are respectively arranged on opposite sides of the substrate 100. Two conductive members 110 and a cavity 120 are arranged in the substrate 100, the conductive member 110 is arranged on one side of the cavity 120, one end of the beam structure 300 is suspended above the cavity 120, and the other end of the beam structure 300 is connected to the substrate 100. It should be noted that one end of one conductive member 110 is connected to the top electrode of the beam structure 300, one end of the other conductive member 110 is connected to the bottom electrode of the beam structure 300, and the other ends of the two conductive members 110 are connected to the driving circuit structure 200.

[0079] The beam structure 300 includes a first beam, a second beam and a connecting beam. The first beam and the second beam are arranged opposite to each other and connected by the connecting beam. One end of each of the first beam and the second beam is connected to the base 100 .

[0080] The substrate 100 includes a top silicon layer 140, a buried oxide layer 150 and a substrate silicon 160 arranged in sequence from the bottom to the top, a cavity 120 is arranged on the side of the substrate silicon 160 facing the buried oxide layer 150, and a through hole 130 sequentially penetrates the top silicon layer 140, the buried oxide layer 150 and the substrate silicon 160. Two through holes are arranged on the substrate 100, and the conductive member 110 is connected to the through holes one by one and embedded in the through holes. Specifically, the inner wall of the through hole 130 is provided with silicon oxide.

[0081] The beam structure 300 includes a bottom electrode layer 310, a piezoelectric layer 320 and a top electrode layer 330. The piezoelectric layer 320 is located between the bottom electrode layer 310 and the top electrode layer 330. The piezoelectric layer 320 is provided with a piezoelectric pattern, the top electrode layer 330 is provided with a top electrode pattern, and the bottom electrode layer 310 is provided with a bottom electrode pattern.

[0082] Specifically, the piezoelectric layer 320 is located between the bottom electrode layer 310 and the top electrode layer 330, and the piezoelectric layer 320 is provided with a piezoelectric pattern, such as removing the piezoelectric layer by photolithography and ICP dry etching process, and patterning the piezoelectric layer. The top electrode layer 330 is provided with a top electrode pattern, such as removing the top metal by photolithography and IBE metal dry etching process, and patterning the top electrode layer. The bottom electrode layer 310 is provided with a bottom electrode pattern. In some embodiments, one end of the piezoelectric layer 320 is connected to the top silicon layer 140. In some embodiments, both ends of the piezoelectric layer 320 are not connected to the top silicon layer 140.

[0083] In some embodiments, the top electrode layer 330 is sequentially arranged from the conductive member 110 to the direction above the piezoelectric layer 320, and the bottom electrode layer 310 is sequentially arranged from the conductive member 110 to the direction below the piezoelectric layer 320, and the piezoelectric layer 320 is sandwiched between the top electrode layer 330 and the bottom electrode layer 310. For example, some piezoelectric layers 320 are arranged in parallel, and some piezoelectric layers 320 are arranged obliquely.

[0084] An electrical connector 210 is provided on at least one side of the driving circuit structure 200, and the electrical connector 210 is used to connect to the power supply circuit. An electrical connector 210 is provided on at least one side of the driving circuit structure 200, and the electrical connector 210 is used to connect to the power supply circuit. For example, there are four electrical connectors 210, and the electrical connectors 210 are arranged on both sides of the driving circuit structure 200 in pairs. The outer frame of the driving circuit structure 200 is square or rectangular, and the embodiment of the present application is not limited to this.

[0085] A conductive member 110 is disposed in the substrate 100 by magnetron sputtering and electroplating processes; a driving circuit structure 200 is disposed on one side of the substrate 100 by a CMOS process; a bottom electrode layer 310, a piezoelectric layer 320 and a top electrode layer 330 are sequentially deposited on the side of the substrate 100 away from the driving circuit structure 200, and a beam structure 300 is disposed by photolithography and DRIE dry etching processes; the beam structure 300 is electrically connected to the bottom electrode layer 310 and the top electrode layer 330 through the conductive member 110 by metal deposition.

[0086] In the present application, the position and shape of the through hole 130 are defined by photolithography technology, and then the DRIE process is used for precise etching, and finally the etched through hole 130 is filled with a conductive material to establish an electrical connection.

[0087] The substrate 100 is placed on a workbench; a through hole 130 is etched on the substrate silicon 160 of the substrate 100 by photolithography and DRIE processes; a conductive member 110 is filled in the through hole 130 and on one side of the substrate silicon 160 by magnetron sputtering and electroplating processes; a driving circuit structure 200 is set on the substrate silicon 160 by a CMOS process; photolithography is performed in the area of ​​the through hole 130 corresponding to the top silicon layer 140, the top silicon layer and the buried oxide layer are etched by DRIE and RIE processes, and the bottom electrode layer 310 is electrically connected to the conductive member 110 by metal deposition; a bottom electrode pattern is set on the bottom electrode layer 310 by photolithography and etching processes, a piezoelectric layer 320 and a top electrode layer 330 are sequentially deposited on the bottom electrode layer 310, and a bottom electrode pattern and a top electrode pattern are set by photolithography, IBE process and ICP etching process; the top silicon layer is removed by photolithography and DRIE dry etching process, and the beam structure 300 is etched.

[0088] TSV is the abbreviation of Through-Silicon Via, which is a technology for making tiny through holes perpendicular to the surface in semiconductor wafers. These through holes can establish electrical connections between different layers of the wafer. TSV includes the following steps: Etching: Etching vertical through holes in the wafer using etching technology (such as deep reactive ion etching DRIE). Filling: Filling metal or other conductive materials in the through hole to establish an electrical connection. Sealing: In order to protect the through hole and the filling material, the through hole usually needs to be sealed.

[0089] Photolithography is a key technology in semiconductor manufacturing, used to transfer circuit patterns to the surface of the wafer. Before making TSV vias, photolithography is usually required to define the areas that need to be etched. In this process, photoresist and masks are used to define the location and shape of the vias, and then ultraviolet light or other light sources are used to illuminate the pattern on the mask to cause chemical changes in the photoresist in the corresponding areas.

[0090] DRIE process etches through holes. DRIE is the abbreviation of Deep Reactive Ion Etching, which is an advanced process for etching semiconductor materials such as silicon. The DRIE process can achieve deep and uniform etching and is very suitable for manufacturing TSV through holes 130 because it can accurately etch the required depth and size without damaging the surface layer of the wafer.

[0091] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0092] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for preparing an integrated oscillator, characterized in that: include: A conductive member (110) is arranged in the substrate (100); A driving circuit structure (200) is formed on the side of the substrate (100); the conductive element (110) is electrically connected to the driving circuit structure (200); A bottom electrode layer (310), a piezoelectric layer (320) and a top electrode layer (330) are sequentially stacked on the substrate (100) to form a beam structure (300); The bottom electrode layer (310) and the top electrode layer (330) are both electrically connected to the conductive member (110).

2. The method for preparing an integrated oscillator according to claim 1, characterized in that: The bottom electrode layer (310), the piezoelectric layer (320) and the top electrode layer (330) are sequentially stacked on the substrate (100) to form a beam structure (300), comprising: Two connection holes (180) are arranged on the base (100) to expose one end of the conductive element (110) facing away from the driving circuit structure (200), wherein two conductive elements (110) are arranged; The bottom electrode layer (310) is arranged in the connection hole (180) and on the substrate (100); The piezoelectric layer (320) and the top electrode layer (330) are sequentially stacked on the bottom electrode layer (310), and the bottom electrode layer (310) and the top electrode layer (330) are both located on one side of the connection hole (180), and the top electrode layer (330) extends into another connection hole (180) to be connected to the conductive member (110).

3. The method for preparing an integrated oscillator according to claim 2, characterized in that: The base (100) is provided with two connection holes (180), including: A top silicon layer (140), a buried oxide layer (150) and a substrate silicon (160) are stacked in sequence to form the base (100); The connection hole (180) is arranged on the top silicon layer (140) and the buried oxide layer (150), wherein the conductive element (110) is located on the substrate silicon (160).

4. The method for preparing an integrated oscillator according to claim 3, characterized in that: The top silicon layer (140), the buried oxide layer (150) and the substrate silicon (160) are stacked in sequence to form the base (100), comprising: The buried oxide layer (150) with a thickness of 1um to 5um is arranged on the top silicon layer (140) with a thickness of 2um to 20um, and the substrate silicon (160) with a thickness of 300um to 800um is arranged on the buried oxide layer (150), wherein a cavity (120) is arranged in the substrate silicon (160), the depth of the cavity (120) is 2um to 5um, and the width and length of the cavity (120) are both 400um to 500um.

5. The method for preparing an integrated oscillator according to claim 3, characterized in that: The method of arranging a conductive member (110) in a substrate (100) comprises: A through hole (130) is provided in the base (100); A passivation layer (170) is provided on the surface of the substrate (100) and the surface of the inner wall of the through hole (130), and the conductive member (110) is provided in the through hole (130).

6. The method for preparing an integrated oscillator according to claim 5, characterized in that: The step of providing a through hole (130) on the base (100) comprises: The through hole (130) having a diameter of 10 um to 200 um is etched using photolithography and DRIE technology.

7. The method for preparing an integrated oscillator according to any one of claims 3 to 5, characterized in that: The base (100) is provided with two connection holes (180), including: The top silicon layer (140) and the buried oxide layer (150) are sequentially etched by photolithography, DRIE, and RIE processes to form the connection hole (180); The diameter of the connecting hole (180) is larger than that of the through hole (130).

8. The method for preparing an integrated oscillator according to any one of claims 1 to 4, characterized in that: The bottom electrode layer (310), the piezoelectric layer (320) and the top electrode layer (330) are sequentially stacked on the substrate (100) to form a beam structure (300), comprising: Depositing the piezoelectric electrode layer (320) with a thickness of 500 nm to 2000 nm on the bottom electrode layer (310) with a thickness of 20 nm to 100 nm by a PVD process, and depositing a top electrode layer (330) with a thickness of 20 nm to 500 nm on the piezoelectric electrode layer (320); The bottom electrode layer (310) is patterned by photolithography and etching process, the piezoelectric electrode layer (320) is patterned by photolithography and ICP etching process, and the top electrode layer (330) is patterned by photolithography and IBE process; The top silicon layer (140) is removed by photolithography and DRIE dry etching process, and the beam structure (300) is formed by etching.

9. The method for preparing an integrated oscillator according to claim 8, characterized in that: The driving circuit structure (200) is formed on the side of the substrate (100), comprising: The driving circuit structure (200) is formed on the side of the substrate silicon (160) of the base (100) by CMOS technology and 40nm-180nm process, and the side of the substrate silicon (160) is passivated.

10. An integrated oscillator, characterized in that: The integrated oscillator is prepared by any of the above preparation methods, including: A substrate (100), a driving circuit structure (200) and a beam structure (300); The driving circuit structure (200) and the beam structure (300) are respectively arranged on two opposite sides of the substrate (100); a conductive member (110) is arranged in the substrate (100); the driving circuit structure (200) and the beam structure (300) are electrically connected via the conductive member (110); one end of the beam structure (300) is connected to the substrate (100); and the other end of the beam structure (300) is suspended above the substrate (100).

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