Duty ratio calibration circuit of high-speed clock

Abstract

The invention relates to the technical field of clock signal adjustment, in particular to a duty ratio calibration circuit of a high-speed clock, which comprises a duty ratio adjustment module with a first input end connected with an external clock generation circuit and an output end connected with an external functional circuit; the input end of the feedback module is connected with the output end of the duty ratio adjusting module, and the output end is connected with the second input end of the duty ratio adjusting module; the duty ratio adjustment module performs duty ratio adjustment on the clock signal to form an adjusted clock signal; the feedback module generates a duty ratio calibration code according to the adjustment clock signal and the inverted clock signal which are input in sequence, and the duty ratio adjustment module adjusts the duty ratio according to the duty ratio calibration code. The duty ratio calibration method has the beneficial effects that the two adjacent groups of adjustment clock signals are selected to carry out phase inversion processing and then comparison is carried out, the calibration code is generated, mismatch voltage possibly generated in the comparison process is eliminated by carrying out phase inversion processing on the adjustment clock signals, and the accuracy of duty ratio calibration is improved.

Description

Technical Field

[0001] The invention relates to the technical field of clock signal adjustment, and in particular to a duty cycle calibration circuit for a high-speed clock. Background Art

[0002] Clock signal is the basis of sequential logic. It is used to determine when the state in the logic unit is updated. It is a signal with a fixed cycle and is independent of operation. Clock signal is usually used in synchronous circuits to play the role of timer to ensure that related electronic components can operate synchronously. For high-speed interface chips, the duty cycle of the internal high-speed clock is relatively high, and it is usually necessary to control the duty cycle of the high-speed clock signal to be stable at about 50%.

[0003] In the prior art, in order to achieve this process, a duty cycle detection and calibration circuit is usually set behind the clock signal generating circuit. For example, Chinese patent CN202010884835.3 discloses a precise clock signal duty cycle correction circuit, which extracts the DC component of the output signal by using a charge pump and a low-pass filter by setting negative feedback in the duty cycle adjustment loop and feeds it back to the waveform correction module. The waveform correction module adjusts the duty cycle of the input clock signal by comparing the relative size of the feedback voltage and the reference voltage, and outputs an adjusted precise 50% duty cycle clock signal.

[0004] However, during the actual implementation process, the inventors found that in this type of circuit, since a comparator needs to be introduced to compare the signal, and the comparator itself is prone to a certain device mismatch, an additional mismatch voltage is introduced. This voltage will directly affect the comparison result, thereby causing the calibration code generated by the subsequent digital circuit to deviate, affecting the accuracy of the duty cycle adjustment. Summary of the invention

[0005] In view of the above problems existing in the prior art, a high-speed clock duty cycle calibration circuit is now provided.

[0006] The specific technical solutions are as follows:

[0007] A high-speed clock duty cycle calibration circuit, comprising:

[0008] A duty cycle adjustment module, wherein a first input end of the duty cycle adjustment module is connected to an external clock generation circuit, and an output end of the duty cycle adjustment module is connected to an external functional circuit;

[0009] A feedback module, wherein an input end of the feedback module is connected to an output end of the duty cycle adjustment module, and an output end of the feedback module is connected to a second input end of the duty cycle adjustment module;

[0010] The duty cycle adjustment module adjusts the duty cycle of the clock signal generated by the clock generation circuit to form an adjusted clock signal;

[0011] The feedback module generates a duty cycle calibration code according to the adjustment clock signal and the inverted clock signal input in sequence, and the duty cycle adjustment module performs duty cycle adjustment according to the duty cycle calibration code.

[0012] On the other hand, the feedback module comprises:

[0013] An inverting control module, wherein the inverting control module receives the inputted adjusting clock signal and outputs the adjusting clock signal or the inverted clock signal according to the number of cycles of the adjusting clock signal currently received;

[0014] A first comparator, wherein a non-inverting input terminal of the first comparator is connected to a reference power supply module, and a reverse input terminal of the first comparator is connected to an output terminal of the first comparator;

[0015] A signal generating module, wherein the input end of the signal generating module is connected to the output end of the first comparator, and the output end of the signal generating module is the output end of the feedback module.

[0016] On the other hand, the reverse control module includes:

[0017] A switching module, wherein the input end of the switching module is the input end of the inversion control module, and the switching module selects to output the adjustment clock signal or the inversion clock signal according to the cycle counting result;

[0018] A first resistor, wherein a first end of the first resistor is connected to the switching module, and a second end of the first resistor is connected to an output end of the inverting control module;

[0019] A first capacitor, wherein a first end of the first capacitor is connected to the second end of the first resistor, and a second end of the first capacitor is grounded.

[0020] On the other hand, the switching module includes:

[0021] A counting module, wherein an input end of the counting module is connected to an input end of the switching module, and the counting module counts according to a rising edge or a falling edge of the input adjustment clock signal to obtain the cycle counting result;

[0022] A first branch, an output end of the first branch is connected to an output end of the switching module;

[0023] a second branch, wherein an output end of the second branch is connected to an output end of the switching module;

[0024] The second branch is connected in series with a first inverter;

[0025] A switch module, wherein an input end of the switch module is connected to the counting module, and an output end of the switch module is respectively connected to an input end of the first branch and an input end of the second branch;

[0026] The switch module selects to switch to the first branch or the second branch according to the cycle counting result generated by the counting module.

[0027] On the other hand, the reference power module comprises:

[0028] a second resistor, wherein a first end of the second resistor is connected to an external power supply, and a second end of the second resistor is connected to an output end of the reference power supply module;

[0029] A third resistor, wherein a first end of the third resistor is connected to the second end of the second resistor, and a second end of the third resistor is grounded.

[0030] On the other hand, the power supply voltage of the external power supply is the same as the peak voltage of the clock signal;

[0031] The second resistor and the third resistor have the same resistance value.

[0032] On the other hand, the duty cycle adjustment module includes:

[0033] At least one duty cycle controller, wherein a first input terminal of the duty cycle controller is connected to a first input terminal of the duty cycle adjustment module, a second input terminal of the duty cycle controller is connected to a second input terminal of the duty cycle adjustment module, and an output terminal of the duty cycle controller is connected to an output terminal of the duty cycle adjustment module;

[0034] A second capacitor, wherein a first end of the second capacitor is connected to the output end of the duty cycle controller, and a second end of the second capacitor is grounded.

[0035] On the other hand, the duty cycle calibration code includes a P-type switch tube control signal and an N-type switch tube control signal, and the second input end includes a P-type switch tube input end and an N-type switch tube input end;

[0036] The duty cycle controller comprises:

[0037] A P-type switch tube, wherein the input end of the P-type switch tube is connected to an external power supply circuit, and the gate of the P-type switch tube is connected to the input end of the P-type switch tube;

[0038] A first switch tube, wherein an input end of the first switch tube is connected to an output end of the P-type switch tube, and a gate of the first switch tube is connected to the first input end;

[0039] a second switch tube, wherein an input end of the second switch tube is connected to an output end of the first switch tube, and a gate of the second switch tube is connected to the first input end;

[0040] An N-type switch tube, wherein the input end of the N-type switch tube is connected to the input end of the second switch tube, the gate of the N-type switch tube is connected to the input end of the N-type switch tube, and the output end of the N-type switch tube is grounded;

[0041] A third capacitor, a first end of the third capacitor is connected to the output end of the first switch tube, and a second end of the third capacitor is grounded;

[0042] A second inverter, wherein an input end of the second inverter is connected to a first end of the third capacitor, and an output end of the second inverter is connected to an output end of the duty cycle controller.

[0043] The above technical solution has the following advantages or beneficial effects:

[0044] In view of the problem that the mismatch voltage introduced by the comparator can easily cause the duty cycle to deviate in the duty cycle calibration circuit in the prior art, the adjustment clock signal of the input feedback module is changed in this scheme, and two adjacent groups of adjustment clock signals are selected to be inverted before comparison and calibration code generation. The mismatch voltage that may be generated in the comparison process is eliminated by inverting the adjustment clock signal, thereby improving the accuracy of duty cycle calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The embodiments of the present invention will be described more fully with reference to the attached drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0046] Figure 1 is an overall schematic diagram of an embodiment of the present invention;

[0047] Figure 2 Schematic diagram of feedback module 2 in an embodiment of the present invention;

[0048] Figure 3 It is a schematic diagram of comparator signal output in the prior art;

[0049] Figure 4 is a schematic diagram of a comparator signal output in an embodiment of the present invention;

[0050] Figure 5 Schematic diagram of an inverting control module in an embodiment of the present invention;

[0051] Figure 6 A schematic diagram of a switching module in an embodiment of the present invention;

[0052] Figure 7A schematic diagram of a reference power supply module in an embodiment of the present invention;

[0053] Figure 8 A schematic diagram of a duty cycle adjustment module in an embodiment of the present invention;

[0054] Fig. 9 Schematic diagram of a duty cycle controller in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0057] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0058] The present invention comprises:

[0059] A high-speed clock duty cycle calibration circuit, comprising:

[0060] A duty cycle adjustment module 1, wherein a first input end of the duty cycle adjustment module 1 is connected to an external clock generation circuit clk, and an output end of the duty cycle adjustment module 1 is connected to an external functional circuit 3;

[0061] Feedback module 2, where the input end of the feedback module 2 is connected to the output end of the duty cycle adjustment module 1, and the output end of the feedback module 2 is connected to the second input end of the duty cycle adjustment module;

[0062] The duty cycle adjustment module 1 adjusts the duty cycle of the clock signal generated by the clock generation circuit to form an adjusted clock signal;

[0063] The feedback module 2 generates a duty cycle calibration code according to the sequentially input adjustment clock signal and the inverted inverted clock signal, and the duty cycle adjustment module performs duty cycle adjustment according to the duty cycle calibration code.

[0064] Specifically, in order to solve the problem that the duty cycle calibration circuit in the prior art is prone to deviation in the actual generated duty cycle due to the mismatch voltage in the comparator part, in the present embodiment, by improving the feedback module 2, when two groups of adjustment clock signals are received in sequence, one group of the adjustment clock signals is inverted to generate an inverted clock signal, and the inverted clock signal and the adjustment clock signal are compared in sequence, thereby avoiding the problem that the output signal flipping time is easily deviated due to device mismatch when the comparator part relies only on the adjustment clock signal in a single direction for comparison, thereby improving the accuracy of the comparison.

[0065] In one embodiment, Figure 2 As shown, the feedback module 2 includes:

[0066] An inverting control module 21, the inverting control module 21 receives an input adjustment clock signal, and outputs an adjustment clock signal or an inverted clock signal according to the number of cycles of the currently received adjustment clock signal;

[0067] A first comparator 22, wherein the same-direction input terminal of the first comparator 22 is connected to the reference power module 23, and the reverse input terminal of the first comparator 22 is connected to the output terminal of the first comparator;

[0068] The signal generating module 24 has an input end connected to the output end of the first comparator 22 , and an output end of the signal generating module is an output end of the feedback module.

[0069] Specifically, in order to achieve a better duty cycle calibration effect, in this embodiment, an inverting control module 21, a first comparator 22 and a signal generating module 23 are sequentially arranged in the feedback module 2. Among them, the first comparator is used to compare the input adjustment clock signal or the inverted clock signal with the reference voltage output by the reference power module 23, so as to realize sampling and output to the signal generating module 24, and the signal generating module 24 times the sampled signal, determines its duty cycle, and generates a corresponding duty cycle calibration code and sends it to the duty cycle adjusting module 1. Among them, since the first comparator 22 is in the prior art, the problem of device mismatch is prone to occur.

[0070] like Figure 3As shown, when the clock signal Clk1 is sequentially input into the inverting end of the comparator, the corresponding reference voltage Ref1 is input into the same direction end. Ideally, the first output signal Comp1 of the comparator should have the same phase as the clock signal Clk1. However, due to the mismatch voltage of the device, the actual flip time of the level of the comparator may be earlier / latter than the ideal state. For example, in one embodiment, the reference voltage Ref1 is 500mv, but the comparator may flip at a level of 498mv. This will cause the duty cycle of the actual output signal Comp2 to deviate from the actual duty cycle of the clock signal Clk1, which in turn causes a deviation in the duty cycle calibration code generated by the subsequent signal generation module 24.

[0071] To solve the above problems, the present embodiment introduces an inversion control module 21, which can count the input clock signal and sequentially select the output adjustment clock signal or the inverted inverted clock signal, and is composed of: Figure 4 The Clk2 shown in the figure, the dot-dash line separation part is the inversion point. When the inversion control module 21 is not added, the comparator may flip ahead of schedule at the rising edge relative to the ideal state; correspondingly, a delayed flip will occur at the falling edge. Therefore, by adding the inversion control module 21, two inverted clock signals are input successively, and the part of the offset time can be eliminated by taking the average of the flipping time, thereby achieving a more accurate detection effect of the actual duty ratio, which is convenient for the subsequent signal generation module 24 to generate an accurate duty ratio calibration code.

[0072] In one embodiment, Figure 5 As shown, the inversion control module 21 includes:

[0073] A switching module 211, the input end of the switching module 211 is the input end of the inverting control module, and the switching module 211 selects to output the adjustment clock signal or the inverted clock signal according to the cycle counting result;

[0074] A first resistor R1, a first end of the first resistor R1 is connected to the switching module 211, and a second end of the first resistor is connected to the output end of the inverting control module;

[0075] A first capacitor C1 , wherein a first end of the first capacitor C1 is connected to a second end of the first resistor R1 , and a second end of the first capacitor C1 is grounded.

[0076] Specifically, in order to achieve a better input effect, in this embodiment, in the inverting control module 21, a first resistor R1 and a first capacitor C1 are added to form an RC oscillator, and a better input process is achieved by charging the first capacitor C1. At the same time, the switching module 211 selects the output adjustment clock signal or the inverted clock signal according to the cycle counting result, so that the subsequent stage can accurately detect the duty cycle.

[0077] In one embodiment, Figure 6 As shown, the switching module 211 includes:

[0078] A counting module 2111, wherein the input end of the counting module 2111 is connected to the input end of the switching module 211, and the counting module 2111 counts according to the rising edge or falling edge of the input adjustment clock signal to obtain a cycle counting result;

[0079] A first branch 2112, an output end of the first branch 2112 is connected to an output end of the switching module;

[0080] A second branch 2113, an output end of the second branch 2113 is connected to an output end of the switching module;

[0081] The second branch 2113 is serially connected with a first inverter INV1;

[0082] A switch module 2114, wherein a first input end of the switch module 2114 is connected to the counting module 2111, a second input end of the switch module 2114 is connected to an input end of the switching module 211, and an output end of the switch module 2114 is respectively connected to an input end of the first branch 2112 and an input end of the second branch 2113;

[0083] The switch module 2114 selects to switch to the first branch 2112 or the second branch 2113 according to the cycle counting result generated by the counting module.

[0084] Specifically, in order to achieve a better switching effect, in this embodiment, a first branch 2112 that does not include an inverter and is used to transmit the adjustment clock signal and a second branch 2113 that is provided with a first inverter INV1 and is used to transmit the inverted clock signal are respectively provided, and the control signal is selected to flow into the first branch 2112 or the second branch 2113 through the switch module 2114. The switch module 2114 is controlled by the counting module 2111, and is flipped based on the rising edge or falling edge of the input adjustment clock signal, thereby realizing the above-mentioned inversion control process.

[0085] In one embodiment, Figure 7 As shown, the reference power supply module 23 includes:

[0086] A second resistor R2, wherein a first end of the second resistor R2 is connected to an external power source VDD, and a second end of the second resistor R2 is connected to an output end of the reference power source module 23;

[0087] The third resistor R3 has a first end connected to the second end of the second resistor R2 and a second end of the third resistor R3 is grounded.

[0088] The power supply voltage of the external power supply VDD is the same as the peak voltage of the clock signal;

[0089] The second resistor R2 and the third resistor R3 have the same resistance value.

[0090] Specifically, to achieve a better duty cycle detection effect, in this embodiment, a voltage divider circuit consisting of a second resistor R2 and a third resistor R3 is provided. The reference voltage input to the first comparator 22 is controlled near 50% of the peak voltage through resistor voltage division, thereby achieving effective extraction of the duty cycle.

[0091] In one embodiment, Figure 8 As shown, the duty cycle adjustment module 1 includes:

[0092] At least one duty cycle controller 11, a first input terminal of the duty cycle controller 11 is connected to a first input terminal of the duty cycle adjustment module, a second input terminal of the duty cycle controller 11 is connected to a second input terminal of the duty cycle adjustment module, and an output terminal of the duty cycle controller 11 is connected to an output terminal of the duty cycle adjustment module;

[0093] A second capacitor C2, a first end of the second capacitor C2 is connected to the output end of the duty cycle controller 11, and a second end of the second capacitor C2 is grounded.

[0094] In one embodiment, the duty cycle calibration code includes a P-type switch tube control signal and an N-type switch tube control signal, and the second input end includes a P-type switch tube input end and an N-type switch tube input end;

[0095] like Fig. 9 As shown, the duty cycle controller 11 includes:

[0096] A P-type switch tube P1, wherein the input end of the P-type switch tube P1 is connected to an external power supply circuit, and the gate of the P-type switch tube P1 is connected to the input end of the P-type switch tube;

[0097] A first switch tube MOS1, wherein an input end of the first switch tube MOS1 is connected to an output end of the P-type switch tube P1, and a gate of the first switch tube MOS1 is connected to a first input end;

[0098] A second switch tube MOS2, wherein an input end of the second switch tube MOS2 is connected to an output end of the first switch tube MOS1, and a gate of the second switch tube MOS2 is connected to the first input end;

[0099] An N-type switch tube N1, the input end of the N-type switch tube N1 is connected to the input end of the second switch tube MOS2, the gate of the N-type switch tube N1 is connected to the input end of the N-type switch tube, and the output end of the N-type switch tube N1 is grounded;

[0100] A third capacitor C3, a first end of the third capacitor C3 is connected to the output end of the first switch tube MOS1, and a second end of the third capacitor C3 is grounded;

[0101] The second inverter INV2 has an input end connected to the first end of the third capacitor C3, and an output end of the second inverter INV2 connected to the output end of the duty cycle controller.

[0102] Specifically, in order to achieve a better duty cycle calibration effect, in this embodiment, the P-type switch control signal Pnode and the N-type switch control signal Nnode are respectively generated by the signal generation module 24, and then the duty cycle controller 11 is controlled. The adjustment clock signal Clk flows into the gates of the first switch tube MOS1 and the second switch tube MOS2 respectively, and at the same time, the output of the actual clock signal is adjusted by controlling the on / off of the P-type switch tube P1 and the N-type switch tube N1 at both ends, and is charged by the third capacitor C3 and output via the second inverter INV2, thereby achieving a better duty cycle adjustment process.

[0103] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed clock duty cycle calibration circuit, characterized in that: include: A duty cycle adjustment module, wherein a first input end of the duty cycle adjustment module is connected to an external clock generation circuit, and an output end of the duty cycle adjustment module is connected to an external functional circuit; A feedback module, wherein an input end of the feedback module is connected to an output end of the duty cycle adjustment module, and an output end of the feedback module is connected to a second input end of the duty cycle adjustment module; The duty cycle adjustment module adjusts the duty cycle of the clock signal generated by the clock generation circuit to form an adjusted clock signal; The feedback module generates a duty cycle calibration code according to the adjustment clock signal and the inverted clock signal input in sequence, and the duty cycle adjustment module performs duty cycle adjustment according to the duty cycle calibration code.

2. The duty cycle calibration circuit according to claim 1, characterized in that: The feedback module comprises: an inverting control module, wherein the inverting control module receives the inputted adjusting clock signal and outputs the adjusting clock signal or the inverted clock signal according to the number of cycles of the adjusting clock signal currently received; A first comparator, wherein a non-inverting input terminal of the first comparator is connected to a reference power supply module, and a reverse input terminal of the first comparator is connected to an output terminal of the first comparator; A signal generating module, wherein the input end of the signal generating module is connected to the output end of the first comparator, and the output end of the signal generating module is the output end of the feedback module.

3. The duty cycle calibration circuit according to claim 2, characterized in that: The reverse control module comprises: A switching module, wherein the input end of the switching module is the input end of the inversion control module, and the switching module selects to output the adjustment clock signal or the inversion clock signal according to the cycle counting result; A first resistor, wherein a first end of the first resistor is connected to the switching module, and a second end of the first resistor is connected to an output end of the inverting control module; A first capacitor, wherein a first end of the first capacitor is connected to the second end of the first resistor, and a second end of the first capacitor is grounded.

4. The duty cycle calibration circuit according to claim 3, characterized in that: The switching module comprises: A counting module, wherein an input end of the counting module is connected to an input end of the switching module, and the counting module counts according to a rising edge or a falling edge of the input adjustment clock signal to obtain the cycle counting result; A first branch, an output end of the first branch is connected to an output end of the switching module; a second branch, wherein an output end of the second branch is connected to an output end of the switching module; The second branch is connected in series with a first inverter; A switch module, wherein a first input end of the switch module is connected to the counting module, a second input end of the switch module is connected to an input end of the switching module, and an output end of the switch module is respectively connected to an input end of the first branch and an input end of the second branch; The switch module selects to switch to the first branch or the second branch according to the cycle counting result generated by the counting module.

5. The duty cycle calibration circuit according to claim 2, characterized in that: The reference power supply module comprises: a second resistor, wherein a first end of the second resistor is connected to an external power supply, and a second end of the second resistor is connected to an output end of the reference power supply module; A third resistor, wherein a first end of the third resistor is connected to the second end of the second resistor, and a second end of the third resistor is grounded.

6. The duty cycle calibration circuit according to claim 5, characterized in that: The power supply voltage of the external power supply is the same as the peak voltage of the clock signal; The second resistor and the third resistor have the same resistance value.

7. The duty cycle calibration circuit according to claim 1, characterized in that: The duty cycle adjustment module comprises: At least one duty cycle controller, wherein a first input terminal of the duty cycle controller is connected to a first input terminal of the duty cycle adjustment module, a second input terminal of the duty cycle controller is connected to a second input terminal of the duty cycle adjustment module, and an output terminal of the duty cycle controller is connected to an output terminal of the duty cycle adjustment module; A second capacitor, wherein a first end of the second capacitor is connected to the output end of the duty cycle controller, and a second end of the second capacitor is grounded.

8. The duty cycle calibration circuit according to claim 7, characterized in that: The duty cycle calibration code includes a P-type switch tube control signal and an N-type switch tube control signal, and the second input end includes a P-type switch tube input end and an N-type switch tube input end; The duty cycle controller comprises: A P-type switch tube, wherein the input end of the P-type switch tube is connected to an external power supply circuit, and the gate of the P-type switch tube is connected to the input end of the P-type switch tube; A first switch tube, wherein an input end of the first switch tube is connected to an output end of the P-type switch tube, and a gate of the first switch tube is connected to the first input end; a second switch tube, wherein an input end of the second switch tube is connected to an output end of the first switch tube, and a gate of the second switch tube is connected to the first input end; An N-type switch tube, wherein the input end of the N-type switch tube is connected to the input end of the second switch tube, the gate of the N-type switch tube is connected to the input end of the N-type switch tube, and the output end of the N-type switch tube is grounded; A third capacitor, a first end of the third capacitor is connected to the output end of the first switch tube, and a second end of the third capacitor is grounded; A second inverter, wherein an input end of the second inverter is connected to a first end of the third capacitor, and an output end of the second inverter is connected to an output end of the duty cycle controller.

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