CMOS-CML converter, semiconductor device and electronic apparatus including the same

Abstract

A complementary metal oxide semiconductor (CMOS)-current mode logic (CML) converter, a semiconductor device including the same, and an electronic apparatus are provided. A CMOS-CML converter for converting a CMOS input signal into a CML output signal, the CMOS-CML converter comprising: a low pass filter comprising a fixed resistor and a first fixed capacitor; and a swing width control circuit configured to adjust a swing width of a voltage swing of the CML output signal based on a common mode level, in which the swing width control circuit includes: a second fixed capacitor; and a variable capacitor, the variable capacitor comprising a capacitor array.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly, to a complementary metal oxide semiconductor (CMOS)-current mode logic (CML) converter, a semiconductor device including the CMOS-CML converter, and an electronic device. Background Art

[0002] In data transmission systems, semiconductor devices are becoming more and more integrated, and their sizes are becoming smaller and smaller. Therefore, when designing semiconductor devices, various aspects of the semiconductor devices, such as operating speed, power consumption, and noise, may be considered. The characteristics of CMOS signals and CML signals may be different from each other. Therefore, when designing semiconductor devices and electronic devices including the semiconductor devices, it may be beneficial to combine CMOS signal domain circuits and CML signal domain circuits to compensate for their deficiencies. Summary of the invention

[0003] Provided are a complementary metal oxide semiconductor (CMOS)-current mode logic (CML) converter capable of adjusting a swing width of a CML signal without changing the waveform characteristics of the signal, a semiconductor device including the CMOS-CML converter, and an electronic device.

[0004] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0005] According to one aspect of the present disclosure, a complementary metal oxide semiconductor (CMOS)-current mode logic (CML) converter is used to convert a CMOS input signal into a CML output signal, the CMOS-CML converter comprising: a low-pass filter, the low-pass filter comprising a fixed resistor and a first fixed capacitor; and a swing width control circuit, the swing width control circuit being configured to adjust the swing width of the voltage swing of the CML output signal based on a common mode level, wherein the swing width control circuit comprises: a second fixed capacitor; and a variable capacitor, the variable capacitor comprising a capacitor array.

[0006] According to one aspect of the present disclosure, a semiconductor device includes a complementary metal oxide semiconductor (CMOS)-current mode logic (CML) converter, the CMOS-CML converter being used to convert a CMOS input signal into a CML output signal, wherein the CMOS-CML converter includes: a low-pass filter configured to generate an internal signal by attenuating a component of the CMOS input signal; and a swing width control circuit configured to generate the CML output signal by adjusting a swing width of a voltage swing of the internal signal, wherein the swing width control circuit includes: a fixed capacitor; and a variable capacitor, the variable capacitor including a capacitor array.

[0007] According to one aspect of the present disclosure, an electronic device includes: a complementary metal oxide semiconductor (CMOS) signal domain circuit, the CMOS signal domain circuit being configured to operate based on a CMOS signal; and a semiconductor device, the semiconductor device including: a CML signal domain circuit configured to operate using a current mode logic (CML) signal and a CMOS-CML converter that converts a CMOS input signal into a CML output signal, wherein the CMOS-CML converter includes: a low-pass filter, the low-pass filter includes a fixed resistor and a first fixed capacitor; and a swing width control circuit, wherein the swing width control circuit includes a second fixed capacitor and a variable capacitor, the variable capacitor including a capacitor array. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram showing an electronic device including a semiconductor device according to an embodiment;

[0010] Figure 2 is a circuit diagram of a complementary metal oxide semiconductor (CMOS)-current mode logic (CML) converter in a semiconductor device according to an embodiment;

[0011] Figure 3A is a graph for explaining the operation of a CMOS-CML converter according to a comparative example;

[0012] Figure 3B is a graph for explaining the operation of the CMOS-CML converter according to the embodiment;

[0013] Figure 4 is a circuit diagram of a swing width control circuit in a CMOS-CML converter according to an embodiment;

[0014] Figure 5 is a circuit diagram of a CMOS-CML converter in a semiconductor device according to an embodiment;

[0015] Figure 6 is a circuit diagram of a swing width control circuit in a CMOS-CML converter according to an embodiment;

[0016] Figure 7 is a block diagram showing a semiconductor device according to an embodiment;

[0017] Figure 8 is a diagram showing a CMOS signal domain circuit and a CML signal domain circuit;

[0018] Fig. 9 is a circuit diagram of a CMOS-CML converter in a semiconductor device according to an embodiment;

[0019] Fig.10 is a cross-sectional view showing a memory device which is a semiconductor device in an electronic device according to an embodiment;

[0020] Fig.11 is a block diagram illustrating a system on chip (SoC) in an electronic device according to an embodiment;

[0021] Fig.12 is a diagram showing a system to which a semiconductor device according to an embodiment can be applied;

[0022] Fig.13 is a diagram showing a data center to which the semiconductor device according to the embodiment can be applied. DETAILED DESCRIPTION

[0023] Hereinafter, various embodiments are described with reference to the accompanying drawings.

[0024] According to the tradition of the art, the embodiment is described and shown in the accompanying drawings in the form of functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors, etc., software (e.g., microcodes) can be used to program blocks, units and / or modules to perform various functions discussed herein, and blocks, units and / or modules can be optionally driven by firmware and / or software. Optionally, each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions. In addition, without departing from the scope, each block, unit and / or module of the embodiment can be physically separated into two or more interacting and discrete blocks, units or modules. Furthermore, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope.

[0025] Figure 1 is a block diagram showing an electronic device 100 including a semiconductor device 10 according to an embodiment. Figure 2 is a circuit diagram of a complementary metal oxide semiconductor (CMOS)-current mode logic (CML) converter 11 in a semiconductor device 10 according to an embodiment.

[0026] refer to Figure 1 , the electronic device 100 may include a smart phone, a smart watch, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet personal computer (PC), a laptop, a netbook, a television, a video game, an automotive device, etc. However, the embodiment is not limited thereto, and the electronic device 100 may include any other electronic device that can process data.

[0027] The electronic device 100 may include a semiconductor device 10. The semiconductor device 10 may be included in the electronic device 100, and may receive a CMOS signal from a device outside the semiconductor device 10. In addition, the semiconductor device 10 may receive a CMOS signal from a circuit outside the electronic device 100. For example, the semiconductor device 10 may receive a CMOS signal from a processor. For example, the processor may include a processing unit such as a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), an encryption processing unit, and a physical processing unit, and a machine learning processing unit.

[0028] The semiconductor device 10 may include an interface circuit I / F for communicating with an external device, and the interface circuit I / F may include a CMOS-CML converter 11 that converts a CMOS signal into a CML signal. The CML signal may refer to a signal used in a CML signal domain circuit inside the semiconductor device 10. The desired characteristics of the CML signal may vary depending on the characteristics of the CML signal domain circuit included in the semiconductor device 10. In some embodiments, the CMOS-CML converter 11 may not be included in the interface circuit I / F. For example, the CMOS-CML converter 11 may be an internal component of the semiconductor device 10 instead of the interface circuit I / F.

[0029] Here, the CMOS signal may include a signal that swings between a power supply voltage and a ground voltage, and the CML signal may include a signal that swings with a specific swing width based on a determined CML reference level (which may be referred to as a common mode level). For example, the swing width of the CML signal may refer to the difference between the highest voltage of the CML signal and the lowest voltage of the CML signal. The swing width of the CML signal may be designed to be smaller than the swing width of the CMOS signal, and the CML signal may be used as a high-frequency clock signal capable of high-speed switching.

[0030] refer to Figure 1 and Figure 2 The CMOS-CML converter 11 may receive and convert a CMOS input signal VCMOS and output a CML output signal VCML. The CMOS-CML converter 11 may include a low pass filter 111 and a swing width control circuit 113.

[0031] The low pass filter 111 may include an RC filter including a resistor R and a capacitor C. Here, the resistor R may include a fixed resistor, and the capacitor C may include a fixed capacitor. Therefore, the resistance of the resistor R and the capacitance of the capacitor C may be constant.

[0032] Since the cutoff frequency of the low-pass filter 111 can be determined according to the resistance of the resistor R and the capacitance of the capacitor C, the cutoff frequency of the low-pass filter 111 may not change and may have a constant value. The low-pass filter 111 may generate an internal signal INS by attenuating a signal having a frequency higher than a cutoff frequency in the CMOS input signal VCMOS, and the internal signal INS may include a CML signal. For example, the CMOS input signal VCMOS may have a constant frequency (eg, Figure 3B The internal signal INS may have a square wave shape that switches between the power supply voltage and the ground voltage. For example, the internal signal INS may have a triangular waveform with a constant frequency fin and a constant swing width.

[0033] The swing width control circuit 113 may receive the internal signal INS and adjust the swing width of the internal signal INS to generate the CML output signal VCML. The swing width control circuit 113 may include a fixed capacitor CA and a variable capacitor CB. The swing width SWF of the CML output signal VCML may be calculated according to the following formula 1. Here, SWF may represent the swing width of the CML output signal VCML, and SWP may represent the swing width of the internal signal INS.

[0034]

[0035] The swing width control circuit 113 can generate the CML output signal VCML by adjusting the swing width of the internal signal INS while maintaining the shape of the internal signal INS. Therefore, the CML output signal VCML can have a triangular waveform with a constant frequency fin and a constant swing width.

[0036] Therefore, the semiconductor device 10 can adjust the swing width SWF of the CML output signal VCML by adjusting the capacitance of the variable capacitor CB. In an embodiment, the capacitance of the variable capacitor CB can be set to a predetermined value according to the specifications of the semiconductor device 10. In addition, in an embodiment, the capacitance of the variable capacitor CB within the semiconductor device 10 can be adjusted by the semiconductor device 10 or any element included therein according to the operation result of the internal circuit of the semiconductor device 10 that operates using the CML output signal VCML. In addition, in an embodiment, the capacitance of the variable capacitor CB can be adjusted by a command outside the semiconductor device 10 according to the operation result of the internal circuit of the semiconductor device 10 that operates using the CML output signal VCML.

[0037] According to an embodiment, a semiconductor device 10 and an electronic device 100 including the semiconductor device 10 may include a CMOS-CML converter 11 including a low-pass filter 111 and a swing width control circuit 113. Therefore, a CMOS-CML conversion operation of removing high-frequency harmonic components of a CMOS input signal VCMOS may be performed by the low-pass filter 111. In addition, a swing width of a CML output signal VCML may be adjusted by the swing width control circuit 113 without changing the waveform characteristics of the signal. Therefore, the CMOS-CML converter 11 may generate a CML output signal VCML having a shape relatively close to a sine wave.

[0038] Figure 3A is a graph for explaining the operation of a CMOS-CML converter according to a comparative example. Figure 3B is a graph for explaining the operation of the CMOS-CML converter 11 according to the embodiment.

[0039] refer to Figure 3A , the CMOS-CML converter according to the comparative example may include a low-pass filter, which may be an RC filter including a variable resistor and a variable capacitor. The CMOS-CML converter according to the comparative example may remove high-frequency harmonic components in the CMOS-CML conversion process. However, in order to adjust the swing width (or slew rate) of the CML output signal of the CMOS-CML converter, the resistance of the variable resistor or the capacitance of the variable capacitor may be adjusted. For example, if the resistance of the variable resistor is R and the capacitance of the variable capacitor is C (corresponding to Figure 3A solid line in the figure), then the variable resistor can be changed to R1 and the variable capacitor to C1 (corresponding to Figure 3A In addition, the swing width can be reduced by changing the resistance of the variable resistor to R2 and the capacitance of the variable capacitor to C2 (corresponding to Figure 3A to increase the swing width.

[0040] However, in the comparative example, when the resistance of the variable resistor or the capacitance of the variable capacitor is adjusted to control the swing width of the CML output signal of the CMOS-CML converter, in addition to the change in the swing width of the CML output signal, the cutoff frequency of the RC filter also changes. Therefore, the bandwidth of the RC filter also changes, and the harmonic characteristics also change. In other words, the high-frequency component of the CML output signal changes. For example, in the case where the resistance of the variable resistor is R and the capacitance of the variable capacitor is C (corresponding to Figure 3A solid line in the figure), when the resistance of the variable resistor and the capacitance of the variable capacitor are changed to R2 and C2 respectively (corresponding to Figure 3A The cutoff frequency can have a value And the phase of the CML output signal can be changed, resulting in a change in the waveform from a triangular wave. In addition, the time point at which the CML output signal reaches the common mode level can be changed. Here, the common mode level can refer to the midpoint of the peak-to-peak of the CML output signal. In a semiconductor device including a CMOS-CML converter according to a comparative example, an internal circuit using the CML output signal can operate according to the common mode level of the CML output signal, and thus it may be difficult to optimize the CML output signal.

[0041] On the contrary, reference Figure 2 and Figure 3B The CMOS-CML converter 11 according to the embodiment of the present disclosure may independently include a low-pass filter 111 for removing high-frequency harmonic components of the CMOS input signal VCMOS and a swing width control circuit 113 for adjusting the swing width of the CML output signal VCML. Therefore, the cutoff frequency of the low-pass filter 111 may have a constant value. Therefore, the time point at which the CML output signal VCML reaches the common mode level can be kept constant without changing the shape or phase of the CML output signal VCML. In addition, the magnitude of the CML output signal VCML can be changed only by adjusting the capacitance of the variable capacitor CB of the swing width control circuit 113.

[0042] For example, in the CMOS-CML converter according to the comparative example, the swing width of the CML output signal varies depending on the gain value change of the bandwidth of the RC filter and the signal frequency fin of the CMOS input signal. However, in the CMOS-CML converter 11 according to the embodiment of the present disclosure, the swing width of the CML output signal VCML is changed only by the capacitance ratio of the fixed capacitor CA and the variable capacitor CB of the swing width control circuit 113. Therefore, the user can obtain the accurate size of the CML output signal VCML at a desired step interval.

[0043] Figure 4 is a circuit diagram of the swing width control circuit 113 in the CMOS-CML converter 11 according to the embodiment.

[0044] refer to Figure 4 , the swing width control circuit 113 may receive the internal signal INS and adjust the swing width of the internal signal INS to generate the CML output signal VCML. The swing width control circuit 113 may include a fixed capacitor CA and a variable capacitor CB. Here, the variable capacitor CB may include: a connection capacitor C0 and a plurality of capacitors (e.g., first to nth capacitors C1 to Cn (where n is a natural number)) included in the capacitor array, and a plurality of switches (e.g., first to nth switches SW1 to SWn).

[0045] In an embodiment, a first end of each of the first to nth capacitors C1 to Cn may be connected to the output node NO, and a second end of each of the first to nth capacitors C1 to Cn may be connected to a corresponding switch among the first to nth switches SW1 to SWn. Each of the first to nth switches SW1 to SWn may connect a second end of a corresponding capacitor among the first to nth capacitors C1 to Cn to a ground voltage.

[0046] Based on the on / off state of the first to nth switches SW1 to SWn, each of the first to nth capacitors C1 to Cn may be connected between the output node NO and the ground voltage and may be connected in parallel to the connection capacitor C0. The magnitude of the CML output signal VCML may be controlled by an n-bit switch control signal for controlling the first to nth switches SW1 to SWn.

[0047] In an embodiment, each of the first capacitor C1 to the nth capacitor Cn may have the same capacitance. In addition, in an embodiment, the capacitance of one or more of the first capacitor C1 to the nth capacitor Cn may be different from each other. The capacitance of the first capacitor C1 to the nth capacitor Cn may be freely modified.

[0048] In an embodiment, when the connection capacitor C0 has a reference capacitance CR, the values ​​of the first capacitor C1 to the nth capacitor Cn may be CR, 2CR, 4CR, . . . , 2 n-1 ×CR. For example, the capacitances of the first capacitor C1 to the nth capacitor Cn may sequentially increase by two times (eg, sequentially doubled capacitances). For example, the first capacitor to the nth capacitor may have capacitances corresponding to a geometric sequence having a common ratio of 2.

[0049] As the first switch SW1 to the nth switch SWn are sequentially changed from the off state to the on state, the signal attenuation rate may be reduced, and the signal attenuation rate may refer to the ratio of the swing width of the CML output signal VCML to the swing width of the internal signal INS. For example, based on the lower bits of the n-bit switch control signals sequentially input from the first switch SW1 to the nth switch SWn, when the n-bit switch control signals are 00…000, 00…001, 00…010, 00…011, …, 11…111, the values ​​of the signal attenuation rates may be respectively

[0050] In an embodiment, the on / off states of the first to n-th switches SW1 to SWn may be predetermined according to the specifications of the semiconductor device 10. For example, based on the characteristics of the circuit that operates using the CML output signal VCML, the on / off states of the first to n-th switches SW1 to SWn may be predetermined. In addition, in an embodiment, based on the operation result of the circuit that operates using the CML output signal VCML, a switch control signal may be generated in the semiconductor device 10 to adjust the on / off states of the first to n-th switches SW1 to SWn. In addition, in an embodiment, based on the operation result of the circuit that operates using the CML output signal VCML, the on / off states of the first to n-th switches SW1 to SWn may be adjusted by a command from outside the semiconductor device 10.

[0051] Figure 5 is a circuit diagram of a CMOS-CML converter 11A that may be included in the semiconductor device 10 according to the embodiment. Figure 6 is a circuit diagram of a swing width control circuit 113A included in a CMOS-CML converter 11A according to the embodiment.

[0052] refer to Figure 5 , the CMOS-CML converter 11A may receive and convert CMOS input signals VCMOS+ and VCMOS- as differential signals, and may output CML output signals VCML+ and VCML- as differential signals. The CML output signals VCML+ and VCML- may be defined as the difference between a first CML output signal VCML+ and a second CML output signal VCML-. The CMOS-CML converter 11A may include a low pass filter 111A and a swing width control circuit 113A.

[0053] The low pass filter 111A may include an RC filter including a first resistor RA, a second resistor RB, and a capacitor C. In an embodiment, resistances of the first resistor RA and the second resistor RB may be equal to each other, but the embodiment is not limited thereto.

[0054] The swing width control circuit 113A may receive an internal signal output from the low pass filter 111A and generate CML output signals VCML+ and VCML- by adjusting the swing width of the internal signal. The internal signal may also include a differential signal. The swing width control circuit 113A may include a first fixed capacitor CA1, a second fixed capacitor CA2, and a variable capacitor CB'. In an embodiment, the capacitances of the first fixed capacitor CA1 and the second fixed capacitor CA2 may be equal to each other, but the embodiment is not limited thereto.

[0055] refer to Figure 5 and Figure 6 , the swing width control circuit 113A may include a variable capacitor CB'. Here, the variable capacitor CB' may include: a connection capacitor C0 and a plurality of capacitors (e.g., a first capacitor C1 to an nth capacitor Cn (where n is a natural number)) included in the capacitor array, and a plurality of switches (e.g., a first switch SW1 to an nth switch SWn).

[0056] Each of the first to n-th capacitors C1 to Cn may be connected to a corresponding switch among the first to n-th switches SW1 to SWn. Based on the on / off state of the first to n-th switches SW1 to SWn, each of the first to n-th capacitors C1 to Cn may be connected to the first output node NO1 and the second output node NO2, and may be connected in parallel to the connection capacitor C0. CML output signals VCML+ and VCML- as differential signals may be output according to a voltage difference between the first output node NO1 and the second output node NO2. The magnitudes of the CML output signals VCML+ and VCML- may be controlled by an n-bit switch control signal for controlling the first to n-th switches SW1 to SWn.

[0057] In an embodiment, each of the first capacitor C1 to the nth capacitor Cn may have the same capacitance. In addition, in an embodiment, the capacitance of one or more of the first capacitor C1 to the nth capacitor Cn may be different from each other. The capacitance of the first capacitor C1 to the nth capacitor Cn may be freely modified. As the number of capacitors connected in parallel with the connection capacitor C0 among the first capacitor C1 to the nth capacitor Cn increases, the capacitance of the variable capacitor CB' may increase. Therefore, the size of the CML output signals VCML+ and VCML- may be reduced, and the swing width may also be reduced.

[0058] Figure 7 is a block diagram showing a semiconductor device 10C according to the embodiment. Figure 8 is a diagram showing a CMOS signal domain circuit and a CML signal domain circuit. Figure 7 The semiconductor device 10C and the first CMOS signal domain circuit 21 and the second CMOS signal domain circuit 23 shown in FIG. Figure 1 In the electronic device 100 shown.

[0059] refer to Figure 7 , the semiconductor device 10C can receive a CMOS signal from the first CMOS signal domain circuit 21, and can transmit the CMOS signal to the second CMOS signal domain circuit 23. The first CMOS signal domain circuit 21 and the second CMOS signal domain circuit 23 can be provided in the same semiconductor device, and can include, for example, a processor.

[0060] The semiconductor device 10C may include a CMOS-CML converter 11, a CML signal domain circuit 13, and a CML-CMOS converter 15. The CMOS-CML converter 11 and the CML-CMOS converter 15 may be provided in an interface circuit (eg, Figure 1 The semiconductor device 10C can communicate with the first CMOS signal domain circuit 21 and the second CMOS signal domain circuit 23 through the interface circuit. The CMOS-CML converter 11 can correspond to Figure 2 CMOS-CML converters 11 and Figure 5 At least one of the CMOS-CML converters 11A.

[0061] The CMOS-CML converter 11 may convert a CMOS signal into a CML signal, and the CML signal domain circuit 13 may operate using the CML signal output from the CMOS-CML converter 11. In order to optimize the characteristics of the CML signal domain circuit 13 (e.g., process, voltage, and temperature (PVT) conditions, circuit structure, etc.), the swing width control circuit (e.g., Figure 2The swing width control circuit 113 or Figure 5 The variable capacitor (e.g., Figure 2 The variable capacitor CB or Figure 5 The capacitance of the variable capacitor CB′) is determined, and the characteristics of the CML signal output from the CMOS-CML converter 11, such as the swing width (or slew rate), can be determined.

[0062] The CML-CMOS converter 15 may receive a CML signal output as a result of the operation of the CML signal domain circuit 13 and may convert the received CML signal into a CMOS signal. The CML-CMOS converter 15 may convert the CML signal into a CMOS signal in a form suitable for transmission to the second CMOS signal domain circuit 23.

[0063] The swing width of a CML signal may be relatively smaller than that of a CMOS signal. Therefore, it may be relatively difficult to use a CML signal in a device that determines the logic level of data based on a voltage level. For example, it may be difficult to use a CML signal as a data signal, and therefore, a CMOS signal with a relatively large swing width may be used in a device that inputs / outputs a data signal.

[0064] refer to Figure 7 and Figure 8 At least one of the first CMOS signal domain circuit 21 and the second CMOS signal domain circuit 23 may operate using CMOS signals and may include digital circuits and logic circuits. For example, the CMOS signal domain circuit may include at least one of an inverter 811, an AND gate 812, a NAND gate 813, an OR gate 814, a NOR gate 815, an XOR gate 816, an XNOR gate 817, and the like.

[0065] The CML signal domain circuit may operate using a CML signal and may include an analog circuit. For example, the CML signal domain circuit may include at least one of a phase interpolation circuit 821 , a current-voltage converter 822 , a CML driver 823 , and the like.

[0066] The phase interpolation circuit 821 can receive multiple clock signals and perform phase interpolation operations using the multiple clock signals to generate clock signals with various interpolation phases. For example, a clock and data recovery (CDR) circuit can generate a clock signal that matches a data signal so that the data signal received by an analog front end (AFE) as a receiver circuit in the semiconductor device 10C is captured at the correct position. The CDR circuit can generate a clock signal using a phase interpolation circuit.

[0067] The CML driver 823 may include a circuit for generating a CML signal that swings at a CML level. For example, the CML driver 823 may include a first N-type transistor N1, a second N-type transistor N2, a first resistor R1, a second resistor R2, and a current source IS. The first input signal IN may be applied to the gate of the first N-type transistor N1, and the magnitude of the first current I1 flowing through the first N-type transistor N1 may be adjusted according to the first input signal IN. The second input signal INB may be applied to the gate of the second N-type transistor N2, and the magnitude of the second current I2 flowing through the second N-type transistor N2 may be adjusted according to the second input signal INB. The phases of the first input signal IN and the second input signal INB may be opposite to each other.

[0068] As an example, based on the voltage level of the first input signal IN rising to turn on the first N-type transistor N1, the voltage level of the second input signal INB may fall to turn off the second N-type transistor N2. Therefore, the first current I1 may flow continuously, but the second current I2 may not flow. As a result, the voltage level of the output signal swinging at the CML level outputted through the second output node OUTB may decrease, but the voltage level of the output signal swinging at the CML level outputted through the first output node OUT may increase.

[0069] As another example, based on the voltage level of the first input signal IN falling to turn off the first N-type transistor N1, the voltage level of the second input signal INB may rise to turn on the second N-type transistor N2. Therefore, the first current I1 may not flow, but the second current I2 may flow continuously. As a result, the voltage level of the output signal swinging at the CML level outputted through the second output node OUTB may increase, but the voltage level of the output signal swinging at the CML level outputted through the first output node OUT may decrease.

[0070] Fig. 9 is a circuit diagram of a CMOS-CML converter 11B that may be included in the semiconductor device 10 according to an embodiment.

[0071] refer to Fig. 9 The CMOS-CML converter 11B can receive and convert CMOS input signals VCMOS+ and VCMOS- as differential signals, and can output CML output signals VCML+ and VCML- as differential signals. The CMOS-CML converter 11B can have a CMOS-CML converter (e.g., Figure 5 CMOS-CML converter 11A) and CML driver (e.g., Figure 8 A circuit structure combined with a CML driver 823).

[0072] The CMOS-CML converter 11B may include a low pass filter 111B and a swing width control circuit 113A, and may also include a first N-type transistor NA, a second N-type transistor NB, and a current source ISC. The first CMOS input signal VCMOS+ may be applied to the gate of the first N-type transistor NA, and the second CMOS input signal VCMOS- may be applied to the gate of the second N-type transistor NB.

[0073] The low pass filter 111B may include an RC filter including a first resistor RA, a second resistor RB, and a capacitor C. In an embodiment, resistances of the first resistor RA and the second resistor RB may be equal to each other, but the embodiment is not limited thereto.

[0074] The swing width control circuit 113A may receive the internal signal output from the low pass filter 111A and generate CML output signals VCML+ and VCML- by adjusting the swing width of the internal signal. The swing width control circuit 113A may include a first fixed capacitor CA1, a second fixed capacitor CA2, and a variable capacitor CB'. In an embodiment, the capacitances of the first fixed capacitor CA1 and the second fixed capacitor CA2 may be equal to each other, but the embodiment is not limited thereto. Here, as Figure 6 As shown, the variable capacitor CB′ may include a connection capacitor C0 and first to nth capacitors C1 to Cn (where n is a natural number) and first to nth switches SW1 to SWn included in the capacitor array.

[0075] Fig.10 2 is a cross-sectional view showing a memory device 200 which is a semiconductor device in an electronic device according to an embodiment.

[0076] refer to Fig.10 , the memory device 200 may include a three-dimensional stacked memory device. The memory device 200 may include a buffer die 220 and a plurality of memory dies stacked on the buffer die 220, such as first to nth memory dies 230_1 to 230_n. n may be a natural number of 3 or greater, such as 4 or 8, and may be modified in various ways. The buffer die 220 and the first to nth memory dies 230_1 to 230_n may be configured as a single semiconductor package.

[0077] The memory device 200 may include: a via TV passing through the buffer die 220 and the first to nth memory dies 230_1 to 230_n, and micro bumps MBP electrically connecting the via TV to each other. The via TV and the micro bumps MBP may provide an electronic path between the buffer die 220 and the first to nth memory dies 230_1 to 230_n in the memory device 200. The number of via TV and micro bumps MBP is not limited to Fig.10 The number shown may be changed in various ways. The nth memory die 230_n may not have a via TV, but the embodiment is not limited thereto.

[0078] Each of the first to nth memory dies 230_1 to 230_n may include a dynamic random access memory (DRAM) chip. For example, each of the first to nth memory dies 230_1 to 230_n may include a general-purpose DRAM device (such as a double data rate synchronous dynamic random access memory (DDR SDRAM)), a DRAM device for mobile use (such as a low power double data rate (LPDDR) SDRAM), a graphic DRAM device (such as a graphic double data rate (GDDR) and a synchronous graphic random access memory (SGRAM)), or a DRAM device for providing high capacity and high bandwidth (such as wide input / output (I / O), high bandwidth memory (HBM), HBM2, HBM3, and hybrid memory cube (HMC)). However, the embodiment is not limited thereto, and each of the first to nth memory dies 230_1 to 230_n may include a volatile memory device other than DRAM, or may include a non-volatile memory device.

[0079] According to an embodiment, the first through nth memory dies 230_1 through 230_n may have substantially the same chip size. For example, the first through nth memory dies 230_1 through 230_n may have substantially the same planar shape and planar size.

[0080] The buffer die 220 may provide the first to nth memory dies 230_1 to 230_n with data input / output signals, commands, addresses, and chip select signals received from the memory controller, or may perform an interface operation to provide the memory controller with data input / output signals received from the first to nth memory dies 230_1 to 230_n. In order to perform the interface operation, the buffer die 220 may include a physical layer (PHY) 210 including an interface circuit. The PHY 210 may correspond to Figure 1 The PHY 210 may include, for example, Figure 2 CMOS-CML converter 11, Figure 5 The CMOS-CML converter 11A and Fig. 9 At least one of the CMOS-CML converters 11B.

[0081] Fig.11 is a block diagram showing a system on chip (SoC) 300 in an electronic device according to an embodiment.

[0082] refer to Fig.11, SoC 300 may include a processor 310, a cache memory 320, a memory controller 330, and a bus 350. Bus 350 may provide a communication path between processor 310, cache memory 320, and memory controller 330. Processor 310 may execute various software (applications, operating systems, file systems, device drivers, etc.) loaded in cache memory 320.

[0083] In an embodiment, SoC 300 may be coupled with Fig.10 The memory device 200 of the SoC 300 may be mounted together on an interposer, and the PHY 340 of the SoC 300 and the PHY 210 of the memory device 200 may be connected to each other via the interposer. In addition, in an embodiment, the memory device 200 may be provided on the SoC 300.

[0084] The processor 310 may include homogeneous multi-core or heterogeneous multi-core. For example, the processor 310 may include any one of a CPU, an image signal processing (ISP) unit, a DSP unit, a GPU, a visual processing unit (VPU), and a neural processing unit (NPU). In addition, the number of processors 310 may be one or more.

[0085] Application programs, operating systems, file systems, device drivers, etc. for driving electronic devices may be loaded on cache memory 320. For example, cache memory 320 may include a static random access memory (SRAM) device having a faster data input / output speed than memory device 200.

[0086] The memory controller 330 may access the memory device 200 through a direct memory access (DMA) method. The memory controller 330 may include a command queue 331, a command scheduler 332, a read data queue 333, a write data queue 334, and a PHY 340. The PHY 340 may correspond to Figure 1 The PHY 340 may include, for example, Figure 2 CMOS-CML converter 11, Figure 5 The CMOS-CML converter 11A and Fig. 9 The above-mentioned components 331 to 334 and 340 of the memory controller 330 may be provided in the SoC 300 by using a hardware method, a software method, or a combination thereof.

[0087] The command queue 331 may store commands and addresses issued by the processor 310 or generated under the control of the processor 310. The commands and addresses stored in the command queue 331 may be provided to the PHY 340 based on the control of the command scheduler 332.

[0088] The command scheduler 332 may adjust the order of commands and addresses stored in the command queue 331 , the time points at which commands and addresses are input to the command queue 331 , the time points at which commands and addresses are output from the command queue 331 , and the like.

[0089] The read data queue 333 may store read data transmitted from the memory device 200 through the PHY 340 by a read command. The read data stored in the read data queue 333 may be provided to the cache memory 320 and processed by the processor 310.

[0090] The write data queue 334 may store write data to be stored in the memory device 200. The write data stored in the write data queue 334 may be transmitted to the memory device 200 via the PHY 340 by a write command.

[0091] The PHY 340 may include a clock generator 341, a command / address generator 342, a data receiver 343, and a data transmitter 344. The clock generator 341 may generate a clock signal CK output to the memory device 200, and the number of clock signals CK may correspond to the number of channels between the SoC 300 and the memory device 200.

[0092] The command / address generator 342 may receive a command or an address from the command queue 331, and transmit the command CMD or the address ADD to the memory device 200. The data receiver 343 may receive read data of the data input / output signal DQ from the memory device 200 based on the read data strobe signal RDQS (or DQS). The data receiver 343 may provide the received read data to the read data queue 333. The data transmitter 344 may receive write data from the write data queue 334. The data transmitter 344 may transmit the received write data to the memory device 200 based on the write data strobe signal WDQS (or DQS).

[0093] Fig.12 is a diagram illustrating a system 1000 to which a semiconductor device according to an embodiment may be applied.

[0094] refer to Fig.12 , Fig.12 The system 1000 may basically include a mobile system, such as a portable mobile phone, a smart phone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Fig.12 The system 1000 is not limited to the above-mentioned mobile system, and may include a personal computer, a laptop, a server, a media player, an automobile device such as a navigation unit, and the like.

[0095] refer to Fig.12 , system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may also include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0096] The main processor 1100 may control the overall operation of the system 1000, and more specifically, may control the operations of all other components included in the system 1000. The main processor 1100 may be configured as a general-purpose processor, a dedicated processor, or an application processor.

[0097] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to an embodiment, the main processor 1100 may also include an accelerator block 1130, which includes a dedicated circuit for high-speed data calculation (such as artificial intelligence data calculation). The accelerator block 1130 may include a GPU, an NPU, and / or a data processing unit (DPU), and may be provided as a separate chip physically independent of other components of the main processor 1100.

[0098] The memories 1200a and 1200b may be used as the main memory device of the system 1000 and include volatile memory such as SRAM and / or DRAM. However, the memories 1200a and 1200b may also include non-volatile memory such as flash memory, phase change random access memory (PRAM) and / or resistive random access memory (RRAM). The memories 1200a and 1200b may also be provided in the same package as the main processor 1100.

[0099] The storage devices 1300a and 1300b may be used as non-volatile storage devices that can store data regardless of whether power is supplied or not, and may have a relatively larger storage capacity than the storage capacity of the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b, respectively, and non-volatile memories (NVMs) 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. The NVMs 1320a and 1320b may include NAND flash memory, but may also include other types of non-volatile memories, such as PRAM and / or RRAM.

[0100] The storage devices 1300a and 1300b may be included in the system 1000 while being physically separated from the main processor 1100, or may be provided in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b have a form such as a solid state device (SSD) or a memory card, and thus may be detachably coupled to other components of the system 1000 via an interface (such as a connection interface 1480 described below). The storage devices 1300a and 1300b may include devices to which a standard protocol such as Universal Flash Storage (UFS) is applied.

[0101] The image capturing device 1410 may capture still images or moving images and may include a camera, a camcorder, and / or a webcam.

[0102] The user input device 1420 may receive various types of data input from a user of the system 1000 and may include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0103] The sensor 1430 may detect various types of physical quantities obtained from outside the system 1000 and convert the sensed physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope.

[0104] The communication device 1440 may transmit signals to other devices outside the system 1000 and receive signals from other external devices according to various communication protocols. The communication device 1440 may include an antenna, a transceiver and / or a modem.

[0105] Display 1450 and speaker 1460 may be used as output devices to output visual information and auditory information, respectively, to a user of system 1000 .

[0106] The power supply device 1470 may appropriately convert power supplied by a built-in battery in the system 1000 and / or an external power source, and may supply the converted power to each component of the system 1000 .

[0107] The connection interface 1480 may provide a connection between the system 1000 and an external device connected to the system 1000 to exchange data with the system 1000. The connection interface 1480 may be provided in various interface ways, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVM Express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS), and Compact Flash (CF) card. The connection interface 1480 may correspond to Figure 1 The connection interface 1480 may include, for example, Figure 2 CMOS-CML converter 11, Figure 5 The CMOS-CML converter 11A and Fig. 9 At least one of the CMOS-CML converters 11B.

[0108] Fig.13 is a diagram showing a data center 3000 to which the semiconductor device according to the embodiment can be applied.

[0109] refer to Fig.13 , the data center 3000 may include equipment for collecting various types of data and providing services, and may also be referred to as a data storage center. The data center 3000 may include a system for operating a search engine and a database, and may include a computing system used in a company such as a bank or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected in various ways according to the embodiment, and the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0110] The application server 3100 or the storage server 3200 may include at least one of the processors 3110 and 3210 and the memories 3120 and 3220. In an embodiment, the processor 3210 may control the overall operation of the storage server 3200 and may access the memory 3220 to execute commands and / or data loaded into the memory 3220. The memory 3220 may include DDR SDRAM, HBM, HMC, dual in-line memory module (DIMM), Optane DIMM or non-volatile DIMM (NVMDIMM). According to an embodiment, the number of processors 3210 and the number of memories 3220 in the storage server 3200 may be selected in various ways. In an embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may also apply to the application server 3100. According to an embodiment, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. The number of storage devices 3250 in the storage server 3200 may be selected in various ways according to an embodiment.

[0111] In an embodiment, the interface 3254 may provide a physical connection between the processor 3210 and the controller 3251, and a physical connection between the network interface card (NIC) 3240 and the controller 3251. For example, the interface 3254 may be set in a direct attached storage method and establish a direct connection with the storage device 3250 through a dedicated cable. In addition, for example, the interface 3254 may be set in various interface methods such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB, SD card, MMC, eMMC, UFS, eUFS, and CF card. The interface 3254 may correspond to Figure 1 Interface circuit I / F. Interface 3254 may include, for example Figure 2 CMOS-CML converter 11, Figure 5 The CMOS-CML converter 11A and Fig. 9 At least one of the CMOS-CML converters 11B.

[0112] The storage server 3200 may further include a switch 3230 and a NIC 3240. Under the control of the processor 3210, the switch 3230 may selectively connect the processor 3210 to the storage device 3250 or connect the NIC 3240 to the storage device 3250.

[0113] In an embodiment, the NIC 3240 may include a network interface card, a network adapter, etc. The NIC 3240 may be connected to the network 3300 via a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC 3240 may include an internal memory, a DSP, a host bus interface, etc., and may be connected to the processor 3210 and / or the switch 3230 via the host bus interface. The host bus interface may be set as one of the examples of the above-mentioned interface 3254. In an embodiment, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0114] While certain embodiments have been particularly shown and described above, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A CMOS-CML converter for converting a CMOS input signal into a CML output signal, wherein: The CMOS is complementary metal oxide semiconductor, the CML is current mode logic, and the CMOS-CML converter includes: a low pass filter comprising a fixed resistor and a first fixed capacitor; and a swing width control circuit configured to adjust a swing width of a voltage swing of the CML output signal based on a common mode level, Wherein, the swing width control circuit comprises: a second fixed capacitor; and A variable capacitor includes a capacitor array.

2. The CMOS-CML converter according to claim 1, wherein: The capacitor array comprises: a connection capacitor connected between a ground voltage and an output node through which the CML output signal is output; and a plurality of capacitors, wherein a first terminal of each of the plurality of capacitors is connected to the output node, The variable capacitor further includes a plurality of switches corresponding to the plurality of capacitors, and Each of the plurality of switches connects a second end of a corresponding capacitor among the plurality of capacitors to the ground voltage.

3. The CMOS-CML converter according to claim 2, wherein: The capacitances of the plurality of capacitors increase sequentially according to a geometric sequence having a common ratio of 2.

4. The CMOS-CML converter according to claim 1, wherein: The CMOS input signal and the CML output signal include differential signals, Wherein, the capacitor array comprises: a connection capacitor connected to a first output node and a second output node outputting the CML output signal; and a plurality of capacitors, wherein a first terminal of each of the plurality of capacitors is connected to the first output node, and The variable capacitor further comprises a plurality of switches, wherein each of the plurality of switches connects the second end of a corresponding capacitor among the plurality of capacitors to the second output node.

5. The CMOS-CML converter according to claim 1, wherein: The swing width changes based on a change in the capacitance of the variable capacitor, and Wherein, a time point at which the CML output signal reaches the common mode level does not change based on a change in the capacitance of the variable capacitor.

6. The CMOS-CML converter according to claim 1, wherein: The capacitance of the variable capacitor changes based on characteristics of a circuit configured to operate based on the CML output signal.

7. The CMOS-CML converter according to claim 1, wherein: The CMOS input signal has a square wave shape, and Wherein, the CML output signal has a triangular waveform.

8. A semiconductor device, comprising: A CMOS-CML converter, wherein the CMOS-CML converter is used to convert a CMOS input signal into a CML output signal, wherein the CMOS is complementary metal oxide semiconductor, and the CML is current mode logic, Wherein, the CMOS-CML converter comprises: a low pass filter configured to generate an internal signal by attenuating a component of the CMOS input signal; and a swing width control circuit, the swing width control circuit being configured to generate the CML output signal by adjusting a swing width of a voltage swing of the internal signal, and wherein the swing width control circuit comprises: Fixed capacitors; and A variable capacitor includes a capacitor array.

9. The semiconductor device according to claim 8, wherein: The capacitor array comprises: a connection capacitor connected between a ground voltage and an output node through which the CML output signal is output; and a plurality of capacitors, wherein a first terminal of each of the plurality of capacitors is connected to the output node, The variable capacitor further includes a plurality of switches corresponding to the plurality of capacitors, and Each of the plurality of switches connects a second end of a corresponding capacitor among the plurality of capacitors to the ground voltage.

10. The semiconductor device according to claim 8, wherein The CMOS input signal and the CML output signal include differential signals, and Wherein, the capacitor array comprises: a connection capacitor connected to a first output node and a second output node through which the CML output signal is output; and a plurality of capacitors, wherein a first terminal of each of the plurality of capacitors is connected to the first output node, and The variable capacitor further comprises a plurality of switches, wherein each of the plurality of switches connects the second end of a corresponding capacitor among the plurality of capacitors to the second output node.

11. The semiconductor device according to claim 8, further comprising a CML signal domain circuit, the CML signal domain circuit being configured to operate based on the CML output signal, in, The capacitance of the variable capacitor is determined based on characteristics of the CML signal domain circuit.

12. The semiconductor device according to claim 11, wherein The semiconductor device is configured to change the capacitance of the variable capacitor based on an operation result of the CML signal domain circuit.

13. The semiconductor device according to claim 11, wherein The CML signal domain circuit includes a phase interpolation circuit. 14 . The semiconductor device according to claim 8 , further comprising a CML-CMOS converter configured to convert the CML signal into a CMOS signal.

15. The semiconductor device according to claim 8, wherein The swing width of the voltage swing of the CML output signal changes based on the change in the capacitance of the variable capacitor, and Wherein, a time point at which the CML output signal reaches a common mode level does not change based on a change in the capacitance of the variable capacitor.

16. The semiconductor device according to claim 8, further comprising an interface circuit configured to communicate with an external device, in, The interface circuit includes the CMOS-CML converter.

17. An electronic device, comprising: A CMOS signal domain circuit, wherein the CMOS signal domain circuit is configured to operate based on a CMOS signal, wherein the CMOS is a complementary metal oxide semiconductor; as well as A semiconductor device, comprising: CML signal domain circuitry configured to operate using CML signals, the CML being current mode logic, and a CMOS-CML converter configured to convert a CMOS input signal into a CML output signal, Wherein, the CMOS-CML converter comprises: a low pass filter comprising a fixed resistor and a first fixed capacitor; and Swing width control circuit, and Wherein, the swing width control circuit comprises: a second fixed capacitor, and A variable capacitor includes a capacitor array.

18. The electronic device according to claim 17, wherein: The swing width control circuit is configured to adjust a swing width of a voltage swing of the CML output signal according to a ratio between a capacitance of the variable capacitor and a capacitance of the second fixed capacitor.

19. The electronic device according to claim 17, wherein: The capacitor array comprises: a connection capacitor connected between a ground voltage and an output node through which the CML output signal is output; and a plurality of capacitors, wherein a first terminal of each of the plurality of capacitors is connected to the output node, The variable capacitor further includes a plurality of switches corresponding to the plurality of capacitors, and Each of the plurality of switches connects a second end of a corresponding capacitor among the plurality of capacitors to the ground voltage.

20. The electronic device according to claim 17, wherein: The CMOS input signal and the CML output signal include differential signals, and Wherein, the capacitor array comprises: a connection capacitor connected to a first output node and a second output node through which the CML output signal is output; and a plurality of capacitors, wherein a first terminal of each of the plurality of capacitors is connected to the first output node, Wherein, the variable capacitor further includes a plurality of switches, Each of the plurality of switches connects a second end of a corresponding capacitor among the plurality of capacitors to the second output node.

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