ADC Circuit with Dynamic Computing Capability and Variable-Precision Quantization in the Asynchronous Paradigm

Abstract

The present invention discloses an ADC circuit with dynamic computing capabilities and variable-precision quantization in an asynchronous paradigm, which includes three stages: a setup stage, a computing stage, and an asynchronous handshake stage. The present invention realizes the adaptive ability of signal quantization accuracy to achieve a balance between high-precision data processing and energy efficiency optimization. In terms of design, the number of successive approximation SA registers is effectively streamlined, thus significantly reducing the overall power consumption of the circuit. At the same time, reducing the use of SA registers also means lower manufacturing costs, making the ADC circuit more economical and efficient in terms of material use and production process.

Description

Technical Field

[0001] The present invention relates to the technical field of ADC circuits, and specifically to an ADC circuit with dynamic computing capabilities and variable-precision quantization in an asynchronous paradigm. Background Art

[0002] In the post-Moore era, with the exponential growth of data volume and the continuous improvement of intelligent processing requirements, traditional computing architectures have been difficult to meet the dual challenges of efficiency and energy consumption. As a disruptive solution, the in-memory computing (CIM) technology integrates storage and computing functions in the same hardware unit, providing an efficient hardware platform for real-time intelligent processing of big data;

[0003] As one of the most cutting-edge artificial intelligence technologies today, the core operation of deep learning neural networks, multiply accumulate (MAC), requires huge computing resources. In traditional von Neumann architectures, data must be frequently moved between the processor and memory, resulting in significant latency and energy waste, which is known as the "von Neumann bottleneck". In contrast, in-memory computing technology significantly reduces the data movement distance and data access time by directly performing calculations within memory cells, thus significantly improving the operation efficiency and reducing energy consumption;

[0004] At the same time as this transformation, the introduction of asynchronous circuit design further optimizes this architecture. Traditional synchronous circuit design relies on a global clock signal and has different processing efficiencies for input signals of different sizes and complexities. Asynchronous circuit design, not limited by the global clock, can dynamically adjust the processing speed according to the actual situation of the input signal, especially excelling in high-speed data processing and low-power operation. This design provides higher flexibility and efficiency when processing complex deep learning tasks, while reducing energy waste caused by fixed clock cycles, providing a more efficient and responsive solution for the computing requirements in the post-Moore era;

[0005] One of the important branches of the current mainstream memory - in - computing technology is analog memory - in - computing implemented using storage media such as SRAM, ReRAM, Flash, etc. These media can not only store information but also perform basic arithmetic operations on analog or digital signals, such as addition and multiplication, which is particularly crucial for performing a large number of MAC operations. In this way, the memory - in - computing architecture can directly complete complex computing tasks in the storage unit without the need for data to return to the central processing unit. The external digital input signal needs to be first converted into an analog signal value through a DAC as the input of the analog computing array. The analog computing array consists of a complex number of SRAM, ReRAM, or other storage - medium computing units. The array implements multiply - add calculations and outputs the calculation result of the analog quantity. Finally, the ADC analog - to - digital conversion device converts the analog quantity into a digital signal as the output result;

[0006] In deep learning and other high - performance computing applications, the accuracy of analog computing is crucial, but this accuracy is often restricted by the precision of analog - to - digital conversion (ADC). Traditional multi - bit precision ADCs, although powerful, have two main problems due to the complexity of their design: one is that they usually require a large circuit area, which means higher costs and space limitations in chip design; the other is that they consume a relatively high amount of power, which is a significant disadvantage in modern computing environments that require maximum energy efficiency;

[0007] Traditional synchronous ADC circuits are often limited in efficiency when processing input signals of different amplitudes due to their fixed computing time. This design relies on global clock synchronization, resulting in the same processing time for signals with small amplitudes, thus reducing the overall processing efficiency;

[0008] In addition, there are some inherent problems in the existing charge - integration ADC technology. Due to the delay of the operational amplifier (Op - Amp) and the non - ideality during the charge transfer process, the amount of discharge may vary each time, leading to inconsistency in the integration process. This is particularly prominent in high - speed operations because even small delays and errors will accumulate when processing a large amount of data in a short time, ultimately affecting the output accuracy of the entire system. In addition, during the discharge process, if the input signal continues to change, the current technology may not be able to effectively capture these changes, resulting in data loss. These non - linear errors and synchronization problems are particularly serious in application scenarios with high - precision requirements because the system cannot guarantee the consistency of the discharge amount each time, thus affecting the final computing accuracy. Summary of the Invention

[0009] The present invention provides an ADC circuit with dynamic computing capabilities and variable - precision quantization in an asynchronous paradigm, which can effectively solve the problems raised in the above - mentioned background technology.

[0010] To achieve the above object, the present invention provides the following technical solution: An ADC circuit with dynamic computing ability and variable-precision quantization in an asynchronous paradigm, which includes three stages: a setup stage, a computing stage, and an asynchronous handshake stage;

[0011] Step 1: Setup stage:

[0012] In the setup stage, through the activation control signal SET, the charge storage capacitor C 1 is charged from the charge bit line to the set reference voltage Vref to reserve the charge required for the charging process. In this stage, the NMOS transistor N2 is turned off to isolate C 1 , and at the same time the NMOS transistor N3 is turned on to allow C 2 to discharge to ground, preparing for the next charging operation;

[0013] Step 2: Computing stage:

[0014] In this stage, the control signal SET is disabled, causing the NMOS transistor N2 to conduct and the PMOS transistor N3 to turn off. The charge stored in the bank capacitor C 1 flows to the discharge capacitor C 2 , so that the charge accumulates on C 2 . While the charge is transferring from C 1 to C 2 , the charge voltage Vc on C 2 is continuously compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, triggering the escapement circuit. Discharge triggers the NMOS transistor N4 to conduct, causing C 2 to fully discharge, and the corresponding pulse is recorded by the counter. The discharge action also causes the transistor N2 to turn off through the out_pulse signal, interrupting the charge flow from the CBL to C 2 . If Vc is lower than Vref after discharge, the transistor N4 turns off and N2 conducts again, allowing the CBL and C 1 to recharge C 2 again, preparing for the next counting cycle. In this way, the charging and discharging process of C 2 and the generation of the pulse output sequence constitute a continuous cycle;

[0015] Step 3: Asynchronous handshake stage:

[0016] In this stage, when the voltage of the CBL is lower than Vref, the handshake signal ADCK is activated and raised, prompting the SET signal to be activated, causing the CBL to quickly charge to Vref. The rapid decrease of the ADCK signal then causes the SET signal to be disabled, completing an asynchronous handshake operation and providing a stable voltage environment for the accurate start of the next counting cycle.

[0017] According to the above technical solution, in the calculation stage, the mode selector allows the output unit to adjust the capacitance of the discharge capacitor according to the set mode;

[0018] The mode selector is configured with two modes, corresponding to different resolution ranges respectively:

[0019] a. Mode 0 (Mode = 0): In this mode, the capacitance of the discharge capacitor is set to C 0 , when the charge on CBL is transferred to the discharge capacitor, due to the smaller capacitance, the voltage change caused by the charge accumulated on the capacitor is larger, which enables the same amount of charge on CBL to generate more counting pulses in the counter, thus generating a higher resolution during output;

[0020] b. Mode 1 (Mode = 1): In this mode, the capacitance of the discharge capacitor is n times that in Mode 0, that is, nC 0 , because a larger capacitor can store more charge without significantly changing the voltage. Therefore, in Mode 1, the same charge on CBL will generate fewer pulses in the counter, resulting in a lower output resolution, but allowing a larger range of charge accumulation and processing;

[0021] By switching between these two modes, the system can flexibly configure the precision. For applications that require high-resolution readings, Mode 0 can be selected;

[0022] while for applications that require processing a larger dynamic range but have less demanding resolution requirements, Mode 1 can be selected;

[0023] This flexibility allows the ADC of the present invention to switch between different arithmetic precisions, optimizing power consumption and performance.

[0024] According to the above technical solution, in the counting stage, after the D flip-flop detects the rising edge of X<1>, it pulls high. After the PP_checker detects the rising of out_pulse, it generates a pulse discharge with adjustable width to control the switch of N4, so as to ensure that the charge accumulated in C 2 is completely discharged. The principle of the NP_checker is similar to that of the PP_checker. After identifying the falling edge of discharge, it emits a pulse np as small as possible to control the pulling low of out_pulse;

[0025] The escapement circuit ensures that while the charge in C 2 is completely discharged, N2 is in the off state, avoiding a short circuit phenomenon in the circuit.

[0026] According to the above technical solution, in the calculation stage, it is allowed to store in the bank capacitor C1 The charge in it flows to the discharging capacitor C 2 , causing the charge to accumulate on C 2 . The configurable capacitance array determines the capacitance of C through the setting of the mode selector, which directly affects the charging process and counting accuracy; 2 The discharging action also causes the transistor N2 to turn off through the out_pulse signal, interrupting the charge flow from CBL to C

[0027] While the charge is transferring from C 1 to C 2 , the charge voltage Vc accumulated on C 2 will continuously be compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, thereby triggering the escapement discharge circuit. Discharge triggers the NMOS transistor N4 to conduct, causing C 2 to discharge completely, and the corresponding pulse is recorded by the counter;

[0028] ; 2 ;

[0029] If Vc is lower than Vref after discharge, the transistor N4 turns off and N2 conducts again, allowing CBL and C 1 to recharge C 2 for the next counting cycle;

[0030] In this way, the charging and discharging process of C 2 and the generation of the pulse output sequence constitute a continuous cycle, enabling the ADC circuit to achieve accurate analog-to-digital conversion during high-speed operation.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows: The structure of the present invention is scientifically reasonable, safe and convenient to use, realizing the adaptive ability to the signal quantization accuracy, achieving a balance between high-precision data processing and energy efficiency optimization. The number of successive approximation SA registers is effectively reduced in the design, thus significantly reducing the energy consumption of the overall circuit. At the same time, reducing the use of SA registers also means lower manufacturing costs, making the ADC circuit more economical and efficient in terms of material use and production process. The handshake signal ADCK is introduced. Since it does not rely on external clock synchronization, the sensitivity of the circuit to changes in the external environment is reduced, enabling it to maintain stable performance when facing environmental changes such as temperature fluctuations and power supply noise, thereby improving the robustness;

[0032] In addition, another significant feature of asynchronous circuits is low power consumption. Since they only consume energy during data processing rather than continuously relying on clock signals, they can significantly reduce the overall energy consumption, especially when processing intermittent or sparse data;

[0033] The escapement discharge circuit adopted by the present invention can precisely control the discharge process, can more accurately control the discharge time of the capacitor, reduce the error caused by inaccurate charge transfer, and improve the overall signal conversion accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention.

[0035] In the drawings:

[0036] Figure 1 is the overall circuit diagram of the ADC of the present invention;

[0037] Figure 2 is the handshake circuit diagram of the present invention;

[0038] Figure 3 is the timing diagram of the asynchronous handshake signal of the present invention;

[0039] Figure 4 is the circuit diagram of the mode selector of the present invention;

[0040] Figure 5 is the circuit diagram of the variable-precision quantization of the present invention;

[0041] Figure 6 is the circuit diagram of the escapement discharge unit of the present invention; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] The following describes the preferred embodiments of the present invention with reference to the drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0043] Embodiment: As Figure 1 shown, the present invention provides a technical solution, an ADC circuit with dynamic computing ability and variable-precision quantization in an asynchronous paradigm, including three stages: a setup stage, a computing stage, and an asynchronous handshake stage;

[0044] Step 1: Setup stage:

[0045] In the setup stage, by activating the control signal SET, the charge storage capacitor C 1 is charged from the charge bit line to the set reference voltage Vref to reserve the charge required for the charging process. In this stage, the NMOS transistor N2 is turned off to isolate C 1 , and at the same time, the NMOS transistor N3 is turned on to allow C 2 to discharge to ground to prepare for the next charging operation;

[0046] Step 2: Computing stage:

[0047] At this stage, the control signal SET is disabled, causing the NMOS transistor N2 to conduct and the PMOS transistor N3 to turn off. The charge stored in the bank capacitor C 1 flows to the discharge capacitor C 2 , causing the charge to accumulate on C 2 . While the charge is transferring from C 1 to C 2 , the charge voltage Vc accumulated on C 2 is continuously compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, triggering the escapement discharge circuit. Discharge triggers the NMOS transistor N4 to conduct, fully discharging C 2 , and the corresponding pulse is recorded by the counter. The discharge action also causes the transistor N2 to turn off through the out_pulse signal, interrupting the charge flow from CBL to C 2 . If Vc is lower than Vref after discharge, the transistor N4 turns off and N2 conducts again, allowing CBL and C 1 to recharge C 2 in preparation for the next counting cycle. In this way, the charging and discharging process of C 2 and the generation of the pulse output sequence constitute a continuous cycle;

[0048] Step 3: Asynchronous handshake stage:

[0049] As Figures 2-3 shown: In this stage, when the voltage of CBL is lower than Vref, the handshake signal ADCK is activated and rises, prompting the SET signal to be activated, causing CBL to quickly charge to Vref. The rapid decrease of the ADCK signal then causes the SET signal to be disabled, completing an asynchronous handshake operation and providing a stable voltage environment for the accurate start of the next counting cycle.

[0050] According to the above technical solution, as Figure 4 shown: In the calculation stage, the mode selector allows the output unit to adjust the capacitance of the discharge capacitor according to the set mode, thereby achieving variable-precision quantization;

[0051] The mode selector is configured with two modes, corresponding to different resolution ranges respectively:

[0052] a. Mode 0 (Mode = 0): In this mode, the capacitance of the discharge capacitor is set to C 0 . When the charge on CBL is transferred to the discharge capacitor, due to the smaller capacitance, the voltage change caused by the charge accumulated on the capacitor is larger, which enables the same amount of charge on CBL to generate more counting pulses in the counter, resulting in a higher resolution at the output;

[0053] b. Mode 1 (Mode = 1): In this mode, the capacitance of the discharge capacitor is n times that in Mode 0, i.e., nC 0 , which means that under the action of the same amount of charge, the voltage change across the capacitor will be smaller than that in Mode 0, because a larger capacitance can store more charge without significantly changing the voltage. Therefore, in Mode 1, the same charge on the CBL will generate fewer pulses in the counter, resulting in a lower output resolution, but allowing a larger range of charge accumulation and processing;

[0054] As Figure 5 shown: By switching between these two modes, the system can flexibly configure the precision to adapt to different application requirements. For applications that require high-resolution readings, Mode 0 can be selected;

[0055] while for applications that need to process a larger dynamic range but have less stringent resolution requirements, Mode 1 can be selected;

[0056] This flexibility allows the ADC of the present invention to switch between different arithmetic precisions, optimizing power consumption and performance.

[0057] According to the above technical solution, as Figure 6 shown, where a is the escapement discharge circuit, b is the PP_checker circuit, c is the NP_checker circuit, d is the voltage waveforms of out_pulse, discharge, and np. During the counting stage, the escapement discharge circuit plays a key role. After the D flip-flop detects the rising edge of X<1>, it pulls high. After the PP_checker detects the rising edge of out_pulse, it generates a pulse discharge with an adjustable width to control the switch of N4, so as to ensure that the charge accumulated in C 2 is completely discharged. The principle of the NP_checker is similar to that of the PP_checker. After detecting the falling edge of discharge, it emits a pulse np as small as possible to control out_pulse to pull low;

[0058] The escapement discharge circuit ensures that while C 2 is completely discharged, N2 is in the off state, avoiding a short-term short-circuit phenomenon in the circuit.

[0059] Furthermore, during the calculation stage, it is allowed that the charge stored in the bank capacitor C 1 flows to the discharge capacitor C 2 , so that the charge accumulates on C 2 . The configurable capacitor array determines the capacitance of C 2 through the setting of the mode selector, directly affecting the charging process and counting accuracy;

[0060] While the charge transfers from C 1 to C 2 , the charge voltage Vc accumulated on C 2 is continuously compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, triggering the escapement discharge circuit. Discharge triggers the NMOS transistor N4 to conduct, causing C 2 to discharge completely, and the corresponding pulse is recorded by the counter;

[0061] The discharge action also causes the transistor N2 to turn off through the out_pulse signal, interrupting the charge flow from CBL to C 2 ;

[0062] If Vc is lower than Vref after discharge, the transistor N4 turns off and N2 conducts again, allowing CBL and C 1 to recharge C 2 in preparation for the next counting cycle;

[0063] In this way, the charge and discharge process of C 2 and the generation of the pulse output sequence constitute a continuous cycle, ensuring the synchronization of the counting accuracy and the charge and discharge process, so that the ADC circuit can achieve accurate analog-to-digital conversion during high-speed operation.

[0064] Finally, it should be noted that the above are only preferred examples of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An asynchronous ADC circuit with dynamic computing capability and variable precision quantization, characterized in that: It includes three phases: setup phase, calculation phase and asynchronous handshake phase; Step 1: Setup Phase: In the setting stage, by activating the control signal SET, the charge storage capacitor C1 is charged from the charge bit line to the set reference voltage Vref to reserve the charge required for the charging process. In this stage, the NMOS transistor N2 is turned off to isolate C1, and the NMOS transistor N3 is turned on to allow C2 to discharge to the ground, preparing for the next charging operation; Step 2: Calculation phase: At this stage, the control signal SET is disabled, causing the NMOS transistor N2 to turn on and the PMOS transistor N3 to turn off. The charge stored in the charge storage capacitor C1 flows to the discharge capacitor C2, so that the charge accumulates on C2. While the charge is transferred from C1 to C2, the charge voltage Vc accumulated on C2 is constantly compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, thereby triggering the escapement discharge circuit. The width-adjustable pulse discharge triggers the NMOS transistor N4 to turn on, so that C2 is fully discharged, and the corresponding pulse is recorded by the counter. The discharge action will also cause the transistor N2 to turn off through the out_pulse signal, interrupting the charge from the charge bit line CBL to C2. If Vc is lower than Vref after discharge, the transistor N4 is turned off and N2 is turned on again, allowing CBL and C1 to recharge C2 and prepare for the next counting cycle. In this way, the charging and discharging process of C2 and the generation of the pulse output sequence constitute a continuous cycle; Step 3: Asynchronous handshake phase: During this stage, when the voltage of CBL is lower than Vref, the handshake signal ADCK is activated and increases, prompting the SET signal to be activated, causing CBL to be quickly charged to Vref. The rapid decrease of the ADCK signal then causes the SET signal to be disabled, completing an asynchronous handshake operation and providing a stable voltage environment for the accurate start of the next counting cycle.

2. The asynchronous paradigm ADC circuit with dynamic computing capability and variable precision quantization according to claim 1, characterized in that: During the calculation phase, the mode selector allows the output unit to adjust the capacitance of the discharge capacitor according to the set mode; The mode selector is configured with two modes, corresponding to different resolution ranges: a. Mode 0 (Mode=0): In this mode, the capacitance of the discharge capacitor is set to C0. When the charge on CBL is transferred to the discharge capacitor, the voltage change caused by the charge accumulated on the capacitor is larger due to the smaller capacitance. This enables the same amount of charge on CBL to generate more count pulses in the counter, resulting in higher resolution at the output. b. Mode 1 (Mode=1): In this mode, the capacitance of the discharge capacitor is n times that of Mode 0, i.e. nC0, because a larger capacitor can store more charge without significantly changing the voltage. Therefore, in Mode 1, the same charge on CBL will produce fewer pulses in the counter, resulting in a lower resolution of the output, but allowing a wider range of charge accumulation and processing; By switching between these two modes, the system can flexibly configure the accuracy. For applications that require high-resolution readings, select Mode 0; For applications that need to process a larger dynamic range but not so high resolution, select Mode 1; The ADC switches between different operating precisions to optimize power consumption and performance.

3. The asynchronous paradigm ADC circuit with dynamic computing capability and variable precision quantization according to claim 1, characterized in that: In the counting phase, the D flip-flop detects X <1> After the rising edge, it is pulled high. After the PP_checker detects the rise of out_pulse, it generates a pulse discharge with adjustable width to control the switch of N4 to ensure that the charge accumulated in C2 is completely discharged. The principle of NP_checker is similar to that of PP_checker. After recognizing the falling edge of discharge, it sends out a pulse np as small as possible, thereby controlling out_pulse to be pulled low. The escapement discharge circuit ensures that C2 is fully discharged while N2 is in the closed state, avoiding a brief short circuit in the circuit.

4. The asynchronous paradigm ADC circuit with dynamic computing capability and variable precision quantization according to claim 1, characterized in that: In the calculation phase, the charge stored in the charge reservoir capacitor C1 is allowed to flow to the discharge capacitor C2, so that the charge accumulates on C2. The configurable capacitor array determines the capacitance of C2 through the setting of the mode selector, which directly affects the charging process and counting accuracy. While the charge is transferred from C1 to C2, the charge voltage Vc accumulated on C2 is constantly compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, thereby triggering the escapement discharge circuit. The discharge triggers the NMOS transistor N4 to turn on, causing C2 to be fully discharged, and the corresponding pulse is recorded by the counter. The discharge action also causes transistor N2 to turn off through the out_pulse signal, interrupting the flow of charge from CBL to C2; If Vc is lower than Vref after discharge, transistor N4 turns off and N2 turns on again, allowing CBL and C1 to recharge C2 in preparation for the next counting cycle; In this way, the charging and discharging process of C2 and the generation of the pulse output sequence constitute a continuous cycle, enabling the ADC circuit to achieve accurate analog-to-digital conversion in high-speed operation.

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