Expansion counting analog-to-digital converter structure and electronic component
Through the combined structure of the incremental multi-stage cascaded Sigma-Delta ADC and the margin quantization ADC, the problem that the accuracy of the traditional Sigma-Delta ADC is limited by the oversampling rate and modulator order is solved, and it is realized at a lower High-speed, high-precision quantization output at oversampling rate.
Patent Information
- Application Number
- CN202411416297.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-01-21
AI Technical Summary
Traditional Sigma-Delta analog-to-digital converters (ADCs) are limited by the oversampling rate and modulator order in terms of accuracy, making it difficult to achieve high-speed and high-precision quantized output at lower oversampling rates.
Using the combined structure of incremental multi-stage cascaded Sigma-Delta ADC and margin quantization ADC, the input signal is initially quantized through the incremental multi-stage cascade Sigma-Delta ADC, and the margin quantization ADC quantifies the margin again. , and finally output a high-precision digital output code through the filter module.
It effectively improves the accuracy of the analog-to-digital converter without increasing the oversampling rate, achieving high-speed, high-precision quantized output at a lower oversampling rate.
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Figure CN119341574A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to an extended counting analog-to-digital converter structure and electronic components. Background Art
[0002] In the electronic design of the imaging field, the dynamic range, resolution, accuracy, linearity and noise of the data converter are very stringent. For example, the analog to digital converter (ADC) must have a high resolution of at least 24 bits to obtain better quality and clearer images. At the same time, it must have a fast sampling rate (for example, as short as 100μs) to digitize the detector readings. The Sigma-Delta Analog to Digital Converter (Sigma-Delta ADC) is the most commonly used high-precision ADC. The Sigma-Delta ADC uses oversampling and noise shaping technology, is insensitive to the matching of analog circuit devices, has good robustness, and enables analog circuit devices to achieve high precision.
[0003] However, the traditional Sigma-Delta ADC architecture still has some problems. For example, the accuracy of the traditional Sigma-Delta ADC is limited by the oversampling rate and the modulator order. Summary of the invention
[0004] The purpose of the embodiment of the present invention is to provide an extended counting analog-to-digital converter structure, which can achieve high-speed and high-precision quantized output.
[0005] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides an extended counting analog-to-digital converter structure, which includes an incremental multi-stage cascaded Sigma-Delta ADC, a residual quantization ADC and a filter module. The input interface is connected to the incremental multi-stage cascaded Sigma-Delta ADC and the residual quantization ADC in sequence, the output end of the incremental multi-stage cascaded Sigma-Delta ADC and the output end of the residual quantization ADC are connected to the filter module, and the filter module is connected to the output interface. The incremental multi-stage cascaded Sigma-Delta ADC is used to quantize the input signal, the residual quantization ADC is used to re-quantize the residual sampling after the quantization of the incremental multi-stage cascaded Sigma-Delta ADC, and the filter module is used to output the digital output code corresponding to the input signal.
[0006] Optionally, the residue quantization ADC is a successive approximation ADC.
[0007] Optionally, the incremental multi-stage cascade Sigma-Delta ADC includes a first-stage integrator, a second-stage integrator, a third-stage integrator, and a fourth-stage integrator connected in sequence. The output end of the second-stage integrator is connected to a first comparator, and the output end of the first comparator serves as the first output end of the incremental multi-stage cascade Sigma-Delta ADC and is connected to the filter module; the output end of the fourth-stage integrator is connected to a second comparator, and the output end of the second comparator serves as the second output end of the incremental multi-stage cascade Sigma-Delta ADC and is connected to the filter module; the residual quantization ADC is connected in parallel with the second comparator.
[0008] Optionally, the incremental multi-stage cascaded Sigma-Delta ADC also includes a feedback DAC structure.
[0009] Optionally, when the incremental multi-stage cascade Sigma-Delta ADC is a feedback cascade integrator structure, the feedback DAC structure is: the output end of the first comparator is respectively connected to the operational amplifier of the first-stage integrator and the operational amplifier of the second-stage integrator, and the output end of the second comparator is respectively connected to the operational amplifier of the third-stage integrator and the operational amplifier of the fourth-stage integrator.
[0010] Optionally, when the incremental multi-stage cascaded Sigma-Delta ADC is a feedforward cascaded integrator structure, the feedback DAC structure is: the output of the first comparator is connected to the adder of the first-stage integrator, and the output of the second comparator is connected to the adder of the third-stage integrator. The input interface and the output of the first-stage integrator are connected to the adder of the output of the second-stage integrator, and the output of the first comparator and the output of the third-stage integrator are connected to the adder of the output of the fourth-stage integrator.
[0011] Optionally, the voltage connected to the input interface is V in , the voltage at the output of the first stage integrator is V O1 The voltage across the output of the second stage integrator is V O2 , the voltage at the output of the third stage integrator is V O3 , the voltage at the output end of the fourth stage integrator is V O4 The voltage at the output of the first comparator is d1, the voltage at the output of the second comparator is d2, and the output value of the filter module is D out , then, the time domain relationship of the incremental multi-stage cascaded Sigma-Delta ADC is expressed by the following formula:
[0012]
[0013] Among them, n, l, m, k represent clock cycles, λ1 represents the first-order coefficient, λ2 represents the second-order coefficient, λ3 represents the third-order coefficient, λ4 represents the fourth-order coefficient, λ e represents the error term coefficient, and i represents the i-th clock cycle.
[0014] Optionally, the filter module is configured to: convert the digital code D1 output by the first comparator, the digital code D2 output by the second comparator, and the digital code D output by the residual quantization ADC SAR The extraction filter is performed, and then the digital output code with a preset number of bits is spliced through summation, accumulation and logical operations.
[0015] Optionally, the extended counting analog-to-digital converter structure further includes a clock generation module for generating a switch control signal required for chip operation.
[0016] An embodiment of the present invention further provides an electronic component, wherein the electronic component includes the above-mentioned extended counting analog-to-digital converter structure.
[0017] Through the above technical scheme, the embodiment of the present invention is based on an extended counting analog-to-digital converter structure composed of an incremental multi-stage cascaded Sigma-Delta ADC and a residual quantization ADC. After the input signal is quantized by the incremental multi-stage cascaded Sigma-Delta ADC, the residual sampling (i.e., the residual voltage) is further quantized as the input signal of the residual quantization ADC, and then a high-precision digital output code corresponding to the input signal is output through the filter module; the residual quantization process can effectively improve the accuracy of the extended counting of the embodiment of the present invention without increasing the oversampling rate, and achieve high-speed and high-precision quantization output at a lower oversampling rate.
[0018] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:
[0020] Figure 1 is a structural diagram of an extended counting analog-to-digital converter structure provided by an embodiment of the present invention;
[0021] Figure 2 is a structural diagram of an example extended counting analog-to-digital converter structure;
[0022] Figure 3 is a circuit diagram of an example incremental multi-stage cascade CIFB Sigma-Delta ADC;
[0023] Figure 4 is a block diagram of an example incremental multi-stage cascade CIFB Sigma-Delta ADC;
[0024] Figure 5 is a schematic diagram of the structure of an example incremental multi-stage cascade CIFF Sigma-Delta ADC;
[0025] Figure 6 is a schematic diagram of a principle of implementing extended counting by an example extended counting analog-to-digital converter structure; and
[0026] Figure 7 It is a timing diagram of the operation of the example extended counting analog-to-digital converter structure.
[0027] Description of Reference Numerals
[0028] 10 Incremental multi-stage cascaded Sigma-Delta ADC 20 Residual quantization ADC 30 Filter module DETAILED DESCRIPTION
[0029] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.
[0030] It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) involved in the embodiments of the present invention, the directional indication is only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the drawings). If the specific posture changes, the directional indication will also change accordingly. For ease of description, spatial relative terms such as "under...", "below...", "lower part", "above...", "upper part" and the like can be used here to easily describe the relationship between one element or component and another (or other) elements or components as shown in the figure. In addition to the orientation shown in the figure, the spatial relative terms are intended to include different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in the embodiments of the present invention can be interpreted accordingly. In addition, in the subsequent manufacturing process, there may be one or more additional operations in / between the described operations, and the order of operations can be changed. In the present disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B, and one element from C unless otherwise specified. Materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment may be adopted in other embodiments, and detailed descriptions thereof may be omitted.
[0031] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.
[0032] Figure 1 is a schematic diagram of the structure of the extended counting analog-to-digital converter provided by an embodiment of the present invention, please refer to Figure 1, the extended counting analog-to-digital converter structure may include an incremental multi-stage cascaded Sigma-Delta ADC 10, a residual quantization ADC 20, and a filter module 30. The input interface is sequentially connected to the incremental multi-stage cascaded Sigma-Delta ADC 10 and the residual quantization ADC 20, the output end of the incremental multi-stage cascaded Sigma-Delta ADC 10 and the output end of the residual quantization ADC 20 are connected to the filter module 30, and the filter module 30 is connected to the output interface. The incremental multi-stage cascaded Sigma-Delta ADC 10 is used to quantize the input signal, the residual quantization ADC 20 is used to re-quantize the residual sampling after quantization of the incremental multi-stage cascaded Sigma-Delta ADC 10, and the filter module 30 is used to output the digital output code corresponding to the input signal.
[0033] As a high-precision ADC, Sigma-Delta ADC uses oversampling and noise shaping technology, is insensitive to the matching of analog circuit devices, has good robustness, and enables analog circuit devices to achieve high precision. In addition, the Sigma-Delta ADC sampling rate also supports multiplexing, so that fewer converters can be used and the size and power consumption of the entire system can be reduced.
[0034] Therefore, in the embodiment of the present invention, based on the extended counting analog-to-digital converter structure composed of the incremental multi-stage cascaded Sigma-Delta ADC 10 and the residual quantization ADC 20, after the input signal is quantized by the incremental multi-stage cascaded Sigma-Delta ADC 10, the residual sampling (i.e., the residual voltage) is further quantized as the input signal of the residual quantization ADC 20, and then the high-precision digital output code corresponding to the input signal is output through the filter module 30. The residual quantization process can effectively improve the accuracy of the extended counting of the embodiment of the present invention without increasing the oversampling rate, and realize high-speed and high-precision quantization output at a lower oversampling rate.
[0035] Please refer to Figure 2 In an embodiment of the present invention, the residual quantization ADC may preferably be a successive approximation register analog-to-digital converter (SAR ADC).
[0036] The extended counting analog-to-digital converter structure provided in the embodiment of the present invention is an incremental multi-stage cascaded Sigma-DeltaADC+SAR ADC structure, which has the characteristics of high speed, high precision and low power consumption.
[0037] The residual quantization ADC may also be a Flash ADC structure, a Cyclic ADC structure, a Single Slope ADC structure, etc. Based on this, the extended counting analog-to-digital converter structure provided in the embodiment of the present invention is characterized by a fast speed of an incremental multi-stage cascaded Sigma-Delta ADC+Flash ADC structure; a medium speed and medium precision of an incremental multi-stage cascaded Sigma-Delta ADC+Cyclic ADC structure; and a medium precision and high power consumption of an incremental multi-stage cascaded Sigma-Delta ADC+Single Slope ADC structure.
[0038] The incremental multi-stage cascade Sigma-Delta ADC preferably in the embodiment of the invention may include a first-stage integrator, a second-stage integrator, a third-stage integrator, and a fourth-stage integrator connected in sequence. The output end of the second-stage integrator is connected to a first comparator, and the output end of the first comparator is used as the first output end of the incremental multi-stage cascade Sigma-Delta ADC and connected to the filter module; the output end of the fourth-stage integrator is connected to a second comparator, and the output end of the second comparator is used as the second output end of the incremental multi-stage cascade Sigma-Delta ADC and connected to the filter module; the residual quantization ADC is connected in parallel with the second comparator.
[0039] Please refer to Figure 2 and Figure 3 , to illustrate by example, the incremental multi-stage cascade Sigma-Delta ADC is used to quantize the input signal, and may include a first-stage integrator, a second-stage integrator, a third-stage integrator, and a fourth-stage integrator connected in sequence, and may also include a first comparator, a second comparator, and a number of switches and capacitors. As shown in the figure, the incremental multi-stage cascade Sigma-Delta ADC preferred in the embodiment of the invention is a MASH2-2 Sigma-Delta ADC architecture, that is, the incremental multi-stage cascade Sigma-Delta ADC has two groups of outputs, and two integrators are one group of outputs. And after the input signal is quantized by the incremental multi-stage cascade Sigma-Delta ADC 10, the residual sampling (that is, the residual voltage) of the last stage integrator (for example, the fourth stage integrator) is used as the input signal of the SAR ADC to continue quantization, and the quantization result is added to the final output to improve the overall accuracy, and then the high-precision digital output code corresponding to the input signal is output through the filter module. Further, the overall circuit is implemented by a switch and capacitor structure, and the local chopping technology can be used to eliminate the 1 / f noise and offset of the operational amplifier.
[0040] Need to explain, Figure 3This is an example circuit diagram of an incremental multi-stage cascade Sigma-Delta ADC according to an embodiment of the present invention. The embodiment of the present invention does not limit the order, structure, circuit structure, system parameters, etc. of the incremental multi-stage cascade Sigma-Delta ADC.
[0041] The incremental multi-stage cascaded Sigma-Delta ADC preferably in the embodiment of the present invention may also include a feedback DAC structure.
[0042] Preferably, when the incremental multi-stage cascade Sigma-Delta ADC is a feedback cascade integrator structure, the feedback DAC structure is: the output end of the first comparator is respectively connected to the operational amplifier of the first-stage integrator and the operational amplifier of the second-stage integrator, and the output end of the second comparator is respectively connected to the operational amplifier of the third-stage integrator and the operational amplifier of the fourth-stage integrator.
[0043] Please refer to Figure 3 and Figure 4 To illustrate, the incremental multi-stage cascaded Sigma-Delta ADC can be a feedback cascade integrator structure (CIFB). Each stage of the CIFB structure integrator must process feedback signals containing many high-frequency components, so the bandwidth requirements of the op amps in each stage of the integrator are similar, the power consumption is relatively large, and the output swing of the integrator is generally large, which also requires a large swing of the op amp.
[0044] Preferably, when the incremental multi-stage cascade Sigma-Delta ADC is a feedforward cascade integrator structure, the feedback DAC structure is: the output end of the first comparator is connected to the adder of the first-stage integrator, the output end of the second comparator is connected to the adder of the third-stage integrator, the input interface and the output end of the first-stage integrator are connected to the adder of the output end of the second-stage integrator, and the output end of the first comparator and the output end of the third-stage integrator are connected to the adder of the output end of the fourth-stage integrator.
[0045] Please refer to Figure 5 , for example, the incremental multi-stage cascaded Sigma-Delta ADC can be a feedforward cascade integrator structure (CIFF). In the CIFF structure, only the first-stage integrator needs to process the high-frequency signal fed back, and the bandwidth requirement of the op amp in the subsequent integrator will be reduced step by step, which is conducive to low-power design.
[0046] Preferably, the voltage connected to the input interface is V in , the voltage at the output of the first stage integrator is V O1 The voltage across the output of the second stage integrator is V O2, the voltage at the output of the third stage integrator is V O3 , the voltage at the output end of the fourth stage integrator is V O4 The voltage at the output of the first comparator is d1, the voltage at the output of the second comparator is d2, and the output value of the filter module is D out , then, the time domain relationship of the incremental multi-stage cascaded Sigma-Delta ADC is expressed by the following formula:
[0047]
[0048] Among them, n, l, m, k represent clock cycles, λ1 represents the first-order coefficient, λ2 represents the second-order coefficient, λ3 represents the third-order coefficient, λ4 represents the fourth-order coefficient, λ e represents the error term coefficient, and i represents the i-th clock cycle.
[0049] For example, for an ideal incremental Sigma-Delta ADC, if the input V in If it is an ideal DC signal with a fixed value, then at any cycle after reset, the outputs d1 and d2 of the two comparators can be uniquely determined. Therefore, the output voltage V O1 、V O2 、V O3 、V O4 With V in Based on this, the embodiment of the present invention can obtain the transfer function of the incremental multi-stage cascade Sigma-Delta ADC based on the time domain, and further implement the "decimation filtering" processing of the incremental multi-stage cascade Sigma-Delta ADC code stream, that is, V in The quantitative results of D out Please combine Figure 3 and Figure 4 For example, determining the time domain relationship for an incremental multi-stage cascaded Sigma-Delta ADC includes:
[0050] 1) Set the analog domain signal V in 、V O1 、V O2 、V O3 、V O4 The value range is, for example, [-1, 1], that is, V DD =1, V SS =-1, the reference voltage of the feedback signal V REF =1.
[0051] 2) The outputs d1 and d2 of the two comparators are the quantized code values of their corresponding analog inputs, that is, they are equal to the output after passing through the ideal DAC. From the reset process, we can see that the initial state is:
[0052] V O1 [0] = 0, V O2 [0]=0,V O3 [0]=0,V O4 [0] = 0 (2)
[0053] 3) After one cycle, the integrator is updated:
[0054] V O1 [1]=V O1 [0]+b1V in [0]-a1d1[0] (3)
[0055] V O2 [1]=V O2 [0]+c1V O1 [0]-a2d1[0] (4)
[0056] V O3 [1] = V O3 [0]+c2V O2 [0]-a3d2[0] (5)
[0057] V O4 [1]=V O4 [0]+c3V O3 [0]-a4d2[0] (6)
[0058] 4) Iterate and derive:
[0059]
[0060] 5) Assume V in The input is a constant u, then:
[0061]
[0062] in:
[0063]
[0064] The filter module preferably in the embodiment of the present invention can be configured to: convert the digital code D1 output by the first comparator, the digital code D2 output by the second comparator, and the digital code D output by the residual quantization ADC SAR The extraction filter is performed, and then the digital output code with a preset number of bits is spliced through summation, accumulation and logical operations.
[0065] Continuing with the above example, the coefficients b1, c1, c2, and c3 of the error term shown in formula 13) determine the resolution of the residual quantization ADC. For example, 12 bits are required. Within a limited time, the quantization speed of the Single Slope ADC is too slow. The Flash ADC with a 12-bit resolution requires 256 comparators, which is too costly to implement. Both the Cyclic ADC and the Pipeline ADC require additional op amps, which consume too much power. In order to take into account high speed, high resolution, and low power consumption, the embodiment of the present invention preferably uses a SAR ADC to quantize the residual voltage. Among them, the architecture of the SAR ADC is traditional, RC, and CR hybrid, all of which are within the protection scope of the embodiment of the present invention. Then, through a filter module, such as a digital decimation filter, the digital code D1 output by the first comparator, the digital code D2 output by the second comparator, and the digital code D of the SAR ADC are combined. SAR The decimation filter is performed, and then the digital output code with a preset number of bits (for example, 24 bits) is spliced through summation, accumulation and logical operations. Figure 6 An example implementation of the extended count is shown:
[0066] 1) When the oversampling ratio (OSR) = 32, the precision of the incremental multi-stage cascaded Sigma-Delta ADC is 16 bits. By selecting appropriate system parameters, the high 8-bit data output of the SAR ADC can be aligned with the 16-bit data output of the incremental Sigma-Delta ADC. Then, by shifting right by 4 bits, i.e., 1 / 2, 1 / 4, 1 / 8, and 1 / 16, the 4-bit code value of extended precision can be obtained. ISD <15:0> and D SAR <3:0> is used as the input signal and sent to the digital decimation filter to obtain a 20-bit resolution digital output code D out <19:0>.
[0067] 2) When OSR = 64, the accuracy of the incremental multi-stage cascaded Sigma-Delta ADC reaches 20 bits. At this time, the digital extraction filter adds the 4-bit code value extended by the SAR ADC during the calculation to obtain a 24-bit resolution digital output code D out <23:0>.
[0068] 3) When OSR = 96, the accuracy of the incremental multi-stage cascaded Sigma-Delta ADC reaches 22 bits. At this time, when the digital extraction filter is operating, it only needs to add the 2-bit code value expanded by the SAR ADC to obtain a 24-bit resolution digital output code D out <23:0>.
[0069] 4) When OSR = 128, the accuracy of the incremental multi-stage cascaded Sigma-Delta ADC reaches 24 bits, and the digital extraction filter can directly output a 24-bit resolution digital output code D out <23:0>.
[0070] It can be seen from the above process that, under the four levels of oversampling rate, the digital decimation filters are slightly different, and the circuit structure can be set to, for example, 4 digital decimation filters that match the oversampling rate.
[0071] The extended counting analog-to-digital converter structure preferably in the embodiment of the present invention may also include a clock generation module for generating a switch control signal required for the chip to work. Figure 7 As shown, for example, it may include a two-phase non-overlapping clock, a multi-stage delayed switch control signal, etc.
[0072] Accordingly, in the embodiment of the present invention, based on the extended counting analog-to-digital converter structure composed of an incremental multi-stage cascaded Sigma-Delta ADC and a residue quantization ADC, after the input signal is quantized by the incremental multi-stage cascaded Sigma-Delta ADC, the residue sampling (i.e., the residual voltage) is further quantized as the input signal of the residue quantization ADC, and then the high-precision digital output code corresponding to the input signal is output through the filter module; the residue quantization process can effectively improve the accuracy of the extended counting of the embodiment of the present invention without increasing the oversampling rate, and realize high-speed and high-precision quantization output at a lower oversampling rate.
[0073] Specifically, for the stringent requirements of electronic design in the imaging field (e.g., medical and security inspection fields), for example, for the high-precision requirements of wide input signal swing and at least 24-bit resolution, the accuracy of the traditional Sigma-Delta ADC is limited by the oversampling rate and the modulator order, and the single-loop high-order Sigma-Delta ADC will have system parameter design and stability problems. The embodiments of the present invention solve the above problems through an incremental Sigma-Delta ADC architecture and a high-order multi-stage cascaded Sigma-Delta ADC architecture (e.g., MASH2-2 Sigma-Delta ADC architecture). In addition, another problem caused by the requirement of wide input swing is that the scaling factor of the integrator will be relatively small. It can be seen from the time domain equation of the transfer function derived above that the residual voltage is amplified multiple times by the coefficient, and residual quantization must be performed to meet the requirements of more than 24-bit accuracy.
[0074] Furthermore, the embodiment of the present invention is based on a combination of high-speed, high-precision Sigma-Delta extended count ADC architecture and digital decimation filter time domain filtering technology, which not only combines the high precision of Sigma-Delta ADC and the high speed and low power consumption advantages of Nyquist frequency ADC, but also the time domain filtering scheme of the digital decimation filter is simplified compared to the design of the traditional FIR filter, and has the advantages of high integration, high resolution, high linearity, low offset, low noise, low power consumption, etc. Multi-channel data sampling and readout with a resolution of more than 24 bits can be achieved without a calibration algorithm, reducing the complexity of the sensor interface readout chip system design, and is suitable for application scenarios such as multi-channel signal measurement and industrial control.
[0075] An embodiment of the present invention further provides an electronic component, wherein the electronic component includes the extended counting analog-to-digital converter structure as claimed in the claims.
[0076] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.
[0077] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.
Claims
1. An extended counting analog-to-digital converter structure, characterized in that: The extended counting analog-to-digital converter structure includes an incremental multi-stage cascaded Sigma-Delta ADC, a residual quantization ADC and a filter module. The input interface is connected to the incremental multi-stage cascade Sigma-Delta ADC and the residual quantization ADC in sequence, the output end of the incremental multi-stage cascade Sigma-Delta ADC and the output end of the residual quantization ADC are connected to the filter module, and the filter module is connected to the output interface. The incremental multi-stage cascade Sigma-Delta ADC is used to quantize the input signal, the residual quantization ADC is used to re-quantize the residual sampling after quantization by the incremental multi-stage cascade Sigma-Delta ADC, and the filter module is used to output the digital output code corresponding to the input signal.
2. The extended counting analog-to-digital converter structure according to claim 1, characterized in that: The residual quantization ADC is a successive approximation ADC.
3. The extended counting analog-to-digital converter structure according to claim 1, characterized in that: The incremental multi-stage cascade Sigma-Delta ADC comprises a first-stage integrator, a second-stage integrator, a third-stage integrator, and a fourth-stage integrator which are connected in sequence. The output end of the second-stage integrator is connected to the first comparator, and the output end of the first comparator is used as the first output end of the incremental multi-stage cascaded Sigma-Delta ADC and connected to the filter module. The output end of the fourth-stage integrator is connected to the second comparator, and the output end of the second comparator is used as the second output end of the incremental multi-stage cascade Sigma-Delta ADC and connected to the filter module. The residual quantization ADC is connected in parallel with the second comparator.
4. The extended counting analog-to-digital converter structure according to claim 3, characterized in that: The incremental multi-stage cascaded Sigma-Delta ADC also includes a feedback DAC structure.
5. The extended counting analog-to-digital converter structure according to claim 4, characterized in that: When the incremental multi-stage cascaded Sigma-Delta ADC is a feedback cascaded integrator structure, the feedback DAC structure is: The output end of the first comparator is connected to the operational amplifier of the first stage integrator and the operational amplifier of the second stage integrator respectively. The output end of the second comparator is connected to the operational amplifier of the third stage integrator and the operational amplifier of the fourth stage integrator respectively.
6. The extended counting analog-to-digital converter structure according to claim 4, characterized in that: When the incremental multi-stage cascaded Sigma-Delta ADC is a feedforward cascaded integrator structure, the feedback DAC structure is: The output end of the first comparator is connected to the adder of the first stage integrator, and the output end of the second comparator is connected to the adder of the third stage integrator. The input interface and the output end of the first stage integrator are connected to the adder of the output end of the second stage integrator, An adder is connected to the output end of the first comparator and the output end of the third-stage integrator.
7. The extended counting analog-to-digital converter structure according to claim 3, characterized in that: The voltage connected to the input interface is V in , the voltage at the output of the first stage integrator is V O1 The voltage across the output of the second stage integrator is V O2 , the voltage at the output of the third stage integrator is V O3 , the voltage at the output end of the fourth stage integrator is V O4 The voltage at the output of the first comparator is d1, the voltage at the output of the second comparator is d2, and the output value of the filter module is D out , then, the time domain relationship of the incremental multi-stage cascaded Sigma-Delta ADC is expressed by the following formula: Among them, n, l, m, k represent clock cycles, λ1 represents the first-order coefficient, λ2 represents the second-order coefficient, λ3 represents the third-order coefficient, λ4 represents the fourth-order coefficient, λ e represents the error term coefficient, and i represents the i-th clock cycle.
8. The extended counting analog-to-digital converter structure according to claim 3, characterized in that: The filter module is configured as follows: The digital code D1 output by the first comparator, the digital code D2 output by the second comparator, and the digital code D output by the residual quantization ADC are SAR The extraction filter is performed, and then the digital output code with a preset number of bits is spliced through summation, accumulation and logical operations.
9. The extended counting analog-to-digital converter structure according to claim 1, characterized in that: The extended counting analog-to-digital converter structure also includes a clock generating module for generating a switch control signal required for the chip to work.
10. An electronic component, characterized in that: The electronic component comprises the extended counting analog-to-digital converter structure as described in any one of claims 1-9.