Frequency synthesizer module of frequency conversion module and signal processing method of frequency synthesizer module

Abstract

In order to solve the problem of narrow bandwidth of LO2 signals in the prior art, the invention provides a frequency synthesizer module of a frequency conversion module and a signal processing method of the frequency synthesizer module. The frequency synthesizer module of the frequency conversion module comprises a self-adaptive reference AGC module which is used for realizing automatic gain control of a reference signal; the input end of the clock distribution module is connected with the output end of the self-adaptive reference AGC module, and the clock distribution module is used for generating a clock signal; the input end of the universal local oscillator module is connected with the output end of the clock distribution module, and the universal local oscillator module is used for generating an input signal of the frequency conversion module; the output end of the power supply control module is connected with the input end of the self-adaptive reference AGC module, the input end of the clock distribution module and the input end of the universal local oscillator module, and the power supply control module is used for providing voltage. According to the frequency mixing technology, the upper limit of the LO2 signal frequency is improved by 40.4 GHz. Four paths of LO signals can be output simultaneously, and four frequency conversion channels are supported to work simultaneously.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a frequency synthesis module of a frequency conversion module and a signal processing method of the frequency synthesis module. Background Art

[0002] One of the main functions of the frequency synthesizer module is to generate stable and accurate multiple frequency signals. In the frequency conversion module, it can synthesize the required local oscillator (LO) signal according to the system requirements. The local oscillator (LO) signal includes LO1 signal and LO2 signal. In the communication system, in order to realize the frequency conversion processing of signals in different frequency bands, the frequency synthesizer module can generate multiple local oscillator (LO) signals of different frequencies.

[0003] In the prior art, the LO2 signal frequency generated by the frequency synthesizer module has the defect of a low upper limit, which is basically 40 GHz. Summary of the invention

[0004] In order to solve the problem of narrow bandwidth of LO2 signal in the prior art, the present invention provides a frequency synthesis module of a frequency conversion module and a signal processing method of the frequency synthesis module.

[0005] The technical solution adopted by the present invention is: A frequency synthesis module of a frequency conversion module, comprising: An adaptive reference AGC module, wherein the adaptive reference AGC module is used to implement automatic gain control of a reference signal.

[0006] A clock distribution module, the input end of which is connected to the output end of the adaptive reference AGC module, is used to generate a clock signal.

[0007] A universal local oscillator module, the input end of which is connected to the output end of the clock distribution module, and is used to generate an input signal for the frequency conversion module.

[0008] A power control module, the output end of which is connected to the input end of the adaptive reference AGC module, the input end of the clock distribution module and the input end of the universal local oscillator module, for providing voltage.

[0009] Further, the adaptive reference AGC module includes: Power divider A, Attenuator A, the input end of the attenuator A is connected to an output end of the power divider A.

[0010] Amplifier A, the input end of the amplifier A is connected to the output end of the attenuator A.

[0011] An attenuator B, wherein an input end of the attenuator B is connected to an output end of the amplifier A.

[0012] Amplifier B, the input end of the amplifier B is connected to the output end of the attenuator B. The output end of the amplifier B is the output end of the adaptive reference AGC module.

[0013] Detector A, the input end of the detector A is connected to the other output end of the power divider A.

[0014] An ADC chip, wherein the input end of the ADC chip is connected to the output end of the detector A.

[0015] FPGA, the FPGA is connected to the detector A and is used to receive the data collected by the ADC chip, so as to realize automatic gain control of the reference signal.

[0016] Furthermore, the clock distribution module includes: Attenuator C; the input end of the attenuator C is connected to the output end of the amplifier B.

[0017] A switch A, one input end of the switch A is connected to the output end of the attenuator C, and the other input end of the switch A is grounded.

[0018] A 10M internal reference signal source provides a 10MHz internal reference signal.

[0019] Switch B, one input end of the switch B is connected to the output end of the 10M internal reference signal source, and the other input end of the switch B is grounded.

[0020] Switch C, one input end of the switch C is connected to the output end of the switch A, and the other input end of the switch C is connected to the output end of the switch B.

[0021] A frequency divider A, wherein an input end of the frequency divider A is connected to an output end of the switch C.

[0022] A 100M reference source, wherein the input end of the 100M reference source is connected to the output end of the frequency divider A.

[0023] Amplifier C, the input end of the amplifier C is connected to the output end of the 100M reference source.

[0024] A filter A, wherein the input end of the filter A is connected to the output end of the amplifier C.

[0025] A power divider B, wherein the input end of the power divider B is connected to the output end of the filter A.

[0026] A power divider C, wherein an input end of the power divider C is connected to an output end of the power divider B.

[0027] An attenuator D, wherein an input end of the attenuator D is connected to another output end of the power divider B.

[0028] A power divider D, wherein an input end of the power divider D is connected to an output end of the power divider C.

[0029] An attenuator G, wherein an input end of the attenuator G is connected to an output end of the power divider D. The attenuator G outputs a 100 MHz clock signal.

[0030] An attenuator F, wherein the input end of the attenuator F is connected to the other output end of the power divider D. The attenuator F outputs a 100 MHz clock signal.

[0031] A power divider E, wherein an input end of the power divider E is connected to another output end of the power divider C.

[0032] An attenuator E, wherein an input end of the attenuator E is connected to an output end of the power divider E.

[0033] A power divider F, wherein the input end of the attenuator F is connected to the other output end of the power divider E.

[0034] An attenuator H, wherein an input end of the attenuator H is connected to an output end of the power divider F. The attenuator H outputs a 100 MHz clock signal.

[0035] A power divider G, wherein an input end of the power divider G is connected to another output end of the power divider F.

[0036] Furthermore, the universal local oscillator module, when used as a universal slow-frequency integrated local oscillator module, comprises: A frequency multiplier A, wherein the input end of the frequency multiplier A is connected to the output end of the attenuator D.

[0037] A comb spectrum generator A, wherein the input end of the comb spectrum generator A is connected to the output end of the frequency multiplier A.

[0038] A power divider I, wherein the input end of the power divider I is connected to the output end of the comb spectrum generator A.

[0039] A filter B, wherein an input end of the filter B is connected to an output end of the power divider I.

[0040] An amplifier D, wherein an input end of the amplifier D is connected to an output end of the filter B.

[0041] A filter C, wherein an input end of the filter C is connected to an output end of the amplifier D.

[0042] An amplifier E, wherein an input end of the amplifier E is connected to an output end of the filter C.

[0043] A power divider J, wherein the input end of the power divider J is connected to the output end of the amplifier E. The power divider J outputs two local oscillator signals.

[0044] An amplifier F, wherein an input end of the amplifier F is connected to another output end of the power divider I.

[0045] A switching filter A, wherein the input end of the switching filter A is connected to the output end of the amplifier F.

[0046] An amplifier G, wherein an input end of the amplifier G is connected to an output end of the switching filter A.

[0047] A frequency multiplier B, wherein the input end of the frequency multiplier B is connected to the output end of the amplifier G.

[0048] A filter D, wherein the input end of the filter D is connected to the output end of the frequency multiplier B.

[0049] An amplifier H, wherein an input end of the amplifier H is connected to an output end of the filter D.

[0050] A frequency divider B, wherein an input end of the frequency divider B is connected to an output end of the attenuator E.

[0051] A frequency source A, wherein an input end of the frequency source A is connected to an output end of the frequency divider B.

[0052] A mixer A, one input end of the mixer A is connected to the output end of the frequency source A, and the other input end of the mixer A is connected to the output end of the amplifier H.

[0053] A switching filter B, wherein an input end of the switching filter B is connected to an output end of the mixer A.

[0054] An amplifier I, wherein an input end of the amplifier I is connected to an output end of the switching filter B.

[0055] A filter E, wherein an input end of the filter E is connected to an output end of the amplifier I.

[0056] An amplifier J, wherein an input end of the amplifier J is connected to an output end of the filter E.

[0057] A power divider K, wherein the input end of the power divider K is connected to the output end of the amplifier J. The power divider K outputs two local oscillator signals.

[0058] Furthermore, the universal local oscillator module can be used as a universal fast-frequency integrated local oscillator module, and when used as a universal fast-frequency integrated local oscillator module, it includes: Frequency multiplier A1.

[0059] A comb spectrum generator A1, wherein the input end of the comb spectrum generator A1 is connected to the output end of the frequency multiplier A1.

[0060] A power divider I1, wherein an input end of the power divider I1 is connected to an output end of the comb spectrum generator A1.

[0061] Filter B1, the input end of the filter B1 is connected to an output end of the power divider I1.

[0062] Amplifier D1, the input end of the amplifier D1 is connected to the output end of the filter B1.

[0063] The filter C1 has an input end connected to the output end of the amplifier D1.

[0064] Amplifier E1, the input end of the amplifier E1 is connected to the output end of the filter C1.

[0065] A power divider J1, the input end of which is connected to the output end of the amplifier E1. The power divider J1 outputs two local oscillator signals.

[0066] Amplifier F1, the input end of the amplifier F1 is connected to the other output end of the power divider I1.

[0067] A switching filter A1, wherein the input end of the switching filter A1 is connected to the output end of the amplifier F1.

[0068] Amplifier G1, the input end of the amplifier G1 is connected to the output end of the switching filter A1.

[0069] A frequency multiplier B1, wherein an input end of the frequency multiplier B1 is connected to an output end of the amplifier G1.

[0070] A filter D1, wherein the input end of the filter D1 is connected to the output end of the frequency multiplier B1.

[0071] Amplifier H1, the input end of the amplifier H1 is connected to the output end of the filter D1.

[0072] The frequency divider B1 has an input end connected to the output end of the attenuator E.

[0073] A comb spectrum generator A2, wherein the input end of the comb spectrum generator A2 is connected to the output end of the frequency divider B1.

[0074] A frequency source A1, wherein an input end of the frequency source A1 is connected to an output end of the power divider G.

[0075] DDS, the input end of the DDS is connected to the output end of the frequency source A1.

[0076] A mixer A2, one input end of the mixer A2 is connected to the output end of the comb spectrum generator A2. Another input end of the mixer A2 is connected to the output end of the DDS.

[0077] A switching filter B2, wherein an input end of the switching filter B2 is connected to an output end of the mixer A2.

[0078] A mixer A1, one input end of the mixer A1 is connected to the output end of the amplifier H1. Another input end of the mixer A1 is connected to the output end of the switch filter B2.

[0079] A switching filter B1, wherein an input end of the switching filter B1 is connected to an output end of the mixer A1.

[0080] Amplifier I1, the input end of the amplifier I1 is connected to the output end of the switching filter B1.

[0081] A filter E1, wherein an input end of the filter E1 is connected to an output end of the amplifier I1.

[0082] Amplifier J1, the input end of the amplifier J1 is connected to the output end of the filter E1.

[0083] A power divider K1, the input end of which is connected to the output end of the amplifier J1. The power divider K1 outputs two local oscillator signals.

[0084] Furthermore, the FPGA is connected to the detector A to receive the data collected by the ADC chip, so as to realize the specific method of automatic gain control of the reference signal: the REF signal outside the frequency synthesis module enters the power divider A, and the power divider A outputs 2 signals, 1 of which is detected by the detector A, and then the detected analog voltage is sampled by the ADC chip, and the sampled data is transmitted to the FPGA for data collection, so as to realize the automatic gain control of the reference signal. At the same time, the presence or absence of an external reference signal can be determined according to the data collected by the FPGA, and the automatic switching of the internal and external references can be realized according to the result of the determination of the presence or absence of the external reference signal. The FPGA can also transmit the current internal and external reference status back to the host computer in real time for reporting. The other 1 signal path output by the power divider A enters the clock distribution module after amplification, attenuation, and amplification.

[0085] Further, when the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the frequency source A1 is a 3.5 GHz point frequency source, and the 3.5 GHz point frequency source includes: A point frequency source phase detector, the input end of which is connected to the output end of the power divider G. The input end of the point frequency source phase detector is the input end of the frequency source A1.

[0086] A point frequency source VCO, wherein an input end of the point frequency source VCO is connected to an output end of the point frequency source phase detector.

[0087] A point frequency source power divider, wherein the input end of the point frequency source power divider is connected to the output end of the point frequency source VCO.

[0088] A point frequency source amplifier A, wherein the input end of the point frequency source amplifier A is connected to an output end of the point frequency source power divider. The output end of the point frequency source amplifier A is connected to the input end of the DDS.

[0089] A point frequency source amplifier B, wherein the input end of the point frequency source amplifier B is connected to another output end of the point frequency source power divider. The output end of the point frequency source amplifier B is connected to the input end of the point frequency source phase detector.

[0090] Furthermore, when the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the DDS is connected to the FPGA, the 3.5 GHz point frequency source provides a 3.5 GHz reference signal to the DDS, and the FPGA controls the DDS to make the DDS generate a frequency jump.

[0091] A signal processing method of a frequency synthesis module of a frequency conversion module is implemented based on the frequency synthesis module of the frequency conversion module described above, comprising the steps of: Step S1: The power control module provides voltage to the adaptive reference AGC module, the clock distribution module and the universal local oscillator module.

[0092] Step S2: the reference signal REF outside the frequency synthesis module enters the adaptive reference AGC module, and the adaptive reference AGC module is used to implement automatic gain control of the reference signal to generate an automatic gain signal REF-O.

[0093] Step S3: the automatic gain signal REF-0 enters the clock distribution module, the input end of the clock distribution module is connected to the output end of the adaptive reference AGC module, and is used to generate a clock signal.

[0094] Step S4: the clock signal generated by the adaptive reference AGC module enters the universal local oscillator module, and the universal local oscillator module generates input signals LO1 and LO2 of the frequency conversion module.

[0095] The beneficial effects of the present invention are: The LO1 signal of the present invention directly performs frequency multiplication, filtering, amplification and power division on the reference signal and then outputs it. The design scheme is simple, avoids the introduction of other non-related signals, and ensures better output signal quality. The LO2 signal adds mixing and filtering processing on the basis of the LO1 signal, reducing the introduction of other signals.

[0096] The frequency mixing technology of the present invention increases the upper limit of the LO2 signal frequency by 40.4 GHz, and the function is more powerful.

[0097] The present invention can output 4 LO signals simultaneously and support 4 frequency conversion channels to work simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0098] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0099] Figure 1 This is the overall structure diagram of the frequency synthesis module.

[0100] Figure 2 The general local oscillator module is a structural diagram of a general fast local oscillator module.

[0101] Figure 3 This is the structural diagram of the 3.5GHz point frequency source. DETAILED DESCRIPTION

[0102] The following disclosure provides examples which are not intended to limit the present invention.

[0103] The embodiments of the invention are described in detail below with reference to the accompanying drawings.

[0104] A frequency synthesis module of a frequency conversion module, as shown in the attached Figure 1 As shown, including: An adaptive reference AGC module, wherein the adaptive reference AGC module is used to implement automatic gain control of a reference signal.

[0105] A clock distribution module, wherein an input end of the clock distribution module is connected to an output end of the adaptive reference AGC module, and is used to generate a clock signal.

[0106] A universal local oscillator module, the input end of which is connected to the output end of the clock distribution module, and is used to generate an input signal for the frequency conversion module.

[0107] A power control module, the output end of which is connected to the input end of the adaptive reference AGC module, the input end of the clock distribution module and the input end of the universal local oscillator module, for providing voltage.

[0108] This embodiment adds external devices and modules based on the complete structure of the reference processing module: The reference signal source is used to provide a reference signal, referred to as REF. The host computer is used to send instructions to the frequency synthesis module of this embodiment.

[0109] The reference signal REF enters the adaptive reference AGC module, which generates the automatic gain signal REF-O. REF-O enters the clock distribution module, which provides the clock for the universal local oscillator module. The universal local oscillator module generates a 100MHz signal, LO1 signal, and LO2 signal, which enter the frequency synthesis module. The power control module provides voltage for the adaptive reference AGC module, the clock distribution module, and the universal local oscillator module.

[0110] Further, the adaptive reference AGC module, as shown in the attached Figure 1 As shown, including: A power divider A, wherein the input end of the power divider A is connected to the output end of the reference signal source, and the reference signal source provides a reference signal.

[0111] Attenuator A (attenuation 0.5 dB in this embodiment), the input end of the attenuator A is connected to an output end of the power divider A.

[0112] Amplifier A, the input end of the amplifier A is connected to the output end of the attenuator A.

[0113] Attenuator B (attenuation 0.5 dB in this embodiment), the input end of the attenuator B is connected to the output end of the amplifier A.

[0114] Amplifier B, the input end of the amplifier B is connected to the output end of the attenuator B. The output end of the amplifier B is the output end of the adaptive reference AGC module.

[0115] Detector A, the input end of the detector A is connected to the other output end of the power divider A.

[0116] An ADC chip, wherein the input end of the ADC chip is connected to the output end of the detector A.

[0117] FPGA, the FPGA is connected to the detector A and is used to receive the data collected by the ADC chip, so as to realize automatic gain control of the reference signal.

[0118] Furthermore, the clock distribution module, as shown in the attached Figure 1 As shown, including: Attenuator C; the input end of the attenuator C is connected to the output end of the amplifier B.

[0119] A switch A, one input end of the switch A is connected to the output end of the attenuator C, and the other input end of the switch A is grounded.

[0120] A 10M internal reference signal source provides a 10MHz internal reference signal.

[0121] Switch B, one input end of the switch B is connected to the output end of the 10M internal reference signal source, and the other input end of the switch B is grounded.

[0122] Switch C, one input end of the switch C is connected to the output end of the switch A, and the other input end of the switch C is connected to the output end of the switch B.

[0123] A frequency divider A, wherein an input end of the frequency divider A is connected to an output end of the switch C.

[0124] A 100M reference source, wherein the input end of the 100M reference source is connected to the output end of the frequency divider A.

[0125] Amplifier C, the input end of the amplifier C is connected to the output end of the 100M reference source.

[0126] A filter A, wherein the input end of the filter A is connected to the output end of the amplifier C.

[0127] A power divider B, wherein the input end of the power divider B is connected to the output end of the filter A.

[0128] A power divider C, wherein an input end of the power divider C is connected to an output end of the power divider B.

[0129] Attenuator D (attenuation 5 dB in this embodiment), the input end of the attenuator D is connected to the other output end of the power divider B.

[0130] A power divider D, wherein an input end of the power divider D is connected to an output end of the power divider C.

[0131] Attenuator G (attenuation 2 dB in this embodiment), the input end of the attenuator G is connected to an output end of the power divider D. The attenuator G outputs a 100 MHz clock signal.

[0132] Attenuator F (attenuation 2dB in this embodiment), the input end of the attenuator F is connected to the other output end of the power divider D. The attenuator F outputs a 100MHz clock signal.

[0133] A power divider E, wherein an input end of the power divider E is connected to another output end of the power divider C.

[0134] Attenuator E (attenuation 0 dB in this embodiment), the input end of the attenuator E is connected to an output end of the power divider E.

[0135] A power divider F, wherein the input end of the attenuator F is connected to the other output end of the power divider E.

[0136] Attenuator H (attenuation 3dB in this embodiment), the input end of the attenuator H is connected to an output end of the power divider F. The attenuator H outputs a 100MHz clock signal.

[0137] A power divider G, wherein an input end of the power divider G is connected to another output end of the power divider F.

[0138] As attached Figure 1 As shown. The signal processed by the adaptive reference AGC module is REF-O. After attenuation and amplification processing and the reference signal source within 10M, it can be selected through switch C (the on and off of the switch is controlled by FPGA) to provide reference for the 100M reference source oscillator. The 100M reference source generates a 100M signal. After amplification, the signal passes through a multi-stage power divider to generate multiple output signals, among which 100M-O1 and 100M-O3 provide reference signals for the general local oscillator module. 100M-1, 100M-2 and 100M-O2 are directly output as 100M clocks, and 100M-3 and 100M-4 are reserved ports for function expansion.

[0139] Further, the universal local oscillator module is used as a universal slow frequency integrated local oscillator module. When used as a universal slow frequency integrated local oscillator module, as shown in the attached Figure 1 As shown, including: A frequency multiplier A, wherein the input end of the frequency multiplier A is connected to the output end of the attenuator D.

[0140] A comb spectrum generator A, wherein the input end of the comb spectrum generator A is connected to the output end of the frequency multiplier A.

[0141] A power divider I, wherein the input end of the power divider I is connected to the output end of the comb spectrum generator A.

[0142] A filter B, wherein an input end of the filter B is connected to an output end of the power divider I.

[0143] An amplifier D, wherein an input end of the amplifier D is connected to an output end of the filter B.

[0144] A filter C, wherein an input end of the filter C is connected to an output end of the amplifier D.

[0145] An amplifier E, wherein an input end of the amplifier E is connected to an output end of the filter C.

[0146] A power divider J, wherein the input end of the power divider J is connected to the output end of the amplifier E. The power divider J outputs two local oscillator signals.

[0147] An amplifier F, wherein an input end of the amplifier F is connected to another output end of the power divider I.

[0148] A switching filter A, wherein the input end of the switching filter A is connected to the output end of the amplifier F.

[0149] An amplifier G, wherein an input end of the amplifier G is connected to an output end of the switching filter A.

[0150] A frequency multiplier B, wherein the input end of the frequency multiplier B is connected to the output end of the amplifier G.

[0151] A filter D, wherein the input end of the filter D is connected to the output end of the frequency multiplier B.

[0152] An amplifier H, wherein an input end of the amplifier H is connected to an output end of the filter D.

[0153] A frequency divider B, wherein an input end of the frequency divider B is connected to an output end of the attenuator E.

[0154] A frequency source A, wherein an input end of the frequency source A is connected to an output end of the frequency divider B.

[0155] A mixer A, one input end of the mixer A is connected to the output end of the frequency source A, and the other input end of the mixer A is connected to the output end of the amplifier H.

[0156] A switching filter B, wherein an input end of the switching filter B is connected to an output end of the mixer A.

[0157] An amplifier I, wherein an input end of the amplifier I is connected to an output end of the switching filter B.

[0158] A filter E, wherein an input end of the filter E is connected to an output end of the amplifier I.

[0159] An amplifier J, wherein an input end of the amplifier J is connected to an output end of the filter E.

[0160] A power divider K, wherein the input end of the power divider K is connected to the output end of the amplifier J. The power divider K outputs two local oscillator signals.

[0161] As attached Figure 1 As shown, the signal generated by the 100M-O1 signal after the frequency multiplier is used as the reference signal of the comb spectrum generator A (the 2G comb spectrum generator is selected in this embodiment). The 2G comb spectrum generator generates a series of frequency spectra, which are divided into 2 paths after two power splitters (power splitter I). One path passes through filter B to select the 26GHz signal, which is filtered out by filter B to remove clutter and then divided into 2 LO1 signals for use by the frequency conversion module.

[0162] The other path passes through the amplifier and selects 14G / 16G / 18G / 20G signals respectively through the switch filter A. The signal is amplified by the amplifier F and then doubled by the filter B. The 28~40GHz signal is selected by the filter D. The 28~40G signal is amplified and used as the LO signal of the mixer A.

[0163] After being divided by divider B, 100M-O3 is used as the reference signal of frequency source A (2594 frequency source is selected in this embodiment). The IF signal generated by the 2594 frequency source is mixed with the 28~40GHz LO signal to generate an RF signal. Different filters in the switch filter A are used to select 24.2~26.5GHz / 26.5~30.5GHz / 30.5~34.5GHz / 34.5~38.5GHz / 38.5~40.4GHz signals respectively. After amplification, filtering and power division, two LO2 signals are output for use by the frequency conversion module.

[0164] Furthermore, the universal local oscillator module can be used as a universal fast frequency integrated local oscillator module, as shown in the attached Figure 2 As shown, when used as a general fast frequency integrated local oscillator module, it includes: Frequency multiplier A1.

[0165] A comb spectrum generator A1, wherein the input end of the comb spectrum generator A1 is connected to the output end of the frequency multiplier A1.

[0166] A power divider I1, wherein an input end of the power divider I1 is connected to an output end of the comb spectrum generator A1.

[0167] Filter B1, the input end of the filter B1 is connected to an output end of the power divider I1.

[0168] Amplifier D1, the input end of the amplifier D1 is connected to the output end of the filter B1.

[0169] The filter C1 has an input end connected to the output end of the amplifier D1.

[0170] Amplifier E1, the input end of the amplifier E1 is connected to the output end of the filter C1.

[0171] A power divider J1, the input end of which is connected to the output end of the amplifier E1. The power divider J1 outputs two local oscillator signals.

[0172] Amplifier F1, the input end of the amplifier F1 is connected to the other output end of the power divider I1.

[0173] A switching filter A1, wherein the input end of the switching filter A1 is connected to the output end of the amplifier F1.

[0174] Amplifier G1, the input end of the amplifier G1 is connected to the output end of the switching filter A1.

[0175] A frequency multiplier B1, wherein an input end of the frequency multiplier B1 is connected to an output end of the amplifier G1.

[0176] A filter D1, wherein the input end of the filter D1 is connected to the output end of the frequency multiplier B1.

[0177] Amplifier H1, the input end of the amplifier H1 is connected to the output end of the filter D1.

[0178] The frequency divider B1 has an input end connected to the output end of the attenuator E.

[0179] A comb spectrum generator A2, wherein the input end of the comb spectrum generator A2 is connected to the output end of the frequency divider B1.

[0180] A frequency source A1, wherein an input end of the frequency source A1 is connected to an output end of the power divider G.

[0181] DDS, the input end of the DDS is connected to the output end of the frequency source A1.

[0182] A mixer A2, one input end of the mixer A2 is connected to the output end of the comb spectrum generator A2. Another input end of the mixer A2 is connected to the output end of the DDS.

[0183] A switching filter B2, wherein an input end of the switching filter B2 is connected to an output end of the mixer A2.

[0184] A mixer A1, one input end of the mixer A1 is connected to the output end of the amplifier H1. Another input end of the mixer A1 is connected to the output end of the switch filter B2.

[0185] A switching filter B1, wherein an input end of the switching filter B1 is connected to an output end of the mixer A1.

[0186] Amplifier I1, the input end of the amplifier I1 is connected to the output end of the switching filter B1.

[0187] A filter E1, wherein an input end of the filter E1 is connected to an output end of the amplifier I1.

[0188] Amplifier J1, the input end of the amplifier J1 is connected to the output end of the filter E1.

[0189] A power divider K1, the input end of which is connected to the output end of the amplifier J1. The power divider K1 outputs two local oscillator signals.

[0190] As attached Figure 2 As shown, the signal generated by the 100M-O1 signal after the frequency multiplier is used as the reference signal of the comb spectrum generator A1 (the 2G comb spectrum generator is selected in this embodiment). The 2G comb spectrum generator generates a series of frequency spectra, which are divided into 2 paths after two power splitters (power splitter I1). One path passes through the filter B1 to select the 26G signal, which is filtered out by the filter B1 and then divided into 2 LO1 signals for use by the frequency conversion module.

[0191] The other path passes through the amplifier and selects 14G / 16G / 18G / 20G signals respectively through the switch filter A1. The signal is amplified by the amplifier F1 and then doubled by the filter B1. The filter D1 selects the 28~40G signal. The 28~40G signal is amplified and used as the LO signal of the mixer A1.

[0192] After being divided by the divider, 100M-4 provides a reference signal for the frequency source (a 3.5 GHz point frequency source is selected in this embodiment) to generate a 3.5 GHz signal. The 3.5 GHz signal enters the DDS to provide a clock signal for the DDS. Under the control of the FPGA, the DDS generates a 250-750 MHz baseband signal, which is mixed with the 4.25-7.75 GHz LO signal to generate a 3.5-7.5 GHz intermediate frequency signal, which is then selected by the switch filter to enter the next mixing.

[0193] The 4.25~7.75GHz LO signal is first multiplied by 5 times the 100M-O3 reference signal to generate a 500MHz signal, and then divided by two through the divider B1 to generate a 250MHz signal, thereby driving the comb spectrum generator A2 to generate high-order harmonics 4.25~7.75GHz, and then these point-frequency local oscillator signals are taken out through the switch filter B2 and provided to the baseband mixer for local oscillator drive.

[0194] After entering the next mixing, mixer A1 generates RF signal, and uses different filters in switch filter B1 to select 24.2~26.5GHz / 26.5~30.5GHz / 30.5~34.5GHz / 34.5~38.5GHz / 38.5~40.4GHz signals, and after amplification, filtering and power division, outputs 2 LO2 signals for use by the frequency conversion module.

[0195] Furthermore, the FPGA is connected to the detector A to receive the data collected by the ADC chip, so as to realize the specific method of automatic gain control of the reference signal: the REF signal outside the frequency synthesis module enters the power divider A, and the power divider A outputs 2 signals, 1 of which is detected by the detector A, and then the detected analog voltage is sampled by the ADC chip, and the sampled data is transmitted to the FPGA for data collection, so as to realize the automatic gain control of the reference signal. At the same time, the presence or absence of an external reference signal can be determined according to the data collected by the FPGA, and the automatic switching of the internal and external references can be realized according to the result of the determination of the presence or absence of the external reference signal. The FPGA can also transmit the current internal and external reference status back to the host computer in real time for reporting. The other 1 signal path output by the power divider A enters the clock distribution module after amplification, attenuation, and amplification.

[0196] Further, when the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the frequency source A1 is a 3.5 GHz point frequency source. Figure 3 As shown, including: A point frequency source phase detector, the input end of which is connected to the output end of the power divider G. The input end of the point frequency source phase detector is the input end of the frequency source A1.

[0197] A point frequency source VCO, wherein an input end of the point frequency source VCO is connected to an output end of the point frequency source phase detector.

[0198] A point frequency source power divider, wherein the input end of the point frequency source power divider is connected to the output end of the point frequency source VCO.

[0199] A point frequency source amplifier A, wherein the input end of the point frequency source amplifier A is connected to an output end of the point frequency source power divider. The output end of the point frequency source amplifier A is connected to the input end of the DDS.

[0200] A point frequency source amplifier B, wherein the input end of the point frequency source amplifier B is connected to another output end of the point frequency source power divider. The output end of the point frequency source amplifier B is connected to the input end of the point frequency source phase detector.

[0201] Furthermore, when the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the DDS is connected to the FPGA, the 3.5 GHz point frequency source provides a 3.5 GHz reference signal to the DDS, and the FPGA controls the DDS to make the DDS generate a frequency jump.

[0202] A signal processing method of a frequency synthesis module of a frequency conversion module is implemented based on the frequency synthesis module of the frequency conversion module described above, comprising the steps of: Step S1: The power control module provides voltage to the adaptive reference AGC module, the clock distribution module and the universal local oscillator module.

[0203] Step S2: the reference signal REF outside the frequency synthesis module enters the adaptive reference AGC module, and the adaptive reference AGC module is used to implement automatic gain control of the reference signal to generate an automatic gain signal REF-O.

[0204] Step S3: the automatic gain signal REF-0 enters the clock distribution module, the input end of the clock distribution module is connected to the output end of the adaptive reference AGC module, and is used to generate a clock signal.

[0205] Step S4: the clock signal generated by the adaptive reference AGC module enters the universal local oscillator module, and the universal local oscillator module generates input signals LO1 and LO2 of the frequency conversion module.

Claims

1. A frequency synthesis module of a frequency conversion module, characterized in that: include: An adaptive reference AGC module, wherein the adaptive reference AGC module is used to implement automatic gain control of a reference signal; A clock distribution module, the input end of which is connected to the output end of the adaptive reference AGC module, for generating a clock signal; A universal local oscillator module, the input end of which is connected to the output end of the clock distribution module, and is used to generate an input signal for the frequency conversion module; A power control module, the output end of which is connected to the input end of the adaptive reference AGC module, the input end of the clock distribution module and the input end of the universal local oscillator module, for providing voltage.

2. The frequency synthesis module of the frequency conversion module according to claim 1, characterized in that: The adaptive reference AGC module comprises: Power divider A, An attenuator A, wherein an input end of the attenuator A is connected to an output end of the power divider A; An amplifier A, wherein an input end of the amplifier A is connected to an output end of the attenuator A; an attenuator B, wherein an input end of the attenuator B is connected to an output end of the amplifier A; Amplifier B, the input end of the amplifier B is connected to the output end of the attenuator B; the output end of the amplifier B is the output end of the adaptive reference AGC module; A detector A, the input end of the detector A is connected to the other output end of the power divider A; An ADC chip, wherein the input end of the ADC chip is connected to the output end of the detector A; FPGA, the FPGA is connected to the detector A and is used to receive the data collected by the ADC chip, so as to realize automatic gain control of the reference signal.

3. The frequency synthesis module of the frequency conversion module according to claim 2, characterized in that: The clock distribution module comprises: Attenuator C; the input end of the attenuator C is connected to the output end of the amplifier B; A switch A, one input end of the switch A is connected to the output end of the attenuator C, and the other input end of the switch A is grounded; A 10M internal reference signal source, wherein the 10M internal reference signal source provides a 10MHz internal reference signal; A switch B, wherein one input end of the switch B is connected to the output end of the 10M internal reference signal source, and the other input end of the switch B is grounded; a switch C, wherein one input end of the switch C is connected to the output end of the switch A, and the other input end of the switch C is connected to the output end of the switch B; A frequency divider A, wherein an input end of the frequency divider A is connected to an output end of the switch C; A 100M reference source, the input end of which is connected to the output end of the frequency divider A; An amplifier C, wherein an input end of the amplifier C is connected to an output end of the 100M reference source; A filter A, wherein an input end of the filter A is connected to an output end of the amplifier C; A power divider B, wherein an input end of the power divider B is connected to an output end of the filter A; A power divider C, wherein an input end of the power divider C is connected to an output end of the power divider B; an attenuator D, wherein an input end of the attenuator D is connected to another output end of the power divider B; A power divider D, wherein an input end of the power divider D is connected to an output end of the power divider C; An attenuator G, wherein an input end of the attenuator G is connected to an output end of the power divider D; the attenuator G outputs a 100 MHz clock signal externally; An attenuator F, wherein the input end of the attenuator F is connected to the other output end of the power divider D; the attenuator F outputs a 100 MHz clock signal externally; A power divider E, wherein an input end of the power divider E is connected to another output end of the power divider C; an attenuator E, wherein an input end of the attenuator E is connected to an output end of the power divider E; A power divider F, wherein the input end of the attenuator F is connected to the other output end of the power divider E; An attenuator H, wherein an input end of the attenuator H is connected to an output end of the power divider F; the attenuator H outputs a 100 MHz clock signal externally; A power divider G, wherein an input end of the power divider G is connected to another output end of the power divider F.

4. The frequency synthesis module of the frequency conversion module according to claim 3, characterized in that: The universal local oscillator module, when used as a universal slow-frequency integrated local oscillator module, comprises: A frequency multiplier A, wherein an input end of the frequency multiplier A is connected to an output end of the attenuator D; A comb spectrum generator A, wherein the input end of the comb spectrum generator A is connected to the output end of the frequency multiplier A; A power divider I, wherein an input end of the power divider I is connected to an output end of the comb spectrum generator A; A filter B, wherein an input end of the filter B is connected to an output end of the power divider I; an amplifier D, wherein an input end of the amplifier D is connected to an output end of the filter B; A filter C, wherein an input end of the filter C is connected to an output end of the amplifier D; an amplifier E, wherein an input end of the amplifier E is connected to an output end of the filter C; A power divider J, wherein the input end of the power divider J is connected to the output end of the amplifier E; the power divider J outputs two local oscillator signals externally; an amplifier F, wherein an input end of the amplifier F is connected to another output end of the power divider I; A switching filter A, wherein an input end of the switching filter A is connected to an output end of the amplifier F; An amplifier G, wherein an input end of the amplifier G is connected to an output end of the switching filter A; A frequency multiplier B, wherein an input end of the frequency multiplier B is connected to an output end of the amplifier G; A filter D, wherein an input end of the filter D is connected to an output end of the frequency multiplier B; an amplifier H, wherein an input end of the amplifier H is connected to an output end of the filter D; A frequency divider B, wherein an input end of the frequency divider B is connected to an output end of the attenuator E; A frequency source A, wherein an input end of the frequency source A is connected to an output end of the frequency divider B; A mixer A, one input end of the mixer A is connected to the output end of the frequency source A, and the other input end of the mixer A is connected to the output end of the amplifier H; A switching filter B, wherein an input end of the switching filter B is connected to an output end of the mixer A; An amplifier I, wherein an input end of the amplifier I is connected to an output end of the switching filter B; A filter E, wherein an input end of the filter E is connected to an output end of the amplifier I; An amplifier J, wherein an input end of the amplifier J is connected to an output end of the filter E; A power divider K, wherein the input end of the power divider K is connected to the output end of the amplifier J; the power divider K outputs two local oscillator signals to the outside.

5. The frequency synthesis module of the frequency conversion module according to claim 3, characterized in that: The universal local oscillator module can be used as a universal fast-frequency integrated local oscillator module, and when used as a universal fast-frequency integrated local oscillator module, it includes: Frequency multiplier A1; A comb spectrum generator A1, wherein the input end of the comb spectrum generator A1 is connected to the output end of the frequency multiplier A1; A power divider I1, wherein an input end of the power divider I1 is connected to an output end of the comb spectrum generator A1; A filter B1, wherein an input end of the filter B1 is connected to an output end of the power divider I1; An amplifier D1, wherein an input end of the amplifier D1 is connected to an output end of the filter B1; A filter C1, wherein an input end of the filter C1 is connected to an output end of the amplifier D1; An amplifier E1, wherein an input end of the amplifier E1 is connected to an output end of the filter C1; A power divider J1, wherein the input end of the power divider J1 is connected to the output end of the amplifier E1; the power divider J1 outputs two local oscillator signals externally; An amplifier F1, wherein an input end of the amplifier F1 is connected to another output end of the power divider I1; A switching filter A1, wherein an input end of the switching filter A1 is connected to an output end of the amplifier F1; An amplifier G1, wherein an input end of the amplifier G1 is connected to an output end of the switching filter A1; A frequency multiplier B1, wherein an input end of the frequency multiplier B1 is connected to an output end of the amplifier G1; A filter D1, wherein an input end of the filter D1 is connected to an output end of the frequency multiplier B1; An amplifier H1, wherein an input end of the amplifier H1 is connected to an output end of the filter D1; A frequency divider B1, wherein an input end of the frequency divider B1 is connected to an output end of the attenuator E; A comb spectrum generator A2, wherein the input end of the comb spectrum generator A2 is connected to the output end of the frequency divider B1; A frequency source A1; an input end of the frequency source A1 is connected to an output end of the power divider G; DDS, the input end of the DDS is connected to the output end of the frequency source A1; A mixer A2, one input end of the mixer A2 is connected to the output end of the comb spectrum generator A2; another input end of the mixer A2 is connected to the output end of the DDS; A switching filter B2, wherein an input end of the switching filter B2 is connected to an output end of the mixer A2; A mixer A1, one input end of the mixer A1 is connected to the output end of the amplifier H1; another input end of the mixer A1 is connected to the output end of the switch filter B2; A switching filter B1, wherein an input end of the switching filter B1 is connected to an output end of the mixer A1; An amplifier I1, wherein an input end of the amplifier I1 is connected to an output end of the switching filter B1; A filter E1, wherein an input end of the filter E1 is connected to an output end of the amplifier I1; An amplifier J1, wherein an input end of the amplifier J1 is connected to an output end of the filter E1; A power divider K1, wherein the input end of the power divider K1 is connected to the output end of the amplifier J1; the power divider K1 outputs two local oscillator signals.

6. The frequency synthesis module of the frequency conversion module according to claim 2, characterized in that: The FPGA is connected to the detector A, and the FPGA is connected to the detector A to receive the data collected by the ADC chip, so as to realize the specific method of automatic gain control of the reference signal: the REF signal outside the frequency synthesis module enters the power divider A, and the power divider A outputs 2 signals, one of which is detected by the detector A, and then the detected analog voltage is sampled by the ADC chip, and the sampled data is transmitted to the FPGA for data collection, so as to realize the automatic gain control of the reference signal, and at the same time, the presence or absence of the external reference signal can be judged according to the data collected by the FPGA, and the automatic switching of the internal and external references can be realized according to the result of the judgment of the presence or absence of the external reference signal; the FPGA can also be reported to the host computer in real time according to the current internal and external reference status; the other 1 signal path output by the power divider A enters the clock distribution module after amplification, attenuation and amplification processing.

7. The frequency synthesis module of the frequency conversion module according to claim 5, characterized in that: When the universal local oscillator module is used as a universal fast frequency integrated local oscillator module, the frequency source A1 is a 3.5 GHz point frequency source, and the 3.5 GHz point frequency source includes: Point frequency source phase detector; the input end of the point frequency source phase detector is connected to the output end of the power divider G; the input end of the point frequency source phase detector is the input end of the frequency source A1; A point frequency source VCO; the input end of the point frequency source VCO is connected to the output end of the point frequency source phase detector; A point frequency source power divider; the input end of the point frequency source power divider is connected to the output end of the point frequency source VCO; A point frequency source amplifier A; the input end of the point frequency source amplifier A is connected to an output end of the point frequency source power divider; the output end of the point frequency source amplifier A is connected to the input end of the DDS; Point frequency source amplifier B; the input end of the point frequency source amplifier B is connected to the other output end of the point frequency source power divider; the output end of the point frequency source amplifier B is connected to the input end of the point frequency source phase detector.

8. The frequency synthesis module of the frequency conversion module according to claim 7, characterized in that: When the universal local oscillator module is used as a universal fast-frequency integrated local oscillator module, the DDS is connected to the FPGA; the 3.5 GHz point frequency source provides a 3.5 GHz reference signal for the DDS, and the FPGA controls the DDS to cause the DDS to generate a frequency jump.

9. A signal processing method of a frequency synthesizer module of a frequency conversion module, which is implemented based on a frequency synthesizer module of a frequency conversion module according to any one of claims 1 to 8, characterized in that: Includes steps: Step S1: The power control module provides voltage to the adaptive reference AGC module, the clock distribution module and the universal local oscillator module; Step S2: the reference signal REF outside the frequency synthesis module enters the adaptive reference AGC module, and the adaptive reference AGC module is used to implement automatic gain control of the reference signal and generate an automatic gain signal REF-0; Step S3: the automatic gain signal REF-0 enters a clock distribution module, the input end of the clock distribution module is connected to the output end of the adaptive reference AGC module, and is used to generate a clock signal; Step S4: the clock signal generated by the adaptive reference AGC module enters the universal local oscillator module, and the universal local oscillator module generates input signals LO1 and LO2 of the frequency conversion module.

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