Memory structure and manufacturing method
By designing a gate with a protruding portion in the memory structure, combined with multiple dielectric layers and isolation structures, the problem of insufficient electrical performance of the existing memory structure is solved, and the current turn-on and erasure capabilities are improved.
Patent Information
- Application Number
- CN202311023952.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-18
- Filing Date
- 2023-08-15
- Publication Date
- 2025-01-21
AI Technical Summary
The existing memory structure has shortcomings in electrical performance, especially in terms of turn-on current and erasing capabilities.
A memory structure is designed, in which the gate extends along a first direction and has a protruding portion protruding along the second direction, and the protruding portion is located between two adjacent charge storage layers arranged along the first direction. The structure may also include multiple dielectric layers and isolation structures to further optimize electrical performance.
Through the design of the gate, the opening current and eradication capacity of the memory structure are enhanced, thereby improving electrical expression.
Smart Images
Figure CN119342830A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a manufacturing method, and in particular to a memory structure and a manufacturing method. Background Art
[0002] Since non-volatile memory has the advantage that the stored data will not disappear after power failure, many electrical products must have such memory to maintain normal operation when the electrical products are turned on. However, how to improve the electrical performance of memory devices is an ongoing goal. Summary of the invention
[0003] The invention provides a memory structure and a manufacturing method, which can improve the electrical performance of the memory structure.
[0004] The present invention provides a memory structure, comprising a substrate, a plurality of charge storage layers and a gate. The plurality of charge storage layers are located on the substrate. The gate is located on the substrate on one side of the plurality of charge storage layers. The gate extends along a first direction. The gate has a protrusion protruding along a second direction. The second direction intersects the first direction. The protrusion is located between two adjacent charge storage layers arranged along the first direction.
[0005] According to an embodiment of the present invention, the memory structure may further include a plurality of dielectric layers, which are located between the plurality of charge storage layers and the substrate.
[0006] According to an embodiment of the present invention, the memory structure may further include a dielectric layer, which is located between the gate and the substrate.
[0007] According to an embodiment of the present invention, in the memory structure, the plurality of charge storage layers may be a plurality of floating gates.
[0008] According to an embodiment of the present invention, the above memory structure may further include an isolation structure, which is located in the substrate.
[0009] According to an embodiment of the present invention, in the above memory structure, a trench may be provided between two adjacent charge storage layers arranged along the second direction in the isolation structure, and the trench may extend along the first direction.
[0010] According to an embodiment of the present invention, in the above memory structure, the isolation structure may have a recess between two adjacent charge storage layers arranged along the first direction, the recess may be connected to the trench, and the protrusion may be located in the recess.
[0011] According to an embodiment of the present invention, the memory structure may further include a hard mask layer. The hard mask layer is located on the multiple charge storage layers and the isolation structure. The hard mask layer may extend along the first direction.
[0012] According to an embodiment of the present invention, in the above memory structure, the protrusion may be located between the hard mask layer and the isolation structure.
[0013] According to an embodiment of the present invention, the memory structure may further include a dielectric layer, which is located between the gate and the plurality of charge storage layers and between the gate and the isolation structure.
[0014] According to an embodiment of the present invention, in the memory structure, the width of the protrusion may be greater than 0 and less than or equal to 25 nanometers.
[0015] According to an embodiment of the present invention, the memory structure may further include a plurality of spacers, which are located on a plurality of sidewalls of the plurality of charge storage layers away from the gate.
[0016] According to an embodiment of the present invention, in the above memory structure, the second direction may be perpendicular to the first direction.
[0017] The present invention provides a method for manufacturing a memory structure, comprising the following steps: providing a substrate; forming a plurality of charge storage layers on the substrate; forming a gate on the substrate on one side of the plurality of charge storage layers; the gate extending along a first direction; the gate having a protrusion protruding along a second direction; the second direction intersecting the first direction; the protrusion being located between two adjacent charge storage layers arranged along the first direction.
[0018] According to an embodiment of the present invention, the manufacturing method of the memory structure may further include the following steps: forming a plurality of dielectric layers between the plurality of charge storage layers and the substrate.
[0019] According to an embodiment of the present invention, the manufacturing method of the memory structure may further include the following steps: forming a dielectric layer between the gate and the substrate.
[0020] According to an embodiment of the present invention, the manufacturing method of the memory structure may further include the following steps: forming an isolation structure in a substrate.
[0021] According to an embodiment of the present invention, in the manufacturing method of the memory structure, a trench may be provided in the isolation structure between two adjacent charge storage layers arranged along the second direction, the trench may extend along the first direction, and the trench may expose the sidewall of the isolation structure.
[0022] According to an embodiment of the present invention, in the manufacturing method of the memory structure, the gate forming method may include the following steps: removing a portion of the isolation structure exposed by the trench, and forming a recess in the isolation structure. The portion of the isolation structure exposed by the trench may be removed by a wet etching process. A gate is formed in the trench and the recess.
[0023] According to an embodiment of the present invention, in the method for manufacturing the memory structure, the duration of the wet etching process may be 20 seconds to 130 seconds.
[0024] Based on the above, in the memory structure and the manufacturing method thereof proposed by the present invention, the gate has a protrusion protruding along the second direction, and the protrusion is located between two adjacent charge storage layers arranged along the first direction. Thus, the on-current of the memory structure and the erasing capability during the erase operation of the memory structure can be improved, thereby improving the electrical performance of the memory structure.
[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 A top view of a memory structure according to some embodiments of the present invention;
[0027] Figures 2A to 2P For along Figure 1 A cross-sectional view of the manufacturing process of the memory structure along the I-I' section line;
[0028] Figures 3A to 3P For along Figure 1 A cross-sectional view of the manufacturing process of the memory structure along the II-II' section line.
[0029] Description of Figure Numbers:
[0030] 10: Memory structure
[0031] 100: substrate
[0032] 102: Isolation Structure
[0033] 104,126: Dielectric material layer
[0034] 104a, 118, 120, 124, 126a, 130: dielectric layer
[0035] 106: Charge storage layer
[0036] 108,110,112,138,140,142: Hard mask layer
[0037] 114: Spacer material layer
[0038] 114a: Spacer
[0039] 116,122,128: Patterned photoresist layer
[0040] 132,134a: Gate
[0041] 134: Conductive layer
[0042] 136: Hard mask structure
[0043] 136a: Patterned hard mask structure
[0044] 138a, 140a, 142a: Patterned hard mask layer
[0045] D1: First direction
[0046] D2: Second direction
[0047] D3: Third direction
[0048] P1: protrusion
[0049] R1: Depression
[0050] T1: Groove
[0051] W1: Width DETAILED DESCRIPTION
[0052] The following examples are listed and described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to size. In fact, the size of various features can be arbitrarily increased or decreased for clarity of discussion.
[0053] Figure 1 FIG. 1 is a top view of a memory structure according to some embodiments of the present invention. Figures 2A to 2P For along Figure 1 A cross-sectional view of the manufacturing process of the memory structure along the II' section line. Figures 3A to 3P For along Figure 1 A cross-sectional view of the manufacturing process of the memory structure along the II-II' section line. Figure 1 In the top view, omit Figure 2P and Figure 3P In order to clearly illustrate the positional relationship between the components in the top view. Figure 1In the top view of FIG. 1 , the hard mask layer 112 is represented by a dotted line to clearly illustrate the positional relationship between the various components in the top view.
[0054] Please refer to Figure 2A and Figure 3A , providing a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, an isolation structure 102 may be formed in the substrate 100. The isolation structure 102 may be a shallow trench isolation (STI) structure. The material of the isolation structure 102 is, for example, silicon oxide. In some embodiments, a dielectric material layer 104 may be formed on the substrate 100. The material of the dielectric material layer 104 is, for example, silicon oxide.
[0055] A plurality of charge storage layers 106 are formed on the substrate 100. In some embodiments, the plurality of charge storage layers 106 may be formed on the dielectric material layer 104. In some embodiments, as Figure 1 As shown, a plurality of charge storage layers 106 may be arranged along a first direction D1 and a second direction D2. The material of the charge storage layer 106 is, for example, doped polysilicon. In addition, a trench T1 may be provided between two adjacent charge storage layers 106 arranged along the second direction D2 in the isolation structure 102. The trench T1 may extend along the first direction D1. The trench T1 may expose the sidewall of the isolation structure 102.
[0056] In some embodiments, a hard mask layer 108 may be formed on the charge storage layer 106. The material of the hard mask layer 108 is, for example, silicon oxide. In some embodiments, a hard mask layer 110 may be formed on the hard mask layer 108. The material of the hard mask layer 110 is, for example, silicon nitride. In some embodiments, a hard mask layer 112 may be formed on the plurality of charge storage layers 106 and the isolation structure 102. In some embodiments, the hard mask layer 112 may be formed on the hard mask layer 110. In some embodiments, as Figure 1 As shown, the hard mask layer 112 may extend along the first direction D1. The material of the hard mask layer 112 is, for example, silicon nitride.
[0057] Please refer to Figure 2B and Figure 3B , a spacer material layer 114 may be formed on the dielectric material layer 104, the charge storage layer 106, the hard mask layer 108, the hard mask layer 110, the hard mask layer 112 and the isolation structure 102. The material of the spacer material layer 114 is, for example, silicon oxide. The spacer material layer 114 may be formed by, for example, chemical vapor deposition.
[0058] Please refer to Figure 2C and Figure 3C, a portion of the spacer material layer 114 may be removed to expose a portion of the dielectric material layer 104 and a portion of the isolation structure 102. The method of removing a portion of the spacer material layer 114 is, for example, a dry etching method.
[0059] Please refer to Figure 2D and Figure 3D A patterned photoresist layer 116 may be formed on the dielectric material layer 104, the spacer material layer 114 and the isolation structure 102. The patterned photoresist layer 116 may expose a portion of the dielectric material layer 104 and a portion of the spacer material layer 114. The patterned photoresist layer 116 may be formed by a photolithography process.
[0060] Please refer to Figure 2E and Figure 3E The patterned photoresist layer 116 can be used as a mask to remove a portion of the dielectric material layer 104 and a portion of the spacer material layer 114 to expose a portion of the substrate 100 and a portion of the isolation structure 102. The method of removing a portion of the dielectric material layer 104 and a portion of the spacer material layer 114 is, for example, a wet etching method.
[0061] Next, the patterned photoresist layer 116 may be removed. The patterned photoresist layer 116 may be removed by, for example, dry stripping or wet stripping.
[0062] Please refer to Figure 2F and Figure 3F , a dielectric layer 118 may be formed on the substrate 100. The material of the dielectric layer 118 is, for example, silicon oxide. The dielectric layer 118 may be formed by, for example, thermal oxidation.
[0063] Then, a dielectric layer 120 may be formed on the dielectric material layer 104, the charge storage layer 106, the hard mask layer 108, the hard mask layer 110, the hard mask layer 112, the spacer material layer 114, the dielectric layer 118, and the isolation structure 102. The material of the dielectric layer 120 is, for example, silicon oxide. The method of forming the dielectric layer 120 is, for example, chemical vapor deposition.
[0064] Please refer to Figure 2G and Figure 3G , a patterned photoresist layer 122 may be formed on the dielectric layer 120. The patterned photoresist layer 122 may expose a portion of the dielectric layer 120. The patterned photoresist layer 122 may be formed by a photolithography process.
[0065] Please refer to Figure 2H and Figure 3H, the patterned photoresist layer 122 can be used as a mask to remove a portion of the dielectric layer 120, the dielectric layer 118, a portion of the spacer material layer 114, and a portion of the isolation structure 102. As a result, a portion of the substrate 100 can be exposed, and a portion of the isolation structure 102 exposed by the trench T1 can be removed, and a recess R1 can be formed in the isolation structure 102. The recess R1 can be connected to the trench T1. In some embodiments, a portion of the dielectric layer 120, the dielectric layer 118, a portion of the spacer material layer 114, and a portion of the isolation structure 102 exposed by the trench T1 can be removed by a wet etching process. In some embodiments, the duration of the wet etching process can be 20 seconds to 130 seconds. In some embodiments, the duration of the wet etching process can be 65 seconds to 110 seconds.
[0066] Next, the patterned photoresist layer 122 may be removed. The patterned photoresist layer 122 may be removed by, for example, a dry stripping method or a wet stripping method.
[0067] Please refer to Fig.2I and Fig. 3I , a dielectric layer 124 may be formed on the substrate 100. The material of the dielectric layer 124 is, for example, silicon oxide. The dielectric layer 124 may be formed by, for example, thermal oxidation.
[0068] Then, a dielectric material layer 126 may be formed on the dielectric material layer 104, the charge storage layer 106, the hard mask layer 108, the hard mask layer 110, the hard mask layer 112, the spacer material layer 114, the dielectric layer 120, the dielectric layer 124 and the isolation structure 102. The material of the dielectric material layer 126 is, for example, silicon oxide. The method of forming the dielectric material layer 126 is, for example, chemical vapor deposition.
[0069] Please refer to Figure 2J and Figure 3J , a patterned photoresist layer 128 may be formed on the dielectric material layer 126. The patterned photoresist layer 128 may expose a portion of the dielectric material layer 126. The patterned photoresist layer 128 may be formed by a photolithography process.
[0070] Please refer to Figure 2K and Figure 3K, the patterned photoresist layer 128 can be used as a mask to remove a portion of the dielectric material layer 126, the dielectric layer 120, a portion of the spacer material layer 114, and a portion of the dielectric material layer 104, thereby forming a dielectric layer 126a, a spacer 114a, and a dielectric layer 104a, and exposing a portion of the substrate 100 and a portion of the isolation structure 102. Thus, a plurality of dielectric layers 104a can be formed between the plurality of charge storage layers 106 and the substrate 100, and the spacer 114a can be formed on the sidewalls of the charge storage layer 106, the sidewalls of the hard mask layer 108, the sidewalls of the hard mask layer 110, the sidewalls of the hard mask layer 112, and the sidewalls of the isolation structure 102. The method for removing a portion of the dielectric material layer 126, the dielectric layer 120, a portion of the spacer material layer 114, and a portion of the dielectric material layer 104 is, for example, a wet etching method.
[0071] Next, the patterned photoresist layer 128 may be removed. The patterned photoresist layer 128 may be removed by, for example, a dry stripping method or a wet stripping method.
[0072] Please refer to Figure 2L and Figure 3L , a dielectric layer 130 may be formed on the substrate 100. The material of the dielectric layer 130 is, for example, silicon oxide. The dielectric layer 130 may be formed by, for example, thermal oxidation.
[0073] Please refer to Figure 2M and Figure 3M , a gate 132 may be formed in the trench T1 and the recess R1, and a conductive layer 134 may be formed on the dielectric layer 130 and the isolation structure 102. The gate 132 and the conductive layer 134 may be separated from each other. The gate 132 may have a protrusion P1. The protrusion P1 may be located in the recess R1. In some embodiments, the gate 132 may be formed on the dielectric layer 126a. In some embodiments, the method for forming the gate 132 and the conductive layer 134 may include the following steps. First, a conductive material layer (not shown) may be formed on the dielectric layer 126a, the hard mask layer 112, the spacer 114a, the dielectric layer 130, and the isolation structure 102, and the conductive material layer may be filled in the trench T1 and the recess R1. Next, a chemical mechanical polishing process may be performed on the conductive material layer to form the gate 132 and the conductive layer 134. The material of the gate 132 and the conductive layer 134 is, for example, doped polysilicon.
[0074] Through the above method, a gate 132 may be formed on the substrate 100 on one side of the plurality of charge storage layers 106, a dielectric layer 124 may be formed between the gate 132 and the substrate 100, and a dielectric layer 126a may be formed between the gate 132 and the dielectric layer 124. In addition, the dielectric layer 126a may be formed between the gate 132 and the charge storage layer 106, between the gate 132 and the hard mask layer 108, between the gate 132 and the hard mask layer 110, between the gate 132 and the hard mask layer 112, and between the gate 132 and the isolation structure 102.
[0075] Please refer to Figure 2N and Figure 3N The gate 132, the conductive layer 134, the dielectric layer 126a, the hard mask layer 112 and the spacer 114a may be subjected to an etch-back process. The etch-back process may be, for example, a dry etching process.
[0076] Please refer to Fig.2O and Fig.3O , a hard mask structure 136 may be formed on the gate 132, the conductive layer 134, the dielectric layer 126a, the hard mask layer 112 and the spacer 114a. The hard mask structure 136 may be a single-layer structure or a multi-layer structure. In the present embodiment, the hard mask structure 136 is an example of a multi-layer structure. For example, the hard mask structure 136 may include a hard mask layer 138, a hard mask layer 140 and a hard mask layer 142. The hard mask layer 138 is located on the gate 132, the conductive layer 134, the dielectric layer 126a, the hard mask layer 112 and the spacer 114a. The material of the hard mask layer 138 is, for example, silicon oxide. The method for forming the hard mask layer 138 is, for example, chemical vapor deposition. The hard mask layer 140 is located on the hard mask layer 138. The material of the hard mask layer 140 is, for example, silicon nitride. The method for forming the hard mask layer 140 is, for example, chemical vapor deposition. The hard mask layer 142 is located on the hard mask layer 140. The material of the hard mask layer 142 is, for example, silicon oxide. The hard mask layer 142 is formed by, for example, chemical vapor deposition.
[0077] Please refer to Figure 2P and Figure 3P , the hard mask structure 136 and the conductive layer 134 may be patterned to form a patterned hard mask structure 136a and a gate 134a. Thus, a gate 134a may be formed on the dielectric layer 130 and the isolation structure 102. The patterned hard mask structure 136a may include a patterned hard mask layer 138a, a patterned hard mask layer 140a, and a patterned hard mask layer 142a. The patterned hard mask layer 138a is located on the gate 132, the gate 134a, the dielectric layer 126a, the hard mask layer 112, and the spacer 114a. The patterned hard mask layer 140a is located on the patterned hard mask layer 138a. The patterned hard mask layer 142a is located on the patterned hard mask layer 140a.
[0078] Below, through Figure 1 , Figure 2P and Figure 3P In addition, although the method for forming the memory structure 10 is described by taking the above method as an example, the present invention is not limited thereto.
[0079] Please refer to Figure 1 , Figure 2P and Figure 3P , the memory structure 10 includes a substrate 100, a plurality of charge storage layers 106 and a gate 132. In some embodiments, the memory structure 10 may be a non-volatile memory structure, such as a flash memory structure. The plurality of charge storage layers 106 are located on the substrate 100. In some embodiments, the plurality of charge storage layers 106 may be a plurality of floating gates. The gate 132 is located on the substrate 100 on one side of the plurality of charge storage layers 106. In some embodiments, the gate 132 may be used as an erase gate. The gate 132 extends along a first direction D1. The gate 132 has a protrusion P1 protruding along a second direction D2. In some embodiments, the gate 132 further has a protrusion P1 protruding along a third direction D3 opposite to the second direction D2. The second direction D2 intersects the first direction D1. In some embodiments, the second direction D2 may be perpendicular to the first direction D1. The protrusion P1 is located between two adjacent charge storage layers 106 arranged along the first direction D1. In some embodiments, the width W1 of the protrusion P1 may be greater than 0 and less than or equal to 25 nanometers. In some embodiments, the width W1 of the protrusion P1 may be 4 nanometers to 19 nanometers.
[0080] The memory structure 10 may further include an isolation structure 102. The isolation structure 102 is located in the substrate 100. A trench T1 may be provided between two adjacent charge storage layers 106 arranged along the second direction D2 in the isolation structure 102. The trench T1 may extend along the first direction D1. The isolation structure 102 may have a recess R1 between two adjacent charge storage layers 106 arranged along the first direction D1. The recess R1 may be connected to the trench T1. The protrusion P1 may be located in the recess R1.
[0081] The memory structure 10 may further include a plurality of dielectric layers 104a. The plurality of dielectric layers 104a are located between the plurality of charge storage layers 106 and the substrate 100. The memory structure 10 may further include a dielectric layer 124. The dielectric layer 124 is located between the gate 132 and the substrate 100. The memory structure 10 may further include a dielectric layer 126a. The dielectric layer 126a is located between the gate 132 and the dielectric layer 124. The dielectric layer 126a may also be located between the gate 132 and the plurality of charge storage layers 106 and between the gate 132 and the isolation structure 102.
[0082] The memory structure 10 may further include a hard mask layer 112. The hard mask layer 112 is located on the plurality of charge storage layers 106 and the isolation structure 102. The hard mask layer 112 may extend along the first direction D1. The protrusion P1 may be located between the hard mask layer 112 and the isolation structure 102. The memory structure 10 may further include a hard mask layer 110. The hard mask layer 110 is located between the hard mask layer 112 and the charge storage layer 106. The memory structure 10 may further include a hard mask layer 108. The hard mask layer 108 is located between the hard mask layer 110 and the charge storage layer 106. In addition, a dielectric layer 126a may further be located between the gate 132 and the hard mask layer 108, between the gate 132 and the hard mask layer 110, and between the gate 132 and the hard mask layer 112. The memory structure 10 may further include a plurality of spacers 114a. The plurality of spacers 114 a are located on the sidewalls of the plurality of charge storage layers 106 away from the gate 132 .
[0083] The memory structure 10 may further include a gate 134a and a dielectric layer 130. The gate 134a is located on a side of the charge storage layer 106 away from the gate 132. The gate 134a is located on the dielectric layer 130 and the isolation structure 102. In some embodiments, the gate 134a may be used as a select gate. The spacer 114a may be located between the gate 134a and the charge storage layer 106 and between the gate 134a and the isolation structure 102.
[0084] The memory structure 10 may further include a patterned hard mask structure 136a. The patterned hard mask structure 136a may be a single-layer structure or a multi-layer structure. In the present embodiment, the patterned hard mask structure 136a is an example of a multi-layer structure. For example, the patterned hard mask structure 136a may include a patterned hard mask layer 138a, a patterned hard mask layer 140a, and a patterned hard mask layer 142a. The patterned hard mask layer 138a is located on the gate 132, the gate 134a, the dielectric layer 126a, the hard mask layer 112, and the spacer 114a. The patterned hard mask layer 140a is located on the patterned hard mask layer 138a. The patterned hard mask layer 142a is located on the patterned hard mask layer 140a.
[0085] In some embodiments, a control gate (not shown) may be provided on the charge storage layer 106, and the control gate and the charge storage layer 106 are insulated from each other, and their description is omitted. In some embodiments, a desired doping region (not shown) may be provided in the substrate 100, and its description is omitted.
[0086] In addition, the details of each component in the memory structure 10 (eg, materials and formation methods, etc.) have been described in detail in the above embodiments and will not be described again here.
[0087] Based on the above embodiments, it can be known that in the memory structure 10 and the manufacturing method thereof, the gate 132 has a protruding portion P1 protruding along the second direction D2, and the protruding portion P1 is located between two adjacent charge storage layers 106 arranged along the first direction D1. Therefore, the turn-on current of the memory structure 10 and the erasing capability when the memory structure 10 is erased can be increased, thereby improving the electrical performance of the memory structure 10.
[0088] In summary, in the memory structure and the manufacturing method thereof in the above embodiments, since the gate has a protruding portion, the turn-on current of the memory structure and the erasing capability during the erasing operation of the memory structure can be increased, thereby improving the electrical performance of the memory structure.
[0089] Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.
Claims
1. A memory structure, characterized in that: include: substrate; A plurality of charge storage layers are located on the substrate; as well as A gate is located on the substrate on one side of the plurality of charge storage layers and extends along a first direction, wherein the gate has a protrusion protruding along a second direction, the second direction intersects with the first direction, and the protrusion is located between two adjacent charge storage layers arranged along the first direction.
2. The memory structure according to claim 1, characterized in that: Also includes: A plurality of dielectric layers are located between the plurality of charge storage layers and the substrate.
3. The memory structure according to claim 1, characterized in that: Also includes: A dielectric layer is located between the gate and the substrate.
4. The memory structure according to claim 1, characterized in that: The plurality of charge storage layers include a plurality of floating gates.
5. The memory structure according to claim 1, characterized in that: Also includes: The isolation structure is located in the substrate.
6. The memory structure according to claim 5, characterized in that: A trench is provided between two adjacent charge storage layers arranged along the second direction in the isolation structure, and the trench extends along the first direction.
7. The memory structure according to claim 6, characterized in that: The isolation structure has a recess between two adjacent charge storage layers arranged along the first direction, The recess is connected to the groove, and The protrusion is located in the recess.
8. The memory structure according to claim 5, characterized in that: Also includes: The hard mask layer is located on the plurality of charge storage layers and the isolation structure, and the hard mask layer extends along the first direction.
9. The memory structure according to claim 8, characterized in that: The protrusion is located between the hard mask layer and the isolation structure.
10. The memory structure according to claim 5, characterized in that: Also includes: A dielectric layer is located between the gate and the plurality of charge storage layers and between the gate and the isolation structure.
11. The memory structure according to claim 1, characterized in that: The width of the protrusion is greater than 0 and less than or equal to 25 nanometers.
12. The memory structure according to claim 1, characterized in that: Also includes: A plurality of spacers are located on a plurality of side walls of the charge storage layers away from the gate.
13. The memory structure according to claim 1, characterized in that: The second direction is perpendicular to the first direction.
14. A method for manufacturing a memory structure, characterized in that: include: providing a substrate; forming a plurality of charge storage layers on the substrate; as well as A gate is formed on the substrate on one side of the plurality of charge storage layers, wherein the gate extends along a first direction, the gate has a protrusion protruding along a second direction, the second direction intersects with the first direction, and the protrusion is located between two adjacent charge storage layers arranged along the first direction.
15. The method for manufacturing a memory structure according to claim 14, characterized in that: Also includes: A plurality of dielectric layers are formed between the plurality of charge storage layers and the substrate.
16. The method for manufacturing a memory structure according to claim 14, characterized in that: Also includes: A dielectric layer is formed between the gate and the substrate.
17. The method for manufacturing a memory structure according to claim 14, characterized in that: Also includes: An isolation structure is formed in the substrate.
18. The method for manufacturing a memory structure according to claim 17, characterized in that: A trench is provided between two adjacent charge storage layers arranged along the second direction in the isolation structure, The groove extends along the first direction, and The trench exposes a sidewall of the isolation structure.
19. The method for manufacturing a memory structure according to claim 18, characterized in that: The gate forming method includes: removing a portion of the isolation structure exposed by the trench to form a recess in the isolation structure, wherein the portion of the isolation structure exposed by the trench is removed by a wet etching process; and A gate is formed in the trench and the recess.
20. The method for manufacturing a memory structure according to claim 19, characterized in that: The duration of the wet etching process is 20 seconds to 130 seconds.