Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the following steps: providing a substrate which comprises a base layer and a spacer layer located on the base layer, and is divided into a first region for forming a BCD device and a second region for forming an SGT device, a BCD structure is arranged in the substrate layer of the first area, and a first SGT structure and a second SGT structure which are spaced from each other are arranged in the substrate layer of the second area; forming a patterned photoresist layer on the first SGT structure in the second region and the spacer layer above the BCD structure in the first region, and etching the spacer layer to expose a part of the substrate layer and the second SGT structure; and forming a control gate on the spacer layer above a part of the BCD structure and extending to a part of the exposed substrate layer, wherein the control gate is also formed on the exposed second SGT structure. On the basis of not increasing a photomask and a process, the breakdown voltage can be increased, and the electrical performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] VIP is a process form that combines a vertical device (SGT) with a lateral device (BCD). In recent years, domestic FABs have begun to try to develop this process. BCD (Bipolar CMOSDMOS) refers to the process technology that integrates power devices such as Bipolar, CMOS, DMOS, logic devices, and various resistors, capacitors, and diodes on the same chip. It has the characteristics of low cost, easy packaging, easy design, and simpler peripheral chips. It has rapidly developed into the mainstream technology in the field of power integrated ICs. The Bipolar bipolar transistor in BCD technology has high analog accuracy and is mainly used in analog circuits; CMOS has high integration and is mainly used in logic circuits; DMOS has high power (high voltage) characteristics and is often used as a switch. SGT (Shielded Gate Transistor, shielded gate trench) device is a new type of power semiconductor device. SGT mainly uses a vertical structure to greatly reduce the chip area, and through the vertical field oxide layer setting, the charge balance mechanism can ensure that the concentration of the drift region is increased under a certain withstand voltage, thereby reducing the device on-resistance.

[0003] With the continuous advancement of semiconductor technology, the electrical performance of semiconductor devices obtained by the existing VIP process, especially the breakdown voltage, is increasingly unable to meet market demand. Therefore, it is necessary to provide a new semiconductor preparation process to obtain semiconductor devices with higher electrical performance. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for preparing the same, so as to improve the electrical performance of the semiconductor device.

[0005] In order to achieve the above object and other related objects, the present invention provides a method for preparing a semiconductor device, comprising the following steps: Providing a substrate, the substrate comprising a base layer and a spacer layer located on the base layer, the substrate being divided into a first region for forming a BCD device and a second region for forming an SGT device, the base layer of the first region being provided with a BCD structure, and the base layer of the second region being provided with a first SGT structure and a second SGT structure spaced apart from each other; Forming a patterned photoresist layer on the first SGT structure in the second region and the spacer layer above the BCD structure in the first region, and etching the spacer layer using the patterned photoresist layer as a mask to expose a portion of the base layer and the second SGT structure; A control gate is formed on the spacer layer above a portion of the BCD structure and extends to a portion of the exposed base layer. The control gate is also formed on the exposed second SGT structure.

[0006] Optionally, in the method for preparing the semiconductor device, the material of the base layer includes silicon.

[0007] Optionally, in the method for preparing the semiconductor device, the first SGT structure includes a first shielding gate and a first dielectric layer covering the first shielding gate; the second SGT structure includes a second shielding gate and a second dielectric layer covering the second shielding gate, the upper surface of the second shielding gate is lower than the upper surface of the first shielding gate, and the upper surface of the second dielectric layer is flush with the upper surface of the first dielectric layer.

[0008] Optionally, in the method for preparing the semiconductor device, the material of the first dielectric layer and the second dielectric layer includes silicon oxide.

[0009] Optionally, in the method for preparing the semiconductor device, the material of the second dielectric layer is the same as the material of the spacer layer.

[0010] Optionally, in the method for preparing the semiconductor device, in the step of etching the spacer layer using the patterned photoresist layer as a mask, a portion of the second dielectric layer on the second shielding gate is also etched away.

[0011] Optionally, in the method for preparing the semiconductor device, in the step of etching the spacer layer using the patterned photoresist layer as a mask, a portion of the spacer layer between the first SGT structure and the BCD structure is etched away.

[0012] Optionally, in the method for preparing the semiconductor device, the width of the spacer layer etched away between the first SGT structure and the BCD structure is greater than or equal to 3 μm.

[0013] Optionally, in the method for preparing the semiconductor device, the BCD structure includes a shallow trench isolation structure.

[0014] In order to achieve the above-mentioned object and other related objects, the present invention also provides a semiconductor device, which is prepared by the above-mentioned method for preparing the semiconductor device.

[0015] Compared with the prior art, the technical solution of the present invention has the following unexpected beneficial effects: The present invention can change the structure of the BCD device by only covering a portion of the spacer layer in the first area with a patterned photoresist layer in the second area at the same time without adding a mask and a process, and form two steps in the process of etching the spacer layer, thereby changing the electric field peak of the BCD device from two peaks to three peaks, increasing the breakdown voltage and improving the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the product structure after executing step S01 in the method for preparing a semiconductor device; Figure 2 It is a schematic diagram of the product structure after a patterned photoresist layer is formed in a method for preparing a semiconductor device; Figure 3 is a schematic diagram of a product structure after executing step S02 in a method for preparing a semiconductor device; Figure 4 It is a schematic diagram of the product structure after executing step S03 in the method for preparing a semiconductor device; Figure 5 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention; Figure 6 is a schematic diagram of a product structure after executing step S1 in a method for preparing a semiconductor device according to an embodiment of the present invention; Figure 7 It is a schematic diagram of the product structure after a patterned photoresist layer is formed in a method for preparing a semiconductor device according to an embodiment of the present invention; Figure 8 is a schematic diagram of a product structure after executing step S2 in a method for preparing a semiconductor device according to an embodiment of the present invention; Fig. 9 is a schematic diagram of the product structure after executing step S3 in the method for preparing a semiconductor device according to an embodiment of the present invention; Fig.10 is a comparison diagram of electric field distribution between a BCD device in an existing semiconductor device and a BCD device in a semiconductor device according to an embodiment of the present invention; Figure 1~Figure 4 middle: 01-base layer, 021-first SGT structure, 0211-first shielding gate, 0212-first dielectric layer, 022-second SGT structure, 0221-second shielding gate, 0222-second dielectric layer, 023-BCD structure, 03-spacer layer, 04-patterned photoresist layer, 05-control gate; Figures 5 to 10 middle: 10-base layer, 21-first SGT structure, 211-first shielding gate, 212-first dielectric layer, 22-second SGT structure, 221-second shielding gate, 222-second dielectric layer, 23-BCD structure, 30-spacer layer, 40-patterned photoresist layer, 50-control gate. DETAILED DESCRIPTION

[0017] The semiconductor device and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0018] Figures 1 to 4 The specific process of a method for preparing a semiconductor device (VIP process) is shown, which may include the following steps: Step S01: providing a substrate, the substrate comprising a base layer 01 and a spacer layer 03 located on the base layer 01, the substrate being divided into a first region for forming a BCD device and a second region for forming an SGT device, the base layer 01 of the first region being provided with a BCD structure 023, and the base layer 01 of the second region being provided with a first SGT structure 021 and a second SGT structure 022 spaced apart from each other; Step S02: forming a patterned photoresist layer 04 on the spacer layer 03 above the first SGT structure 021 in the second region, and etching the spacer layer 03 using the patterned photoresist layer 04 as a mask to expose a portion of the base layer 01 and the second SGT structure 022; Step S03 : forming a control gate 05 on a portion of the BCD structure 023 and extending to a portion of the exposed base layer 01 . The control gate 05 is also formed on the exposed second SGT structure 022 .

[0019] In step S01 , the first SGT structure 021 includes a first shielding gate 0211 and a first dielectric layer 0212 covering the first shielding gate 0211 ; the second SGT structure 022 includes a second shielding gate 0221 and a second dielectric layer 0222 covering the second shielding gate 0221 .

[0020] In the above method, the patterned photoresist layer only covers the second region, and the BCD device in the finally formed semiconductor device has only two peak electric fields and a relatively low breakdown voltage.

[0021] In order to improve the electric field and increase the breakdown voltage, the present invention provides a method for preparing a semiconductor device, which can be referred to Figure 5~Figure 9, specifically including the following steps: Step S1: providing a substrate, the substrate comprising a base layer 10 and a spacer layer 30 located on the base layer 10, the substrate being divided into a first region for forming a BCD device and a second region for forming an SGT device, the base layer 10 of the first region being provided with a BCD structure 23, and the base layer 10 of the second region being provided with a first SGT structure 21 and a second SGT structure 22 spaced apart from each other; Step S2: forming a patterned photoresist layer 40 on the spacer layer 30 above the first SGT structure 21 in the second region and the BCD structure 23 in the first region, and etching the spacer layer 30 using the patterned photoresist layer 40 as a mask to expose a portion of the base layer 10 and the second SGT structure 22; Step S3 : forming a control gate 50 on the spacer layer 30 above a portion of the BCD structure 23 and extending to the partially exposed base layer 10 . The control gate 50 is also formed on the exposed second SGT structure 22 .

[0022] See also Figure 6 , perform step S1 to provide a substrate. In this embodiment, the substrate may include a base layer 10 and a spacer layer 30 located on the base layer 10. The substrate of this embodiment may be a structural layer obtained after a high-density plasma deposition process (HDP DEP) is performed in an existing VIP process to form a spacer layer, and the VIP process is preferably a 0.18VIP process. The material of the base layer 10 is preferably Si (silicon), but not limited thereto. The material of the spacer layer 30 is preferably an oxide, and further preferably SiO2 (silicon oxide), but not limited thereto. The substrate may include a first region and a second region, and the first region is used to form a BCD device, and the BCD device may be an LDMOS. In this embodiment, a BCD structure 23 is provided in the base layer 10 of the first region, and the BCD structure 23 may be a shallow trench isolation structure, but not limited thereto. The second region is adjacent to the first region, and the second region is used to form an SGT device. In this embodiment, a first SGT structure 21 and a second SGT structure 22 are provided in the base layer 10 of the second region, and the first SGT structure 21 and the second SGT structure 22 are arranged in the base layer 10 at intervals.

[0023] In this embodiment, the first SGT structure 21 may include a first shielding gate 211 and a first dielectric layer 212, and the second SGT structure 22 may include a second shielding gate 221 and a second dielectric layer 222. The upper surface of the second shielding gate 221 is preferably lower than the upper surface of the first shielding gate 211, and the upper surface of the second dielectric layer 222 is preferably flush with the upper surface of the first dielectric layer 212. The material of the second shielding gate 221 of this embodiment is preferably the same as that of the first shielding gate 211, and further, the materials of the second shielding gate 221 and the first shielding gate 211 are preferably polysilicon, but not limited thereto. The materials of the second dielectric layer 222, the first dielectric layer 212 and the spacer layer 30 are preferably the same. Further, the materials of the second dielectric layer 222, the first dielectric layer 212 and the spacer layer 30 are preferably silicon dioxide, but not limited thereto.

[0024] See also Figure 7 and Figure 8 , perform step S2, form a patterned photoresist layer 40 on the spacer layer 30 above the first SGT structure 21 in the second region and the BCD structure 23 in the first region, and use the patterned photoresist layer 40 as a mask to etch the spacer layer 30. In this embodiment, the method for forming the patterned photoresist layer 40 may include: forming a photoresist layer on the spacer layer 30 in the first region, and extending and covering the spacer layer 30 in the second region; and using a photomask to perform photolithography on the photoresist layer to form the patterned photoresist layer 40. The layout pattern of the photomask covers the photoresist layer above the first SGT structure 21 in the second region and the BCD structure 23 in the first region, and the patterned photoresist layer 40 can be formed by performing photolithography on the photoresist layer using the photomask as a mask. Compared with the prior art in which the pattern of the mask only covers the photoresist layer above the first SGT structure 21, the pattern of the mask in this embodiment also covers the photoresist layer above the BCD structure 23, that is, when the number of masks remains unchanged, the patterned photoresist layer 40 of this embodiment can be obtained by simply adjusting the layout pattern of the mask.

[0025] In this embodiment, the method of etching the spacer layer 30 using the patterned photoresist layer 40 as a mask can be a wet etching method or a dry etching method. The spacer layer 30 not covered by the pattern of the patterned photoresist layer 40 will be etched away, while the spacer layer 30 covered by the pattern of the patterned photoresist layer 40 will be protected and will not be etched away. In this embodiment, the spacer layer 30 not covered by the pattern of the patterned photoresist layer 40 will be completely etched to expose the base layer 10 and the second dielectric layer 222, and since the material of the second dielectric layer 222 in this embodiment is the same as that of the spacer layer 30, after the spacer layer 30 above the second shielding grid 221 is completely etched, the second dielectric layer 222 will also be etched, and the etching will stop after the second dielectric layer 222 is partially etched, and a partial thickness of the second dielectric layer 222 will still be retained above the second shielding grid 221 to protect the second shielding grid 221. The thickness of the second dielectric layer 222 retained on the second shielding grid 221 after the etching process can be set according to process requirements, which will not be described in detail here.

[0026] In this embodiment, part of the spacer layer 30 between the first SGT structure 21 and the BCD structure 23 is not covered with the pattern of the patterned photoresist layer 40, so part of the spacer layer 30 between the first SGT structure 21 and the BCD structure 23 will also be etched away. The width of the spacer layer between the first SGT structure 21 and the BCD structure 23 that is not covered with the pattern of the patterned photoresist layer 40 is preferably greater than or equal to 3μm, that is, the width of the etched spacer layer 30 between the first SGT structure 21 and the BCD structure 23 is preferably greater than or equal to 3μm, so as to avoid the influence of the front injection width of the first SGT structure 21. In this embodiment, after the etching process, the spacer layer 30 on the BCD structure 23 is retained to form two steps, that is, two oxide steps, specifically, silicon oxide steps.

[0027] In this embodiment, after the step of etching the spacer layer 30, the method for preparing the semiconductor device may further include: removing the patterned photoresist layer 40. The method for removing the patterned photoresist layer 40 is preferably an ashing process, but is not limited thereto.

[0028] See also Fig. 9, perform step S3, forming a control gate 50 on the spacer layer 30 above the BCD structure 23 and extending to the partially exposed base layer 10, and the control gate 50 is also formed on the exposed second SGT structure 22. The material of the control gate 50 is preferably polysilicon, but not limited thereto. The control gate 50 covers the spacer layer 30 above the BCD structure 23 and extends to the partially exposed base layer 10 in a direction away from the first SGT structure 21. For details, see Fig. 9 The length of the control gate 50 covering the spacer layer 30 above the BCD structure 23 and the length extending to the base layer 10 can be set according to the prior art, which will not be described in detail here. After the control gate 50 is formed, a BCD device is formed in the first region and an SGT device is formed in the second region. In this embodiment, the presence of the two steps above the BCD structure 23 improves the electric field and generates the third peak electric field of the BCD device. See Fig.10 The BCD device in the prior art has two peak electric fields, while the BCD device of this embodiment has three peak electric fields, and BV (breakdown voltage) = ∫Edx, where E is the electric field and x is the distance. Therefore, the preparation method of the semiconductor device of this embodiment can increase the breakdown voltage.

[0029] In addition, the present invention also provides a semiconductor device, which is prepared by the above-mentioned method for preparing a semiconductor device, that is, prepared by steps S1 to S3. The semiconductor device of the present invention can change the structure of the BCD device by only changing the layout pattern of the mask without increasing the number of masks and processes, forming two steps, thereby changing the electric field peak of the BCD device from two peaks to three peaks, thereby increasing the breakdown voltage and improving the electrical performance of the device.

[0030] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0031] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, usages and applications described herein, which may vary. It should also be understood that the terms described herein are only used to describe specific embodiments, rather than to limit the scope of the present invention. It must be noted that the singular forms "one", "a kind" and "the" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates the opposite meaning. The structure described herein will be understood to also quote the functional equivalent of the structure. Language that can be interpreted as approximate should be understood as such, unless the context clearly indicates the opposite meaning.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a base layer and a spacer layer located on the base layer, the substrate being divided into a first region for forming a BCD device and a second region for forming an SGT device, the base layer of the first region being provided with a BCD structure, and the base layer of the second region being provided with a first SGT structure and a second SGT structure spaced apart from each other; Forming a patterned photoresist layer on the first SGT structure in the second region and the spacer layer above the BCD structure in the first region, and etching the spacer layer using the patterned photoresist layer as a mask to expose a portion of the base layer and the second SGT structure; A control gate is formed on the spacer layer above a portion of the BCD structure and extends to a portion of the exposed base layer. The control gate is also formed on the exposed second SGT structure.

2. The method for preparing a semiconductor device according to claim 1, wherein: The material of the base layer includes silicon.

3. The method for preparing a semiconductor device according to claim 1, wherein: The first SGT structure includes a first shielding gate and a first dielectric layer covering the first shielding gate; the second SGT structure includes a second shielding gate and a second dielectric layer covering the second shielding gate, the upper surface of the second shielding gate is lower than the upper surface of the first shielding gate, and the upper surface of the second dielectric layer is flush with the upper surface of the first dielectric layer.

4. The method for preparing a semiconductor device according to claim 3, wherein: The materials of the first dielectric layer and the second dielectric layer include silicon oxide.

5. The method for preparing a semiconductor device according to claim 3, wherein: The material of the second dielectric layer is the same as that of the spacer layer.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: In the step of etching the spacer layer using the patterned photoresist layer as a mask, a portion of the second dielectric layer on the second shielding gate is also etched away.

7. The method for preparing a semiconductor device according to claim 3, wherein: In the step of etching the spacer layer using the patterned photoresist layer as a mask, a portion of the spacer layer between the first SGT structure and the BCD structure is etched away.

8. The method for preparing a semiconductor device according to claim 7, wherein: The width of the spacer layer etched away between the first SGT structure and the BCD structure is greater than or equal to 3 μm.

9. The method for preparing a semiconductor device according to claim 1, wherein: The BCD structure includes a shallow trench isolation structure.

10. A semiconductor device, characterized in that: The semiconductor device is prepared by the method for preparing the semiconductor device according to any one of claims 1 to 9.

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