Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device and a preparation method thereof, and a storage system. The semiconductor device comprises a first stack structure, a second stack structure and a conductive column. The first stacking structure comprises first electrode layers and first dielectric layers which are stacked alternately, and the second stacking structure is located on the first stacking structure and comprises word line layers and second dielectric layers which are stacked. The conductive column penetrates through the first stacking structure and the second stacking structure and comprises a main body structure and a protruding structure protruding out of the side wall of the main body structure, and the protruding structure is located between the main body structure and the first electrode layer. Wherein the protruding structure comprises a storage function layer and a second electrode layer, and the storage function layer is located between the second electrode layer and the first electrode layer. The first electrode layer in the projection structure and the first stacking structure can form a storage capacitor, and the word line layer gathered by the main body structure and the second stacking structure can form a transistor, so that the storage capacitor and the transistor can be integrally formed through the conductive column, and the process cost is greatly reduced.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and more specifically, to a semiconductor device and a method for manufacturing the same, and a storage system. Background Art

[0002] Planar memory devices have reached their practical expansion limit. In order to further increase storage capacity and reduce storage cost per bit, three-dimensional memory has been proposed.

[0003] How to reduce the cost of three-dimensional memory is a direction that urgently needs to be optimized.

[0004] Application Contents

[0005] The purpose of the embodiments of the present application is to provide a semiconductor device and a method for manufacturing the same, and a storage system, in order to reduce the process cost of the semiconductor device.

[0006] In one aspect, the present application provides a semiconductor device, comprising:

[0007] A first stacking structure includes first electrode layers and first dielectric layers that are alternately stacked;

[0008] A second stacked structure, located on the first stacked structure, and comprising a stacked word line layer and a second dielectric layer;

[0009] a conductive column, which penetrates the first stacking structure and the second stacking structure and comprises a main structure and a protruding structure protruding from a side wall of the main structure, wherein the protruding structure is located between the main structure and the first electrode layer;

[0010] Wherein, the protruding structure includes a storage function layer and a second electrode layer, and the storage function layer is located between the second electrode layer and the first electrode layer.

[0011] In some embodiments, the protrusion structure further comprises:

[0012] The connecting layer is located between the second electrode layer and the main structure.

[0013] In some embodiments, the connecting layer and the main structure include the same material.

[0014] In some embodiments, the main structure includes a semiconductor layer or includes a semiconductor layer and an insulating layer surrounded by the semiconductor layer.

[0015] In some embodiments, the storage functional layer includes a ferroelectric material, and the ferroelectric material includes hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, niobium oxide, tantalum oxide, tungsten oxide, molybdenum oxide, vanadium oxide, lanthanum oxide, and / or combinations thereof.

[0016] In some embodiments, the semiconductor device further comprises:

[0017] A gate insulating layer is located between the main structure and the second stacking structure.

[0018] In some embodiments, the gate insulating layer and the storage function layer include the same material.

[0019] In some embodiments, the semiconductor device further comprises:

[0020] The first lead-out contact is located at an end of the main structure away from the first stacking structure.

[0021] In some embodiments, the semiconductor device further comprises:

[0022] The second lead contact is connected to the first electrode layer.

[0023] In another aspect, the present application provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising:

[0024] forming a first stacking structure, wherein the first stacking structure comprises first electrode layers and first dielectric layers that are alternately stacked;

[0025] forming a second stacked structure on the first stacked structure, the second stacked structure comprising a stacked word line layer and a second dielectric layer;

[0026] forming a conductive column penetrating the first stacking structure and the second stacking structure, wherein the conductive column comprises a main structure and a protruding structure protruding from a side wall of the main structure, and the protruding structure is located between the main structure and the first electrode layer;

[0027] Wherein, the protruding structure includes a second electrode layer and a storage function layer, and the storage function layer is located between the second electrode layer and the first electrode layer.

[0028] In some embodiments, the step of forming a conductive column penetrating the first stacking structure and the second stacking structure includes:

[0029] forming a first through hole penetrating the first stacking structure and the second stacking structure;

[0030] etching the first electrode layer through the first through hole to form a groove, so as to form a second through hole including the first through hole and the groove;

[0031] forming a storage function layer and a second electrode layer in the groove in sequence to form the protrusion structure;

[0032] A main structure connected to the protruding structure is formed in the first through hole, and the main structure and the protruding structure constitute a conductive column.

[0033] In some embodiments, the step of sequentially forming a storage function layer and a second electrode layer in the groove includes:

[0034] forming a storage function layer, a second electrode layer and a sacrificial layer in sequence in the second through hole, wherein the sacrificial layer includes a connection layer located in the groove;

[0035] removing the sacrificial layer outside the groove;

[0036] The second electrode layer outside the groove is removed.

[0037] In some embodiments, the storage function layer on the sidewall of the second stacked structure serves as a gate insulating layer, and the gate insulating layer is located between the second stacked structure and the main structure.

[0038] In some embodiments, the method for preparing the semiconductor device further includes:

[0039] removing the storage function layer outside the groove;

[0040] A gate insulating layer is formed between the main structure and the second stacked structure.

[0041] In some embodiments, the main structure includes a semiconductor layer, and the sacrificial layer and the main structure include the same material.

[0042] On the other hand, the present application provides a storage system, comprising:

[0043] The semiconductor device in any of the above embodiments;

[0044] A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

[0045] The present application provides a semiconductor device and a preparation method thereof, and a storage system, wherein the semiconductor device includes a first stacking structure, a second stacking structure, and a conductive column. The first stacking structure includes a first electrode layer and a first dielectric layer that are alternately stacked, and the second stacking structure is located on the first stacking structure and includes a stacked word line layer and a second dielectric layer. The conductive column runs through the first stacking structure and the second stacking structure, and includes a main structure and a protruding structure protruding from the side wall of the main structure, and the protruding structure is located between the main structure and the first electrode layer. Among them, the protruding structure includes a storage function layer and a second electrode layer, and the storage function layer is located between the second electrode layer and the first electrode layer. Since the protruding structure and the first electrode layer in the first stacking structure can constitute a storage capacitor, the word line layer summarized by the main structure and the second stacking structure can constitute a transistor, and the storage capacitor and the transistor are also connected through the main structure, the storage capacitor and the transistor can be formed as one piece through the conductive column, which greatly reduces the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0047] Figure 1 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application;

[0048] Figure 2 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application;

[0049] Figure 3 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application;

[0050] Figure 4 is a schematic flow chart of a method for preparing a semiconductor device provided in some embodiments of the present application;

[0051] Figure 5a-5e is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application;

[0052] Figure 6 It is a schematic diagram of the structure of the storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0054] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0055] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0056] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.

[0057] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0058] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0059] See also Figure 1 , Figure 11 is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application. The semiconductor device 100 may be a wafer, a memory, or a part of a memory, such as a three-dimensional memory or a part of a three-dimensional memory. The three-dimensional memory may be applied to communication products, consumer electronic products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronic products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0060] The semiconductor device 100 includes a substrate 10, a first stacked structure 20, a second stacked structure 30 and a conductive pillar 40. The first stacked structure 20 is located on the substrate 10 and includes a first electrode layer 21 and a first dielectric layer 22 that are alternately stacked. The second stacked structure 30 is located on the first stacked structure 20 and includes a stacked word line layer 31 and a second dielectric layer 32. The conductive pillar 40 runs through the first stacked structure 20 and the second stacked structure 30, and can also extend into the substrate 10. The conductive pillar 40 includes a main structure 41 and a protruding structure 42 protruding from the sidewall of the main structure 41, and the protruding structure 42 is located between the main structure 41 and the first electrode layer 21. Among them, the protruding structure 42 includes a storage function layer 421 and a second electrode layer 422, and the storage function layer 421 is located between the second electrode layer 422 and the first electrode layer 21.

[0061] The protruding structure 42 protrudes from the side wall of the main structure 41 and surrounds the side wall of the main structure 41 along the circumference of the main structure 41. Accordingly, the first electrode layer 21 forms a groove 211 in a direction away from the main structure 41 relative to the first dielectric layer 22 to accommodate the protruding structure 42, that is, the storage function layer 421 and the second electrode layer 422 are located in the groove 211. Specifically, the storage function layer 421 is located on the inner surface of the groove 211, and the second electrode layer 422 is located on the inner surface of the storage function layer 421.

[0062] In some embodiments, the storage function layer 421 may also be located at the interface between the first dielectric layer 22 and the main structure 41 , so that the storage function layers 421 in two adjacent grooves 211 are connected.

[0063] In some embodiments, the storage function layer 421 is also located between the main structure 41 and the substrate 10 , that is, the storage function layer 421 also surrounds the bottom of the main structure 41 .

[0064] In some embodiments, the storage function layer 421 and the second electrode layer 422 fill the entire groove 211 , and the side of the second electrode layer 422 not surrounded by the storage function layer 421 is in direct contact with the main structure 41 , so the second electrode layers 422 in two adjacent grooves 211 are separated.

[0065] The first electrode layer 21 in the first stacked structure 20 and the storage function layer 421 and the second electrode layer 422 in the protruding structure 42 can form a storage capacitor C, and the first electrode layer 21 and the second electrode layer 422 can form two electrodes of the storage capacitor C. One first electrode layer 21 and one protruding structure 42 can form a storage capacitor C, and multiple storage capacitors C can be connected in series through the main structure 41, and the number of the protruding structures 42 can be determined according to the number of the first electrode layers 21.

[0066] The number of stacked layers of the first electrode layer 21 determines the number of storage capacitors C. The number of stacked layers of the first stacked structure 20 can be, for example, 32 layers, 64 layers, 96 layers, 128 layers, etc. The more stacked layers of the first stacked structure 20, the higher the integration, that is, the more storage capacitors C. The number of stacked layers and the stacking height of the first electrode layer 21 in the first stacked structure 20 can be designed according to actual storage requirements, and this application does not impose specific restrictions on this.

[0067] The first electrode layer 21 can be made of a conductive material, for example, and the conductive material can include one or more of TiN (titanium nitride), TaN (tantalum nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), Pt (platinum) and the like.

[0068] The storage function layer 421 may include a ferroelectric material, which may include transition metal oxides such as hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (Mo3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof. On this basis, the ferroelectric material may also be doped. For example, the storage function layer 421 may be HfO2 doped with silicon (Si), yttrium (Y), gadolinium (Gd), lanthanum (La), zirconium (Zr) or aluminum (Al) or any combination thereof.

[0069] Among them, ferroelectric material polarization is non-volatile because once polarization occurs, an external electric field cannot change the polarization direction until the amplitude of the electric field reaches a threshold. Ferroelectric memory (FeRAM) uses the polarization reversal or switching effect and stores digital bits "0" and "1" based on the direction of spontaneous polarization.

[0070] The second electrode layer 422 can be made of a conductive material, which can include, for example, one or more of TiN (titanium nitride), TaN (tantalum nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), Pt (platinum) and the like.

[0071] The word line layer 31 in the second stacked structure 30 serves as a control gate and can form a transistor T with the main structure 41. In addition, since the main structure 41 continuously runs through the first stacked structure 20 and the second stacked structure 30, the control gate can be connected to the storage capacitor C below through the main structure 41 to control the storage capacitor C to realize its function of storing data. The number of transistors T can be determined according to the number of word line layers 31, and the present application does not specifically limit the number of stacked layers of the word line layers 31.

[0072] The material of the word line layer 31 may be a conductive material. In some embodiments, the word line layer 31 may be one or more of conductive materials such as poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.

[0073] The first dielectric layer 22 and the second dielectric layer 32 may be made of the same material, for example, an insulating material, which may include at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0074] It should be noted that, in the first stacked structure 20, the thicknesses of the plurality of first dielectric layers 22 may be substantially the same or different. The thicknesses of the plurality of first electrode layers 21 may be substantially the same or different, and may be selected according to actual needs.

[0075] In some embodiments, the semiconductor device 100 may further include a gate insulating layer 50 , and the gate insulating layer 50 is located between the main structure 41 and the second stacked structure 30 , that is, the gate insulating layer 50 is located between the word line layer 31 and the main structure 41 .

[0076] In some embodiments, the gate insulating layer 50 may be connected to the memory function layer 421 .

[0077] In some embodiments, the gate insulating layer 50 and the storage functional layer 421 may include the same material, such as a transition metal oxide of hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (Mo3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof.

[0078] In some embodiments, the main structure 41 may include a semiconductor layer, and the storage capacitor C and the transistor T may be electrically connected via the semiconductor layer, wherein the semiconductor layer corresponding to the second stacked structure 30 serves as a channel of the transistor T.

[0079] The material of the semiconductor layer can be one or more of semiconductor materials such as Si (silicon), poly-Si (p-Si, polycrystalline silicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) multi-compound, ZnO (zinc oxide), ITO (indium tin oxide), TiO2 (titanium dioxide), MoS2 (molybdenum disulfide), WS2 (tungsten disulfide), etc.

[0080] In some embodiments, the main structure 41 may further include an insulating layer (not shown) surrounded by the semiconductor layer. The insulating layer may include at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0081] The semiconductor device 100 may further include a first lead-out contact 410 . The first lead-out contact 410 is located at one end of the main structure 41 away from the first stacked structure 20 . The other end of the first lead-out contact 410 may be connected to a bit line.

[0082] The semiconductor device 100 may further include a second lead-out contact 210, the bottoms of which are respectively connected to the first electrode layers 21 to lead out the first electrode layers 21. The bottoms of the second lead-out contacts 210 may be located on the first electrode layer 21 or in the first electrode layer 21.

[0083] In order to reserve space for the second lead-out contact 210 , the word line layer 31 may not be disposed in the area where the second lead-out contact 210 is located.

[0084] The semiconductor device 100 may further include a third lead-out contact 310 located on a side of the word line layer 31 away from the first stacked structure 20 to lead out the word line layer 31. The bottom of the third lead-out contact 310 may be located on the word line layer 31 or in the word line layer 31.

[0085] In some embodiments, the third lead contact 310 may be spaced apart from the second lead contact 210 by at least one conductive pillar 40 to reduce signal interference between the second lead contact 210 and the third lead contact 310 .

[0086] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiment, and the same structures are not described in detail again, and only the differences are described.

[0087] The conductive pillar 40 a in the semiconductor device 200 includes a main structure 41 and a protruding structure 42 a . The protruding structure 42 a includes not only a storage function layer 421 and a second electrode layer 422 , but also a connecting layer 423 . The connecting layer 423 is located between the second electrode layer 422 and the main structure 41 .

[0088] Specifically, the connection layer 423 protrudes from the side wall of the main structure 41 and surrounds the main structure 41 along the circumference of the main structure 41, the second electrode layer 422 surrounds the outer surface of the connection layer 423, and the storage function layer 421 surrounds the outer surface of the second electrode layer 422. In other words, the first electrode layer 21 shrinks inward relative to the first dielectric layer 22 in a direction away from the main structure 41 to form a groove 211, and the storage function layer 421, the second electrode layer 422 and the connection layer 423 fill the groove 211 in sequence.

[0089] In some embodiments, the connection layer 423 may be a conductive material, and the connection layer 423 and the main structure 41 may include the same material. The main structure 41 may include a semiconductor layer, and the connection layer 423 and the semiconductor layer may include the same material. In one embodiment, the connection layer 423 and the semiconductor layer may be made of the same material, such as polysilicon.

[0090] See also Figure 3 , Figure 3 1 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiment, and the same structures are not described in detail again, and only the differences are described.

[0091] The gate insulating layer 50 a in the semiconductor device 300 may be made of insulating material, for example, the same material as the first dielectric layer 22 or the second dielectric layer 32 , and may specifically include at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0092] The embodiment of the present application provides a semiconductor device, including a first stacking structure 20, a second stacking structure 30 and a conductive pillar 40 / 40a. The conductive pillar 40 / 40a runs through the first stacking structure 20 and the second stacking structure 30, and includes a main structure 41 and a protruding structure 42 / 42a protruding from the side wall of the main structure 41, and the protruding structure 42 / 42a is located between the main structure 41 and the first electrode layer 21. Among them, the protruding structure 42 / 42a includes a storage function layer 421 and a second electrode layer 422, and the storage function layer 421 is located between the second electrode layer 422 and the first electrode layer 21. Due to the conductive pillar 40 / 40a that continuously runs through the first stacking structure 20 and the second stacking structure 30, the storage capacitor C and the transistor T are formed in one piece, so the process steps can be reduced and the process cost can be greatly reduced. In addition, compared with the process of first forming the storage capacitor C and then forming the transistor T, there is no problem of alignment between the transistor T and the storage capacitor C, and the process window can be increased.

[0093] See also Figure 4 , Figure 4 is a schematic diagram of a method for preparing a semiconductor device provided in some embodiments of the present application. Figure 5a-5e , Figure 5a-5e 200 is a schematic diagram of the structure of the semiconductor device in the preparation process provided by some embodiments of the present application. This embodiment takes the preparation of the above-mentioned semiconductor device 200 as an example to illustrate the preparation method of the semiconductor device. Figure 2 The method for preparing the semiconductor device includes the following steps S1-S3.

[0094] Step S1: forming a first stacked structure 20 , wherein the first stacked structure 20 includes first electrode layers 21 and first dielectric layers 22 that are alternately stacked.

[0095] Step S2 : forming a second stacked structure 30 on the first stacked structure 20 , wherein the second stacked structure 30 includes a stacked word line layer 31 and a second dielectric layer 32 .

[0096] Specifically, Figure 5a As shown, a substrate 10 may be formed first, and then a first dielectric layer 22 and a first electrode layer 21 may be alternately deposited on the substrate 10, and then a second dielectric layer 32 and a word line layer 31 may be alternately deposited on the first stacked structure 20. The first electrode layer 21 and the word line layer 31 are isolated by the first dielectric layer 22 or the second dielectric layer 32.

[0097] The deposition method may include but is not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering and other methods.

[0098] Step S3: forming a conductive column 40a penetrating the first stacking structure 20 and the second stacking structure 30, wherein the conductive column 40a comprises a main structure 41 and a protruding structure 42a protruding from a side wall of the main structure 41, and the protruding structure 42a is located between the main structure 41 and the first electrode layer 21.

[0099] Specifically, step S3 may include the following steps.

[0100] 1) If Figure 5a As shown, the second stack structure 30 and the first stack structure 20 are first etched to form a first through hole 401 that penetrates the first stack structure 20 and the second stack structure 30. The bottom of the first through hole 401 may extend into the substrate 10.

[0101] 2) If Figure 5b As shown, the first electrode layer 21 is etched through the first through hole 401 to form a groove 211, so as to form a second through hole 402 including the first through hole 401 and the groove 211. The groove 211 is located between adjacent first dielectric layers 22, or between the first dielectric layer 22 and the second dielectric layer 32, and the groove 211 is connected through the first through hole 401.

[0102] 3) If Figure 5b-5d As shown, a storage function layer 421 and a second electrode layer 422 are sequentially formed in the groove 211 to form the protruding structure 42a.

[0103] In some specific embodiments, Figure 5b As shown, a storage function layer 421, a second electrode layer 422 and a sacrificial layer 424 may be sequentially formed in the second through hole 402, that is, the storage function layer 421 may be deposited on the sidewall of the first through hole 401 and the inner surface of the groove 211, the second electrode layer 422 may be deposited on the inner surface of the storage function layer 421, and the sacrificial layer 424 may be deposited on the inner surface of the second electrode layer 422. The sacrificial layer 424 fills up the groove 211, but does not fill up the first through hole 401.

[0104] In some embodiments, the storage function layer 421 on the sidewall of the second stacked structure 30 may serve as a gate insulating layer 50 , and the gate insulating layer 50 is located between the second stacked structure 30 and the main structure 41 .

[0105] like Figure 5c As shown, the sacrificial layer 424 outside the groove 211 is removed to expose the second electrode layer 422 located on the side wall of the first through hole 401 .

[0106] like Figure 5d As shown, the second electrode layer 422 outside the groove 211 is removed, that is, the second electrode layer 422 is only retained in the groove 211, so the second electrode layers 422 in different grooves 211 are isolated from each other, and the second electrode layer 422 on the side wall of the gate insulating layer 50 is removed. The sacrificial layer 424 retained in the groove 211 can be used as a connecting layer 423 to be connected to the main structure 41 formed subsequently.

[0107] 4) A main structure 41 connected to the protruding structure 42 a is formed in the first through hole 401 , and the main structure 41 and the protruding structure 42 a constitute a conductive column 40 a .

[0108] like Figure 5e As shown, a semiconductor layer may be filled in the first through hole 401 to form a main structure 41 , or a semiconductor layer and an insulating layer may be sequentially filled in the first through hole 401 to form a main structure 41 , and the insulating layer may increase the supporting performance of the conductive column 40a .

[0109] In some embodiments, the sacrificial layer 424 may include the same material as the main structure 41. Specifically, the sacrificial layer 424 may also include the semiconductor layer, such as polysilicon.

[0110] The method for preparing the semiconductor device may further include: Figure 2 As shown, a third dielectric layer 60 covering the second dielectric layer 32 and the conductive pillar 40 a is first formed, and then a first lead contact 410 is formed in the third dielectric layer 60 to connect the end of the conductive pillar 40 a away from the substrate 10 (or the first stacked structure 20 ).

[0111] The method for preparing the semiconductor device may further include: Figure 2 As shown, a second lead contact 210 connected to the first electrode layer 21 is formed. Specifically, an etching process can be performed first to form a conductive hole (not shown in the figure) located on each first electrode layer 21, and then an isolation layer and a conductive layer are sequentially formed in each conductive hole, wherein the bottom of the conductive layer is connected to the first electrode layer 21.

[0112] The method for preparing the semiconductor device may further include: Figure 2 As shown, a third lead contact 310 connected to the word line layer 31 may be formed in the third dielectric layer 60 .

[0113] In other embodiments, if the depth of the formed groove 211 is shallow, that is, the distance between the first electrode layer 21 and the first through hole 401 is small, when the second electrode layer 422 is deposited, the second electrode layer 422 can fill the groove 211 and the second electrode layer 422 may overflow from the groove 211 (refer to Figure 5b ). If the remaining second electrode layer 422 in the step of removing the second electrode layer 422 can still fill the groove 211 (refer to Figure 5d ), then after forming the main structure 41, the following can be formed: Figure 1 A semiconductor device 100 is shown.

[0114] In other embodiments, Figure 5d Based on the above, the method for preparing the semiconductor device may further include: removing the storage function layer 421 outside the groove 211; and forming a gate insulating layer 50 between the main structure 41 and the second stacked structure 30. The gate insulating layer 50 may be made of a material different from that of the storage function layer 421, but the same as that of the second dielectric layer 32. In these embodiments, the following may be finally formed: Figure 3 A semiconductor device 300 is shown.

[0115] In the method for preparing a semiconductor device provided in an embodiment of the present application, the through hole of the storage capacitor C and the through hole of the transistor T can be formed integrally through the second through hole 402, that is, the through hole of the storage capacitor C and the through hole of the transistor T can be formed together. There is no need to first form the through hole of the storage capacitor C and the storage capacitor C located in the through hole of the storage capacitor C, and then form the through hole of the transistor T and the transistor T located in the through hole of the transistor T. The method for preparing the semiconductor device omits the process step of forming the transistor T separately, which can greatly reduce the process steps, thereby reducing costs. Since the transistor T needs to be aligned and connected with the storage capacitor C, the method for preparing the semiconductor device provided in the embodiment of the present application does not have the problem of alignment, and the formed semiconductor device is a self-aligned structure.

[0116] See also Figure 6 , Figure 6 6 is a schematic diagram of a storage system provided in some embodiments of the present application. The storage system 600 includes a semiconductor device 601 and a controller 602. The semiconductor device 601 may include any of the semiconductor devices in the above embodiments. The semiconductor device 601 may be a memory or a part of a memory. The controller 602 is electrically connected to the semiconductor device 601 and is used to control the semiconductor device 601 to store data. The semiconductor device 601 may perform an operation of storing data based on the control of the controller 602.

[0117] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0118] The semiconductor device 601 includes: a first stacking structure, including alternately stacked first electrode layers and first dielectric layers; a second stacking structure, located on the first stacking structure, and including stacked word line layers and second dielectric layers; a conductive column, penetrating the first stacking structure and the second stacking structure, and including a main structure and a protruding structure protruding from the side wall of the main structure, the protruding structure is located between the main structure and the first electrode layer; wherein the protruding structure includes a storage function layer and a second electrode layer, the storage function layer is located between the second electrode layer and the first electrode layer.

[0119] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A first stacking structure includes first electrode layers and first dielectric layers that are alternately stacked; A second stacked structure, located on the first stacked structure, and comprising a stacked word line layer and a second dielectric layer; a conductive column, which penetrates the first stacking structure and the second stacking structure and comprises a main structure and a protruding structure protruding from a side wall of the main structure, wherein the protruding structure is located between the main structure and the first electrode layer; Wherein, the protruding structure includes a storage function layer and a second electrode layer, and the storage function layer is located between the second electrode layer and the first electrode layer.

2. The semiconductor device according to claim 1, wherein: The protrusion structure further comprises: The connecting layer is located between the second electrode layer and the main structure.

3. The semiconductor device according to claim 2, characterized in that The connecting layer and the main structure include the same material.

4. The semiconductor device according to claim 1, wherein: The main structure includes a semiconductor layer or includes a semiconductor layer and an insulating layer surrounded by the semiconductor layer.

5. The semiconductor device according to claim 1, wherein: The storage function layer includes a ferroelectric material, and the ferroelectric material includes hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, niobium oxide, tantalum oxide, tungsten oxide, molybdenum oxide, vanadium oxide, lanthanum oxide, and / or a combination thereof.

6. The semiconductor device according to claim 5, characterized in that The semiconductor device further comprises: A gate insulating layer is located between the main structure and the second stacking structure.

7. The semiconductor device according to claim 6, characterized in that The gate insulating layer and the storage function layer include the same material.

8. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The first lead-out contact is located at an end of the main structure away from the first stacking structure.

9. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The second lead contact is connected to the first electrode layer.

10. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises: forming a first stacking structure, wherein the first stacking structure comprises first electrode layers and first dielectric layers that are alternately stacked; forming a second stacked structure on the first stacked structure, the second stacked structure comprising a stacked word line layer and a second dielectric layer; forming a conductive column penetrating the first stacking structure and the second stacking structure, wherein the conductive column comprises a main structure and a protruding structure protruding from a side wall of the main structure, and the protruding structure is located between the main structure and the first electrode layer; Wherein, the protruding structure includes a second electrode layer and a storage function layer, and the storage function layer is located between the second electrode layer and the first electrode layer.

11. The method for preparing a semiconductor device according to claim 10, characterized in that: The step of forming a conductive column penetrating the first stacking structure and the second stacking structure includes: forming a first through hole penetrating the first stacking structure and the second stacking structure; etching the first electrode layer through the first through hole to form a groove, so as to form a second through hole including the first through hole and the groove; forming a storage function layer and a second electrode layer in the groove in sequence to form the protrusion structure; A main structure connected to the protruding structure is formed in the first through hole, and the main structure and the protruding structure constitute a conductive column.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: The step of sequentially forming a storage function layer and a second electrode layer in the groove comprises: forming a storage function layer, a second electrode layer and a sacrificial layer in sequence in the second through hole, wherein the sacrificial layer includes a connection layer located in the groove; removing the sacrificial layer outside the groove; The second electrode layer outside the groove is removed.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: The storage function layer on the side wall of the second stacked structure serves as a gate insulating layer, and the gate insulating layer is located between the second stacked structure and the main structure.

14. The method for preparing a semiconductor device according to claim 12, characterized in that: The method for preparing the semiconductor device further includes: removing the storage function layer outside the groove; A gate insulating layer is formed between the main structure and the second stacked structure.

15. The method for preparing a semiconductor device according to claim 12, characterized in that: The main structure includes a semiconductor layer, and the sacrificial layer and the main structure include the same material.

16. A storage system, characterized in that: include: The semiconductor device according to any one of claims 1 to 9; A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

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