Wide bandgap semiconductor power MOS chip and preparation method thereof

Abstract

The invention belongs to the technical field of power semiconductor devices, and provides a wide bandgap semiconductor power MOS chip and a preparation method thereof. A junction temperature detection area is arranged on a wide bandgap semiconductor power MOS (Metal Oxide Semiconductor) chip (MOS chip for short) by adopting a material (force-electricity material for short) which generates an electric signal under stress, if pressure is applied to the force-electricity material, a potential difference is generated, otherwise, mechanical stress is generated, namely, the force-electricity material can convert the force into the electric signal; the source of pressure is as follows: when the MOS chip works, the temperature can rise, thermal expansion can cause a force-electric material to be stressed due to different thermal expansion coefficients among materials of the MOS chip, then potential difference is generated at two poles of the force-electric material, and finally temperature monitoring of the MOS chip is realized. According to the invention, the force-electric material in the junction temperature detection area can sense the temperature change generated by the interaction of the forces of the whole MOS chip.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a wide bandgap semiconductor power MOS chip and a preparation method thereof. Background Art

[0002] In the current wide bandgap semiconductor power MOS chip technology, after the wide bandgap semiconductor power MOS chip is packaged, the only way to detect the junction temperature of the wide bandgap semiconductor power MOS chip is through optical measurement methods (such as infrared thermal imaging) and physical contact methods (such as thermocouple method). However, both infrared thermal imaging and thermocouple methods have the defect of damaging the package, resulting in subsequent unusability; at the same time, the thermocouple method also has the problem of slow response.

[0003] Therefore, how to detect the junction temperature of wide bandgap semiconductor power MOS chips without destroying the packaging structure of the wide bandgap semiconductor power MOS chips has become a major research hotspot. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a wide bandgap semiconductor power MOS chip and a preparation method thereof. The wide bandgap semiconductor power MOS chip provided by the present invention can accurately measure the junction temperature of the wide bandgap semiconductor power MOS chip without destroying the chip packaging structure.

[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0006] The present invention provides a wide bandgap semiconductor power MOS chip, comprising a drain metal layer, a substrate, a buffer layer and a conductive layer stacked in sequence;

[0007] The conductive layer is divided into a cell area, a terminal area and a junction temperature detection area;

[0008] The junction temperature detection area includes a conductive layer base layer, a silicon dioxide layer, a force-electric signal conversion layer, a dielectric layer and a metal layer from bottom to top, or includes a conductive layer base layer, a silicon dioxide layer, a dielectric layer, a force-electric signal conversion layer and a metal layer from bottom to top;

[0009] The metal layer includes a first voltage monitoring metal and a second voltage monitoring metal;

[0010] The first voltage monitoring metal and the second voltage monitoring metal are used to obtain the potential difference generated by the power-electricity signal conversion layer.

[0011] Preferably, the material of the force-electricity signal conversion layer is aluminum nitride, quartz crystal, lithium gallate, lithium germanate or titanium germanate, and the thickness of the force-electricity signal conversion layer is 0.5-1 mm.

[0012] Preferably, the thickness of the silicon dioxide layer is 0.5-1 mm.

[0013] Preferably, the material of the dielectric layer is silicon oxide doped with boron ions, silicon oxide doped with phosphorus ions, or silicon oxide co-doped with boron and phosphorus ions; and the thickness of the dielectric layer is 0.5 to 3 mm.

[0014] Preferably, the material of the first voltage monitoring metal is aluminum, copper, gold or silver, and the thickness of the first voltage monitoring metal is 5 to 10 μm; the material of the second voltage monitoring metal is aluminum, copper, gold or silver, and the thickness of the second voltage monitoring metal is 5 to 10 μm.

[0015] Preferably, in the vertical structure, the junction temperature detection area is located between two cell areas, or between the cell area and the terminal area;

[0016] In the lateral structure, the junction temperature detection area is located in the middle or edge of the layout of the wide bandgap semiconductor power MOS chip.

[0017] Preferably, the cell region includes a conductive layer base layer, a silicon dioxide layer, a dielectric layer and a metal layer from bottom to top; a planar gate is arranged between the silicon dioxide layer and the dielectric layer; the metal layer includes a source metal and a gate metal;

[0018] The conductive layer base layer includes an N-drift region and a cell body region, and an N+ region and a P+ region are arranged in the cell body region; the P+ region is led out by the source metal through a metal hole, and the planar gate is led out by the gate metal through a metal hole.

[0019] Preferably, the terminal region comprises, from bottom to top, a conductive layer base layer, a silicon dioxide layer and a dielectric layer;

[0020] The conductive layer base layer includes an N-drift region, a cut-off region and a plurality of terminal ring regions, and the cut-off region and the terminal ring region are not connected.

[0021] Preferably, the drain metal layer is a first composite metal layer or a second composite metal layer; the first composite metal layer comprises a nickel layer, a palladium layer and a gold layer stacked in sequence, the nickel layer has a thickness of 1 μm, the palladium layer has a thickness of 3 μm, the gold layer has a thickness of 8 μm, and the nickel layer is in contact with the substrate; the second composite metal layer comprises an aluminum layer, a titanium layer, a nickel layer and a silver layer stacked in sequence, the aluminum layer has a thickness of 1 μm, the titanium layer has a thickness of 1 μm, the nickel layer has a thickness of 4 μm, the silver layer has a thickness of 8 μm, and the aluminum layer is in contact with the substrate;

[0022] The substrate is made of silicon carbide, gallium nitride or diamond;

[0023] The material of the buffer layer is a third-generation semi-substrate doped with phosphorus ions.

[0024] The present invention also provides a method for preparing the wide bandgap semiconductor power MOS chip described in the above technical solution, comprising the following steps:

[0025] (1) sequentially preparing a buffer layer and a conductive layer on one side of a substrate;

[0026] (2) dividing the surface of the conductive layer into a terminal region window, a cell region window and a junction temperature detection region window, and performing a first boron implantation and a second boron implantation on the cell region window and the terminal region window respectively, to form a terminal ring region of the terminal region and a cell body region of the cell region;

[0027] (3) respectively implanting phosphorus into the terminal ring region and the cell body region to form a cutoff region in the terminal region and an N+ region in the cell region;

[0028] (4) preparing a silicon dioxide layer over the entire area;

[0029] (5) depositing a force-electricity signal conversion layer on the silicon dioxide layer, and etching the force-electricity signal conversion layer to retain only the force-electricity signal conversion layer in the junction temperature detection area;

[0030] (6) preparing a planar gate on the silicon dioxide layer in the cell area, and then preparing a dielectric layer on the entire area and reflowing;

[0031] (7) Metal holes are etched in the cell area and the junction temperature detection area to form metal holes, and then high-concentration boron is injected into the metal holes in the cell area to form a P+ area; finally, a metal layer is deposited in the entire area;

[0032] (8) preparing a drain metal layer on the other side of the substrate to obtain the wide bandgap semiconductor power MOS chip;

[0033] or,

[0034] (1) sequentially preparing a buffer layer and a conductive layer on one side of a substrate;

[0035] (2) dividing the surface of the conductive layer into a terminal region window, a cell region window and a junction temperature detection region window, and performing a first boron implantation and a second boron implantation on the cell region window and the terminal region window respectively, to form a terminal ring region of the terminal region and a cell body region of the cell region;

[0036] (3) respectively implanting phosphorus into the terminal ring region and the cell body region to form a cutoff region in the terminal region and an N+ region in the cell region;

[0037] (4) sequentially preparing a silicon dioxide layer over the entire area;

[0038] (5) preparing a planar gate on the silicon dioxide layer in the cell area, and then preparing a dielectric layer on the entire area and reflowing;

[0039] (6) depositing a force-electricity signal conversion layer on the dielectric layer, and etching the force-electricity signal conversion layer to retain only the force-electricity signal conversion layer in the junction temperature detection area;

[0040] (7) Metal holes are etched in the cell area and the junction temperature detection area to form metal holes, and then high-concentration boron is injected into the metal holes in the cell area to form a P+ area; finally, a metal layer is deposited in the entire area;

[0041] (8) A drain metal layer is prepared on the other side of the substrate to obtain the wide bandgap semiconductor power MOS chip.

[0042] The invention provides a wide bandgap semiconductor power MOS chip.

[0043] The present invention sets a junction temperature detection area on a wide bandgap semiconductor power MOS chip (hereinafter referred to as MOS chip) based on the piezoelectric effect of the material that generates an electrical signal when subjected to force: if pressure is applied to the material that generates an electrical signal when subjected to force, it will generate a potential difference, and vice versa, mechanical stress is generated, that is, the material that generates an electrical signal when subjected to force can convert force into an electrical signal; wherein, the source of pressure: when the MOS chip is working, the temperature will rise, and due to the different thermal expansion coefficients between the materials of the MOS chip, thermal expansion will cause the material that generates an electrical signal when subjected to force to be subjected to force, and then a potential difference will be generated between the two poles of the material that generates an electrical signal when subjected to force, and finally the temperature monitoring of the MOS chip is realized. The material that generates an electrical signal when subjected to force in the junction temperature detection area of ​​the present invention can sense the temperature change caused by the interaction of forces of the entire MOS chip. At the same time, the heat in the MOS chip will directly cause pressure changes, and the mechanical to electrochemical conversion can be directly realized through the material that generates an electrical signal when subjected to force in the junction temperature detection area, avoiding temperature hysteresis. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A cross-sectional view of a wide bandgap semiconductor power MOS chip provided by the present invention;

[0045] Figure 2 A cross-sectional view of a wide bandgap semiconductor power MOS chip provided by the present invention;

[0046] Figure 3 A schematic diagram of the product structure obtained in the first step of the first preparation method of the wide bandgap semiconductor power MOS chip provided by the present invention;

[0047] Figure 4 A schematic diagram of the product structure obtained in the second step of the first preparation method of the wide bandgap semiconductor power MOS chip provided by the present invention;

[0048] Figure 5 A schematic diagram of the product structure obtained in the third step of the first preparation method of the wide bandgap semiconductor power MOS chip provided by the present invention;

[0049] Figure 6 A schematic diagram of the product structure obtained in the fourth step of the first preparation method of the wide bandgap semiconductor power MOS chip provided by the present invention;

[0050] Figure 7 A schematic diagram of the product structure obtained in the fifth step of the first method for preparing a wide bandgap semiconductor power MOS chip provided by the present invention;

[0051] Figure 8 A schematic diagram of the product structure obtained in the sixth step of the first method for preparing the wide bandgap semiconductor power MOS chip provided by the present invention;

[0052] Fig. 9 A schematic diagram of the product structure obtained in the seventh step of the first method for preparing a wide bandgap semiconductor power MOS chip provided by the present invention;

[0053] Fig.10 This is a schematic diagram of the product structure obtained in the eighth step of the first preparation method of the wide bandgap semiconductor power MOS chip provided by the present invention. DETAILED DESCRIPTION

[0054] The present invention provides a wide bandgap semiconductor power MOS chip, comprising a drain metal layer, a substrate, a buffer layer and a conductive layer stacked in sequence;

[0055] The conductive layer is divided into a cell area, a terminal area and a junction temperature detection area;

[0056] The junction temperature detection area includes a conductive layer base layer, a silicon dioxide layer, a force-electric signal conversion layer, a dielectric layer and a metal layer from bottom to top, or includes a conductive layer base layer, a silicon dioxide layer, a dielectric layer, a force-electric signal conversion layer and a metal layer from bottom to top;

[0057] The metal layer includes a first voltage monitoring metal and a second voltage monitoring metal;

[0058] The first voltage monitoring metal and the second voltage monitoring metal are used to obtain the potential difference generated by the power-electricity signal conversion layer.

[0059] Figure 1 A cross-sectional view of a wide bandgap semiconductor power MOS chip provided by the present invention, Figure 2 A cross-sectional view of a wide bandgap semiconductor power MOS chip provided by the present invention; Figure 1 and Figure 2 The structure of the wide bandgap semiconductor power MOS chip provided by the present invention is described in detail.

[0060] In the present invention, unless otherwise specified, the raw materials used in the present invention are preferably commercially available products.

[0061] In the present invention, the wide bandgap semiconductor power MOS chip is preferably a SiC MOS device.

[0062] The wide bandgap semiconductor power MOS chip provided by the present invention includes a drain metal layer, and the material of the drain metal layer is preferably a first composite metal layer or a second composite metal layer. In the present invention, the first composite metal layer preferably includes a nickel layer, a palladium layer and a gold layer stacked in sequence, the thickness of the nickel layer is preferably 1 μm, the thickness of the palladium layer is preferably 3 μm, the thickness of the gold layer is preferably 8 μm, and the nickel layer is preferably in contact with the substrate. In the present invention, the second composite metal layer preferably includes an aluminum layer, a titanium layer, a nickel layer and a silver layer stacked in sequence, the thickness of the aluminum layer is preferably 1 μm, the thickness of the titanium layer is preferably 1 μm, the thickness of the nickel layer is preferably 4 μm, the thickness of the silver layer is preferably 8 μm, and the aluminum layer is preferably in contact with the substrate.

[0063] The wide bandgap semiconductor power MOS chip provided by the present invention comprises a substrate, and the material of the substrate is preferably silicon carbide, gallium nitride or diamond, specifically silicon carbide.

[0064] The wide bandgap semiconductor power MOS chip provided by the present invention comprises a buffer layer, and the material of the buffer layer is preferably a third-generation semi-substrate doped with high-concentration phosphorus ions. In the present invention, the thickness of the buffer layer is preferably 10-20 μm.

[0065] The wide bandgap semiconductor power MOS chip provided by the present invention comprises a conductive layer; the conductive layer is divided into a cell area, a terminal area and a junction temperature detection area.

[0066] In the present invention, the junction temperature detection area includes a conductive layer base, a silicon dioxide layer, a force-electric signal conversion layer, a dielectric layer and a metal layer from bottom to top, or includes a conductive layer base, a silicon dioxide layer, a dielectric layer, a force-electric signal conversion layer and a metal layer from bottom to top. In the present invention, the thickness of the conductive layer base is preferably 150-200μm; the thickness of the conductive layer base is preferably 150-200μm. In the present invention, the thickness of the silicon dioxide layer is preferably 0.5-1mm, specifically 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm or 1mm. In the present invention, the material of the force-electric signal conversion layer is preferably aluminum nitride, and the thickness of the force-electric signal conversion layer is preferably 0.5-1mm, specifically 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm or 1mm. In the present invention, the material of the dielectric layer is preferably silicon oxide doped with boron ions, silicon oxide doped with phosphorus ions, or silicon oxide co-doped with boron and phosphorus ions; the thickness of the dielectric layer is preferably 0.5 to 3 mm, specifically 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm or 3 mm. In the present invention, the metal layer includes a first voltage monitoring metal and a second voltage monitoring metal; the first voltage monitoring metal and the second voltage monitoring metal are used to obtain the potential difference generated by the force-electric signal conversion layer. In the present invention, the material of the first voltage monitoring metal is preferably aluminum, copper, gold or silver, and the thickness of the first voltage monitoring metal is preferably 5 to 10 μm; the material of the second voltage monitoring metal is preferably aluminum, copper, gold or silver, and the thickness of the second voltage monitoring metal is preferably 5 to 10 μm.

[0067] In the present invention, in the vertical structure, the junction temperature detection area is preferably located between two cell areas, or preferably located between the cell area and the terminal area, see Figure 1 and Figure 2 In the present invention, in the lateral structure, the junction temperature detection area is preferably located in the middle or edge of the layout of the wide bandgap semiconductor power MOS chip.

[0068] In the present invention, the cell region preferably includes a conductive layer base layer, a silicon dioxide layer, a dielectric layer and a metal layer from bottom to top; a planar gate is preferably arranged between the silicon dioxide layer and the dielectric layer; the metal layer preferably includes a source metal and a gate metal; the material of the source metal is preferably aluminum, copper, gold or silver, and the thickness of the source metal is preferably 5 to 10 μm; the material of the gate metal is preferably aluminum, copper, gold or silver, and the thickness of the gate metal is preferably 5 to 10 μm. In the present invention, the conductive layer base layer preferably includes an N-drift region and a cell body region, and an N+ region and a P+ region are preferably arranged in the cell body region; the P+ region is preferably led out by the source metal through a metal hole. In the present invention, the planar gate is preferably led out by the gate metal through a metal hole. In the present invention, the material and thickness of the silicon dioxide layer and the dielectric layer in the cell region are preferably consistent with the parameters of the junction temperature detection region, which will not be repeated here.

[0069] In the present invention, the terminal region preferably includes a conductive layer base, a silicon dioxide layer and a dielectric layer from bottom to top. In the present invention, the conductive layer base preferably includes an N-drift region, a cut-off region and a plurality of terminal ring regions, and the cut-off region and the terminal ring region are not connected. In the present invention, the parameters of the silicon dioxide layer and the dielectric layer in the terminal region are preferably consistent with the parameters of the silicon dioxide layer and the dielectric layer in the junction temperature detection region, and will not be repeated here.

[0070] The present invention also provides a first method for preparing the wide bandgap semiconductor power MOS chip described in the above technical solution, comprising the following steps:

[0071] (1) sequentially preparing a buffer layer and a conductive layer on one side of a substrate;

[0072] (2) dividing the surface of the conductive layer into a terminal region window, a cell region window and a junction temperature detection region window, and performing a first boron implantation and a second boron implantation on the cell region window and the terminal region window respectively, to form a terminal ring region of the terminal region and a cell body region of the cell region;

[0073] (3) respectively implanting phosphorus into the terminal ring region and the cell body region to form a cutoff region in the terminal region and an N+ region in the cell region;

[0074] (4) preparing a silicon dioxide layer over the entire area;

[0075] (5) depositing a force-electricity signal conversion layer on the silicon dioxide layer, and etching the force-electricity signal conversion layer to retain only the force-electricity signal conversion layer in the junction temperature detection area;

[0076] (6) preparing a planar gate on the silicon dioxide layer in the cell area, and then preparing a dielectric layer on the entire area and reflowing;

[0077] (7) Metal holes are etched in the cell area and the junction temperature detection area to form metal holes, and then high-concentration boron is injected into the metal holes in the cell area to form a P+ area; finally, a metal layer is deposited in the entire area;

[0078] (8) A drain metal layer is prepared on the other side of the substrate to obtain the wide bandgap semiconductor power MOS chip.

[0079] Figures 3 to 10 The schematic diagram of the product structure obtained by the eight steps of the first preparation method of the wide bandgap semiconductor power MOS chip provided by the present invention is shown below in combination with Figures 3 to 10 The first preparation method is described in detail.

[0080] The present invention sequentially prepares a buffer layer and a conductive layer on one side of a substrate.

[0081] The present invention does not specifically limit the method for preparing the buffer layer and the conductive layer.

[0082] After forming the conductive layer, the present invention divides the surface of the conductive layer into a terminal area window, a cell area window and a junction temperature detection area window, and performs a first boron injection and a second boron injection on the cell area window and the terminal area window respectively to form a terminal ring area of ​​the terminal area and a cell body area of ​​the cell area.

[0083] In the present invention, the first boron implantation prepares the terminal ring region of the terminal region, and the second boron implantation prepares the cell body region of the cell region. The present invention does not specifically limit the manner and method of the first boron implantation and the second boron implantation.

[0084] After forming the terminal ring region of the terminal region and the cell body region of the cell region, the present invention performs phosphorus implantation on the terminal ring region and the cell body region respectively to form a cutoff region of the terminal region and an N+ region of the cell region.

[0085] The present invention does not specifically limit the method of phosphorus implantation.

[0086] After phosphorus implantation, the present invention prepares a silicon dioxide layer on the entire area.

[0087] The present invention does not specifically limit the method for preparing the silicon dioxide layer.

[0088] After forming the silicon dioxide layer, the present invention deposits a force-electricity signal conversion layer on the silicon dioxide layer, etches the force-electricity signal conversion layer, and only retains the force-electricity signal conversion layer in the junction temperature detection area.

[0089] The present invention does not specifically limit the deposition and etching methods of the electromechanical signal conversion layer.

[0090] After etching, the present invention prepares a planar gate on the silicon dioxide layer in the cell area, and then prepares a dielectric layer on the entire area and reflows.

[0091] The present invention does not specifically limit the method for preparing the planar gate and the dielectric layer.

[0092] After reflow, the present invention performs metal hole etching on the cell area and the junction temperature detection area to form metal holes, and then performs high-concentration boron injection on the metal holes in the cell area to form a P+ area; finally, a metal layer is deposited on the entire area.

[0093] The present invention does not specifically limit the metal hole etching, high concentration boron injection and metal layer deposition, and methods well known to those skilled in the art may be used.

[0094] After depositing the metal layer, the present invention prepares a drain metal layer on the other side of the substrate to obtain the wide bandgap semiconductor power MOS chip.

[0095] The present invention does not specifically limit the method for preparing the drain metal layer.

[0096] The present invention also provides a second method for preparing the wide bandgap semiconductor power MOS chip described in the above technical solution, comprising the following steps:

[0097] (1) sequentially preparing a buffer layer and a conductive layer on one side of a substrate;

[0098] (2) dividing the surface of the conductive layer into a terminal region window, a cell region window and a junction temperature detection region window, and performing a first boron implantation and a second boron implantation on the cell region window and the terminal region window respectively, to form a terminal ring region of the terminal region and a cell body region of the cell region;

[0099] (3) respectively implanting phosphorus into the terminal ring region and the cell body region to form a cutoff region in the terminal region and an N+ region in the cell region;

[0100] (4) sequentially preparing a silicon dioxide layer over the entire area;

[0101] (5) preparing a planar gate on the silicon dioxide layer in the cell area, and then preparing a dielectric layer on the entire area and reflowing;

[0102] (6) depositing a force-electricity signal conversion layer on the dielectric layer, and etching the force-electricity signal conversion layer to retain only the force-electricity signal conversion layer in the junction temperature detection area;

[0103] (7) Metal holes are etched in the cell area and the junction temperature detection area to form metal holes, and then high-concentration boron is injected into the metal holes in the cell area to form a P+ area; finally, a metal layer is deposited in the entire area;

[0104] (8) A drain metal layer is prepared on the other side of the substrate to obtain the wide bandgap semiconductor power MOS chip.

[0105] In the present invention, the second method of the wide bandgap semiconductor power MOS chip is preferably consistent with the above technical solution, which will not be described in detail here.

[0106] The wide bandgap semiconductor power MOS chip and the preparation method thereof provided by the present invention are described in detail below in conjunction with the embodiments, but they should not be construed as limiting the protection scope of the present invention.

[0107] Example 1

[0108] (1) A silicon carbide substrate (180 μm thick) was used as the substrate, which was cleaned and dried before use. A buffer layer and a conductive layer were sequentially prepared on one side of the silicon carbide substrate.

[0109] (2) Dividing the surface of the conductive layer into a terminal area window, a cell area window and a junction temperature detection area window, performing a first boron implantation and a second boron implantation on the cell area window and the terminal area window respectively, to form a terminal ring area of ​​the terminal area and a cell body area of ​​the cell area.

[0110] (3) Phosphorus is implanted into the terminal ring region and the cell body region respectively to form a cutoff region of the terminal region and an N+ region of the cell region.

[0111] (4) A silicon dioxide layer (3 μm thick) was formed on the entire area.

[0112] (5) depositing a force-electricity signal conversion layer (made of aluminum nitride) on the silicon dioxide layer, and etching the force-electricity signal conversion layer to retain only the force-electricity signal conversion layer in the junction temperature detection area.

[0113] (6) A planar gate is prepared on the silicon dioxide layer in the cell area, and then a dielectric layer (made of silicon oxide co-doped with boron and phosphorus ions) is prepared on the entire area and reflowed.

[0114] (7) Metal holes are etched in the cell area and the junction temperature detection area to form metal holes, and then high-concentration boron is injected into the metal holes in the cell area to form a P+ area; finally, a metal layer (made of aluminum and 5 μm thick) is deposited in the entire area.

[0115] (8) A drain metal layer is prepared on the other side of the substrate to obtain the wide bandgap semiconductor power MOS chip.

[0116] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A wide bandgap semiconductor power MOS chip, characterized in that: It includes a drain metal layer, a substrate, a buffer layer and a conductive layer which are stacked in sequence; The conductive layer is divided into a cell area, a terminal area and a junction temperature detection area; The junction temperature detection area includes a conductive layer base layer, a silicon dioxide layer, a force-electric signal conversion layer, a dielectric layer and a metal layer from bottom to top, or includes a conductive layer base layer, a silicon dioxide layer, a dielectric layer, a force-electric signal conversion layer and a metal layer from bottom to top; The metal layer includes a first voltage monitoring metal and a second voltage monitoring metal; The first voltage monitoring metal and the second voltage monitoring metal are used to obtain the potential difference generated by the power-electricity signal conversion layer.

2. The wide bandgap semiconductor power MOS chip according to claim 1, characterized in that: The material of the force-electricity signal conversion layer is aluminum nitride, quartz crystal, lithium gallate, lithium germanate or titanium germanate, and the thickness of the force-electricity signal conversion layer is 0.5-1 mm.

3. The wide bandgap semiconductor power MOS chip according to claim 1, characterized in that: The thickness of the silicon dioxide layer is 0.5-1 mm.

4. The wide bandgap semiconductor power MOS chip according to claim 1, characterized in that: The material of the dielectric layer is silicon oxide doped with boron ions, silicon oxide doped with phosphorus ions, or silicon oxide co-doped with boron and phosphorus ions; the thickness of the dielectric layer is 0.5-3 mm.

5. The wide bandgap semiconductor power MOS chip according to claim 1, characterized in that: The material of the first voltage monitoring metal is aluminum, copper, gold or silver, and the thickness of the first voltage monitoring metal is 5 to 10 μm; the material of the second voltage monitoring metal is aluminum, copper, gold or silver, and the thickness of the second voltage monitoring metal is 5 to 10 μm.

6. The wide bandgap semiconductor power MOS chip according to claim 1, characterized in that: In the vertical structure, the junction temperature detection area is located between two cell areas, or between the cell area and the terminal area; In the lateral structure, the junction temperature detection area is located in the middle or edge of the layout of the wide bandgap semiconductor power MOS chip.

7. The wide bandgap semiconductor power MOS chip according to claim 1, characterized in that: The cell region includes a conductive layer base layer, a silicon dioxide layer, a dielectric layer and a metal layer from bottom to top; a planar gate is arranged between the silicon dioxide layer and the dielectric layer; the metal layer includes a source metal and a gate metal; The conductive layer base layer includes an N-drift region and a cell body region, and an N+ region and a P+ region are arranged in the cell body region; the P+ region is led out by the source metal through a metal hole, and the planar gate is led out by the gate metal through a metal hole.

8. The wide bandgap semiconductor power MOS chip according to claim 1, characterized in that: The terminal region includes a conductive layer base layer, a silicon dioxide layer and a dielectric layer in order from bottom to top; The conductive layer base layer includes an N-drift region, a cut-off region and a plurality of terminal ring regions, and the cut-off region and the terminal ring region are not connected.

9. The wide bandgap semiconductor power MOS chip according to claim 1, characterized in that: The drain metal layer is a first composite metal layer or a second composite metal layer; the first composite metal layer comprises a nickel layer, a palladium layer and a gold layer stacked in sequence, the nickel layer has a thickness of 1 μm, the palladium layer has a thickness of 3 μm, the gold layer has a thickness of 8 μm, and the nickel layer is in contact with the substrate; the second composite metal layer comprises an aluminum layer, a titanium layer, a nickel layer and a silver layer stacked in sequence, the aluminum layer has a thickness of 1 μm, the titanium layer has a thickness of 1 μm, the nickel layer has a thickness of 4 μm, the silver layer has a thickness of 8 μm, and the aluminum layer is in contact with the substrate; The substrate is made of silicon carbide, gallium nitride or diamond; The material of the buffer layer is a third-generation semi-substrate doped with high-concentration phosphorus ions.

10. The method for preparing a wide bandgap semiconductor power MOS chip according to any one of claims 1 to 9, characterized in that: The following steps are involved: (1) sequentially preparing a buffer layer and a conductive layer on one side of a substrate; (2) dividing the surface of the conductive layer into a terminal region window, a cell region window and a junction temperature detection region window, and performing a first boron implantation and a second boron implantation on the cell region window and the terminal region window respectively, to form a terminal ring region of the terminal region and a cell body region of the cell region; (3) respectively implanting phosphorus into the terminal ring region and the cell body region to form a cutoff region in the terminal region and an N+ region in the cell region; (4) preparing a silicon dioxide layer over the entire area; (5) depositing a force-electricity signal conversion layer on the silicon dioxide layer, and etching the force-electricity signal conversion layer to retain only the force-electricity signal conversion layer in the junction temperature detection area; (6) preparing a planar gate on the silicon dioxide layer in the cell area, and then preparing a dielectric layer on the entire area and reflowing; (7) Metal holes are etched in the cell area and the junction temperature detection area to form metal holes, and then high-concentration boron is injected into the metal holes in the cell area to form a P+ area; finally, a metal layer is deposited in the entire area; (8) preparing a drain metal layer on the other side of the substrate to obtain the wide bandgap semiconductor power MOS chip; or, (1) sequentially preparing a buffer layer and a conductive layer on one side of a substrate; (2) dividing the surface of the conductive layer into a terminal region window, a cell region window and a junction temperature detection region window, and performing a first boron implantation and a second boron implantation on the cell region window and the terminal region window respectively, to form a terminal ring region of the terminal region and a cell body region of the cell region; (3) respectively implanting phosphorus into the terminal ring region and the cell body region to form a cutoff region in the terminal region and an N+ region in the cell region; (4) sequentially preparing a silicon dioxide layer over the entire area; (5) preparing a planar gate on the silicon dioxide layer in the cell area, and then preparing a dielectric layer on the entire area and reflowing; (6) depositing a force-electricity signal conversion layer on the dielectric layer, and etching the force-electricity signal conversion layer to retain only the force-electricity signal conversion layer in the junction temperature detection area; (7) Metal holes are etched in the cell area and the junction temperature detection area to form metal holes, and then high-concentration boron is injected into the metal holes in the cell area to form a P+ area; finally, a metal layer is deposited in the entire area; (8) A drain metal layer is prepared on the other side of the substrate to obtain the wide bandgap semiconductor power MOS chip.

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