Groove type fast recovery diode and preparation method thereof

Abstract

The invention discloses a groove type fast recovery diode and a preparation method thereof. A groove of the diode comprises a square groove (5) used for improving the current density of the diode and an arc groove (7) formed in the bottom of the square groove (5) and used for improving the reverse withstand voltage of the diode. And oxide layers are formed on the inner side walls of the square grooves (5) and the arc-shaped grooves (7). The oxide layers with certain thicknesses are respectively grown on the inner side walls of the square groove and the arc-shaped groove in the diode, and the oxide layers are used up to bear pressure when the diode is reversed, so that high reverse withstand voltage is ensured, the epitaxial resistivity and thickness of the diode are reduced, and the VF of the diode is reduced. The configuration of the arc-shaped groove provides a space for the growth of the oxide layer, guarantees that the oxide layer is used up for bearing pressure during reversing, and guarantees high reverse withstand voltage.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices, in particular to a trench type fast recovery diode and a preparation method thereof. Background Art

[0002] Fast recovery diode (FRD for short) is a semiconductor diode with good switching characteristics and short reverse recovery time. The internal structure of fast recovery diode is different from that of ordinary PN junction diode. It belongs to PIN junction diode, that is, a base region I is added between P-type silicon material and N-type silicon material to form a PIN silicon wafer. Because the substrate is very thin and the reverse recovery charge is very small, the reverse recovery time of fast recovery diode is short, the forward voltage drop is low, and the reverse breakdown voltage (withstand voltage value) is high.

[0003] Fast recovery diodes (FRDs) are mainly used in electronic circuits such as switching power supplies, PWM pulse width modulators, and frequency converters as high-frequency rectifier diodes, freewheeling diodes, or damping diodes. Fast recovery diodes (FRDs) are used in anti-parallel with controllable switching devices such as IGBTs that serve as main switching devices to provide protection (when the main switching device is turned off, the current on the inductive load continues to be maintained to prevent voltage spikes caused by a sudden drop in current). Their main purpose is to reduce power consumption, protect the main switch IGBT, and improve reliability.

[0004] In order to meet the working process of the diode, the fast recovery diode is required to have the characteristics of low forward voltage drop, high withstand voltage, small leakage current, shorter reverse recovery time and good softness. The conventional PIN structure diode is composed of a heavily doped anode p+ region, a low doped N-drift region (i.e., base region I), and a heavily doped cathode N+ substrate. When forward conduction occurs, the base region I reduces the transient forward voltage drop and withstands the voltage in the reverse direction. During reverse recovery, the thickness and doping concentration of the base region I will affect trr (trr refers to the reverse recovery time of the fast recovery diode. During the process from forward conduction to reverse blocking, the diode will flow through the current in the reverse direction. The time required for internal carrier recombination is trr. The definition is: the time interval from the current passing through the zero point from forward to reverse, and then from reverse to a specified low value). To achieve high withstand voltage, it is necessary to increase the epitaxial resistivity or increase the epitaxial thickness. However, this will reduce the current density of the chip, increase the forward conduction voltage drop VF, and also increase the reverse recovery time trr, resulting in the above parameters of the fast recovery diode being difficult to compromise, affecting the performance of the fast recovery diode. Summary of the invention

[0005] In view of the above technical problems, the present invention provides a trench fast recovery diode, which can improve the current density, achieve a lower forward conduction voltage drop VF, and a shorter reverse recovery time trr while meeting the high reverse withstand voltage requirement, thereby improving the performance of the fast recovery diode.

[0006] The trench of the trench type fast recovery diode provided by the present invention comprises a square trench for improving the diode current density and an arc trench formed at the bottom of the square trench for improving the reverse withstand voltage of the diode; an oxide layer is formed on the inner side walls of the square trench and the arc trench.

[0007] In some embodiments, the width H of the square groove is smaller than the diameter R of the arc groove.

[0008] In some embodiments, the thickness of the oxide layer on the inner sidewall of the arc-shaped groove is greater than the thickness of the oxide layer on the inner sidewall of the square groove.

[0009] In some embodiments, the arc-shaped grooves have a pitch of 0.5-1.0 um.

[0010] In some embodiments, the diode includes an N+ substrate, an N buffer region, an N-drift region, and a p-type region; a trench is formed in the N-drift region and extends upward to cut off the p-type region; and a junction depth of the p-type region does not exceed the bottom of the square trench.

[0011] The present invention also provides a method for preparing a trench-type fast recovery diode, wherein the diode prepared by the method comprises an N+ substrate, an N buffer region, an N-drift region, a p-type region, and a trench formed in the N-drift region and extending upward to cut off the p-type region; the trench comprises a square trench for increasing the current density of the diode and an arc-shaped trench formed at the bottom of the square trench for increasing the reverse withstand voltage of the diode;

[0012] The method comprises the following steps:

[0013] Step 1: forming an N buffer region on an N+ substrate, and forming an N-drift region on the N buffer region;

[0014] Step 2: Perform maskless P-type ion implantation on the upper surface of the N-drift region to form a P-type region;

[0015] Step 3: Photolithography the p-type region to expose the N-drift region, and then etching the N-drift region to form a square groove;

[0016] Step 4: depositing SiN on the upper surface of the p-type region and the inner sidewall of the square trench and performing strip etching to form a SiN layer;

[0017] Step 5: Wet etching the silicon wafer with KOH to form an arc-shaped groove at the bottom of the square groove;

[0018] Step 6: forming a first oxide layer of a certain thickness on the inner wall of the arc-shaped groove by thermal growth;

[0019] Step 7: Dry etching to remove the SiN layer;

[0020] Step 8: forming a second oxide layer of a certain thickness on the upper surface of the p-type region, the inner sidewall of the square trench and the first oxide layer respectively by thermal growth;

[0021] Step nine: depositing polysilicon poly material to fill the square trench and arc trench;

[0022] Step 10: Etching the deposited polysilicon poly material to make the upper surface of the polysilicon poly material in the square groove flush with the second oxide layer on the upper surface of the p-type region;

[0023] Step 11: Etching away the second oxide layer on the upper surface of the p-type region;

[0024] Step 12: Deposit metal on the surface of the upper surface of the p-type region to form a first metal layer; subsequently perform electron irradiation, thin the back of the N+ substrate, and then perform metallization to form a second metal layer, thereby finally forming the trench fast recovery diode.

[0025] In some embodiments, the P-type ion implantation energy in step 2 is 60-150 KeV, the implantation dose is 2E13-5E15, and a high-temperature junction is performed to form a p-type region with a junction depth of about 3-4 um.

[0026] In some embodiments, the square grooves have a groove depth of 5.0 to 6.0 um, a groove spacing L of 1.0 to 2.0 um, and a groove width H of 2.0 to 4.0 um.

[0027] In some embodiments, the relationship between the diameter R of the arc-shaped groove and the width H of the square groove is:

[0028] R=H+(0.5~1.0)um.

[0032] In some embodiments, the thicknesses of the first oxide layer and the second oxide layer are

[0033] The beneficial effects of the present invention include at least: an oxide layer of a certain thickness is grown on the inner walls of the square groove and the arc groove in the diode, and when the diode is reversed, the oxide layer is exhausted and pressure-bearing, which ensures high reverse withstand voltage while reducing the resistivity and thickness of the diode epitaxy and reducing the VF of the diode.

[0034] The configuration of the arc-shaped groove provides space for the growth of the oxide layer, ensuring that the oxide layer is depleted and withstands pressure in the reverse direction, ensuring high reverse withstand voltage. Based on this, the thickness of the oxide layer in the square groove is reduced, the chip's flow area is increased, the current density of the diode is increased, and a lower on-state voltage drop VF and a smaller reverse recovery time trr are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings herein are incorporated into and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0036] Figure 1 A schematic cross-sectional structure diagram of a square trench diode described in the present invention;

[0037] Figure 2 A schematic diagram of the cross-sectional structure of a diode provided by the present invention;

[0038] Figure 3-Figure 13 This is a process diagram of the preparation method provided by the present invention. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0041] Existing FRDs usually use low anode injection efficiency or CIBH structures to improve reverse recovery characteristics, but this has little effect on the contradiction between reverse withstand voltage and on-state voltage drop. To solve this technical problem, FRDs use square trench structures (such as Figure 1 As shown in the figure, an oxide layer of a certain thickness is grown inside the groove. When the oxide layer is exhausted in the reverse direction, it can reduce the resistivity and thickness of the epitaxy while ensuring high withstand voltage, thereby reducing VF. However, with the presence of the groove and the need to ensure high withstand voltage, the flow area of ​​the chip is reduced (the flow area is the area of ​​the p-type region 4. With the presence of the square groove, the p-type region 4 will be cut off, so the flow area will be reduced), sacrificing VF to a certain extent.

[0042] Compared with the conventional PIN structure, the square trench FRD introduces the charge coupling effect brought by the oxide layer in the trench, and adds horizontal depletion on the basis of the original vertical depletion, which greatly improves the device's withstand voltage. The formula for the trench spacing and the thickness of the oxide layer in the trench is as follows:

[0043]

[0044] ε o : Vacuum dielectric constant

[0045] ε si : Relative dielectric constant of Si

[0046] E y : Average vertical electric field

[0047] W Mesa : Mesa zone width

[0048] ε ox : Relative dielectric constant of the oxide layer

[0049] BV: target voltage

[0050] Ttox is the thickness of the oxide layer in the trench; Mesa area width refers to the spacing between the trenches.

[0051] From the above formula, it can be obtained that under the premise of achieving the same pressure-bearing capacity, the trench spacing is inversely proportional to the oxide layer thickness. Therefore, to achieve a higher voltage resistance, a thicker oxide layer is required, which will make the trench spacing smaller. However, a reduction in the trench spacing will lead to a decrease in the device current density, sacrificing VF to a certain extent.

[0052] Please refer to Figure 2 The groove of the trench-type fast recovery diode provided by the present invention includes a square groove 5 for improving the current density of the diode and an arc-shaped groove 7 formed at the bottom of the square groove 5 for improving the reverse withstand voltage of the diode. Compared with the fast recovery diode with a square groove structure, the present invention forms an arc-shaped groove at the bottom of the square groove, so that the oxide layer in the arc-shaped groove bears the main responsibility of depletion pressure, and the oxide layer in the square groove bears the secondary responsibility of depletion pressure, so that the thickness of the oxide layer in the square groove can be reduced, the spacing between the square grooves is increased, the flow area is increased, and the current density is improved; and the oxide layers in the square groove and the arc-shaped groove jointly bear the depletion pressure, which meets the high reverse withstand voltage while providing space for reducing the epitaxial resistivity or epitaxial thickness, and can achieve a lower on-state voltage drop VF and reverse recovery time trr; on the other hand, the chip area can be reduced and the cost can be saved.

[0053] The outer side of the square groove of the diode has an overcurrent, which increases the current density, and the oxide layer in the arc groove is mainly depleted to bear the pressure and improve the withstand voltage.

[0054] The diode is prepared by the following method:

[0055] Step 1: N+ substrate 1 and N buffer region 2 are formed on N+ substrate 1, and N-drift region 3 is formed on N buffer region 2. The structure is as follows: Figure 3 As shown;

[0056] Step 2: Perform maskless P-type ion implantation on the upper surface of the N-drift region 3, with an implantation energy of 60-150 KeV and an implantation dose of 2F13-5F15, and perform high-temperature junction pushing to form a p-type region 4 with a junction depth of about 3-4um. The structure is as follows: Figure 4 As shown;

[0057] Step 3: Use a mask to perform photolithography, then etch the silicon wafer, and etch at the specified position to form a square groove 5, the groove depth is 5.0-6.0um, the groove spacing L is about 1.0-2.0um, the groove width H is about 2.0-4.0um, and the structure is as follows Figure 5 As shown;

[0058] Step 4: Deposit SiN and perform strip etching to form a SiN layer 6, the structure of which is as follows: Figure 6 As shown;

[0059] Step 5: Use KOH wet etching to etch the silicon wafer to form an arc-shaped groove 7 at the bottom of the square groove 5. The diameter R of the arc-shaped groove 7 is 0.5-1.0um wider than the square groove 5. (

[0061] R=

[0062] H+

[0063] (0.5~1.0)um

[0064] ), the arc groove spacing L1 is 0.5-1.0um, the structure is as follows Figure 7 As shown in the figure, the arc-shaped groove is wider than the square groove, so there is more space for the oxide layer to grow in the groove to bear the pressure, and the spacing between the arc-shaped grooves also needs to ensure the flow;

[0065] Step 6: Form a first oxide layer 8 of a certain thickness on the inner wall of the arc-shaped groove 7 by thermal growth. The thickness is generally selected to be Structure Figure 8 As shown;

[0066] Step 7: Dry etching to remove the SiN layer 6, the structure is as follows Fig. 9 As shown;

[0067] Step 8: Form a second oxide layer 9 of a certain thickness on the upper surface of the p-type region 4, the inner sidewall of the square trench 5 and the first oxide layer 8 by thermal growth. The thickness is generally selected to be Structure Fig.10 As shown;

[0068] Step 9: Deposit polysilicon poly material 10 to fill the square groove 5 and the arc groove 7. The structure is as follows: Fig.11 As shown;

[0069] Step 10: Etch the deposited polysilicon poly material 10 so that the upper surface of the polysilicon poly material 10 in the square groove 5 is flush with the second oxide layer 9 on the upper surface of the p-type region 4. Fig.12 As shown;

[0070] Step 11: Etch away the second oxide layer 9 on the upper surface of the p-type region 4. The structure is as follows: Fig.13 As shown;

[0071] Step 12: metal deposition is performed on the surface where the upper surface of the p-type region 4 is located to form a first metal layer 11; subsequently, electron irradiation is performed, and the back of the N+ substrate 1 is thinned and metallized to form a second metal layer 12, and finally the trench type fast recovery diode is formed, such as Figure 2 shown.

[0072] The diode provided by the present invention uses wet etching to etch an arc groove at the bottom of the square groove, and thermally grows an oxide layer inside the groove. The thickness of the oxide layer in the arc groove (the first oxide layer thickness plus the second oxide layer thickness) is greater than the thickness of the oxide layer in the square groove (the first oxide layer thickness). While adding a lateral electric field, the current density is increased.

[0073] The fast recovery diode introduces an arc-shaped groove, and the oxide layer at the bottom of the arc-shaped groove is thicker, which can reduce reverse leakage on the one hand, and improve device reliability on the other hand.

[0074] The square trench of this fast recovery diode is filled with poly, and the sidewalls of the trench are uniformly covered with an oxide layer for pressure bearing (charge coupling pressure bearing). Whether the square trench has an oxide layer will affect the hole concentration distribution; if the sidewalls of the square trench do not have an oxide layer, the holes in the p-type silicon will participate in the depletion process of the pn junction during the reverse recovery process, thereby affecting the reverse recovery current peak.

[0075] During the reverse recovery process of the diode, the concentration of the p-type region determines the concentration of holes. When a reverse voltage is applied, the higher the concentration of the p-type region, the higher the reverse current peak. In addition, it can be concluded from formula (1) that different trench spacings will also affect the withstand voltage of the oxide layer; the larger the trench spacing, the smaller the withstand voltage. The definition of the trench in this fast recovery diode can achieve high withstand voltage and lower reverse current peak.

[0076] The fast recovery diode is an improvement on the PIN structure. Compared with the PIN structure, the MPS structure introduces a Schottky barrier. Since the Schottky barrier is lower than the PN junction barrier, the MPS structure will have a larger leakage current when a reverse voltage is applied.

[0077] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present invention, which should be included in the scope of the claims of the present invention. The techniques, shapes, and structural parts not described in detail in the present invention are all known technologies.

Claims

1. A trench fast recovery diode, characterized in that: The groove of the diode comprises a square groove (5) for improving the current density of the diode and an arc groove (7) formed at the bottom of the square groove (5) for improving the reverse withstand voltage of the diode; an oxide layer is formed on the inner side walls of the square groove (5) and the arc groove (7).

2. The trench fast recovery diode according to claim 1, characterized in that: The width H of the square groove (5) is smaller than the diameter R of the arc groove (7).

3. The trench fast recovery diode according to claim 1, characterized in that: The thickness of the oxide layer on the inner side wall of the arc-shaped groove (7) is greater than the thickness of the oxide layer on the inner side wall of the square groove (5).

4. The trench fast recovery diode according to claim 1, characterized in that: The pitch of the arc-shaped grooves (7) is 0.5-1.0 um.

5. The trench fast recovery diode according to claim 1, characterized in that: The diode comprises an N+ substrate (1), an N buffer zone (2), an N-drift zone (3), and a p-type zone (4); a trench is formed in the N-drift zone (3) and extends upward to cut off the p-type zone (4); and the junction depth of the p-type zone (4) does not exceed the bottom of the square trench (5).

6. A method for preparing a trench type fast recovery diode, characterized in that: The diode prepared by the method comprises an N+ substrate (1), an N buffer zone (2), an N-drift zone (3), a p-type zone (4), and a groove formed in the N-drift zone (3) and extending upward to cut off the p-type zone (4); the groove comprises a square groove (5) for improving the current density of the diode and an arc groove (7) formed at the bottom of the square groove (5) for improving the reverse withstand voltage of the diode; The method comprises the following steps: Step 1: forming an N buffer region (2) on an N+ substrate (1), and forming an N-drift region (3) on the N buffer region (2); Step 2: Performing maskless P-type ion implantation on the upper surface of the N-drift region (3) to form a p-type region (4); Step 3: performing photolithography on the p-type region (4) to expose the N-drift region (3), and then etching the N-drift region (3) to form a square groove (5); Step 4: depositing SiN on the upper surface of the p-type region (4) and the inner sidewall of the square groove (5) and performing strip etching to form a SiN layer (6); Step 5: using KOH wet etching to etch the silicon wafer, forming an arc-shaped groove (7) at the bottom of the square groove (5); Step 6: forming a first oxide layer (8) of a certain thickness on the inner wall of the arc-shaped groove (7) by thermal growth; Step 7: Dry etching to remove the SiN layer (6); Step 8: forming a second oxide layer (9) of a certain thickness on the upper surface of the p-type region (4), the inner side wall of the square groove (5) and the first oxide layer (8) respectively by thermal growth; Step nine: depositing polysilicon poly material (10) to fill the square groove (5) and the arc groove (7); Step 10: etching the deposited polysilicon poly material (10) so that the upper surface of the polysilicon poly material (10) in the square groove (5) is flush with the second oxide layer (9) on the upper surface of the p-type region (4); Step 11: etching away the second oxide layer (9) on the upper surface of the p-type region (4); Step 12: metal deposition is performed on the surface where the upper surface of the p-type region (4) is located to form a first metal layer (11); subsequently, electron irradiation is performed, and the back side of the N+ substrate (1) is thinned and metallized to form a second metal layer (12), thereby finally forming the trench type fast recovery diode.

7. The preparation method according to claim 6, characterized in that: In the second step, the P-type ion implantation energy is 60-150 KeV, the implantation dose is 2E13-5E15, and a high temperature junction is performed to form a p-type region (4), with a junction depth of about 3-4 um.

8. The preparation method according to claim 6, characterized in that: The groove depth of the square groove (5) is 5.0-6.0 um, the groove spacing L is 1.0-2.0 um, and the groove width H is 2.0-4.0 um.

9. The preparation method according to claim 6, characterized in that: The relationship between the diameter R of the arc-shaped groove (7) and the width H of the square groove (5) is: R=H+(0.5~1.0)um.

10. The preparation method according to claim 6, characterized in that: The thicknesses of the first oxide layer (8) and the second oxide layer (9) are respectively

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