Semiconductor device and forming method thereof, chip and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device, a forming method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and is used for improving the reliability of the semiconductor device. The semiconductor device includes an insulating layer, and a first crystalline silicon strip formed on the insulating layer, the first crystalline silicon strip extending in a first direction parallel to the insulating layer, and an induced metal content in the first crystalline silicon strip being less than 1 e17 cm-3.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same, a chip, and an electronic device. Background Art

[0002] Generally, crystalline silicon has high field effect mobility and is therefore widely used in semiconductor devices. Semiconductor devices formed using crystalline silicon are also widely used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. However, the reliability of semiconductor devices formed using crystalline silicon is reduced. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor device and a method for forming the same, a chip, and an electronic device, for further improving the reliability of the semiconductor device.

[0004] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] In a first aspect, a semiconductor device is provided, the semiconductor device comprising: an insulating layer, and a first crystalline silicon strip formed on the insulating layer, the first crystalline silicon strip extending along a first direction parallel to the insulating layer, and the induced metal content in the first crystalline silicon strip is less than 1e17 cm -3 .

[0006] The semiconductor device provided in this embodiment includes an insulating layer and a first crystalline silicon strip formed on the insulating layer. Since the first crystalline silicon strip is obtained by epitaxial growth of the second crystalline silicon strip, the first crystalline silicon strip replicates the crystal orientation of the crystalline silicon in the second crystalline silicon strip, which can ensure that the first crystalline silicon strip has a high crystal quality, so that the semiconductor device has better performance. At the same time, since the residual induced metal in the second crystalline silicon strip has a weak diffusion ability during the epitaxial growth process, the induced metal content in the first crystalline silicon strip is less than 1e17 cm -3 , improving the reliability of semiconductor devices.

[0007] In a possible implementation, the crystalline silicon in the first crystalline silicon strip is single crystal silicon.

[0008] In this embodiment, since the first crystalline silicon strip is obtained by epitaxy, the crystalline silicon in the first crystalline silicon strip is single crystal silicon, thereby improving the stability and reliability of the semiconductor device.

[0009] In a possible implementation manner, the length of the first crystalline silicon strip is greater than or equal to 1 μm.

[0010] In a possible implementation, the crystalline silicon in the first crystalline silicon strip has multiple crystal orientations.

[0011] In this embodiment, since the crystal orientations of the crystalline silicon in the first crystalline silicon strip are multiple, it is possible to ensure that the first crystalline silicon strip has a higher crystal quality, so that the semiconductor device has better performance.

[0012] In one possible implementation, the semiconductor device also includes: a source structure and a drain structure, the source structure and the drain structure are respectively arranged at two ends of the first crystalline silicon strip; a channel, the channel is arranged between the source structure and the drain structure; and a gate structure, the gate structure spans the first crystalline silicon strip, and the source structure, the drain structure and the gate structure are electrically isolated.

[0013] In a possible implementation, the semiconductor device further includes: a source electrode disposed on the source structure, a drain electrode disposed on the drain structure, and a gate electrode disposed on the gate structure. The source electrode, the drain electrode, and the gate electrode may be connected to other electronic devices.

[0014] In a second aspect, a method for forming a semiconductor device is provided, which includes: forming an insulating layer; forming a second crystalline silicon strip on the insulating layer, wherein the second crystalline silicon strip extends in a first direction parallel to the insulating layer; forming an epitaxial silicon layer covering the second crystalline silicon strip; removing part of the epitaxial silicon layer and the second crystalline silicon strip, and forming the remaining epitaxial silicon layer into a first crystalline silicon strip, wherein the projection of the removed epitaxial silicon layer on the insulating layer covers the projection of the second crystalline silicon strip on the insulating layer.

[0015] In one possible embodiment, a portion of the epitaxial silicon layer and the second crystalline silicon strip is removed, and the remaining epitaxial silicon layer forms a first crystalline silicon strip, including: forming a photoresist layer covering the epitaxial silicon layer; forming a window on the photoresist layer, the projection of the window on the insulating layer covers the projection of the second crystalline silicon strip on the insulating layer, and the projection of the epitaxial silicon layer on the insulating layer covers the projection of the window on the insulating layer; removing a portion of the epitaxial silicon layer and the second crystalline silicon strip using the photoresist layer as a mask; and removing the photoresist layer.

[0016] In a possible embodiment, the method further includes: forming a planarization layer covering the first crystalline silicon strip; planarizing the planarization layer and the side of the first crystalline silicon strip away from the insulating layer to expose the first crystalline silicon strip; and removing the planarization layer to form a first crystalline silicon strip with a flat top.

[0017] In a possible embodiment, the method also includes: depositing a gate material on the first crystalline silicon strip to form a gate structure spanning the first crystalline silicon strip; injecting an impurity ion doped material into the first crystalline silicon strip to form a source structure and a drain structure at both ends of the first crystalline silicon strip, and forming a channel between the source structure and the drain structure.

[0018] In one possible embodiment, forming a second crystalline silicon strip on the insulating layer includes: forming an amorphous silicon layer on the insulating layer; removing a portion of the amorphous silicon layer to form an amorphous silicon strip, wherein the amorphous silicon strip extends along a first direction of the insulating layer; and inducing metal to crystallize the amorphous silicon material in the amorphous silicon strip into crystalline silicon to form a second crystalline silicon strip.

[0019] In a possible implementation, the method further includes: depositing conductive materials on the source structure, the drain structure and the gate structure respectively to form a source electrode on the source structure, a drain electrode on the drain structure and a gate electrode on the gate structure respectively. The formed source electrode, drain electrode and gate electrode can be connected to other semiconductor devices or electronic devices.

[0020] In a third aspect, a chip is provided, comprising: a first semiconductor device and a second semiconductor device which are stacked, an isolation layer being provided between the first semiconductor device and the second semiconductor device, and the second semiconductor device being the semiconductor device provided in the first aspect.

[0021] In a fourth aspect, an electronic device is provided, comprising a printed circuit board and a semiconductor device formed by the forming method provided in the first aspect; the semiconductor device is electrically connected to the printed circuit board.

[0022] In a fifth aspect, an electronic device is provided, which includes a printed circuit board and the chip provided in the third aspect; the chip is electrically connected to the printed circuit board.

[0023] Among them, the technical effects brought about by any possible implementation method of the second to fifth aspects can refer to the technical effects brought about by different implementation methods of the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of the induced metal residue in the semiconductor device provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of the structure of a semiconductor device provided in another embodiment of the present application;

[0028] Figure 4 A schematic cross-sectional view of a seed layer provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of a semiconductor device provided in another embodiment of the present application;

[0030] Figure 6 A schematic flow chart of a method for forming a semiconductor device provided in an embodiment of the present application;

[0031] Figure 7-Figure 19 A schematic diagram of the structure of each stage in the process of forming a semiconductor device provided in an embodiment of the present application;

[0032] Fig. 20 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0033] Fig.21 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0034] Fig. 22 A schematic diagram of the structure of an electronic device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0036] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0037] Additionally, for ease of description, spatially relative terms such as "bottom," "below," "below," "above," "above," etc. may be used herein to describe the relationship of one component or feature to another component, or function as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0038] Typically, in order to improve the response speed of a semiconductor device, a crystalline silicon strip having a high field effect mobility may be provided in the semiconductor device. In some optional embodiments, the amorphous silicon material in the amorphous silicon layer is crystallized into crystalline silicon using solid phase crystallization (SPC) technology or excimer laser annealing (ELA) technology. Using the solid phase crystallization (SPC) technology, the amorphous silicon layer needs to be annealed for several hours to several tens of hours at a temperature not higher than about 700°C, and therefore has a higher thermal budget.

[0039] In order to reduce the thermal budget, the present application embodiment provides a semiconductor device. Figure 1 In (i), the semiconductor device includes an insulating layer 110, and a second crystalline silicon strip 120, a gate dielectric layer 151, and a gate electrode layer 152 sequentially formed on the insulating layer 110. The second crystalline silicon strip 120 extends along a first direction of the insulating layer 110, the gate dielectric layer 151 covers the second crystalline silicon strip 120, and an opening is provided in the gate dielectric layer 151, and the projection of the opening on the insulating layer is covered by the projection of the second crystalline silicon strip 120 on the insulating layer, that is, a partial area L1 in the second crystalline silicon strip 120 is exposed by the opening.

[0040] In some specific embodiments, the process of forming the semiconductor device is as follows: forming an insulating layer 110, forming an amorphous silicon layer on the insulating layer 110, removing a portion of the amorphous silicon layer to form an amorphous silicon strip 121, wherein the amorphous silicon strip 121 extends in a first direction parallel to the insulating layer 110. Then forming a gate dielectric layer 151 on the amorphous silicon strip 121, and forming a gate electrode layer 152 on the gate dielectric layer 151. The projection of the gate electrode layer 152 on the insulating layer 110 is covered by the projection of the gate dielectric layer 151 on the insulating layer 110. Then forming an opening in the gate dielectric layer 151, wherein the opening exposes a portion of the amorphous silicon strip 121. Then depositing an inductive metal on the gate dielectric layer 151 to form an inductive metal layer 105, that is, the inductive metal contacts the amorphous silicon strip exposed by the opening, or the inductive metal is injected into the amorphous silicon strip through the opening. At this time, the semiconductor device is as follows: Figure 1 As shown in (ii), the amorphous silicon material in the amorphous silicon strip 121 is then crystallized into crystalline silicon by metal induced crystallization (MIC) technology or metal induced lateral crystallization (MILC) technology to form a second crystalline silicon strip 120. Finally, the induced metal layer 105 is removed.

[0041] In this embodiment, the inducing metal is brought into contact with the amorphous silicon strip 121 through the opening or the inducing metal is injected into the amorphous silicon strip 121, and the inducing metal causes the amorphous silicon material in the amorphous silicon strip 121 to crystallize, thereby forming crystalline silicon. The amorphous silicon material can be controlled to form crystalline silicon at a specified position by the metal induced crystallization technology (MIC) or the metal induced lateral crystallization (MILC) technology, and the size of the crystal nucleus of the single crystal silicon can be controlled, so that the crystalline silicon can have a higher electron and hole mobility. However, the metal induced crystallization technology (MIC) or the metal induced lateral crystallization (MILC) technology will inevitably cause more inducing metal residues to exist in the crystalline silicon. Figure 2 FIG. 1 is a schematic diagram showing the residual amount of induced metal Ni in the second crystalline silicon strip 120 of the semiconductor device. Figure 2 It can be seen that there is a lot of induced metal Ni residue in the second crystalline silicon strip 120, especially in the area L1 of the second crystalline silicon strip exposed by the opening, where the maximum residual amount of induced metal Ni is -0.4at%, and the minimum residual amount is -0.02at%, that is, the residual amount of induced metal Ni is greater than 1e18 cm -3 , which does not meet the requirement that the induced metal residue should be less than 1e17 cm -3 Moreover, too much induced metal residue will increase the possibility of leakage of semiconductor devices and reduce the reliability of semiconductor devices.

[0042] In order to reduce the induced metal content in the second crystalline silicon strip of the semiconductor device, the embodiment of the present application also provides a semiconductor device. Figure 3 ,in Figure 3 (a) is a cross-sectional view of the semiconductor device along the extension direction of the second crystalline silicon strip, Figure 3 (B) is a cross-sectional view of the semiconductor device along a direction perpendicular to the extension direction of the second crystalline silicon strip, and the semiconductor device includes a substrate 101, an insulating layer 110 and a dielectric layer 102 sequentially arranged on the substrate 101, and a second crystalline silicon strip 120 extending from the insulating layer 110.

[0043] In some specific embodiments, the process of forming the semiconductor device is: forming a substrate 101, an insulating layer 110 and a dielectric layer 102 in sequence. A through hole is formed in the dielectric layer 102 to penetrate the dielectric layer 102, and a cooling hole is formed on the side of the insulating layer 110 away from the substrate, and the cooling hole in the insulating layer 110 is opposite to the through hole in the dielectric layer 102. Then, an amorphous silicon material (a-Si) is deposited in the cooling hole in the insulating layer 110 to form a seed layer 115. An ultrashort laser pulse is used to locally heat the area in the dielectric layer 102 where the through hole is provided, so as to induce the metal ions in the seed layer 115 in the cooling hole to extend through the through hole in the dielectric layer to the dielectric layer 102. And refer to Figure 4 After being heated by an ultrashort laser pulse, the amorphous silicon material (a-Si) in the seed layer 115 crystallizes into crystalline silicon (Si), thereby forming a second crystalline silicon strip 120 extending from the insulating layer 110 .

[0044] In this embodiment, the amorphous silicon material disposed in the insulating layer 110 is irradiated with ultrashort laser pulses, thereby inducing the amorphous silicon material to crystallize and extend from the through hole in the dielectric layer 102 to form the second crystalline silicon strip 120, so that the amorphous silicon material can be crystallized with a lower thermal budget, and the crystallization effect is good, and there is no impurity in the second crystalline silicon strip. However, the equipment for generating ultrashort laser pulses is expensive, has high requirements on the thickness of the amorphous silicon material, increases the manufacturing cost of the semiconductor device, and increases the complexity of the manufacturing process.

[0045] In order to solve the above problems, the present application also provides a semiconductor device. Figure 5 ,in, Figure 5 The (1) is Figure 5 The semiconductor device comprises an insulating layer 110 and a first crystalline silicon strip 130 formed on the insulating layer 110, wherein the first crystalline silicon strip 130 extends along a first direction parallel to the insulating layer 110, and the induced metal content in the first crystalline silicon strip is less than 1e17 cm -3 .

[0046] In a specific embodiment, forming the semiconductor device includes: first forming an insulating layer 110, and forming a second crystalline silicon strip 120 on the insulating layer 110, wherein the second crystalline silicon strip 120 extends in a first direction parallel to the insulating layer 110. Next, forming an epitaxial silicon layer covering the second crystalline silicon strip 120, wherein the crystal orientation of the crystalline silicon in the epitaxial silicon layer is the same as the crystal orientation of the crystalline silicon in the second crystalline silicon strip 120. Finally, removing part of the epitaxial silicon layer and the second crystalline silicon strip 120, and the remaining epitaxial silicon layer forms a first crystalline silicon strip 130, wherein the projection of the removed epitaxial silicon layer on the insulating layer 110 covers the projection of the second crystalline silicon strip 120 on the insulating layer 110.

[0047] The semiconductor device provided in this embodiment includes an insulating layer 110 and a first crystalline silicon strip 130 formed on the insulating layer 110. Since the first crystalline silicon strip 130 is obtained by epitaxial growth of the second crystalline silicon strip 120, the first crystalline silicon strip 130 replicates the crystal orientation of the crystalline silicon in the second crystalline silicon strip 120, which can ensure that the first crystalline silicon strip 130 has a high crystal quality, so that the semiconductor device has better performance. At the same time, since the impurities in the second crystalline silicon strip, such as the induced metal introduced during the formation of the second crystalline silicon strip, have a weak diffusion ability during the epitaxial growth process, the induced metal content in the first crystalline silicon strip is less than 1e17 cm -3 , reducing the risk of short circuit in semiconductor devices and improving the reliability of semiconductor devices.

[0048] It should be noted that the number of the first crystalline silicon strips 130 can be adjusted according to practical applications, and is not limited to forming only one first crystalline silicon strip 130 on the insulating layer 110. In some other optional embodiments, the first crystalline silicon strip 130 may also have a width that gradually increases from the top to the bottom.

[0049] In an optional embodiment, Figure 6 Taking the process of forming the semiconductor device shown as an example, various parts of the above-mentioned semiconductor device are described in detail.

[0050] S10: forming a substrate 101.

[0051] In this embodiment, if Figure 7 As shown, the semiconductor device includes a substrate 101. The substrate 101 may be made of a metal or semiconductor material. Optionally, the substrate 101 is a bulk silicon material layer. The substrate 101 includes an elemental semiconductor, such as silicon or germanium in a crystal structure; a compound semiconductor, such as germanium silicon, silicon carbon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, or a combination thereof. Optionally, the substrate 101 is a metal material layer.

[0052] S20 : ​​forming an insulating layer 110 on the substrate 101 .

[0053] like Figure 8As shown, the insulating layer 110 is formed by a deposition process, such as a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, a sputtering process, or other applicable processes. In some embodiments, the insulating layer 110 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), or other insulating materials. In a specific example, the insulating layer 110 is made of silicon oxide.

[0054] S30: forming a second crystalline silicon strip 120 on the insulating layer 110, wherein the second crystalline silicon strip 120 extends along a first direction parallel to the insulating layer 110. This step further includes:

[0055] S31 : forming an amorphous silicon layer on the insulating layer 110 .

[0056] An amorphous silicon material is deposited on the insulating layer 110 to form an amorphous silicon layer by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0057] S32 : patterning the amorphous silicon layer through a patterning process to form an amorphous silicon strip 121 , wherein the amorphous silicon strip 121 extends along a first direction parallel to the insulating layer 110 .

[0058] like Fig. 9As shown, the amorphous silicon layer is patterned by a patterning process, thereby forming an amorphous silicon strip 121 on the insulating layer 110. Among them, the patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. The dry etching process includes using an etching gas such as carbon tetrafluoride (CF4), argon (Ar), nitrogen trifluoride (NF3), chlorine (Cl2), helium (He), hydrogen bromide (HBr), oxygen (O2), nitrogen (N2), fluoromethane (CH3F), methane (CH4), difluoromethane (CH2F2) or a combination thereof.

[0059] S33 : crystallizing the amorphous silicon material in the amorphous silicon strip 121 into crystalline silicon by inducing metal to form a second crystalline silicon strip 120 .

[0060] In this embodiment, if Fig.10 As shown, the semiconductor device includes a substrate 101, an insulating layer 110 and a second crystalline silicon strip 120 formed on the substrate 101. In order to form the second crystalline silicon strip 120, it is necessary to crystallize the amorphous silicon material in the amorphous silicon strip 121. Exemplarily, the amorphous silicon strip 121 can be brought into contact with an inducing metal, or the inducing metal can be injected into the amorphous silicon strip 121 to crystallize the amorphous silicon material. The inducing metal can be at least one of nickel (Ni), palladium (Pd), titanium (Ti), silver (Ag), gold (Au), aluminum (Al), tin (Sn), antimony (Sb), copper (Cu), cobalt (Co), molybdenum (Mo), ruthenium (Ru), cadmium (Cd), platinum (Pt), etc., or any combination thereof. Exemplarily, nickel (Ni) is deposited at one end of the amorphous silicon strip 121, and then the diffusion of NiSi2 in the amorphous silicon strip is controlled by low-temperature metal induced lateral crystallization (MILC) technology in the amorphous silicon material, so that the amorphous silicon material is combined with the induced metal to form a metal silicide, and the metal silicide forms a crystallization nucleus, thereby crystallizing the amorphous silicon material into crystalline silicon at a relatively low temperature to form the second crystalline silicon strip 120. Considering that under natural conditions (including an environment of oxygen and water), the silicon atoms in the second crystalline silicon strip 120 are easily oxidized, such as Fig.11 As shown, an oxide layer 122 is formed on the surface of the second crystalline silicon strip 120 exposed to the air. The oxide layer 122 is also called a natural oxide layer. Therefore, in an optional embodiment, the process of forming the semiconductor device may further include:

[0061] S34: cleaning the surface of the second crystalline silicon strip 120 .

[0062] In this embodiment, in order to prevent the oxide layer 122 formed on the surface of the second crystalline silicon strip 120 from affecting the electrical parameters of the subsequent semiconductor device, it is necessary to clean the surface of the second crystalline silicon strip 120, for example, placing the semiconductor device with the second crystalline silicon strip 120 into a groove containing a cleaning agent, and the cleaning agent can be a hydrofluoric acid (HF) agent, or other acidic agents containing hydrofluoric acid (HF). At the same time, ultrasonic vibration can be accompanied during the cleaning process to enhance the strength of the cleaning agent in removing the oxide layer 122 on the surface of the second crystalline silicon strip 120, so that the particles of the oxide layer 122 are more easily detached from the surface of the second crystalline silicon strip 120.

[0063] After forming the second crystalline silicon strip 120, in order to remove the residual inductive metal, the second crystalline silicon strip 120 is subjected to a gettering process. The conventional gettering process uses impurities such as phosphorus or inert gas to treat the inductive metal. However, there is still a lot of inductive metal residue in the second crystalline silicon strip 120 after the gettering process. These residues still increase the risk of leakage of the semiconductor device and reduce the reliability of the semiconductor device. In addition, cross contamination is easily caused in the subsequent formation process, which is not conducive to the application of the semiconductor device.

[0064] S40 : forming an epitaxial silicon layer 131 covering the second crystalline silicon strip 120 .

[0065] In this embodiment, compared with the above-mentioned embodiment in which an amorphous silicon material disposed in an insulating layer is irradiated with an ultrashort laser pulse to induce crystallization of the amorphous silicon material to form a second crystalline silicon strip, the length of the epitaxial silicon layer in this embodiment is not limited. After the length of the second crystalline silicon strip formed by ultrashort laser pulse irradiation exceeds a first threshold value, for example, the first threshold value is 1 μm, the crystalline silicon in the second crystalline silicon strip is polycrystalline silicon, thus reducing the performance of the semiconductor device. Fig.12As shown, in this embodiment, an epitaxial silicon layer 131 can be generated on the surface exposed by the second crystalline silicon strip 120 by epitaxial growth technology, that is, the epitaxial silicon layer covers the sidewall and upper surface of the second crystalline silicon strip 120, and the epitaxial silicon layer has an inverted U-shaped cross section. It can be understood that the upper surface of the second crystalline silicon strip 120 here refers to the surface of the second crystalline silicon strip 120 away from the insulating layer 110. Exemplarily, the length of the epitaxial silicon is greater than or equal to 1μm. The epitaxial growth technology can be liquid phase epitaxy (liquid phase epitaxy, LEP) technology, molecular beam epitaxy (molecular beam epitaxy, MBE) technology, chemical molecular beam epitaxy (chemical beam epitaxy, CBE) technology, metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD) technology or plasma epitaxy technology. Since the induced metal has a weak diffusion ability during the epitaxial growth process, the induced metal content in the epitaxial silicon layer 131 is extremely low, which reduces the risk of short circuit of the semiconductor device and improves the reliability of the semiconductor device. At the same time, the epitaxial silicon layer 131 replicates the crystal orientation of the crystalline silicon in the second crystalline silicon strip 120 and has a higher crystal quality, so that the semiconductor device has better performance.

[0066] S50: removing part of the epitaxial silicon layer 131 and the second crystalline silicon strip 120, and the remaining epitaxial silicon layer forms the first crystalline silicon strip 130. This step further includes:

[0067] S51: forming a photoresist layer 140 covering the epitaxial silicon layer. For example, the photoresist layer 140 covering the epitaxial silicon layer is formed by spin coating.

[0068] S52 : forming a window 141 on the photoresist layer 140 , wherein the projection of the window 141 on the insulating layer 110 covers the projection of the second crystalline silicon strip 120 on the insulating layer 110 , and the projection of the epitaxial silicon layer on the insulating layer 110 covers the projection of the window on the insulating layer 110 .

[0069] In this embodiment, if Fig.13 As shown, the photoresist layer is patterned by a patterning process to form a window 141 on the photoresist layer. The photoresist layer 140 after the window 141 is formed covers the sidewall of the epitaxial silicon layer, and the window 141 on the photoresist layer exposes part of the epitaxial silicon layer 131, and the projection of the exposed epitaxial silicon layer 131 on the insulating layer 110 covers the projection of the second crystalline silicon strip 120 on the insulating layer 110. Among them, the patterning process includes a photolithography process and an etching process. The photolithography process includes soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing and drying (for example, hard baking). The etching process includes a dry etching process or a wet etching process.

[0070] S53: Using the photoresist layer 140 as a mask, a portion of the epitaxial silicon layer 131 and the second crystalline silicon strip 120 is removed.

[0071] like Fig.14 As shown, the epitaxial silicon layer 131 exposed by the window of the photoresist and the second crystalline silicon strip 120 located under the exposed epitaxial silicon layer 131 are removed by a dry etching process or a wet etching process using a photoresist layer 140 as a mask. The epitaxial silicon layer 131 that is not removed constitutes a first crystalline silicon strip 130. The first crystalline silicon strip 130 has an I-shaped cross section. In some optional embodiments, the length of the first crystalline silicon strip 130 is greater than or equal to 1 μm. In some embodiments, a portion of the epitaxial silicon layer and the second crystalline silicon strip 120 are removed by a dry etching process. The dry etching process includes using a fluorine-based etchant gas, such as sulfur hexafluoride (SF6), fluorocarbon (C x F y ), nitrogen trifluoride (NF3), or a combination thereof.

[0072] In some optional embodiments, the crystalline silicon in the formed first crystalline silicon strip is single crystal silicon.

[0073] In this embodiment, since the first crystalline silicon strip is obtained by epitaxy of the second crystalline silicon strip, the crystalline silicon in the first crystalline silicon strip is single crystal silicon, and single crystal silicon has good electronic properties, high thermal stability, low noise, high thermal stability, and high thermoelectric conversion efficiency. It can also resist electromagnetic interference, thermal shock, and corrosion, thereby improving the stability and reliability of semiconductor devices.

[0074] In some optional embodiments, the crystalline silicon in the formed first crystalline silicon strip has multiple crystal orientations.

[0075] In this embodiment, since the first crystalline silicon strip is obtained by epitaxy of the second crystalline silicon strip, the crystalline silicon in the first crystalline silicon strip replicates the crystal orientation of the crystalline silicon in the second crystalline silicon strip, so that the crystalline silicon in the first crystalline silicon strip has a variety of different crystal orientations, such as <100> , <110> , <111> Etc., so that semiconductor devices have better performance.

[0076] It can be understood that the crystal direction in this embodiment refers to the direction of crystalline silicon. Crystalline silicon has directionality, and the crystal properties are different along different directions of the lattice.

[0077] S54: removing the photoresist layer 140.

[0078] In this embodiment, if Fig.15As shown, the photoresist layer 140 can be dissolved by a stripping solution to remove the photoresist layer 140, or the photoresist layer 140 can be stripped by a stripping device, and only the first crystalline silicon strip 130 is left on the insulating layer 110 after the photoresist layer 140 is stripped. That is, after the photoresist layer 140 is removed, the semiconductor device includes a substrate 101, and an insulating layer 110 and a first crystalline silicon strip 130 sequentially disposed on the substrate.

[0079] S61 : forming a planarization layer 145 covering the first crystalline silicon strip 130 .

[0080] In this embodiment, in order to make the first crystalline silicon strip 130 have a flat top surface, Fig.16 As shown, a planarization layer 145 covering the first crystalline silicon strip 130 is formed by a deposition process. The planarization layer 145 is made of a dielectric material, such as silicon nitride, silicon oxynitride, or other insulating materials. In a specific example, the planarization layer 145 is made of silicon nitride. The deposition process can be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0081] S62: planarizing the planarization layer 145 and the side of the first crystalline silicon strip 130 away from the insulating layer 110 to expose the first crystalline silicon strip 130.

[0082] In this embodiment, the planarization layer 145 is thinned by a chemical mechanical polishing (CMP) process until the top of the first crystalline silicon strip 130 is exposed. When the first crystalline silicon strip 130 is exposed, the top of the first crystalline silicon strip 130 is planarized so that the top of the first crystalline silicon strip 130 is flat.

[0083] It is understandable that when the semiconductor device includes a plurality of first crystalline silicon strips 130 , this step can be used to make the tops of the plurality of first crystalline silicon strips 130 located on the same horizontal line, thereby forming a silicon strip array with uniform morphology and flat tops.

[0084] S63: removing the planarization layer 145. For example, the planarization layer 145 is removed by a wet etching process. After the planarization layer 145 is removed, the semiconductor device is Fig.17 shown.

[0085] S71 : depositing a gate material on the first crystalline silicon strip 130 to form a gate structure 150 spanning the first crystalline silicon strip 130 .

[0086] In this embodiment, if Fig.18 As shown, Fig.18 The (1) is Fig.18 (ii) is a cross-sectional view on the AA' plane. A gate structure 150 including a gate dielectric layer 151 and a gate electrode layer 152 is formed by depositing a gate material, and the gate structure 150 spans the first crystalline silicon strip 130, that is, the gate structure 150 extends along a second direction parallel to the insulating layer 110, wherein the first direction and the second direction of the insulating layer 110 are not parallel, and in a specific example, the first direction and the second direction of the insulating layer 110 are perpendicular. The gate dielectric layer 151 is made of silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or one or more of the other insulating materials. In some embodiments, the gate dielectric layer 151 is deposited by a plasma enhanced chemical vapor deposition (PECVD) process or by a spin coating process.

[0087] In some other optional embodiments, the gate electrode layer 152 is made of a metal material. The metal material may include an N work function metal or a P work function metal. The N work function metal includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or a combination thereof. The P work function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru) or a combination thereof.

[0088] S72 : implanting an impurity ion doping material into the first crystalline silicon strip 130 to form a source structure 161 and a drain structure 162 at two ends of the first crystalline silicon strip 130 , and forming a channel 163 between the source structure 161 and the drain structure 162 .

[0089] like Fig.19 As shown, an impurity ion doping material is injected into the first crystalline silicon strip 130 and the source structure 161 and the drain structure 162 are activated by laser spike annealing (LSA) technology or rapid thermal processing (RTP) technology, so that the source structure 161 and the drain structure 162 are formed at both ends of the first crystalline silicon strip 130, and a channel 163 is formed between the source structure 161 and the drain structure 162. The impurity ion doping material can be a P-type ion doping material or an N-type ion doping material. The P-type ion doping material can be at least one of boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof. The N-type ion doping material can be phosphorus (P), PH x +and / or P2H x + At least one of (x=1, 2, 3, ...) or a combination thereof.

[0090] In a specific example, when the semiconductor device is a PMOS device, boron (B) ions are used as the impurity ion doping material. -3 The boron ions of 1000 nm are implanted into the first crystalline silicon strip 130 to form a source structure 161 and a drain structure 162 at both ends of the first crystalline silicon strip 130, and a channel 163 is formed in the region between the source structure 161 and the drain structure 162, and the source structure 161 and the drain structure 162 are electrically isolated (insulated) by the channel 163. The source structure 161 and the drain structure 162 are activated by laser annealing (LSA) technology.

[0091] S81 : depositing conductive materials on the source structure 161 , the drain structure 162 and the gate structure 150 , respectively, to form a source electrode on the source structure, a drain electrode on the drain structure and a gate electrode on the gate structure, respectively.

[0092] In this embodiment, a conductive material may be deposited on the source structure 161, the drain structure 162, and the gate structure 150, respectively. The conductive material may be a metal material, such as tungsten, copper, their alloys, or any metal material with suitable resistance and gap filling capability and a combination thereof. The conductive material may also be some metal silicides with conductive capability. In some embodiments, the conductive material layer is deposited on the source structure, the drain structure, and the gate structure, respectively, by sputtering, CVD, or electrochemical plating (ECP). The formed source electrode, drain electrode, and gate electrode may be subsequently connected to other semiconductor devices or electronic devices.

[0093] Finally, the formed semiconductor device includes a substrate 101, an insulating layer 110 and a first crystalline silicon strip 130 sequentially disposed on the substrate, a source structure 161 and a drain structure 162 are disposed at both ends of the first crystalline silicon strip 130, and the first crystalline silicon strip 130 located between the source structure 161 and the drain structure 162 serves as a channel 163 to electrically isolate the source structure 161 and the drain structure 162. A gate structure 150 is also disposed on the first crystalline silicon strip 130 and spans the first crystalline silicon strip 130. The first crystalline silicon strip 130 replicates the crystal orientation of the crystalline silicon in the second crystalline silicon strip 120, that is, there are multiple different crystal orientations along the carrier transmission direction in the channel, including <100> , <110> , <111> At the same time, since the impurities in the second crystalline silicon strip 120, such as the induced metal introduced during the formation of the second crystalline silicon strip 120, have a weak diffusion ability during the epitaxial growth process, the first crystalline silicon strip 130 contains fewer impurities, thereby improving the reliability of the semiconductor device.

[0094] In the above-described embodiments, a "gate first" process is performed to form the semiconductor device. However, by using a process similar to that herein, another process such as a "gate last" process or another type of semiconductor device (eg, a planar device) is applied.

[0095] It should be noted that the above embodiments are only specific examples for better understanding the technical methods of the embodiments of the present application, and are not intended to be the sole limitation of the embodiments of the present application. The order of semiconductor devices can also be appropriately adjusted according to the formation method provided in the embodiments of the present application, or increased or decreased according to actual conditions, or combined with other manufacturing process flows of semiconductor devices to produce another type of semiconductor device.

[0096] Considering the rapid development of technologies such as graphics computing, neural networks, artificial intelligence, cloud computing, and high-performance computing clusters, the area of ​​semiconductor devices has been continuously reduced to increase the integration of chips. However, due to the limitations of substrate thickness and alignment accuracy, the connection density between different integrated chips is difficult to exceed 10. 6 mm 2 In order to further improve the integration of the chip, a first semiconductor device and a second semiconductor device can be stacked on the same substrate, and the connection density can exceed 10 8 mm 2, which greatly improves the connection density of the chip. However, when forming the second semiconductor, in order not to affect the existing first semiconductor device, the metal induced crystallization (MIC) technology or metal induced lateral crystallization (MILC) is used to generate the middle crystalline silicon strip of the second semiconductor device. There are also many induced metal residues in the middle crystalline silicon strip of the second semiconductor device. Excessive induced metal residues will increase the possibility of leakage of the second semiconductor device, thereby reducing the reliability of the chip.

[0097] To this end, the present application embodiment also provides a chip. Fig. 20 The chip includes a first semiconductor device 02 that is stacked and a second semiconductor device 01 that is formed using the formation method provided in the above embodiment. An isolation layer 200 is provided between the first semiconductor device 02 and the second semiconductor device 01 to electrically isolate the first semiconductor device 02 from the second semiconductor device 01.

[0098] In some optional embodiments, the first semiconductor device 02 may be a PMOS device, and the second semiconductor device 01 may be an NMOS device; or, the first semiconductor device 02 is an NMOS device, and the second semiconductor device 01 is a PMOS device. An isolation layer 200 is provided between the first semiconductor device 02 and the second semiconductor device 01, and a plurality of conductive structures may be provided in the isolation layer 200, so that the gate structure of the first semiconductor device 02 is electrically connected to the gate structure of the second semiconductor device 01, and the drain structure of the first semiconductor device 02 is electrically connected to the drain structure of the second semiconductor device 01.

[0099] For example, the first semiconductor device 02 is a PMOS device, and the second semiconductor device 01 is an NMOS device. Then, the source electrode on the source structure of the PMOS device in the lower layer can be used as the first terminal Vdd of the chip to connect to the first power supply, the source electrode on the source structure in the NMOS device in the upper layer can be used as the second terminal Vss of the chip to connect to the second power supply, the gate electrode on the gate structure in the PMOS device and the gate electrode on the gate structure in the NMOS can be used as the input terminal Vin of the chip, and the drain electrode on the drain structure in the PMOS device and the drain electrode on the drain structure in the NMOS device can be used as the output terminal Vout of the chip, thereby facilitating the electrical connection of the chip with the rest of the circuit.

[0100] It is understandable that the formation process of the first semiconductor device is not limited by temperature, so the first semiconductor device can be formed using the semiconductor device formation method provided in the above embodiment, and can also be formed using other formation methods, and this application does not impose any restrictions.

[0101] The semiconductor device according to the embodiment of the present application can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (for example, other forms of transistors, etc.), electrically connecting them to a printed circuit board, and thereby constructing an electronic device. Therefore, the embodiment of the present application also provides an electronic device, such as Fig.21 As shown, the electronic device includes a semiconductor device 03 formed by the formation method provided in the above embodiment and a printed circuit board (PCB) 04. The electronic device may also include a display screen matched with the printed circuit board 04 and a wireless transceiver matched with the printed circuit board. Such electronic devices include smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, etc.

[0102] The present application embodiment provides another electronic device. Fig. 22 As shown, the electronic device may include the chip 05 and the printed circuit board (PCB) 04 provided in the above embodiment. The electronic device may include a CMOS image sensor, a NAND flash memory, a high bandwidth memory, a mobile phone, a tablet computer (pad), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device and other electronic products. The embodiments of the present application do not impose any special restrictions on the specific form of the above electronic device.

[0103] Another embodiment of the present application also provides a non-transitory computer-readable storage medium for use with a computer, the computer having software for creating and manufacturing the above-mentioned semiconductor device, and one or more computer-readable data structures are stored on the computer-readable storage medium, and the one or more computer-readable data structures have control data for manufacturing the semiconductor device provided in any one of the diagrams provided above, such as photoresist layer data.

[0104] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: an insulating layer, and a first crystalline silicon strip formed on the insulating layer, wherein the first crystalline silicon strip extends along a first direction parallel to the insulating layer, and the induced metal content in the first crystalline silicon strip is lower than 1e17 cm -3 .

2. The semiconductor device according to claim 1, wherein: The crystalline silicon in the first crystalline silicon strip is single crystal silicon.

3. The semiconductor device according to claim 1 or 2, characterized in that: The length of the first crystalline silicon strip is greater than or equal to 1 μm.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The crystalline silicon in the first crystalline silicon strip has multiple crystal orientations.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The semiconductor device further comprises: a source structure and a drain structure, wherein the source structure and the drain structure are respectively arranged at two ends of the first crystalline silicon strip; a channel, the channel being disposed between the source structure and the drain structure; A gate structure is provided, wherein the gate structure spans across the first crystalline silicon strip, and the source structure, the drain structure and the gate structure are electrically isolated from each other.

6. The semiconductor device according to claim 5, characterized in that The semiconductor device further includes: a source electrode disposed on the source structure, a drain electrode disposed on the drain structure, and a gate electrode disposed on the gate structure.

7. A method for forming a semiconductor device, characterized in that: include: forming an insulating layer; forming a second crystalline silicon strip on the insulating layer, wherein the second crystalline silicon strip extends along a first direction parallel to the insulating layer; forming an epitaxial silicon layer covering the second crystalline silicon strip; Part of the epitaxial silicon layer and the second crystalline silicon strip is removed, and the remaining epitaxial silicon layer forms a first crystalline silicon strip, wherein the projection of the removed epitaxial silicon layer on the insulating layer covers the projection of the second crystalline silicon strip on the insulating layer.

8. The method according to claim 7, characterized in that Removing a portion of the epitaxial silicon layer and the second crystalline silicon strip, and forming the remaining epitaxial silicon layer into the first crystalline silicon strip comprises: forming a photoresist layer covering the epitaxial silicon layer; forming a window on the photoresist layer, wherein a projection of the window on the insulating layer covers a projection of the second crystalline silicon strip on the insulating layer, and a projection of the epitaxial silicon layer on the insulating layer covers a projection of the window on the insulating layer; Using the photoresist layer as a mask, removing the portion of the epitaxial silicon layer and the second crystalline silicon strip; The photoresist layer is removed.

9. The method according to claim 7 or 8, characterized in that: The method further comprises: forming a planarization layer covering the first crystalline silicon strip; Planarizing the planarization layer and the side of the first crystalline silicon strip away from the insulating layer to expose the first crystalline silicon strip; The planarization layer is removed.

10. The method according to any one of claims 7 to 9, characterized in that: Forming a second crystalline silicon strip on the insulating layer includes: forming an amorphous silicon layer on the insulating layer; removing a portion of the amorphous silicon layer to form an amorphous silicon strip, wherein the amorphous silicon strip extends along a first direction parallel to the insulating layer; The amorphous silicon material in the amorphous silicon strip is crystallized into crystalline silicon by inducing metal to form a second crystalline silicon strip.

11. The method according to any one of claims 7 to 10, characterized in that: The method further comprises: Depositing a gate material on the first crystalline silicon strip to form a gate structure spanning the first crystalline silicon strip; An impurity ion doping material is implanted into the first crystalline silicon strip to form a source structure and a drain structure at two ends of the first crystalline silicon strip, and a channel is formed between the source structure and the drain structure.

12. The method according to claim 11, characterized in that The method further comprises: Conductive materials are deposited on the source structure, the drain structure and the gate structure respectively to form a source electrode on the source structure, a drain electrode on the drain structure and a gate electrode on the gate structure respectively.

13. A chip, characterized in that: include: A first semiconductor device and a second semiconductor device are stacked, an isolation layer is arranged between the first semiconductor device and the second semiconductor device, and the second semiconductor device is the semiconductor device according to any one of claims 1 to 6.

14. An electronic device, characterized in that: The invention comprises a printed circuit board and a semiconductor device as claimed in any one of claims 1 to 6; the semiconductor device and the printed circuit board are electrically connected.

15. An electronic device, characterized in that: It comprises a printed circuit board and the chip as claimed in claim 13; the chip and the printed circuit board are electrically connected.

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