Ultrathin and large-area high-power MOSFET chip

Abstract

The invention relates to an ultrathin and large-area high-power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) chip, which comprises an active region, strip-shaped source electrode lead holes of the active region are arranged at intervals, the strip-shaped source electrode lead holes are arranged in a transverse and vertical alternating manner, the whole lead hole is divided into a plurality of shorter lead holes, dielectric layers are arranged between the multiple sections of lead holes, and the dielectric layers are arranged at intervals between the multiple sections of lead holes. After the lead hole is etched, the micro-warping effect of the wafer is obviously reduced, the stress is obviously reduced, the stress after the lead hole is etched can be mutually counteracted in the horizontal direction and the vertical direction, the warping problem is eliminated, the surface of the wafer is very smooth, the chip area can be larger, the problems of micro-warping and stress of the wafer cannot occur, the wafer can be thinned, and the yield of the wafer is improved. And the product is lower in on resistance, lower in thermal resistance and higher in power density.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductors, in particular to an ultra-thin and large-area high-power MOSFET chip. Background Art

[0002] like Figure 1 , which is a common cell structure of high-power MOSFET. The source of these structures is led out from the front through the lead hole. For the long strip cell structure MOSFET, the source line hole is equivalent to a strip dug out of the dielectric layer, where Figure 1 The a in the formula indicates a plane type. Figure 1 The b in the formula indicates a planar groove type. Figure 1 The c in the figure indicates a split-gate type. Power devices such as MOSFETs are made up of tens of thousands of cells connected in parallel, so a single chip has tens of thousands of source lead holes. After the lead holes are etched, the wafer will be slightly warped and face stress problems. For ultra-high power MOSFETs, as the chip area continues to increase, the source lead holes are longer and more numerous, so the micro-warping of the wafer becomes more obvious. During the processing, there will be problems with wafer transfer and excessive backside thinning fragmentation.

[0003] The traditional solution is to use 2 For power MOSFET products, the wafer thinning thickness is limited. For example, for 100V separated-gate MOSFET, in order to reduce the thinning fragmentation rate to less than 1%, many FAB factories limit the wafer thinning thickness to more than 150 microns. The limited wafer thinning thickness will introduce too much chip substrate resistance, making it impossible to further reduce the product's on-resistance and thermal resistance, limiting the power of a single power MOSFET. For some high-power applications greater than 1KW, end users can only use many power MOSFET products in parallel to achieve high system power, which is not conducive to the small size of the system. It also brings problems such as parameter consistency in parallel applications. The stress problem after the source lead hole bar etching is restricting the technical development of ultra-high power MOSFETs.

[0004] In the prior art, in order to simplify the layout, the lead holes are drawn in a uniform direction, that is, the lead holes in the active area of ​​the entire chip are uniformly drawn in a horizontal direction or a vertical direction (such as Figure 2 As shown, Figure 2 The a in the figure indicates that the lead hole is in the horizontal direction of the whole piece. Figure 2 b in the figure indicates that the lead holes are in the vertical direction of the whole piece). After the lead holes are etched, all the lead holes will be slightly warped in the same direction (such as Figure 3 ), which causes wafer stress. When the chip area continues to increase (for example >25mm 2), wafer warpage will affect wafer transfer and lead to excessive thinning fragmentation rate. FAB factories can only limit the maximum chip area and minimum thinning thickness (for example, for 100V insulated gate MOSFET products, the chip area is not more than 25mm 2 , the thickness is not less than 150 microns). This increases the on-resistance and thermal resistance of a single MOSFET, sacrificing product performance. Summary of the invention

[0005] The purpose of the present invention is to provide an ultra-thin and large-area high-power MOSFET chip. A unique design is adopted for the layout of the chip lead holes to significantly reduce or fundamentally eliminate the micro-warping phenomenon of the wafer after the lead holes are etched, thereby realizing an ultra-thin and large-area ultra-high-power MOSFET.

[0006] To achieve the above object, the present invention provides an ultra-thin and large-area high-power MOSFET chip, wherein the MOSFET chip comprises an active area, and strip-shaped source lead holes of the active area are discontinuously arranged.

[0007] More preferably, the strip-shaped source lead holes are arranged alternately horizontally and vertically.

[0008] More preferably, the active area is divided into a plurality of active area blocks, and the strip-shaped source lead holes of the plurality of active area blocks are arranged alternately horizontally and vertically.

[0009] More preferably, the plurality of active area blocks are arranged in a 2*2 block layout, a 2*3 block layout, or a 3*3 block layout.

[0010] More preferably, the discontinuously arranged source lead holes are arranged in parallel with the grooves or the polycrystalline strip gates.

[0011] More preferably, the trench or the polycrystalline strip gate surrounds the discontinuously arranged source lead holes.

[0012] More preferably, the source metal is provided in a whole piece to form a unique source wiring area, and the gate metal strip surrounds the source metal and is connected to the gate wiring area.

[0013] More preferably, each source metal block is independent of each other and forms a source wiring area respectively, and the gate metal strip surrounds each source metal block and is connected to the gate wiring area.

[0014] More preferably, the MOSFET chip includes a power MOSFET chip using a Si-based process or a SiC-based process.

[0015] Preferably, during package wire bonding, the source lead adopts a double solder point or multi-solder point method.

[0016] The ultra-thin and large-area high-power MOSFET chip of the present invention has at least the following beneficial effects: the MOSFET chip comprises an active area, the strip-shaped source lead holes of the active area are intermittently arranged, the strip-shaped source lead holes are arranged alternately horizontally and vertically, the whole lead hole is divided into a plurality of lead holes with shorter lengths, a dielectric layer is provided between the plurality of lead holes, after the lead holes are etched, the micro-warping effect of the wafer is significantly alleviated, the stress is significantly reduced, the stress after the lead holes are etched can be offset mutually in the horizontal and vertical directions, the warping problem is eliminated, and the wafer surface is very flat. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] By reading the following detailed description with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein: Figure 1 It is a structural diagram of a MOSFET chip in the prior art; Figure 2 It is a schematic diagram of the source lead hole of the MOSFET chip in the prior art; Figure 3 A wafer cross-sectional view of a MOSFET chip in the prior art; Figure 4 A cross-sectional view of a wafer of a MOSFET chip according to an embodiment of the present invention; Figure 5 A schematic diagram of discontinuous arrangement of source lead holes in an ultra-thin and large-area high-power MOSFET chip according to an embodiment of the present invention; Figure 6 A schematic diagram of an ultra-thin and large-area high-power MOSFET chip alternately arranged horizontally and vertically in an embodiment of the present invention; Figure 7 A schematic diagram of a polysilicon gate or trench and a source lead hole according to an embodiment of the present invention; Figure 8 A schematic diagram of a metal and wiring area with discontinuous source lead holes in an ultra-thin and large-area high-power MOSFET chip according to an embodiment of the present invention; Fig. 9 A schematic diagram of a metal and wiring area with source lead holes alternating horizontally and vertically in an ultra-thin and large-area high-power MOSFET chip according to an embodiment of the present invention; Fig.10 The figure is a schematic diagram of welding an ultra-thin and large-area high-power MOSFET chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0019] The specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0020] Please refer to Figure 5 , shows a schematic diagram of the discontinuous arrangement of source lead holes in an ultra-thin and large-area high-power MOSFET chip according to an embodiment of the present invention. The MOSFET chip includes an active area, and the strip-shaped source lead holes in the active area are discontinuously arranged, dividing the entire lead hole into a number of shorter lead holes, and a dielectric layer is provided between the multiple lead holes, and each hole line does not exceed 500 microns. Therefore, after the lead hole is etched, the micro-warping effect of the wafer is significantly reduced, and the stress is significantly reduced. Accordingly, referring to Figure 8 , showing a schematic diagram of the metal and bonding area with discontinuous source lead holes in an ultra-thin and large-area high-power MOSFET chip according to an embodiment of the present invention. The source metal is a whole piece, forming a unique source bonding area, and the gate metal surrounds the source metal and is connected to the gate bonding area.

[0021] Reference Figure 6 , shows a schematic diagram of an ultra-thin and large-area high-power MOSFET chip in an embodiment of the present invention, in which the horizontal and vertical alternating arrangement is adopted. In the product layout design stage, the source lead hole is arranged in a horizontal and vertical alternating manner. The stress after the lead hole is etched can offset each other in the horizontal and vertical directions, the warping problem is eliminated, and the wafer surface is very flat. The specific effect is as follows Figure 4 As shown, accordingly, the active area adopts a block design, and multiple active area blocks are 2*2 block layout, 2*3 block layout, and 3*3 block layout to facilitate gate routing and package wiring. Figure 6 , showing a schematic diagram of an ultra-thin and large-area high-power MOSFET chip in an embodiment of the present invention alternately arranged horizontally and vertically, there are three main arrangements of active area blocks: Figure 6 2*2 blocks in a, Figure 6 2*3 blocks in b or Figure 6 The 3*3 block in middle c.

[0022] Reference Fig. 9, shows a schematic diagram of a metal and wiring area with source lead holes alternating horizontally and vertically in an ultra-thin and large-area high-power MOSFET chip according to an embodiment of the present invention. The source metal and source wiring area of ​​each active block are independent of each other and are connected in parallel through package leads. The gate metal just surrounds each source metal block and is then connected to the gate wiring area through metal.

[0023] Reference Fig.10 , showing a schematic diagram of welding of an ultra-thin and large-area high-power MOSFET chip according to an embodiment of the present invention, the source wire bonding adopts a double welding point or a double welding point method to realize the parallel connection of each source metal.

[0024] The technical solution of the embodiment of the present invention is applicable to planar, trench, and split-gate structure power MOSFET chips. From the process point of view, the embodiment of the present invention is also applicable to Si-based and SiC-based power MOSFET products. Reference Figure 7 , shows a schematic diagram of a polysilicon gate or trench and a polysilicon gate or trench according to an embodiment of the present invention, wherein the trench or polycrystalline strip gate is kept parallel to the source lead hole, that is, the discontinuously arranged source lead hole is arranged parallel to the trench or polycrystalline strip gate, or the trench or polycrystalline strip gate surrounds the discontinuously arranged source lead hole The ultra-thin and large-area high-power MOSFET chip of the present invention comprises an active area, wherein the strip-shaped source lead holes of the active area are intermittently arranged, and the direction of the strip-shaped source lead holes is alternately horizontal and vertical, and the whole lead hole is divided into a plurality of lead holes with shorter lengths, and a dielectric layer is provided between the plurality of lead holes. After the lead holes are etched, the micro-warping effect of the wafer is significantly alleviated, and the stress is significantly reduced. The stress after the lead holes are etched can be offset in the horizontal and vertical directions, and the warping problem is eliminated. The wafer surface is very flat, and the chip area can be made larger without the problem of wafer micro-warping and stress. The wafer thinning thickness can be thinner without increasing the thinning fragmentation rate, and the product has lower on-resistance, lower thermal resistance and higher power density.

[0025] In the above description of this specification, unless otherwise clearly specified and limited, the terms "fixed", "installed", "connected" or "connected" should be understood in a broad sense. For example, with regard to the term "connection", it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. Therefore, unless otherwise clearly defined in this specification, those skilled in the art can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0026] According to the above description of this specification, those skilled in the art may also understand that the terms used below, such as "up", "down", "front", "back", "left", "right", "length", "width", "thickness", "vertical", "horizontal", "top", "bottom", "inside", "outside", "axial", "radial", "circumferential", "center", "longitudinal", "lateral", "clockwise" or "counterclockwise", etc., which indicate the orientation or position relationship, are based on the orientation or position relationship shown in the drawings of this specification, and are only for the purpose of facilitating the explanation of the scheme of the present invention and simplifying the description, rather than explicitly or implicitly indicating that the device or element involved must have the specific orientation, be constructed and operate in a specific orientation. Therefore, the above-mentioned orientation or position relationship terms cannot be understood or interpreted as limitations on the scheme of the present invention.

[0027] In addition, the terms "first" or "second" used in this specification to refer to numbers or ordinals are only used for descriptive purposes and cannot be understood as explicitly or implicitly indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this specification, the meaning of "plurality" is at least two, such as two, three or more, etc., unless otherwise clearly and specifically defined.

[0028] Although this specification has shown and described a plurality of embodiments of the present invention, it is apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art will think of many changes, modifications and alternatives without departing from the thought and spirit of the present invention. It should be understood that in the process of practicing the present invention, various alternatives to the embodiments of the present invention described herein may be adopted. The attached claims are intended to define the scope of protection of the present invention, and therefore cover the modular composition, equivalent or alternatives within the scope of these claims.

Claims

1. An ultra-thin and large-area high-power MOSFET chip, characterized in that: The MOSFET chip comprises an active region, and the strip-shaped source lead holes of the active region are intermittently arranged.

2. The ultra-thin and large-area high-power MOSFET chip according to claim 1, characterized in that: The strip-shaped source lead holes are oriented alternately horizontally and vertically.

3. The ultra-thin and large-area high-power MOSFET chip according to claim 2, characterized in that: The active area is divided into a plurality of active area blocks, and the strip-shaped source lead holes of the plurality of active area blocks are arranged alternately horizontally and vertically.

4. The ultra-thin and large-area high-power MOSFET chip according to claim 1, characterized in that: The multiple active area blocks are arranged in a 2*2 block layout, a 2*3 block layout, or a 3*3 block layout.

5. The ultra-thin and large-area high-power MOSFET chip according to claim 1, characterized in that: The discontinuously arranged source lead holes are arranged in parallel with the grooves or the polycrystalline strip gates.

6. The ultra-thin and large-area high-power MOSFET chip according to claim 5, characterized in that: The trench or the polycrystalline strip gate surrounds the discontinuously arranged source lead holes.

7. The ultra-thin and large-area high-power MOSFET chip according to claim 1, characterized in that: The source metal is provided as a whole piece to form a unique source wiring area, and the gate metal strip surrounds the source metal and is connected to the gate wiring area.

8. The ultra-thin and large-area high-power MOSFET chip according to claim 2, characterized in that: Each source metal block is independent of each other and forms a source wiring area respectively. After the gate metal strip surrounds each source metal block, it is connected to the gate wiring area.

9. The ultra-thin and large-area high-power MOSFET chip according to claim 1, characterized in that: The MOSFET chips include power MOSFET chips using Si-based technology and SiC-based technology.

10. The ultra-thin and large-area high-power MOSFET chip according to claim 1, characterized in that: When the package is wired, the source lead adopts a double solder point or multi-solder point method.

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