Semiconductor structure and forming method thereof
By introducing an inversion doped region into the semiconductor structure, the short channel effect and leakage current problems that the semiconductor structure in the existing technology exhibits at smaller process nodes are solved, and better performance is achieved.
Patent Information
- Application Number
- CN202310878357.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-17
- Publication Date
- 2025-01-21
AI Technical Summary
Existing semiconductor structures exhibit short channel effects and leakage current problems on smaller process nodes, resulting in insufficient performance.
A semiconductor structure is used, which includes a substrate, a channel structure layer, a gate structure, a source-drain doping layer and an inversion doping region. The inversion doping region is located within the edge of the sidewall of the channel layer and is doped with inversion ions of different types from the source and drain doping layers, thereby enhancing the potential barrier of the channel layer and reducing the probability of diffusion of doped ions.
By increasing the potential barrier of the channel layer, reducing the probability of diffusion to doping to the ditmaneous layer, improved the leakage current and short -channel effects between the source leakage doping layer and the dovet layer, and optimized the performance of the semiconductor structure.
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Figure CN119342885A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistor size is getting smaller and smaller, and Fin-type field-effect transistor (FinFET) came into being. However, to maintain the original driving current performance, this structure is no longer suitable for smaller nodes. So the all-around gate transistor (Gate-All-Around, GAAFET) appeared. Its control of short channel effects and superior electrical performance make it replace FinFET and become the mainstream at smaller process nodes.
[0003] GAAFET is a four-sided ring gate structure that can better suppress the short channel effect and achieve better electrical performance.
[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a channel structure layer suspended on the substrate, the channel structure layer comprising one or more channel layers spaced in sequence from bottom to top; a gate structure spanning the channel structure layer, the gate structure filling between the channel layer and the substrate and between adjacent channel layers, the gate structure surrounding the channel layer; a source-drain doping layer located in the channel structure layer on both sides of the gate structure and in a partial thickness of the substrate; an inversion doping region located within the edge of the side wall of the channel layer, the inversion doping region being doped with inversion ions, the doping type of the inversion ions being different from the doping type of the source-drain doping layer.
[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate and one or more channel stacks stacked in sequence on the substrate, each of the channel stacks comprising a sacrificial layer and a channel layer on the sacrificial layer; forming a pseudo-gate structure spanning the channel stack on the substrate; doping anti-type ions in the channel stacks on both sides of the pseudo-gate structure, wherein the doping type of the anti-type ions is different from the channel conductivity type of the MOS transistor; removing the channel stacks on both sides of the pseudo-gate structure to form source-drain grooves, wherein the remaining anti-type ions within the edge of the channel layer on the sidewalls of the source-drain grooves are used to constitute an anti-type doping region; and forming a source-drain doping layer in the source-drain grooves, wherein the source-drain doping layer is adjacent to the anti-type doping region.
[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0009] The semiconductor structure provided by the embodiment of the present invention is further provided with an inversion doping region, which is located within the edge of the side wall of the channel layer. The inversion doping region is doped with inversion ions, and the doping type of the inversion ions is different from the doping type of the source and drain doping layers. The source and drain doping layers are adjacent to the inversion doping region. The inversion doping region located within the edge of the channel layer can increase the potential barrier of the channel layer adjacent to the side wall of the source and drain doping layer, increase the difficulty of the doped ions in the source and drain doping layer to diffuse into the channel layer, and correspondingly reduce the probability of the doped ions in the source and drain doping layer to diffuse into the channel layer, thereby improving the leakage current between the source and drain doping layer and the channel layer and improving the short channel effect, thereby optimizing the performance of the semiconductor structure.
[0010] Moreover, the inversion doping region is located within the edge of the channel layer, which is beneficial for reducing the probability of doping ions in the source and drain doping layers diffusing into the channel layer while avoiding adverse effects on carrier mobility in the channel region when the device is working.
[0011] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming a dummy gate structure, inversion ions are doped in the channel stacks on both sides of the dummy gate structure, and then heat treatment is performed to diffuse the inversion ions into the channel stacks at the bottom of the dummy gate structure, forming an initial inversion doping region in the channel stack, and then the channel stacks on both sides of the dummy gate structure are removed to form source-drain grooves, and the remaining initial inversion doping region located within the edge of the channel layer on the sidewalls of the source-drain grooves is used as an inversion doping region, so that after forming a source-drain doping layer in the groove, the source-drain doping layer is adjacent to the inversion doping region, and the inversion doping region located within the edge of the channel layer can increase the potential barrier of the channel layer adjacent to the sidewalls of the source-drain doping layer, increase the difficulty of the doped ions in the source-drain doping layer to diffuse into the channel layer, and correspondingly reduce the probability of the doped ions in the source-drain doping layer to diffuse into the channel layer, thereby improving the leakage current between the source-drain doping layer and the channel layer and improving the short channel effect, thereby optimizing the performance of the semiconductor structure.
[0012] Moreover, the inversion doping region is formed within the edge of the channel layer, thereby reducing the probability of doping ions in the source and drain doping layers diffusing into the channel layer while avoiding adverse effects on carrier mobility in the channel region when the device is operating.
[0013] In an optional scheme, the method for forming the semiconductor structure also includes: after doping the channel stacks on both sides of the pseudo-gate structure with anti-type ions, and before removing the channel stacks on both sides of the pseudo-gate structure to form the grooves, performing heat treatment to diffuse the anti-type ions into the channel stacks at the bottom of the pseudo-gate structure, thereby, on the one hand, activating the anti-type ions doped in the channel layer and repairing the lattice damage caused by ion doping, and on the other hand, increasing the concentration and concentration of the anti-type ions in the edge of the channel layer, thereby increasing the effect of the anti-type doping region on reducing the probability of the doped ions in the source and drain doping layers diffusing into the channel layer.
[0014] In an optional scheme, an ion implantation process is used, and the step of doping inversion ions in the channel stacks on both sides of the pseudo-gate structure includes: performing a first ion implantation on the channel stacks on both sides of the pseudo-gate structure, the first ion implantation having a first implantation depth; performing a second ion implantation on the channel stacks on both sides of the pseudo-gate structure, the second ion implantation having a second implantation depth, the second implantation depth being less than the first implantation depth; performing a third ion implantation on the channel stacks on both sides of the pseudo-gate structure, the third ion implantation having a third implantation depth, the third implantation depth being less than the second implantation depth; by performing ion implantation of different depths in sequence, it is possible to ensure that inversion ions are implanted in each channel layer, and to improve the uniformity of distribution of inversion ions in each channel layer, thereby ensuring that the inversion doping regions subsequently formed in each channel layer can all play a role in reducing the probability of doped ions in the source and drain doping layers diffusing into the channel layers. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;
[0016] Figures 2 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0017] As can be seen from the background technology, the performance of current semiconductor structures needs to be improved.
[0018] Specifically, in a fully enclosed gate transistor, the ion doping concentration in the source and drain doping layers is relatively high, and in the formation process of the fully enclosed gate transistor, multiple heat treatment steps are usually required. The doped ions in the source and drain doping layers are easily diffused into the channel layer during the heat treatment, which can easily aggravate the short channel effect and deteriorate the performance of the semiconductor structure.
[0019] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, which is also provided with an inversion doping region, which is located within the edge of the side wall of the channel layer, and the inversion doping region is doped with inversion ions. The doping type of the inversion ions is different from the doping type of the source and drain doping layers. The source and drain doping layers are adjacent to the inversion doping region. The inversion doping region located within the edge of the channel layer can increase the potential barrier of the channel layer adjacent to the side wall of the source and drain doping layer, increase the difficulty of the doped ions in the source and drain doping layer to diffuse into the channel layer, and correspondingly reduce the probability of the doped ions in the source and drain doping layer to diffuse into the channel layer, thereby improving the leakage current between the source and drain doping layer and the channel layer, improving the short channel effect, and optimizing the performance of the semiconductor structure.
[0020] Moreover, the inversion doping region is located within the edge of the channel layer, which is beneficial for reducing the probability of doping ions in the source and drain doping layers diffusing into the channel layer while avoiding adverse effects on carrier mobility in the channel region when the device is working.
[0021] In order to solve the technical problem, an embodiment of the present invention further provides a method for forming a semiconductor structure. After forming a pseudo-gate structure, inversion ions are doped in the channel stacks on both sides of the pseudo-gate structure, and then heat treatment is performed to diffuse the inversion ions into the channel stacks at the bottom of the pseudo-gate structure to form an initial inversion doping region in the channel stack. Then, the channel stacks on both sides of the pseudo-gate structure are removed to form source-drain grooves. The remaining initial inversion doping region within the edge of the channel layer on the sidewalls of the source-drain grooves is used as an inversion doping region, so that after forming a source-drain doping layer in the groove, the source-drain doping layer is adjacent to the inversion doping region. The inversion doping region within the edge of the channel layer can increase the potential barrier of the channel layer adjacent to the sidewalls of the source-drain doping layer, increase the difficulty of the doped ions in the source-drain doping layer to diffuse into the channel layer, and correspondingly reduce the probability of the doped ions in the source-drain doping layer to diffuse into the channel layer, thereby improving the leakage current between the source-drain doping layer and the channel layer and improving the short channel effect, thereby optimizing the performance of the semiconductor structure.
[0022] Moreover, the inversion doping region is formed within the edge of the channel layer, thereby reducing the probability of doping ions in the source and drain doping layers diffusing into the channel layer while avoiding adverse effects on carrier mobility in the channel region when the device is operating.
[0023] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0024] refer to Figure 1 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.
[0025] like Figure 1As shown, in this embodiment, the semiconductor structure includes: a substrate 100; a channel structure layer 170, suspended on the substrate 100, the channel structure layer 170 includes one or more channel layers 20 arranged in sequence from bottom to top; a gate structure 190, spanning the channel structure layer 170, the gate structure 190 is filled between the channel layer 20 and the substrate 100 and between adjacent channel layers 20, and the gate structure 190 surrounds the channel layer 20; a source-drain doping layer 210, located in the channel structure layer 170 on both sides of the gate structure 190 and in a partial thickness of the substrate 100; an inversion doping region (not shown), located within the edge of the side wall of the channel layer 20, the inversion doping region is doped with inversion ions 140, and the doping type of the inversion ions 140 is different from the doping type of the source-drain doping layer 210.
[0026] The substrate 100 is used to provide a process platform for forming a semiconductor structure.
[0027] In this embodiment, the semiconductor structure is a gate all around (GAA) transistor as an example for description. In other embodiments, the semiconductor structure may also be a forksheet transistor or a complementary field effect transistor (CFET).
[0028] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium arsenide, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0029] In this embodiment, the semiconductor structure further includes a well region (not shown), which is located in the substrate 100, and the doping type of the well region is different from the doping type of the source-drain doping layer 210. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.
[0030] In this embodiment, the semiconductor structure further includes: an isolation layer (not shown), which is located in the substrate 100 between adjacent device regions and exposes the channel structure layer 170. The isolation layer is used to achieve isolation between adjacent devices.
[0031] In this embodiment, the isolation layer is a shallow trench isolation structure. The material of the isolation layer may include one or more of silicon oxide, silicon oxynitride and silicon nitride.
[0032] In this embodiment, the channel structure layer 170 includes a plurality of channel layers 20 as an example for description, and the plurality of channel layers 20 are stacked and arranged on the substrate 100 in a direction perpendicular to the surface of the substrate 100. In other embodiments, based on actual process requirements, the number of the channel layer can also be one.
[0033] Specifically, the channel layer 20 is used to form a conductive channel of a MOS transistor.
[0034] In this embodiment, an NMOS transistor is formed, and the material of the channel layer 20 is the same as that of the substrate 100, both of which are silicon. In other embodiments, when a PMOS transistor is formed, in order to improve the performance of the PMOS transistor, a silicon germanium channel technology may be used, that is, the material of the channel layer is silicon germanium.
[0035] In other embodiments, based on actual process requirements, other materials may be selected for the channel layer.
[0036] When the device is working, the gate structure 190 is used to control the opening and closing of the conductive channel. Specifically, in this embodiment, the gate structure 190 is formed on the isolation layer.
[0037] In this embodiment, the portion of the gate structure 190 located between the substrate 100 and the channel layer 20 or between adjacent channel layers 20 is the first portion 191 ; the portion of the gate structure 190 spanning the channel structure layer 170 is the second portion 192 .
[0038] In this embodiment, the gate structure 190 is a metal gate structure, and the gate structure 190 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through groove and the gate opening.
[0039] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.
[0040] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.
[0041] The work function layer is used to adjust the work function of the gate structure 190, and then adjust the threshold voltage of the field effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.
[0042] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 190 to an external circuit. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.
[0043] In this embodiment, the semiconductor structure further includes: a gate spacer 125 located on the sidewall of the second portion 192 and used to protect the sidewall of the gate structure 190 .
[0044] In this embodiment, the material of the gate spacer 125 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric or ultra-low-k dielectric material, and the gate spacer 125 is a single-layer or stacked structure. As an example, the gate spacer 125 is a single-layer structure, and the material of the gate spacer 125 is silicon nitride.
[0045] In this embodiment, the semiconductor structure further includes: an inner sidewall 180 , which is located between the first portion 191 and the source-drain doped layer 210 along the extension direction of the channel layer 20 .
[0046] In this embodiment, the inner sidewall 180 is used to achieve isolation between the source-drain doped layer 210 and the gate structure 190 , and also increases the distance between the source-drain doped layer 210 and the gate structure 190 , which is beneficial to reducing the parasitic capacitance between the source-drain doped layer 210 and the gate structure 190 .
[0047] In this embodiment, the material of the inner sidewall 180 is an insulating material to achieve isolation between the source-drain doped layer 210 and the gate structure 190, thereby reducing the parasitic capacitance between the source-drain doped layer 210 and the gate structure 190. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.
[0048] The source-drain doped layer 210 is used as a source or a drain of the MOS transistor. When the MOS transistor is working, the source-drain doped layer 210 is used to provide a carrier source.
[0049] In this embodiment, the material of the source-drain doping layer 210 includes a stress layer doped with ions. When the all-around gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doping ions in the source-drain doping layer 210 are P-type ions; when the all-around gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doping ions in the source-drain doping layer 210 are N-type ions.
[0050] The inversion doping region is located within the edge of the side wall of the channel layer 20, and the inversion doping region is doped with inversion ions 140. The doping type of the inversion ions 140 is different from the doping type of the source-drain doping layer 210. The source-drain doping layer 210 is adjacent to the inversion doping region. The inversion doping region located within the edge of the channel layer 20 can increase the potential barrier of the channel layer 202 adjacent to the side wall of the source-drain doping layer 210, increase the difficulty of the doped ions 140 in the source-drain doping 210 layer to diffuse into the channel layer 20, and correspondingly reduce the probability of the doped ions 140 in the source-drain doping layer 210 to diffuse into the channel layer 20, thereby improving the leakage current between the source-drain doping layer 210 and the channel layer 20 and improving the short channel effect, thereby optimizing the performance of the semiconductor structure.
[0051] Moreover, the inversion doping region is located within the edge of the channel layer 20, which is beneficial to reduce the probability of doping ions in the source and drain doping layer 210 diffusing into the channel layer 20 while avoiding adverse effects on carrier mobility in the channel region when the device is working.
[0052] The doping type of the counter ions 140 is different from the channel conductivity type of the MOS transistor, thereby increasing the inversion doping concentration in the channel layer 20. Specifically, the doping type of the counter ions 140 is the same as the doping type of the well region.
[0053] In this embodiment, when an NMOS transistor is formed, the counter ions 140 are P-type ions, such as boron ions; when a PMOS transistor is formed, the counter ions 140 are N-type ions, such as phosphorus ions.
[0054] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer (not shown) located on the substrate 100 at the side of the gate structure 190 and covering the source-drain doped layer 210. Specifically, in this embodiment, the interlayer dielectric layer is located on the isolation layer and covers the source-drain doped layer 210.
[0055] The interlayer dielectric layer is used to cover the source-drain doped layer 210 and protect the source-drain doped layer 210. The interlayer dielectric layer is also used to achieve electrical isolation between adjacent devices. The material of the interlayer dielectric layer includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer is silicon nitride.
[0056] The semiconductor structure may be formed by the method for forming a semiconductor structure provided by an embodiment of the present invention, or may be formed by other methods.
[0057] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 2 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0058] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.
[0059] refer to Figures 2 to 3 A substrate 100 and one or more sequentially stacked channel stacks 110 located on the substrate 100 are provided, each of the channel stacks 110 includes a sacrificial layer 10 and a channel layer 20 located on the sacrificial layer 10 .
[0060] The substrate 100 is used to provide a process platform for subsequent process steps. In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example for description. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field effect transistor (CFET).
[0061] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium arsenide, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0062] In this embodiment, the channel stack 110 provides a process basis for subsequently forming the channel layer 20 with suspended spacing.
[0063] In this embodiment, the number of the channel stacks 110 is multiple as an example for description, and the stacking direction of the multiple channel stacks on the substrate 100 is perpendicular to the surface of the substrate 100. More specifically, in this embodiment, the number of the channel stacks 110 is three. In other embodiments, the number of the channel stacks may also be two, four, etc. In other embodiments, based on actual process requirements, the number of the channel stacks may also be only one.
[0064] Specifically, the channel layer 20 is used to form a conductive channel of the MOS transistor, and the sacrificial layer 10 is used to support the channel layer 20, thereby providing a process basis for the subsequent realization of the spaced suspended arrangement of the channel layer 20. The sacrificial layer 10 is also used to occupy a spatial position for the subsequent formation of a gate structure.
[0065] In this embodiment, the formation of an NMOS transistor is taken as an example for explanation. The material of the channel layer 20 is the same as that of the substrate 100 , both of which are silicon; and the material of the sacrificial layer 10 is silicon germanium.
[0066] In the subsequent process of removing the sacrificial layer 10, the etching selectivity of silicon germanium and silicon is relatively high. Therefore, by setting the material of the sacrificial layer 10 to silicon germanium and the material of the channel layer 20 to silicon, the effect of the removal process of the sacrificial layer 10 on the channel layer 20 can be effectively reduced, thereby improving the quality of the channel layer 20, which is beneficial to improving device performance.
[0067] In other embodiments, when forming a PMOS transistor, in order to improve the performance of the PMOS transistor, a silicon germanium channel technology may be used, that is, the material of the channel layer is silicon germanium, and the material of the sacrificial layer is silicon.
[0068] In other embodiments, based on actual process requirements, other materials may be selected for the channel layer and the sacrificial layer.
[0069] It should be noted that, in this embodiment, a well region (not shown) is also formed in the substrate 100 and the channel layer 106, and the doping type of the well region is different from the channel conductivity type of the MOS transistor. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.
[0070] As an example, the step of providing the substrate 100 and the channel stack 110 includes:
[0071] like Figure 2 As shown, a substrate 100 is provided.
[0072] like Figure 2 As shown, a well region (not shown) is formed in the substrate 100 , and the doping type of the well region is different from the channel conductivity type of the MOS transistor.
[0073] As an example, the step of forming a well region in the substrate 100 includes: performing ion doping treatment on the substrate 100 ; and performing heat treatment on the substrate 100 to form a well region in the substrate 100 .
[0074] As an example, an ion implantation process is used to perform ion doping treatment on the substrate 100 .
[0075] As an example, an annealing process is used to heat-treat the substrate 100. For example, a rapid thermal annealing process is used to heat-treat the substrate 100.
[0076] like Figure 3 As shown, one or more stacked channel stacks 110 are formed on a substrate 100 .
[0077] As an example, the step of forming one or more stacked channel stacks 110 on the substrate 100 includes: forming one or more stacked channel material stacks (not shown) on the substrate 100, each channel material stack including a sacrificial material layer and a channel material layer located on the sacrificial material layer; performing patterning on the channel material stack, and the remaining channel material stack is used as the channel stack 110.
[0078] In a specific implementation, in the step of patterning the channel material stack, a portion of the thickness of the substrate 100 may also be patterned so that the substrate 100 in the adjacent device area forms a groove (not shown). The groove is used to define the isolation area between adjacent devices so as to provide a spatial position for forming an isolation layer in the groove.
[0079] Correspondingly, in this embodiment, the step of providing a substrate may further include: forming an isolation layer (not shown) in the trench, wherein the isolation layer exposes the channel stack 110 .
[0080] The isolation layer is used to isolate adjacent devices. In this embodiment, the isolation layer is a shallow trench isolation structure. The material of the isolation layer may include one or more of silicon oxide, silicon oxynitride and silicon nitride.
[0081] refer to Figure 4 , a dummy gate structure 120 is formed on the substrate 100 and crosses the channel stack 110 .
[0082] The dummy gate structure 120 is used to pre-occupy a space position for the subsequent formation of the gate structure. Specifically, in this embodiment, the dummy gate structure 120 is formed on the isolation layer and across the channel stack 110 , and the dummy gate structure 120 covers part of the top and part of the sidewall of the channel stack 110 .
[0083] In this embodiment, the dummy gate structure 120 includes a dummy gate oxide layer 121 and a dummy gate layer 122 located on the dummy gate oxide layer 121. In this embodiment, the material of the dummy gate oxide layer 121 includes one or more of silicon oxide and silicon oxynitride. In this embodiment, the material of the dummy gate layer 122 includes polysilicon or amorphous silicon.
[0084] In a specific implementation, a dummy gate mask layer 135 is further formed on the top of the dummy gate layer 122. The dummy gate mask layer is used as an etching mask for patterning the dummy gate material layer to form the dummy gate structure 120.
[0085] As an example, the material of the dummy gate mask layer 135 is silicon nitride.
[0086] In this embodiment, after forming the dummy gate structure 120 , the method for forming a semiconductor structure further includes: forming a gate spacer 125 on the sidewall of the dummy gate structure 120 .
[0087] The gate sidewall 125 is used together with the dummy gate layer 122 and the dummy gate mask layer 135 as an etching mask for the subsequent formation of source and drain grooves to define the formation position of the source and drain doping layers. The gate sidewall 125 is also used to protect the dummy gate layer 122 and the sidewalls of the subsequent gate structure.
[0088] The material of the gate spacer 125 is an insulating dielectric material. In this embodiment, the material of the gate spacer 125 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric or ultra-low-k dielectric material, and the gate spacer 125 is a single-layer or stacked structure. As an example, the gate spacer 125 is a single-layer structure, and the material of the gate spacer 125 is silicon nitride.
[0089] refer to Figure 5 , counter ions 140 are doped in the channel stack 110 on both sides of the dummy gate structure 120 , and the doping type of the counter ions 140 is different from the channel conductivity type of the MOS transistor.
[0090] Inversion ions 140 are doped in the channel stack 110 on both sides of the dummy gate structure 120 so that after the channel stack 110 on both sides of the dummy gate structure 120 is subsequently removed to form source and drain grooves, the remaining inversion ions within the edge of the channel layer 20 located on the sidewalls of the source and drain grooves can form an inversion doping region.
[0091] The doping type of the counter ions 140 is different from the channel conductivity type of the MOS transistor, thereby increasing the inversion doping concentration in the channel layer 20. Specifically, the doping type of the counter ions 140 is the same as the doping type of the well region.
[0092] In this embodiment, when an NMOS transistor is formed, the counter ions 140 are P-type ions, such as boron ions; when a PMOS transistor is formed, the counter ions 140 are N-type ions, such as phosphorus ions.
[0093] In this embodiment, an ion implantation process is used to dope the counter ions 140 in the channel stack 110 on both sides of the dummy gate structure 120. The ion implantation process can easily control the ion doping concentration and doping depth in the substrate 100 by controlling the energy, dose, implantation angle and number of implantations, thereby making it easy to make the doping concentration, doping depth and doping profile of the counter ions 140 in the substrate 100 meet the process requirements.
[0094] In this embodiment, an ion implantation process is adopted, and the step of doping inversion ions 140 in the channel stack 110 on both sides of the dummy gate structure 120 includes: performing a first ion implantation on the channel stack 110 on both sides of the dummy gate structure 120, the first ion implantation having a first implantation depth; performing a second ion implantation on the channel stack 110 on both sides of the dummy gate structure 120, the second ion implantation having a second implantation depth, the second implantation depth being less than the first implantation depth; performing a third ion implantation on the channel stack 110 on both sides of the dummy gate structure 120, the third ion implantation having a third implantation depth, the third implantation depth being less than the second implantation depth.
[0095] By sequentially performing ion implantation at different depths, it is possible to ensure that the inversion ions 140 are implanted in each channel layer 20, and to improve the uniformity of the distribution of the inversion ions 140 in the channel layer, thereby ensuring that the inversion doping regions subsequently formed in each channel layer can all play a role in reducing the probability of the doped ions in the source and drain doping layers diffusing into the channel layers.
[0096] In particular, in this embodiment, there are multiple channel stacks 110. By sequentially performing ion implantation at different depths, it is possible to ensure that counter ions are implanted into the channel layers 20 in each channel stack 110 and improve the distribution uniformity of the counter ions 140 in each channel layer 20.
[0097] In this embodiment, the first ion implantation is used to implant counter ions 140 into the channel stack 110 adjacent to the substrate 100 .
[0098] The implantation dose of the first ion implantation should not be too low or too high. If the implantation dose of the first ion implantation is too low, it is easy to cause the doping concentration of the counter ion 140 in the channel stack 110 adjacent to the substrate 100 to be too low; if the implantation dose of the first ion implantation is too high, it is easy to increase the risk of the counter ion 140 diffusing into the substrate 100. For this reason, in this embodiment, when forming an NMOS transistor, the counter ion 140 includes boron ions, and the implantation dose of the first ion implantation is 1e13 atoms per square centimeter to 5e13 atoms per square centimeter; when forming a PMOS transistor, the counter ion 140 includes phosphorus ions, and the implantation dose of the first ion implantation is 1e13 atoms per square centimeter to 5e13 atoms per square centimeter.
[0099] The injection energy of the first ion injection should not be too low or too high. If the injection energy of the first ion injection is too low, it is easy to cause the injection depth of the first ion injection to be too low, which in turn increases the difficulty of injecting the counter ion 140 into the channel stack 110 adjacent to the substrate 100; if the injection energy of the first ion injection is too high, it increases the risk of injecting the counter ion 140 into the substrate 100, and easily causes excessive lattice damage. For this reason, in this embodiment, when forming an NMOS transistor, the counter ions include boron ions, and the injection energy of the first ion injection is 20KeV to 60KeV; when forming a PMOS transistor, the counter ions include phosphorus ions, and the injection energy of the first ion injection is 50KeV to 150KeV.
[0100] The injection angle of the first ion injection should not be too large, otherwise it is easy to reduce the injection efficiency of the first ion injection, and it is also easy to cause the injection distance of the counter ion 140 in the channel layer 20 along the channel length direction to be too deep, thereby easily increasing the risk of affecting the carrier mobility when the device is working. For this reason, in this embodiment, the injection angle of the first ion injection is 0° to 5°.
[0101] In this embodiment, the implantation angle refers to the angle between the ion implantation direction and the surface normal direction of the substrate 100 .
[0102] In this embodiment, the second ion implantation is used to implant the counter ions 140 into the middle number of channel stacks 110. The middle number of channel stacks 110 refers to the channel stacks 110 that are neither adjacent to the substrate 100 nor located at the top layer.
[0103] The implantation dose of the second ion implantation should not be too low or too high. If the implantation dose of the second ion implantation is too low, it is easy to cause the doping concentration of the counter ions 140 in the channel stack 110 of the middle number of layers to be too low; if the implantation dose of the second ion implantation is too high, it is easy to increase the risk of the counter ions 140 diffusing into the channel layer 20 along the channel length direction, and then it is easy to increase the risk of affecting the carrier mobility when the device is working. For this reason, in this embodiment, when forming an NMOS transistor, the counter ions include boron ions, and the implantation dose of the second ion implantation is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter; the implantation dose of the second ion implantation is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter.
[0104] The injection energy of the second ion injection should not be too low or too high. If the injection energy of the second ion injection is too low, it is easy to cause the injection depth of the second ion injection to be too low, which in turn increases the difficulty of injecting the counter ion 140 into the channel stack 110 of the middle number of layers; if the injection energy of the second ion injection is too high, it is easy to increase the risk of causing excessive lattice damage. For this reason, in this embodiment, when forming an NMOS transistor, the counter ions include boron ions, and the injection energy of the second ion injection is 10KeV to 20KeV; when forming a PMOS transistor, the counter ions include phosphorus ions, and the injection energy of the second ion injection is 20KeV to 50KeV.
[0105] The injection angle of the second ion injection should not be too large, otherwise it is easy to reduce the injection efficiency of the second ion injection, and it is also easy to cause the injection distance of the counter ion 140 in the channel layer 20 along the channel length direction to be too deep, thereby easily increasing the risk of affecting the carrier mobility when the device is working. For this reason, in this embodiment, the injection angle of the second ion injection is 0° to 5°.
[0106] In this embodiment, the third ion implantation is used to implant the counter ions 140 into the topmost channel stack 110 .
[0107] The implantation dose of the third ion implantation should not be too low or too high. If the implantation dose of the third ion implantation is too low, it is easy to cause the doping concentration of the counter ions 140 in the topmost channel stack 110 to be too low; if the implantation dose of the third ion implantation is too high, it is easy to increase the risk of the counter ions 140 diffusing into the channel layer 20 along the channel length direction, and then it is easy to increase the risk of affecting the carrier mobility when the device is working. For this reason, in this embodiment, when forming an NMOS transistor, the counter ions include boron ions, and the implantation dose of the third ion implantation is 2e12 atoms per square centimeter to 1e13 atoms per square centimeter; when forming a PMOS transistor, the counter ions include phosphorus ions, and the implantation dose of the third ion implantation is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter.
[0108] The injection energy of the third ion injection should not be too low or too high. If the injection energy of the third ion injection is too low, it is easy to reduce the uniformity of the doping distribution of the counter ions 140 in the channel stack 110; if the injection energy of the third ion injection is too high, it is easy to cause the injection depth in the channel stack 110 to be too large, which in turn easily leads to too few counter ions 140 injected into the topmost channel stack 110, and easily increases the risk of causing excessive lattice damage. For this reason, in this embodiment, when forming an NMOS transistor, the counter ions 140 include boron ions, and the injection energy of the third ion injection is 2KeV to 10KeV; when forming a PMOS transistor, the counter ions 140 include phosphorus ions, and the injection energy of the third ion injection is 5KeV to 20KeV.
[0109] The injection angle of the third ion injection should not be too large, otherwise it is easy to reduce the injection efficiency of the third ion injection, and it is also easy to cause the injection distance of the counter ion 140 in the channel layer 20 along the channel length direction to be too deep, thereby easily increasing the risk of affecting the carrier mobility when the device is working. For this reason, in this embodiment, the injection angle of the third ion injection is 0° to 5°.
[0110] In other embodiments, the counter ions may be doped by other times of ion implantation.
[0111] In some other embodiments, the sequence of the first ion implantation, the second ion implantation and the third ion implantation can be adjusted.
[0112] refer to Figure 6In this embodiment, the method for forming the semiconductor structure further includes: after doping the channel stack 110 on both sides of the dummy gate structure 120 with counter ions 140 and before removing the channel stack 110 on both sides of the dummy gate structure 120 to form source and drain grooves, performing heat treatment 200 to diffuse the counter ions 140 into the channel stack 110 at the bottom of the dummy gate structure 120.
[0113] A heat treatment 200 is performed to diffuse the inversion ions 140 into the channel stack 110 at the bottom of the pseudo gate structure 120, so that after the channel stack 110 on both sides of the pseudo gate structure 120 is removed to form the source-drain grooves, the remaining inversion ions 140 located in the edge of the channel layer 20 on the sidewalls of the source-drain grooves can be retained to form an inversion doping region, and the concentration and concentration of the inversion ions 140 in the edge of the channel layer 20 can be increased, thereby improving the effect of the inversion doping region on reducing the probability of the doped ions in the source-drain doping layer diffusing into the channel layer 20.
[0114] On the other hand, the heat treatment 200 is also used to activate the counter ions 140 and repair the lattice damage caused to the substrate 100 .
[0115] It should be noted that in the step of performing the heat treatment 200, the temperature of the heat treatment 200 should not be too low or too high. If the temperature of the heat treatment 200 is too low, it is easy to cause the diffusion rate of the counter ions to be too slow, and it is also easy to reduce the activation effect of the counter ions 140 and the repair effect of the lattice damage; if the temperature of the heat treatment 200 is too high, it is easy to cause the diffusion rate of the counter ions 140 to be too fast, which is not only easy to cause the distribution concentration of the counter ions 140 at the edge of the channel layer 20 to decrease, thereby reducing the subsequent blocking effect of the counter doping region on the diffusion of the doped ions in the source and drain doping layer into the channel layer 20, but also easily increases the risk of the counter ions 140 causing adverse effects on the carrier mobility of the device. For this reason, in this embodiment, the temperature of the heat treatment 200 is 800°C to 1000°C.
[0116] It should also be noted that in the step of performing the heat treatment 200, the process time of the heat treatment 200 should not be too short or too long. If the process time of the heat treatment 200 is too short, it is easy to cause the diffusion distance of the counter ions 140 to be too small, and it is also easy to reduce the activation effect of the counter ions 140 and reduce the repair effect of the lattice damage; if the process time of the first heat treatment 200 is too long, it is easy to increase the probability of the counter ions diffusing into the channel layer 20, which is not only easy to cause the distribution concentration of the counter ions 140 at the edge of the channel layer 20 to decrease, but also easy to increase the risk of the counter ions 140 causing adverse effects on the carrier mobility of the device, and it is also easy to cause a waste of work time. For this reason, in this embodiment, the process time of the heat treatment 200 is 10 seconds to 60 seconds.
[0117] It should also be noted that in the step of performing the heat treatment 200, the ramp rate should not be too low or too high. If the ramp rate is too low, the gradient of the temperature change is small, which may easily lead to a too long time required for the heat treatment 200; if the ramp rate is too high, it may easily lead to a too slow diffusion rate of the counter ion 140. For this reason, in this embodiment, the ramp rate of the heat treatment 200 is 25°C / second to 80°C / second.
[0118] In this embodiment, an annealing process is used to perform the heat treatment 200 .
[0119] As an example, the heat treatment 200 is performed by using a rapid thermal annealing process.
[0120] refer to Figure 7 , the channel stack 110 on both sides of the dummy gate structure 120 is removed to form a source-drain groove 160, and the remaining inversion ions 140 located in the edge of the channel layer 20 on the sidewall of the source-drain groove 160 are used to form an inversion doping region (not shown).
[0121] The source-drain grooves 160 are used to provide a space for the subsequent formation of source-drain doping layers.
[0122] In this embodiment, the inversion doping region is formed within the edge of the channel layer 20, which is beneficial for reducing the probability of doping ions in the source and drain doping layers diffusing into the channel layer while avoiding adverse effects on carrier mobility in the channel region when the device is operating.
[0123] As an example, the step of forming the source-drain groove 160 includes: using an anisotropic dry etching process to etch the channel stack 110 exposed by the dummy gate structure 120 to form the source-drain groove 160 .
[0124] The anisotropic dry etching process has anisotropic etching characteristics, which is beneficial to improving the profile control of forming the source-drain groove 160. The dry etching process has high etching accuracy and fast etching rate. The dry etching process is easy to achieve a higher etching selectivity ratio, which is beneficial to reducing the probability of damage to other film layer structures in the process of forming the source-drain groove 160.
[0125] refer to Figure 8 , a source-drain doping layer 210 is formed in the source-drain groove 160 , and the source-drain doping layer 210 is adjacent to the inversion doping region.
[0126] The source-drain doping layer 210 is adjacent to the inversion doping region. The inversion doping region located within the edge of the channel layer 20 can increase the potential barrier of the channel layer 20 adjacent to the side wall of the source-drain doping layer 210, increase the difficulty of the doped ions in the source-drain doping layer 210 diffusing into the channel layer 20, and correspondingly reduce the probability of the doped ions in the source-drain doping layer 210 diffusing into the channel layer 20, thereby improving the leakage current between the source-drain doping layer 210 and the channel layer 20 and improving the short channel effect, thereby optimizing the performance of the semiconductor structure.
[0127] In this embodiment, an epitaxial process is adopted to form the stress layer, and ions are self-doped in situ during the process of forming the stress layer. The stress layer doped with ions is used as the source-drain doping layer 210 .
[0128] Specifically, based on the substrate 100 and the channel layer 20 exposed by the source-drain grooves 160 , epitaxial growth is performed to form the source-drain doped layer 210 .
[0129] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 210 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SIC, and the doped ions in the source and drain doping layer 210 are N-type ions.
[0130] In this embodiment, the method for forming a semiconductor structure also includes: after forming the source-drain groove 160 and before forming the source-drain doping layer 210, laterally etching a portion of the sacrificial layer 10 exposed on the side wall of the source-drain groove 160 in a direction parallel to the substrate 100 and perpendicular to the extension direction of the dummy gate structure 120 to form an inner groove (not shown), the inner groove is surrounded by the adjacent channel layer 20 and the remaining sacrificial layer 10, or the inner groove is surrounded by the substrate 100, the channel layer 20 adjacent to the substrate 100 and the remaining sacrificial layer 10; forming an inner sidewall 180 in the inner groove.
[0131] Specifically, the inner groove provides a spatial location for forming the inner side wall.
[0132] In this embodiment, the process of laterally etching the portion of the sacrificial layer 10 exposed along the sidewall of the source-drain groove 160 includes an isotropic etching process. The isotropic etching process has the characteristics of isotropic etching, and is easy to achieve a large etching selectivity, so that the portion of the sacrificial layer 10 exposed along the sidewall of the source-drain groove 160 can be laterally etched, which is conducive to reducing the difficulty of etching the sacrificial layer 10 and reducing the probability of damage to other film structures.
[0133] Subsequently, a source-drain doped layer is formed in the source-drain groove 160, and a gate structure is formed at the position of the pseudo-gate structure 120 and the sacrificial layer 10. The inner sidewall 180 is used to achieve isolation between the source-drain doped layer and the gate structure, and also to increase the distance between the source-drain doped layer and the gate structure, which is beneficial to reducing the parasitic capacitance between the source-drain doped layer and the gate structure.
[0134] In this embodiment, the material of the inner sidewall 180 is an insulating material to achieve isolation between the source and drain doping layers and the gate structure. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.
[0135] refer to Fig. 9 In this embodiment, the method for forming a semiconductor structure further includes: after forming a source-drain doped layer 210, forming an interlayer dielectric layer (not shown) on the substrate 100 at the side of the dummy gate structure 120, the interlayer dielectric layer covers the source-drain doped layer 210 and exposes the top of the dummy gate structure 111; removing the dummy gate structure 120, forming a gate opening (not shown) in the interlayer dielectric layer, exposing the channel stack 110; removing the sacrificial layer 10 exposed by the gate opening, forming a through groove (not shown), the through groove being connected to the gate opening; filling the gate opening and the through groove with a gate structure 190, the gate structure 190 surrounding the channel layer 20.
[0136] The interlayer dielectric layer is used to cover the source-drain doped layer 210, and plays a role in protecting the source-drain doped layer 210 when the gate opening is subsequently formed. The interlayer dielectric layer is also used to achieve electrical isolation between adjacent devices. The material of the interlayer dielectric layer includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer is silicon nitride.
[0137] Specifically, in this embodiment, the interlayer dielectric layer is formed on the isolation layer and covers the source-drain doped layer 210 .
[0138] The gate opening and the through groove are used to provide a spatial location for forming a gate structure.
[0139] After removing the sacrificial layer, one or more channel layers 20 are suspended and arranged at intervals, so that the subsequent gate structure can surround the channel layer 20. Among them, one or more channel layers 20 that are suspended and arranged at intervals in sequence are used to form a channel structure layer 170.
[0140] When the device is operating, the gate structure 190 is used to control the opening and closing of the conductive channel.
[0141] In this embodiment, the portion of the gate structure 190 located between the substrate 100 and the channel layer 20 or between adjacent channel layers 20 is the first portion 191 ; the portion of the gate structure 190 spanning the channel structure layer 170 is the second portion 192 .
[0142] In this embodiment, the gate structure 190 is a metal gate structure, and the gate structure 190 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through groove and the gate opening.
[0143] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.
[0144] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.
[0145] The work function layer is used to adjust the work function of the gate structure 190, and then adjust the threshold voltage of the field effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.
[0146] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 190 to an external circuit. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.
[0147] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A channel structure layer is suspended on the substrate, and the channel structure layer includes one or more channel layers sequentially arranged from bottom to top; A gate structure, spanning the channel structure layer, the gate structure is filled between the channel layer and the substrate and between adjacent channel layers, and the gate structure surrounds the channel layer; Source and drain doping layers are located in the channel structure layer on both sides of the gate structure and in a portion of the thickness of the substrate; The inversion doping region is located in the edge of the side wall of the channel layer, and the inversion doping region is doped with inversion ions, and the doping type of the inversion ions is different from the doping type of the source and drain doping layers.
2. The semiconductor structure according to claim 1, wherein: When an NMOS transistor is formed, the counter ions are P-type ions; when a PMOS transistor is formed, the counter ions are N-type ions.
3. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a well region located in the substrate, wherein the doping type of the well region is different from the doping type of the source and drain doping layers.
4. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate and one or more sequentially stacked channel stacks located on the substrate, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure across the channel stack on the substrate; doping anti-type ions in the channel stacks on both sides of the pseudo-gate structure, wherein the doping type of the anti-type ions is different from the channel conductivity type of the MOS transistor; Removing the channel stack on both sides of the dummy gate structure to form source-drain grooves, and the remaining inversion ions located in the edge of the channel layer on the sidewalls of the source-drain grooves are used to form an inversion doping region; A source-drain doping layer is formed in the source-drain groove, and the source-drain doping layer is adjacent to the inversion doping region.
5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the semiconductor structure also includes: after doping the channel stacks on both sides of the dummy gate structure with inversion ions, and before removing the channel stacks on both sides of the dummy gate structure to form source and drain grooves, performing heat treatment to diffuse the inversion ions into the channel stacks at the bottom of the dummy gate structure.
6. The method for forming a semiconductor structure according to claim 5, wherein: The process parameters for the heat treatment include: a process temperature of 800° C. to 1000° C., a process time of 10 seconds to 60 seconds, and a temperature change rate of 25° C. / second to 80° C. / second.
7. The method for forming a semiconductor structure according to claim 4, wherein: When an NMOS transistor is formed, the counter ions are P-type ions; when a PMOS transistor is formed, the counter ions are N-type ions.
8. The method for forming a semiconductor structure according to claim 4, wherein: An ion implantation process is used to dope anti-type ions in the channel stacks on both sides of the pseudo-gate structure.
9. The method for forming a semiconductor structure according to claim 8, wherein: The step of doping inversion ions in the channel stacks on both sides of the dummy gate structure by using an ion implantation process comprises: performing a first ion implantation on the channel stacks on both sides of the dummy gate structure, wherein the first ion implantation has a first implantation depth; Performing a second ion implantation on the channel stacks on both sides of the dummy gate structure, wherein the second ion implantation has a second implantation depth, and the second implantation depth is less than the first implantation depth; A third ion implantation is performed on the channel stacks on both sides of the dummy gate structure, wherein the third ion implantation has a third implantation depth, and the third implantation depth is less than the second implantation depth.
10. The method for forming a semiconductor structure according to claim 9, wherein: The process parameters of the first ion implantation include: When forming an NMOS transistor, the counter ions include boron ions, the implantation dose is 1e13 atoms per square centimeter to 5e13 atoms per square centimeter, the implantation energy is 20 KeV to 60 KeV, and the implantation angle is 0° to 5°; When forming a PMOS transistor, the counter ions include phosphorus ions, the implantation dose is 1e13 atoms per square centimeter to 5e13 atoms per square centimeter, the implantation energy is 50 KeV to 150 KeV, and the implantation angle is 0° to 5°.
11. The method for forming a semiconductor structure according to claim 9, wherein: The process parameters of the second ion implantation include: When forming an NMOS transistor, the counter ions include boron ions, the implantation dose is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter, the implantation energy is 10 KeV to 20 KeV, and the implantation angle is 0° to 5°; When forming a PMOS transistor, the counter ions include phosphorus ions, the implantation dose is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter, the implantation energy is 20 KeV to 50 KeV, and the implantation angle is 0° to 5°.
12. The method for forming a semiconductor structure according to claim 9, wherein: The process parameters of the third ion implantation include: When forming an NMOS transistor, the counter ions include boron ions, the implantation dose is 2e12 atoms per square centimeter to 1e13 atoms per square centimeter, the implantation energy is 2KeV to 10KeV, and the implantation angle is 0° to 5°; When forming a PMOS transistor, the counter ions include phosphorus ions, the implantation dose is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter, the implantation energy is 5KeV to 20KeV, and the implantation angle is 0° to 5°.
13. The method for forming a semiconductor structure according to claim 4, wherein: The step of providing a substrate and one or more sequentially stacked channel stacks on the substrate comprises: providing a substrate; forming the one or more stacked channel stacks on the substrate; The method for forming the semiconductor structure further comprises: after providing the substrate and before forming the channel stack, forming a well region in the substrate, wherein the doping type of the well region is different from the channel conductivity type of the MOS tube.
14. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the semiconductor structure also includes: after forming the source-drain doping layer, removing the dummy gate structure to form a gate opening to expose the channel stack; removing the sacrificial layer exposed by the gate opening to form a through groove, wherein the through groove is connected to the gate opening; and filling the gate opening and the through groove with a gate structure, wherein the gate structure surrounds the channel layer.