Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device of the present disclosure includes: a first transistor having a first substrate and a first gate; a second transistor having a second substrate and a second gate; the interval dielectric layer is arranged between the first substrate and the second grid electrode, and the bottom of the first substrate and the top of the second grid electrode are integrated together through the interval dielectric layer. According to the semiconductor device, after the bottom of the first substrate and the top of the second grid electrode are bonded together through the interval dielectric layer, the interval dielectric layer is post-processed through the annealing process and / or the ultraviolet irradiation process, stress of different properties is obtained in the interval dielectric layer, and improvement of the semiconductor device in the aspects of stress and performance is balanced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] like Figure 1 As shown in FIG. 1 , the field effect transistor (FET) structure has undergone the development of a planar FET, a fin FET, and a gate-all-around FET (GAAFET).

[0003] As the feature size of integrated circuits continues to shrink, traditional three-gate or dual-gate FinFETs are limited at nodes below 3nm. GAAFET, which is compatible with the mainstream high-k metal gate FinFET process, will be the next-generation key structure to achieve size shrinkage. Its channel is mainly a stacked nanosheet structure.

[0004] However, as the size of GAAFET devices continues to shrink, the volume of original stress sources including source / drain, contact etch stop layer (CESL), and metal gradually decreases, resulting in a decrease in the effect of stress and a decrease in device performance improvement. Summary of the invention

[0005] The purpose of the present disclosure is to provide a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device.

[0006] A first aspect of the present disclosure provides a semiconductor device, comprising:

[0007] A first transistor having a first substrate and a first gate;

[0008] a second transistor having a second substrate and a second gate;

[0009] The spacer dielectric layer is arranged between the first substrate and the second gate, and the bottom of the first substrate and the top of the second gate are integrated together through the spacer dielectric layer.

[0010] In a possible implementation, the material for making the spacer dielectric layer includes one or more of SiNx, SiC, SiCN, SiOCN, SiOC, SiON, BN, SiBN, SiBCN, aC, SOG, and polymer.

[0011] In a possible implementation manner, the thickness of the spacer dielectric layer is between 10 nm and 10 μm.

[0012] In a possible implementation, both the first transistor and the second transistor are gate-all-around (GAA) transistors.

[0013] In a possible implementation manner, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

[0014] In a possible implementation manner, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0015] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0016] Providing a first substrate, and forming a first transistor on the first substrate;

[0017] Providing a second substrate, forming a second transistor on the second substrate, wherein a top of the second transistor has a second gate;

[0018] Depositing a spacer dielectric layer at the bottom of the first substrate;

[0019] Bonding the top of the second gate to the spacer dielectric layer;

[0020] The spacer dielectric layer is post-processed by a preset annealing process and / or an ultraviolet light irradiation process to apply stress.

[0021] A third aspect of the present disclosure provides an electronic device, comprising the semiconductor device described in the first aspect.

[0022] The advantages of the present invention compared with the prior art are:

[0023] The semiconductor device disclosed in the present invention includes a first transistor having a first substrate and a first gate; a second transistor having a second substrate and a second gate; and a spacing dielectric layer disposed between the first substrate and the second gate, wherein the bottom of the first substrate and the top of the second gate are bonded together through the spacing dielectric layer. After the bottom of the first substrate and the top of the second gate are integrated together through the spacing dielectric layer, the present application further performs post-processing on the spacing dielectric layer through a preset annealing process and / or ultraviolet light irradiation process, thereby obtaining stresses of different properties in the spacing dielectric layer, so that the improvement of the stress and performance of the semiconductor device is balanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present disclosure. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0025] Figure 1 The schematic diagrams of structures of various existing field effect transistors are shown;

[0026] Figure 2 A schematic diagram of the structure of an existing complementary field effect transistor is shown;

[0027] Figure 3 A structural diagram of a semiconductor device provided by the present disclosure is shown;

[0028] Figure 4 A flow chart of a method for manufacturing a semiconductor device provided by the present disclosure is shown;

[0029] FIG. 5A to FIG. 5I It is a schematic diagram of the structure formed at various stages of the fabrication of the gate-all-around transistor;

[0030] Figure 6 A schematic diagram of the structure formed after the ring-gate transistor substrate provided by the present disclosure is thinned and a spacer dielectric layer is deposited is shown. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0032] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0033] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist between them. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0034] like Figure 2As shown in Figure 1, the complementary field effect transistor (CFET) in GAAFET combines PMOS and NMOS together, making the switching speed and driving capability complementary, thereby improving the overall performance of the transistor. However, in CFET, there is an imbalance in N / PFET performance. Therefore, for the study of CFET, stress improvement and performance balance have become an important topic.

[0035] In order to solve the above problems existing in the prior art, the embodiments of the present disclosure provide a semiconductor device, a method for manufacturing a semiconductor device and an electronic device, which are described below with reference to the accompanying drawings.

[0036] Figure 3 A structural diagram of a semiconductor device provided by the present disclosure is shown; Figure 3 The middle left figure is a cross-sectional view of the semiconductor device along the X direction; Figure 3 The middle right figure is a cross-sectional view of the semiconductor device along the Y direction.

[0037] Please refer to Figure 3 The semiconductor device includes: a first transistor 100, a spacer dielectric layer 300 and a second transistor 200 which are arranged in sequence in a vertical direction.

[0038] The first transistor 100 has a first substrate 110 and a first gate 120 .

[0039] The second transistor 200 has a second substrate 210 and a second gate 220 .

[0040] Specifically, the first transistor 100 and the second transistor 200 are both gate-all-around (GAA) transistors. For example, the semiconductor device may be a CFET.

[0041] In some embodiments, the first transistor 100 may be an NMOS transistor, and the second transistor 200 may be a PMOS transistor.

[0042] In some other embodiments, the first transistor 100 may be a PMOS transistor, and the second transistor 200 may be an NMOS transistor.

[0043] The spacer dielectric layer 300 is disposed between the first substrate 110 and the second gate 220 , and the bottom of the first substrate 110 and the top of the second gate 220 are integrated together through the spacer dielectric layer 300 .

[0044] After bonding the bottom of the first substrate 110 and the top of the second gate 220 together through the spacing dielectric layer 300, the present application further post-processes the spacing dielectric layer 300 through a preset annealing process and / or ultraviolet light irradiation process or other post-processing methods, thereby obtaining stresses (tensile or compressive) of different properties in the spacing dielectric layer 300, thereby achieving a balance between the stress and performance improvements of the semiconductor device.

[0045] It can be seen that if the conductor device is a CFET, the present application uses the spacer dielectric layer in the CFET to achieve the wafer-level stress application effect. The N / PFET in the CFET can be located at the top or bottom, respectively, and different processing methods can be selected according to different positions to achieve performance balance and improvement.

[0046] In some embodiments, the material used to make the spacer dielectric layer 300 can be an insulating material, which can specifically include one or more insulating materials such as silicon nitride (SiNx), silicon carbide (SiC), silicon carbide nitride (SiCN), silicon carbon oxide nitride (SiOCN), silicon carbon oxide (SiOC), silicon oxynitride (SiON), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiBCN), amorphous carbon (aC), silicon-glass bonding structure (Silicon On Glass, SOG), and polymers.

[0047] In some embodiments, the thickness of the spacer dielectric layer is between 10 nm and 10 μm.

[0048] Please refer to Figure 4 , the embodiment of the present disclosure also provides a method for manufacturing a semiconductor device, which is used to prepare the semiconductor device in the above embodiment; FIG. 5A to FIG. 5I It is a schematic diagram of the structure formed at various stages of the ring gate transistor production.

[0049] The method for manufacturing the semiconductor device comprises the following steps:

[0050] Step S101 : providing a first substrate 110 , and forming a first transistor 100 on the first substrate 110 ; a first gate 120 is provided on the top of the first transistor 100 .

[0051] Step S102: providing a second substrate 210, forming a second transistor 200 on the second substrate 210, wherein the second transistor 200 has a second gate 220 on its top;

[0052] Specifically, the first transistor 100 and the second transistor 200 are both GAAFETs.

[0053] Specifically, the manufacturing process of GAAFET first deposits ultra-thin alternating layers of silicon germanium (SiGe) and silicon (Si) on a silicon substrate to form a super-lattice structure with multiple layers of each material. The sheet is exposed and etched in the super-lattice structure. Then the internal spacer is formed; when the sidewalls are etched, the surface of the silicon germanium layer in the super-lattice structure is partially recessed and then filled with dielectric material. Then the source and drain are formed; the silicon germanium layer in the super-lattice structure is removed, leaving a silicon-based sheet, which is the channel. Finally, the gate is formed by depositing high-k (high dielectric constant) dielectric and metal gate materials.

[0054] For details, please refer to FIG. 5A to FIG. 5I , FIG. 5A to FIG. 5I The left figure is a cross-sectional view of the semiconductor device along the X direction, and the right figure is a cross-sectional view of the semiconductor device along the Y direction.

[0055] Figure 5A The figure shows the formation of SiGe / Si stacked epitaxy on a silicon substrate. Figure 5B Shown in Figure 5A Fin is formed on the basis of. Figure 5C Shown in Figure 5B Shallow trench isolation (STI) is performed on the basis of the silicon nitride mask, specifically, a trench is formed by depositing, patterning, and etching silicon, and the trench is filled with deposited oxide for isolation from the silicon substrate. Figure 5D Shown in Figure 5C A polysilicon false gate is formed on the basis of Figure 5E Shown in Figure 5D forming side walls on the basis of Fig. 5F Shown in Figure 5E The source and drain are etched on this basis. Figure 5G Shown in Fig. 5F The inner wall is formed on the basis of Figure 5H Shown in Figure 5G The source and drain are formed epitaxially on this basis. Figure 5H Shown in Figure 5G A source and a drain are formed epitaxially on the basis of the silicon germanium doped with boron (SiGe:B) or germanium doped with boron (Ge:B). Fig.5I Shown in Figure 5H Channel release is performed on the basis of and a high-k metal gate (HKMG) is formed.

[0056] In some embodiments, the first transistor 100 may be an NMOS transistor, and the second transistor 200 may be a PMOS transistor.

[0057] In some other embodiments, the first transistor 100 may be a PMOS transistor, and the second transistor 200 may be an NMOS transistor.

[0058] Step S103: depositing a spacer dielectric layer 300 at the bottom of the first substrate 110;

[0059] Specifically, the first substrate 110 and the second substrate 210 may be thinned to a set thickness, and then the spacer dielectric layer 300 may be formed by deposition. Figure 6 As shown, the silicon substrate can be thinned, and then silicon nitride deposition is performed to form the spacer dielectric layer 300 .

[0060] In some embodiments, the material used to make the spacer dielectric layer 300 can be an insulating material, which can specifically include one or more insulating materials such as silicon nitride (SiNx), silicon carbide (SiC), silicon carbide nitride (SiCN), silicon carbon oxide nitride (SiOCN), silicon carbon oxide (SiOC), silicon oxynitride (SiON), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiBCN), amorphous carbon (aC), silicon-glass bonding structure (Silicon On Glass, SOG), and polymers.

[0061] In some embodiments, the thickness of the spacer dielectric layer is between 10 nm and 10 μm.

[0062] Step S104: bonding the top of the second gate 220 to the spacer dielectric layer 300;

[0063] Step S105: performing post-processing on the spacer dielectric layer 300 through a preset annealing process and / or ultraviolet light irradiation process to apply stress.

[0064] Specifically, after bonding the first transistor 100 and the second transistor 200 of the thinned substrate together with the dielectric layer 300, the dielectric layer 300 is post-processed by annealing processes and / or ultraviolet irradiation processes under different atmospheres to obtain stresses of different properties. Stresses of different properties can have different stress effects such as tension or compression to improve the performance of semiconductor devices, so that the improvement of stress and performance of semiconductor devices is balanced.

[0065] The present disclosure also provides an electronic device, which includes the semiconductor device in the above embodiment. The semiconductor device can be incorporated into at least one of a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a mobile power supply.

[0066] Please refer to Figure 3The semiconductor device includes: a first transistor 100, a spacer dielectric layer 300 and a second transistor 200 which are arranged in sequence in a vertical direction.

[0067] The first transistor 100 has a first substrate 110 and a first gate 120 .

[0068] The second transistor 200 has a second substrate 210 and a second gate 220 .

[0069] Specifically, the first transistor 100 and the second transistor 200 are both gate-all-around (GAA) transistors. For example, the semiconductor device may be a CFET.

[0070] In some embodiments, the first transistor 100 may be an NMOS transistor, and the second transistor 200 may be a PMOS transistor.

[0071] In some other embodiments, the first transistor 100 may be a PMOS transistor, and the second transistor 200 may be an NMOS transistor.

[0072] The spacer dielectric layer 300 is disposed between the first substrate 110 and the second gate 220 , and the bottom of the first substrate 110 and the top of the second gate 220 are bonded together through the spacer dielectric layer 300 .

[0073] After bonding the bottom of the first substrate 110 and the top of the second gate 220 together through the spacing dielectric layer 300, the present application further post-processes the spacing dielectric layer 300 through a preset annealing process and / or ultraviolet light irradiation process or other post-processing methods, thereby obtaining stresses (tensile or compressive) of different properties in the spacing dielectric layer 300, thereby achieving a balance between the stress and performance improvements of the semiconductor device.

[0074] In some embodiments, the material used to make the spacer dielectric layer 300 can be an insulating material, which can specifically include one or more insulating materials such as silicon nitride (SiNx), silicon carbide (SiC), silicon carbide nitride (SiCN), silicon carbon oxide nitride (SiOCN), silicon carbon oxide (SiOC), silicon oxynitride (SiON), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiBCN), amorphous carbon (aC), silicon-glass bonding structure (Silicon On Glass, SOG), and polymers.

[0075] In some embodiments, the thickness of the spacer dielectric layer is between 10 nm and 10 μm.

[0076] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0077] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A first transistor having a first substrate and a first gate; a second transistor having a second substrate and a second gate; The spacer dielectric layer is arranged between the first substrate and the second gate, and the bottom of the first substrate and the top of the second gate are integrated together through the spacer dielectric layer.

2. The semiconductor device according to claim 1, wherein: The material for making the spacer dielectric layer includes one or more of SiNx, SiC, SiCN, SiOCN, SiOC, SiON, BN, SiBN, SiBCN, aC, SOG, and polymer.

3. The semiconductor device according to claim 1 or 2, characterized in that: The thickness of the spacing dielectric layer is between 10 nm and 10 μm.

4. The semiconductor device according to claim 1, wherein: The first transistor and the second transistor are both gate-all-around transistors.

5. The semiconductor device according to claim 4, characterized in that The first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

6. The semiconductor device according to claim 4, characterized in that The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

7. A method for manufacturing a semiconductor device, characterized in that: include: Providing a first substrate, and forming a first transistor on the first substrate; Providing a second substrate, forming a second transistor on the second substrate, wherein a top of the second transistor has a second gate; Depositing a spacer dielectric layer at the bottom of the first substrate; Bonding the top of the second gate to the spacer dielectric layer; The spacer dielectric layer is post-processed by a preset annealing process and / or an ultraviolet light irradiation process to apply stress.

8. The method according to claim 7, characterized in that: The material for making the spacer dielectric layer includes one or more of SiNx, SiC, SiCN, SiOCN, SiOC, SiON, BN, SiBN, SiBCN, aC, SOG, and polymer.

9. The production method according to claim 7 or 8, characterized in that: The thickness of the spacing dielectric layer is between 10 nm and 10 μm.

10. An electronic device, characterized in that: A semiconductor device comprising any one of claims 1 to 6.

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