Silicon-on-insulator device and preparation method thereof

Abstract

The invention discloses a silicon-on-insulator device and a preparation method thereof, which are applied to the field of semiconductor devices, and the silicon-on-insulator device comprises a high-resistance substrate, a first interconnection layer, an active device layer, a buried oxide layer and a second interconnection layer which are sequentially stacked, the first interconnection layer comprises at least one conducting layer and a dielectric layer arranged between the conducting layer in the first interconnection layer and the high-resistance substrate, and the second interconnection layer at least comprises one conducting layer. After the active device is prepared in the silicon-on-insulator layer, the first interconnection layer is prepared on the side opposite to the buried oxide layer, the dielectric layer in the first interconnection layer is utilized to complete insulation isolation, and the high-resistance substrate is connected to the side opposite to the buried oxide layer of the first interconnection layer. Therefore, the buried oxide layer is not in direct contact with the high-resistance substrate, so that a high-capture layer does not need to be prepared before the buried oxide layer is prepared, and the yield of the prepared device is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a silicon-on-insulator device and a method for preparing the silicon-on-insulator device. Background Art

[0002] The source and drain of SOI (Silicon-On-Insulator) devices are isolated by a BOX (Buried Oxide) layer between the substrate to reduce parasitic capacitance, improve the response speed and performance of the device, and reduce the risk of leakage. It is widely used in high-speed response and low-power devices. In the traditional SOI structure, because there is a parallel conductive layer at the interface between SiO2 (silicon dioxide) in the BOX layer and Si (silicon) in the substrate, a polysilicon Trap Rich layer is currently added between the BOX layer and the silicon substrate.

[0003] However, the above-mentioned polysilicon Trap Rich layer is made before the BOX layer. The flatness and doping uniformity of the Trap Rich layer affect the quality of the BOX layer, and further affect the crystal quality and electrical properties of the SOI layer prepared on the BOX layer. In addition, the prepared Trap Rich layer must undergo high temperature and other processes in the production process of active devices, which will lead to a reduction in trap density, thereby weakening the Trap Rich layer's ability to capture charges.

[0004] Therefore, how to provide a silicon-on-insulator device that avoids the preparation quality of the high capture layer affecting the crystal quality and electrical properties of the silicon-on-insulator layer, and avoids the high-temperature process during the preparation of active devices weakening the charge capture ability of the high capture layer, is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a silicon-on-insulator device and a method for preparing a silicon-on-insulator device, which solves the problem in the prior art that the flatness and doping uniformity of the Trap Rich layer affect the quality of the BOX layer, thereby affecting the crystal quality and electrical properties of the SOI layer prepared on the BOX layer, and the prepared Trap rich layer must undergo high temperature and other processes in the manufacturing process of active devices, which will lead to a reduction in trap density, thereby weakening the Trap Rich layer's ability to capture charges.

[0006] In order to solve the above technical problems, the present invention provides a silicon-on-insulator device, comprising:

[0007] A high-resistance substrate, a first interconnection layer, an active device layer, a buried oxide layer, and a second interconnection layer are stacked in sequence; the initial substrate is an insulating substrate for preparing the buried oxide layer on the surface;

[0008] The first interconnect layer includes at least one conductive layer, and a dielectric layer disposed between the conductive layer in the first interconnect layer and the high-resistance substrate, and the second interconnect layer includes at least one conductive layer;

[0009] The conductive layer in the first interconnect layer is conductively connected to the active device layer, and the conductive layer in the second interconnect layer is conductively connected to the conductive layer in the first interconnect layer;

[0010] The conductive layer in the second interconnect layer is conductively connected to a pad exposed on the surface of the silicon-on-insulator device.

[0011] Optionally, a high capture layer having charge trap sites is provided on the surface of the buried oxide layer facing away from the active device layer.

[0012] Optionally, the thickness of the high capture layer is 0.1 micrometer to 5 micrometers.

[0013] Optionally, the conductive layer in the second interconnect layer is conductively connected to the conductive layer in the first interconnect layer via a first conductive via penetrating the active device layer and the buried oxide layer.

[0014] Optionally, a passivation layer is provided on a side of the second interconnect layer facing away from the buried oxide layer;

[0015] The passivation layer is provided with an opening exposing the pad.

[0016] Optionally, the second interconnect layer further includes a dielectric layer;

[0017] The conductive layer in the second interconnect layer is conductively connected to the pad through a second conductive via.

[0018] The present invention also provides a method for preparing a silicon-on-insulator device, comprising:

[0019] Providing an SOI wafer preform; the SOI wafer preform comprises an initial substrate, a buried oxide layer and an SOI layer which are stacked in sequence;

[0020] After the active device is prepared on the SOI layer in the SOI wafer preform, a first interconnection layer is prepared on the surface of the active device layer; the first interconnection layer includes at least one conductive layer, and a dielectric layer arranged on the side of the conductive layer in the first interconnection layer facing away from the active device layer, and the conductive layer in the first interconnection layer is conductively connected to the active device layer;

[0021] Preparing a high-resistance substrate on the surface of the first interconnect layer facing away from the active device layer, and then removing the initial substrate to expose the buried oxide layer;

[0022] A second interconnect layer and a pad are prepared on the side of the buried oxide layer facing away from the active device layer to complete the preparation of the silicon-on-insulator device; the second interconnect layer includes at least one conductive layer, and the conductive layer in the second interconnect layer is conductively connected to the conductive layer in the first interconnect layer, and the conductive layer in the second interconnect layer is conductively connected to the pad, and the pad is exposed on the surface of the silicon-on-insulator device.

[0023] Optionally, after removing the initial substrate to expose the buried oxide layer, the method further includes:

[0024] On the surface of the buried oxide layer facing away from the active device layer, a high capture layer having charge trap positions is prepared;

[0025] Accordingly, a second interconnect layer and a pad are prepared on the side of the buried oxide layer facing away from the active device layer to complete the preparation of the silicon-on-insulator device, including:

[0026] The second interconnect layer and the pad are prepared on the surface of the high capture layer facing away from the buried oxide layer to complete the preparation of the silicon-on-insulator device.

[0027] Optionally, a high capture layer having charge trap sites is prepared on a surface of the buried oxide layer facing away from the active device layer, comprising:

[0028] A polysilicon layer is epitaxially grown on a surface of the buried oxide layer facing away from the active device layer to serve as the high capture layer.

[0029] Optionally, removing the initial substrate to expose the buried oxide layer includes:

[0030] The initial substrate is removed by an etching process or a chemical mechanical polishing process to expose the buried oxide layer.

[0031] Optionally, before preparing the second interconnect layer and the pad on the side of the buried oxide layer facing away from the active device layer, the method further includes:

[0032] Opening a first conductive via structure passing through the active device layer and the buried oxide layer by a through silicon via process, so as to lead the conductive layer in the first interconnect layer to a side of the buried oxide layer facing away from the active device layer;

[0033] Accordingly, a second interconnect layer and a pad are prepared on the side of the buried oxide layer facing away from the active device layer to complete the preparation of the silicon-on-insulator device, including:

[0034] A second interconnect layer and a pad are prepared on the side of the buried oxide layer facing away from the active device layer, and the conductive layer in the second interconnect layer is conductively connected to the conductive layer in the first interconnect layer through the first conductive via structure to complete the preparation of the silicon-on-insulator device.

[0035] It can be seen that the silicon-on-insulator device provided by the present invention comprises a high-resistance substrate, a first interconnection layer, an active device layer, a buried oxide layer and a second interconnection layer which are stacked in sequence; the initial substrate is an insulating substrate for preparing a buried oxide layer on the surface, the first interconnection layer comprises at least one conductive layer, and a dielectric layer arranged between the conductive layer in the first interconnection layer and the high-resistance substrate, the second interconnection layer comprises at least one conductive layer, the conductive layer in the first interconnection layer is conductively connected to the active device layer, the conductive layer in the second interconnection layer is conductively connected to the conductive layer in the first interconnection layer, and the conductive layer in the second interconnection layer is conductively connected to a pad exposed on the surface of the silicon-on-insulator device. The present invention prepares a first interconnection layer on the side facing away from the buried oxide layer after completing the preparation of active devices in the silicon-on-insulator layer, and uses the dielectric layer in the first interconnection layer to complete insulation isolation, and connects a high-resistance substrate on the side of the first interconnection layer facing away from the buried oxide layer, so that the buried oxide layer and the high-resistance substrate are not in direct contact. Therefore, it is not necessary to prepare a high-capture layer before preparing the buried oxide layer, thereby avoiding the preparation quality of the high-capture layer affecting the crystal quality and electrical properties of the silicon-on-insulator layer, and thus avoiding the high-temperature process during the preparation of the active device to weaken the charge capture ability of the high-capture layer, thereby improving the quality rate of the prepared device.

[0036] In addition, the present invention also provides a method for preparing a silicon-on-insulator device, which also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0038] Figure 1 It is a schematic diagram of the structure of a conventional silicon-on-insulator device;

[0039] Figure 2 A schematic structural diagram of a silicon-on-insulator device provided in an embodiment of the present invention;

[0040] Figure 3 A schematic structural diagram of another silicon-on-insulator device provided in an embodiment of the present invention;

[0041] Figure 4A flow chart of a method for preparing a silicon-on-insulator device provided by an embodiment of the present invention;

[0042] Figure 5 A flow chart of another method for preparing a silicon-on-insulator device provided by an embodiment of the present invention;

[0043] Figures 6 to 12 An exemplary flow chart of a method for preparing a silicon-on-insulator device provided in an embodiment of the present invention;

[0044] Figures 1 to 3 ,as well as Figures 6 to 12 In the figure, the reference numerals are described as follows:

[0045] 10-high resistance substrate, 11-bonding layer, 12-initial substrate;

[0046] 20-a first interconnection layer, 21-a conductive layer in the first interconnection layer;

[0047] 30-active device layer, 31-active region, 32-STI structure, 33-SOI layer;

[0048] 40-buried oxide layer;

[0049] 50 - a second interconnection layer, 51 - a conductive layer in the second interconnection layer;

[0050] 60-passivation layer, 61-soldering pad;

[0051] 71 - first conductive via, 72 - second conductive via;

[0052] 80-high capture layer;

[0053] 90-metal interconnection layer, 91-conductive metal layer in the metal interconnection layer. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] The source / drain of the Silicon-On-Insulator (SOI) device is isolated from the substrate by a Buried Oxide (BOX) layer, which reduces parasitic capacitance, improves the response speed and performance of the device, and reduces leakage. It is widely used in high-speed and low-power applications. In the traditional SOI structure, the BOX layer is set as a silicon dioxide layer, because there are interface defects and impurities between the silicon dioxide and silicon interface. These defects and impurities will form energy levels, which can capture or release carriers. These carriers move freely at the interface to form a conductive path, thereby generating parallel conductive layers. In the prior art, even if a high-resistance silicon substrate is used, the parallel conductive layer will reduce the resistivity of the high-resistance silicon substrate, thereby reducing the electrical isolation effect, increasing leakage, and increasing parasitic capacitance, thereby affecting the linearity of the device response.

[0056] In order to improve the influence of this parallel conductive layer, a polysilicon Trap Rich layer is generally added between the BOX layer and the high-resistance silicon substrate. There are a large number of grain boundaries and defects in the Trap Rich layer, which provide a large number of charge trap positions, which can capture charges and reduce the accumulation of charges between the BOX layer and Si, thereby inhibiting the formation of parallel conductive layers and ensuring the high-resistance properties of the substrate. However, the above structure preparation process is complicated and has the following difficulties:

[0057] (1) The polysilicon Trap Rich layer is made before the BOX is prepared. The flatness and doping uniformity of the polysilicon Trap Rich layer will affect the preparation quality of the BOX layer. If the surface of the Trap Rich layer is uneven or the doping is uneven, it may cause defects or uneven thickness in the BOX layer during the growth process. The quality of the BOX layer directly affects the quality of the SOI layer. A BOX layer of poor quality may introduce defects or stress, affecting the crystal quality and electrical properties of the SOI layer.

[0058] (2) When preparing active devices in the SOI layer, the manufacturing process includes high temperature and other processes (such as oxidation, doping, annealing, metallization, etc.), and high temperature will cause the trap density in the polysilicon trap rich layer to decrease, thereby weakening its function of capturing charges.

[0059] (3) In the long run, the polysilicon trap rich layer is not continuously effective. The traps in the polysilicon trap rich layer will become saturated and lose the function of capturing charges.

[0060] In summary, in order to improve the parallel conductive layer at the interface between the BOX layer and the silicon substrate, the introduction of the polysilicon trap rich layer not only increases the process complexity and the cost of the substrate, but also the polysilicon trap rich layer is not effective in the long term. Figure 1 , Figure 1Schematic diagram of the structure of an existing silicon-on-insulator device. A high-capacitance layer 80, a buried oxide layer 40, an active device layer 30, a metal interconnection layer 90, and a passivation layer 60 are sequentially prepared on one side of a high-resistance substrate 10. The passivation layer 60 is used to protect the device functional layer and has an opening to expose a pad 61. The metal interconnection layer 90 includes a conductive metal layer 91 in the metal interconnection layer, that is, the metal interconnection layer 90 is located on the same side of the active device layer 30 in the prior art. Figure 2 The existing SOI device shown in the figure already includes stacked high-resistance silicon, high-capacitance layer, buried oxide layer, and SOI layer above the buried oxide layer in the wafer material (raw material substrate of unprocessed device). The main process of wafer processing is to process and prepare active devices on the SOI layer, which can include MOS tubes, diodes, resistors, capacitors, inductors, and interconnection wiring structures. Figure 1 The diagram shows an NMOS device, in which adjacent active areas are isolated by an STI structure 32. In the vertical direction, a buried oxide layer is provided under the SOI layer to achieve vertical isolation. The Gate, Source, and Drain are led upward through the metal interconnect layer 90 until the last conductive metal layer. The figure uses four conductive metal layers as an example for illustration, but in reality, there can also be five conductive metal layers, or six conductive metal layers. Because the quality (flatness, uniformity) of each layer determines the quality of the next layer, the quality of the high capture layer 80 directly determines the quality of the buried oxide layer 40, and indirectly determines the quality of the SOI layer. The SOI layer is used to process and prepare the active device layer 30, so its flatness and uniformity are crucial, which increases the difficulty of the manufacturing process of the previous layers.

[0061] The present invention prepares a first interconnection layer on the side facing away from the buried oxide layer after completing the preparation of active devices in the silicon-on-insulator layer, and uses the dielectric layer in the first interconnection layer to complete insulation isolation, and connects a high-resistance substrate on the side of the first interconnection layer facing away from the buried oxide layer, so that the buried oxide layer and the high-resistance substrate are not in direct contact. Therefore, it is not necessary to prepare a high-capture layer before preparing the buried oxide layer, thereby avoiding the preparation quality of the high-capture layer affecting the crystal quality and electrical properties of the silicon-on-insulator layer, and thus avoiding the high-temperature process during the preparation of the active device to weaken the charge capture ability of the high-capture layer, thereby improving the quality rate of the prepared device.

[0062] Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of a silicon-on-insulator device provided in an embodiment of the present invention. The silicon-on-insulator device may include:

[0063] A high-resistance substrate 10, a first interconnection layer 20, an active device layer 30, a buried oxide layer 40 and a second interconnection layer 50 are sequentially stacked; the initial substrate is an insulating substrate for preparing the buried oxide layer 40 on the surface;

[0064] The first interconnect layer 20 includes at least one conductive layer, and a dielectric layer disposed between the conductive layer 21 in the first interconnect layer and the high-resistance substrate 10, and the second interconnect layer 50 includes at least one conductive layer;

[0065] The conductive layer 21 in the first interconnect layer is conductively connected to the active device layer 30, and the conductive layer 51 in the second interconnect layer is conductively connected to the conductive layer 21 in the first interconnect layer;

[0066] The conductive layer 51 in the second interconnect layer is conductively connected to the pad 61 exposed on the surface of the SOI device.

[0067] It should be noted that, in this embodiment, both the first interconnection layer 20 and the second interconnection layer 50 include at least one conductive layer, and the conductive layer 21 in the first interconnection layer is isolated from the high-resistance substrate 10 by a dielectric layer provided between the conductive layer 21 and the high-resistance substrate 10. In this embodiment, the high-resistance substrate 10 can be a high-resistance silicon substrate, and specifically, a substrate with a resistivity greater than 1000 ohm·cm can be selected. In addition, in this embodiment, the conductive layer 21 in the first interconnection layer and the conductive layer 51 in the second interconnection layer can be set as metal conductive layers. This embodiment does not limit the specific number of conductive layers in the first interconnection layer 20, which can be set according to actual working conditions. Accordingly, this embodiment also does not limit the specific number of conductive layers in the second interconnection layer 50. The active device layer 30 is a functional layer obtained by processing the SOI layer, wherein the active device layer 30 includes a plurality of active regions 31, and adjacent active regions 31 are isolated by STI (deep trench isolation) structures 32. The active area 31 generally includes MOS tube structure, diode, resistor, capacitor, inductor, and interconnection wiring. In this embodiment, the BOX layer 40 can be set as a silicon dioxide layer. In this embodiment, the high resistance substrate 10 can be set to be bonded to the first interconnection layer 20 through the bonding layer 11.

[0068] In addition, in this embodiment, the conductive layer 21 in the first interconnect layer is conductively connected to the active device layer 30, and the conductive layer 51 in the second interconnect layer is conductively connected to the conductive layer 21 in the first interconnect layer. At this time, interconnect layers are formed on both sides of the active device layer 30, that is, the interconnect layers of the silicon-on-insulator device are distributed on both sides of the SOI layer used to prepare the active device layer 30, and the second interconnect layer 50 is used to conductively lead the active device layer 30 to the pad 61 to realize the functionality of the silicon-on-insulator device. It needs to be explained that the active device layer 30 prepared in this embodiment needs to be insulated and isolated from the high-resistance substrate 10. However, since the active device layer 30 needs to be conductively led out and an insulating isolation layer needs to be set between the active device layer 30 and the high-resistance substrate 10, the first interconnect layer 20 is used to lead out the active device layer 30 on the one hand and isolate the high-resistance substrate 10 from the active device layer 30 on the other hand, and the second interconnect layer 50 is connected to the first interconnect layer 20, so that the active device layer 30 is connected to the pad 61 by the second interconnect layer 50, thereby completing the conductive lead-out of the silicon-on-insulator device.

[0069] Unlike conventional SOI devices, the high capture layer 80 in this embodiment is not manufactured when the substrate is received, but is manufactured after the active device is manufactured. This has the advantage of reducing the difficulty of manufacturing the buried oxide layer 40 and the SOI layer, and ensuring that the trap density of the high capture layer is not affected by the device manufacturing process. In addition, in the silicon-on-insulator structure provided in this embodiment, the role of the high capture layer 80 is also weakened, because there is no interface between the buried oxide layer 40 and the silicon substrate, and there is no need to use the high capture layer 80 to eliminate the parallel conductive layer.

[0070] Furthermore, in order to avoid leakage current on the surface of the prepared buried oxide layer 40, which affects the response sensitivity of the device, reference can be made to Figure 3 , Figure 3 A schematic diagram of another silicon-on-insulator device structure provided by an embodiment of the present invention is shown in FIG. A high capture layer 80 having charge trap sites is disposed on the surface of the buried oxide layer 40 facing away from the active device layer 30 .

[0071] In this embodiment, a high capture layer 80 can be further prepared on the side of the buried oxide layer 40 facing away from the active device layer 30, and the high capture layer 80 is used to eliminate the free charges on the surface of the buried oxide layer 40 to avoid leakage current on the surface of the buried oxide layer 40. It should be further explained that, since a silicon-on-insulator layer needs to be grown on one side of the buried oxide layer 40 during preparation, and the silicon-on-insulator layer needs to be processed to form the active device layer 30, the high capture layer 80 needs to be prepared on the surface of the buried oxide layer 40. In this embodiment, the high capture layer 80 can capture and fix the charges on the surface of the buried oxide layer 40 and its vicinity to prevent charge accumulation, and can also serve as a shielding layer to reduce electrical interference from the external environment and improve isolation.

[0072] Furthermore, in order to remove leakage current existing on the surface of the buried oxide layer 40, the thickness of the high trapping layer 80 can be set to 0.1 micrometer to 5 micrometers.

[0073] It should be noted that in this embodiment, a high capture layer 80 with a thickness of 0.1 micron to 5 microns is provided, which can further improve the effect of removing leakage current on the surface of the buried oxide layer 40. The specific thickness of the high capture layer is not limited in this embodiment, as long as it is in the range of 0.1 micron to 5 microns. For example, the thickness of the high capture layer 80 can be set to 0.1 micron to avoid uneven thickness of the high capture layer 80 during the preparation process; or the thickness of the high capture layer 80 can be set to 5 microns to ensure the charge capture effect of the high capture layer 80, or the thickness of the high capture layer 80 can be set to between 2 microns and 3 microns, that is, while ensuring the uniformity of the preparation of the high capture layer 80, the charge capture effect of the high capture layer 80 is ensured.

[0074] Furthermore, in order to ensure the simplicity of manufacturing the silicon-on-insulator device, the conductive layer 51 in the second interconnect layer and the conductive layer 21 in the first interconnect layer can be conductively connected via a first conductive via 71 passing through the active device layer 30 and the buried oxide layer 40 .

[0075] In this embodiment, a conductive layer 51 in the second interconnect layer is provided, and is connected to the conductive layer 21 in the first interconnect layer through a first conductive via 71. The first conductive via 71 passing through the active device layer 30 can be provided at the STI structure 32 between adjacent active areas 31 in the active device layer 30 to open a via hole, so as to connect the conductive layer of the first interconnect layer 20 with the conductive layer of the second interconnect layer 50 without affecting the active area 31.

[0076] Furthermore, in order to protect the functional layer in the silicon-on-insulator device, a passivation layer 60 may be provided on the side of the second interconnect layer 50 facing away from the buried oxide layer 40;

[0077] The passivation layer 60 is provided with an opening exposing the pad 61 .

[0078] It should be noted that, in the present embodiment, a passivation layer 60 is provided on the exposed surface of the second interconnection layer 50 to protect the second interconnection layer 50 and prevent the silicon-on-insulator device from being damaged by the outside world, and the pad 61 connected to the conductive layer in the second interconnection layer 50 is exposed by utilizing the openings provided in the passivation layer 60 to make a conductive connection with the outside.

[0079] Furthermore, in order to avoid the risk of leakage, the second interconnect layer 50 may further include a dielectric layer;

[0080] The conductive layer 51 in the second interconnection layer is conductively connected to the pad 61 through the second conductive via 72 .

[0081] It should be noted that, in this embodiment, the conductive layer 51 in the second interconnection layer is configured to be conductively connected to the pad 61 through the second conductive through hole 72, and the dielectric layer in the second interconnection layer 50 insulates and protects the conductive layer 51 in the second interconnection layer to avoid leakage, while ensuring that the conductive layer 51 in the second interconnection layer is conductively connected to the pad 61. Correspondingly, in this embodiment, it can also be configured that the conductive layer 21 in the first interconnection layer and the active device layer 30 form an effective conductive connection through the conductive through hole, and in this case, a dielectric layer is provided between the conductive layer 21 in the first interconnection layer and the active device layer 30.

[0082] The silicon-on-insulator device provided by the embodiment of the present invention comprises a high-resistance substrate 10, a first interconnection layer 20, an active device layer 30, a buried oxide layer 40 and a second interconnection layer 50 which are stacked in sequence; the first interconnection layer 20 comprises at least one conductive layer, and a dielectric layer arranged between the conductive layer 21 in the first interconnection layer and the high-resistance substrate 10; the second interconnection layer 50 comprises at least one conductive layer; the conductive layer 21 in the first interconnection layer is conductively connected to the active device layer 30; the conductive layer 51 in the second interconnection layer is conductively connected to the conductive layer 21 in the first interconnection layer; and the conductive layer 51 in the second interconnection layer is conductively connected to a pad 61 exposed on the surface of the silicon-on-insulator device. According to the present invention, after the active device is prepared in the silicon-on-insulator layer, the first interconnection layer 20 is prepared on the side facing away from the buried oxide layer 40, and the dielectric layer in the first interconnection layer 20 is used to complete the insulation isolation, and the high-resistance substrate 10 is connected on the side of the first interconnection layer 20 facing away from the buried oxide layer 40, so that the buried oxide layer 40 and the high-resistance substrate 10 are not in direct contact. Therefore, it is not necessary to prepare the high-capture layer 80 before preparing the buried oxide layer 40, thereby avoiding the preparation quality of the high-capture layer 80 affecting the crystal quality and electrical properties of the silicon-on-insulator layer, thereby avoiding the high-temperature process during the preparation of the active device from weakening the charge capture ability of the high-capture layer 80, and improving the quality rate of the prepared device.

[0083] In addition, the embodiment of the present invention prepares a high capture layer 80 on the side of the buried oxide layer 40 facing away from the active device layer 30, and uses the high capture layer 80 to eliminate the free charge on the surface of the buried oxide layer 40, thereby avoiding the phenomenon of leakage current on the surface of the buried oxide layer 40; the high capture layer 80 is set to be 0.1 microns to 5 microns thick, which can ensure the effect of eliminating the leakage current on the surface of the buried oxide layer 40; the conductive layer 51 in the second interconnect layer is connected to the conductive layer 21 in the first interconnect layer through the first conductive through hole 71 passing through the active device layer 30 and the buried oxide layer 40, which can ensure the formed insulator The simplicity of the silicon-on-insulator device; a passivation layer 60 is set on the exposed surface of the second interconnection layer 50 to protect the second interconnection layer 50 to prevent the silicon-on-insulator device from being damaged by the outside; the conductive layer 51 in the second interconnection layer is set to be conductively connected to the pad 61 through the second conductive through hole 72, and the dielectric layer in the second interconnection layer 50 insulates and protects the conductive layer 51 in the second interconnection layer to avoid leakage, and at the same time ensures that the conductive layer 51 in the second interconnection layer is conductively connected to the pad 61; a dielectric layer is set between the conductive layer 21 in the first interconnection layer and the active device layer 30 to avoid leakage or short circuit problems.

[0084] The following is an introduction to a method for preparing a silicon-on-insulator device provided in an embodiment of the present invention. The method for preparing a silicon-on-insulator device described below and the silicon-on-insulator device described above can be referred to each other.

[0085] Please refer to Figure 4 , Figure 4 A flowchart of a method for preparing a silicon-on-insulator device provided in an embodiment of the present invention may include:

[0086] S101 : providing an SOI wafer preform; the SOI wafer preform comprises an initial substrate 12 , a buried oxide layer 40 and an SOI layer 33 which are stacked in sequence.

[0087] It should be noted that the SOI wafer preform in this embodiment can refer to Figure 5In this embodiment, a buried oxide layer 40 and an SOI layer 33 are sequentially prepared on the surface of an initial substrate 12. At this time, since the initial substrate 12 is not used as a substrate for a silicon-on-insulator device, but is only used to prepare the buried oxide layer 40 and the SOI layer 33, and the initial substrate 12 needs to be removed later, it is not necessary to prepare a high capture layer 80 between the buried oxide layer 40 and the initial substrate 12. This can avoid uneven surfaces of the buried oxide layer 40 and the SOI layer 33 due to uneven preparation of the high capture layer 80, thereby avoiding damage to the device. In addition, since the high capture layer 80 is not prepared before the preparation of the SOI layer 33 and before the preparation of active devices in the SOI layer 33, the heating treatment process in the process of preparing active devices in the SOI layer 33 is avoided, thereby reducing defects in the high capture layer 80, thereby avoiding reducing defects in the high capture layer 80.

[0088] S102: After completing active device preparation in the SOI layer 33 in the SOI wafer preform and forming the active device layer 30, a first interconnection layer 20 is prepared on the surface of the active device layer 30; the first interconnection layer 20 includes at least one conductive layer, and a dielectric layer arranged on the side of the conductive layer 21 in the first interconnection layer facing away from the active device layer 30, and the conductive layer 21 in the first interconnection layer is conductively connected to the active device layer 30.

[0089] It should be noted that in this embodiment, after the active device is prepared in the SOI layer 33, the active device layer 30 is formed. The structure of the active device layer 30 is as follows: Figure 6 As shown, at this time, the first interconnection layer 20 is prepared on the surface of the formed active device layer 30, and the structure of the first interconnection layer 20 is as shown in FIG. Figure 7 As shown, the dielectric layer in the first interconnect layer 20 is used to protect the conductive layer 21 in the first interconnect layer, so as to prevent the conductive layer 21 in the first interconnect layer from leaking when it is subsequently connected to the outside.

[0090] S103 : preparing a high-resistance substrate 10 on the surface of the first interconnect layer 20 facing away from the active device layer 30 , and then removing the initial substrate 12 to expose the buried oxide layer 40 .

[0091] In this embodiment, a high-resistance substrate 10 is prepared on the surface of the first interconnection layer 20 facing away from the active device layer 30. The structure of the high-resistance substrate 10 after preparation is as follows: Figure 8 As shown, the high-resistance substrate 10 is used as the substrate of the silicon-on-insulator device. After the first interconnect layer 20 is connected to the high-resistance substrate 10, the initial substrate 12 needs to be removed. The structure of removing the initial substrate 12 is as shown in FIG. Fig. 9 As shown, the buried oxide layer 40 is exposed, and the remaining functional layers are formed outwardly from the exposed surface of the buried oxide layer 40. In this embodiment, the conductive layer 21 in the first interconnect layer is isolated from the high-resistance substrate 10 by the dielectric layer.

[0092] Furthermore, in order to eliminate the charge on the surface of the buried oxide layer 40 and avoid leakage, after removing the initial substrate 12 and exposing the buried oxide layer 40, the following steps may be further included:

[0093] A high capture layer 80 with charge trap sites is prepared on the surface of the buried oxide layer 40 facing away from the active device layer 30;

[0094] Accordingly, a second interconnect layer 50 and a pad 61 are prepared on the side of the buried oxide layer 40 facing away from the active device layer 30 to complete the preparation of the silicon-on-insulator device, including:

[0095] On the surface of the high trapping layer 80 facing away from the buried oxide layer 40, a second interconnection layer 50 and a pad 61 are prepared to complete the preparation of the silicon-on-insulator device.

[0096] It should be noted that in this embodiment, after removing the initial substrate 12, a high capture layer 80 is prepared on the surface of the exposed buried oxide layer 40. The structure of the high capture layer 80 prepared in this embodiment is as follows: Fig.10 As shown, the charge trap positions in the high capture layer 80 are used to capture the charges on the surface of the buried oxide layer 40, thereby avoiding the formation of lateral current on the surface of the buried oxide layer 40 and improving the yield of the prepared silicon-on-insulator device. In this embodiment, the second interconnect layer 50 and the pad 61 are prepared on the surface of the high capture layer 80 facing away from the buried oxide layer 40 to complete the preparation of the silicon-on-insulator device. Fig.11 , Fig.11 This is an example diagram of the structure after the preparation of the silicon-on-insulator device is completed as described above.

[0097] Further, in order to ensure the improvement effect of the high capture layer 80 on the leakage phenomenon on the surface of the buried oxide layer 40, the high capture layer 80 with charge trap positions is prepared on the surface of the buried oxide layer 40 facing away from the active device layer 30, which may include:

[0098] On the surface of the buried oxide layer 40 facing away from the active device layer 30 , a polysilicon layer is epitaxially grown to serve as a high trapping layer 80 .

[0099] It should be noted that in this embodiment, a polysilicon layer is epitaxially grown on the surface of the buried oxide layer 40 facing away from the active device layer 30 as a high capture layer 80, which can capture the charges on the surface of the buried oxide layer 40 by utilizing the defects in the polysilicon layer, thereby avoiding leakage current on the surface of the buried oxide layer 40 and improving the compatibility with the device.

[0100] Further, in order to improve the convenience of removing the initial substrate 12, the above-mentioned removal of the initial substrate 12 to expose the buried oxide layer 40 may include:

[0101] The initial substrate 12 is removed by an etching process or a chemical mechanical polishing process to expose the buried oxide layer 40 .

[0102] It should be noted that, in this embodiment, the initial substrate 12 is removed by using an etching process or a chemical mechanical polishing process, which can ensure the accuracy and efficiency of removing the initial substrate 12 .

[0103] S104: preparing a second interconnect layer 50 and a pad 61 on the side of the buried oxide layer 40 facing away from the active device layer 30, and completing the preparation of the silicon-on-insulator device; the second interconnect layer 50 includes at least one conductive layer, and the conductive layer 51 in the second interconnect layer is conductively connected to the conductive layer 21 in the first interconnect layer, and the conductive layer 51 in the second interconnect layer is conductively connected to the pad 61, and the pad 61 is exposed on the surface of the silicon-on-insulator device.

[0104] In this embodiment, a second interconnection layer 50 and a pad 61 are prepared on the side of the buried oxide layer 40 facing away from the active device layer 30, that is, on the surface of the buried oxide layer 40 exposed after the initial substrate 12 is removed, wherein the conductive layer 51 in the second interconnection layer is conductively connected to the pad 61, so that the conductive end in the active device layer 30 connected to the outside can be led out by using the pad 61.

[0105] Furthermore, in order to ensure that the conductive connection terminal in the active device layer 30 is led out, before preparing the second interconnection layer 50 and the pad 61 on the side of the buried oxide layer 40 facing away from the active device layer 30, the following steps may also be included:

[0106] A first conductive via 71 structure is opened through the active device layer 30 and the buried oxide layer 40 by using a through silicon via process, so as to lead the conductive layer 21 in the first interconnect layer to a side of the buried oxide layer 40 facing away from the active device layer 30;

[0107] Accordingly, a second interconnect layer 50 and a pad 61 are prepared on the side of the buried oxide layer 40 facing away from the active device layer 30 to complete the preparation of the silicon-on-insulator device, including:

[0108] A second interconnect layer 50 and a pad 61 are prepared on the side of the buried oxide layer 40 facing away from the active device layer 30, and the conductive layer 51 in the second interconnect layer is conductively connected to the conductive layer 21 in the first interconnect layer through the first conductive via 71 structure to complete the preparation of the silicon-on-insulator device.

[0109] In this embodiment, the first interconnection layer 20 and the second interconnection layer 50 are electrically conductively connected by using the first conductive via 71, thereby ensuring that the conductive connection terminal in the active device layer 30 is led out while ensuring the fabrication efficiency and convenience of the structure.

[0110] The method for preparing a silicon-on-insulator device provided by an embodiment of the present invention comprises providing an SOI wafer preform, wherein the SOI wafer preform comprises an initial substrate 12, a buried oxide layer 40 and an SOI layer 33 which are stacked in sequence, and an active device is prepared on the SOI layer 33 in the SOI wafer preform. After the active device layer 30 is formed, a first interconnection layer 20 is prepared on the surface of the active device layer 30, wherein the first interconnection layer 20 comprises at least one conductive layer, and a dielectric layer which is arranged on a side of the conductive layer 21 in the first interconnection layer facing away from the active device layer 30, and the conductive layer 21 in the first interconnection layer is connected to the active device layer 30. The active device layer 30 is conductively connected, a high-resistance substrate 10 is prepared on the surface of the first interconnect layer 20 facing away from the active device layer 30, and then the initial substrate 12 is removed to expose the buried oxide layer 40, and a second interconnect layer 50 and a pad 61 are prepared on the side of the buried oxide layer 40 facing away from the active device layer 30 to complete the preparation of the silicon-on-insulator device, the second interconnect layer 50 includes at least one conductive layer, and the conductive layer 51 in the second interconnect layer is conductively connected to the conductive layer 21 in the first interconnect layer, and the conductive layer 51 in the second interconnect layer is conductively connected to the pad 61, and the pad 61 is exposed on the surface of the silicon-on-insulator device. According to the present invention, after the active device is prepared in the silicon-on-insulator layer, the first interconnection layer 20 is prepared on the side facing away from the buried oxide layer 40, and the dielectric layer in the first interconnection layer 20 is used to complete the insulation isolation, and the high-resistance substrate 10 is connected on the side of the first interconnection layer 20 facing away from the buried oxide layer 40, so that the buried oxide layer 40 and the high-resistance substrate 10 are not in direct contact. Therefore, it is not necessary to prepare the high-capture layer 80 before preparing the buried oxide layer 40, thereby avoiding the preparation quality of the high-capture layer 80 affecting the crystal quality and electrical properties of the silicon-on-insulator layer, thereby avoiding the high-temperature process during the preparation of the active device from weakening the charge capture ability of the high-capture layer 80, and improving the quality rate of the prepared device.

[0111] In addition, the embodiment of the present invention prepares a high capture layer 80 on the surface of the exposed buried oxide layer 40 after removing the initial substrate 12, thereby avoiding leakage current on the surface of the buried oxide layer 40 and improving the yield of the prepared silicon-on-insulator device; on the surface of the buried oxide layer 40 facing away from the active device layer 30, a polysilicon layer is prepared by epitaxial growth as the high capture layer 80, which can utilize defects in the polysilicon layer to capture charges on the surface of the buried oxide layer 40, while avoiding leakage current on the surface of the buried oxide layer 40 and improving the compatibility with the device; the initial substrate 12 is removed by an etching process or a chemical mechanical polishing process, which can ensure the accuracy and removal efficiency of the removal of the initial substrate 12; the first interconnection layer 20 and the second interconnection layer 50 are electrically conductive by utilizing the first conductive through hole 71, while ensuring that the conductive connection terminal in the active device layer 30 is led out, the preparation efficiency and convenience of the structure are ensured.

[0112] In a feasible embodiment, the above-mentioned method for preparing a silicon-on-insulator device may specifically include the following steps. Figure 5 , Figure 5 A flow chart of another method for preparing a silicon-on-insulator device provided in an embodiment of the present invention:

[0113] Step S1: The initial substrate 12 is provided, and the BOX layer 40 and the SOI layer 33 are sequentially manufactured on the initial substrate 12. Unlike the substrate of the conventional SOI device, the initial substrate 12 does not need high-resistance silicon, and can be a substrate such as ordinary silicon, glass, or sapphire; there is no need to manufacture a polysilicon Trap Rich layer 80 between the BOX layer 40 and the initial substrate 12. This ensures the flatness and uniformity of the BOX layer 40, and thus the flatness and uniformity of the SOI layer 33. This embodiment can refer to Figures 6 to 12 , Figures 6 to 12 This is a flowchart of a method for preparing a silicon-on-insulator device provided in an embodiment of the present invention. The specific steps of step S1 can be referred to in Figure 6 .

[0114] Step S2: After the active device is prepared on the SOI layer 33 and the active device layer 30 is formed, the first interconnect layer 20 is prepared on the surface of the active device layer 30. In this embodiment, the structure of the active device layer 30 is as follows: Figure 7 As shown, this embodiment takes the completion of the M1 metal layer and the M2 metal layer as the first interconnection layer 20 as an example, as shown in FIG. Figure 8 As shown, the M1 metal layer and the M2 metal layer are protected and isolated by the dielectric layer. Another high-resistance substrate 10 is bonded to the side of the first interconnect layer 20 facing away from the active device layer 30. For details, please refer to Fig. 9Specifically, a high-resistance silicon substrate, glass, etc. may be selected, and the resistivity is required to be greater than 1000 ohm·cm. The high-resistance substrate 10 is used as a supporting substrate for subsequent devices. In order to reduce the loss of the substrate, a high-resistance substrate needs to be selected.

[0115] Step S3: Flip the device over and grind away the initial substrate 12 (i.e., the above-mentioned ordinary silicon, glass, sapphire, etc. substrate) by etching or chemical mechanical polishing until the BOX layer 40 is exposed. Fig.10 .

[0116] Step S4: On the surface of the exposed BOX layer 40, a layer of polysilicon is grown by LPCVD process, with a thickness between 0.1 micrometers and 5 micrometers, as the high capture layer 80. For details, please refer to Fig.11 .

[0117] Step S5: Prepare the first conductive via 71 by TSV (Through Silicon Via) process, interconnect the first interconnection layer 20 to the high capture layer 80, the first conductive via 71 passes through the SOI layer 33, the BOX layer 40, and the high capture layer 80, and then make the second interconnection layer 50 on the surface of the high capture layer 80. In this embodiment, the second interconnection layer 50 can be configured to include an M3 metal layer and an M4 metal layer.

[0118] Step S6: A passivation layer 60 is formed on the surface of the top metal layer M4. A window is opened in the passivation layer 60 to expose the PAD 61 (pad) for easy lead connection, thus completing the preparation of the silicon-on-insulator device. Fig.12 .

[0119] In this embodiment, the initial substrate 12 does not need a trap rich layer 80, and does not need a high-resistance silicon substrate, which can reduce the difficulty of the substrate manufacturing process and reduce the cost; after the active device is manufactured on the SOI layer 33, the initial substrate 12 is ground away to eliminate the interface between the BOX layer 40 and the silicon substrate, thereby avoiding the formation of a parallel conductive layer; the Trap Rich layer 80 can be grown after the active device is manufactured, thereby ensuring that the trap density is not affected by the high-temperature process in the active device; the interconnection layer is located on both sides of the active device layer 30, and the first conductive via 71 is used to realize the interconnection of the interconnection layers located on both sides of the active device layer 30. In this embodiment, the complexity of substrate manufacturing process is reduced, the manufacturing cost is reduced, the formation of parallel conductive layers is eliminated, and the performance of silicon-on-insulator devices is improved. The Trap Rich layer 80 is manufactured after the active device is manufactured, thereby ensuring that the trap density is not affected by the high-temperature process in the active device manufacturing.

[0120] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0121] In addition, it should be noted that, in this article, relationships such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0122] The above is a detailed introduction to a silicon-on-insulator device and a method for preparing a silicon-on-insulator device provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A silicon-on-insulator device, characterized in that: include: A high-resistance substrate (10), a first interconnection layer (20), an active device layer (30), a buried oxide layer (40) and a second interconnection layer (50) are sequentially stacked; the initial substrate (12) is an insulating substrate used for preparing the buried oxide layer (40) on the surface; The first interconnection layer (20) comprises at least one conductive layer, and a dielectric layer arranged between the conductive layer (21) in the first interconnection layer and the high-resistance substrate (10), and the second interconnection layer (50) comprises at least one conductive layer; The conductive layer (21) in the first interconnect layer is conductively connected to the active device layer (30), and the conductive layer (51) in the second interconnect layer is conductively connected to the conductive layer (21) in the first interconnect layer; The conductive layer (51) in the second interconnect layer is conductively connected to a pad (61) exposed on the surface of the silicon-on-insulator device.

2. The silicon-on-insulator device according to claim 1, characterized in that: A high capture layer (80) with charge trap positions is provided on the surface of the buried oxide layer (40) facing away from the active device layer (30).

3. The silicon-on-insulator device according to claim 2, characterized in that: The thickness of the high capture layer (80) is 0.1 micrometer to 5 micrometers.

4. The silicon-on-insulator device according to claim 1, characterized in that: The conductive layer (51) in the second interconnect layer is conductively connected to the conductive layer (21) in the first interconnect layer via a first conductive through hole (71) that passes through the active device layer (30) and the buried oxide layer (40).

5. The silicon-on-insulator device according to claim 1, characterized in that: A passivation layer (60) is provided on a side of the second interconnect layer (50) facing away from the buried oxide layer (40); An opening exposing the pad (61) is provided in the passivation layer (60).

6. The silicon-on-insulator device according to claim 1, characterized in that: The second interconnect layer (50) further comprises a dielectric layer; The conductive layer (51) in the second interconnect layer is conductively connected to the pad (61) via a second conductive through hole (72).

7. A method for preparing a silicon-on-insulator device, characterized in that: include: Providing an SOI wafer preform; the SOI wafer preform comprises an initial substrate (12), a buried oxide layer (40), and an SOI layer (33) which are stacked in sequence; After the active device preparation is completed on the SOI layer (33) in the SOI wafer preform to form an active device layer (30), a first interconnection layer (20) is prepared on the surface of the active device layer (30); the first interconnection layer (20) comprises at least one conductive layer, and a dielectric layer arranged on the side of the conductive layer (21) in the first interconnection layer facing away from the active device layer (30), and the conductive layer (21) in the first interconnection layer is conductively connected to the active device layer (30); Preparing a high-resistance substrate (10) on a surface of the first interconnect layer (20) facing away from the active device layer (30), and then removing the initial substrate (12) to expose the buried oxide layer (40); A second interconnection layer (50) and a pad (61) are prepared on the side of the buried oxide layer (40) facing away from the active device layer (30), thereby completing the preparation of the silicon-on-insulator device; the second interconnection layer (50) comprises at least one conductive layer, and the conductive layer (51) in the second interconnection layer is conductively connected to the conductive layer (21) in the first interconnection layer, and the conductive layer (51) in the second interconnection layer is conductively connected to the pad (61), and the pad (61) is exposed on the surface of the silicon-on-insulator device.

8. The method for preparing a silicon-on-insulator device according to claim 7, characterized in that: After removing the initial substrate (12) and exposing the buried oxide layer (40), the method further comprises: Preparing a high capture layer (80) having charge trap sites on a surface of the buried oxide layer (40) facing away from the active device layer (30); Accordingly, a second interconnect layer (50) and a pad (61) are prepared on the side of the buried oxide layer (40) facing away from the active device layer (30), thereby completing the preparation of the silicon-on-insulator device, including: The second interconnection layer (50) and the pad (61) are prepared on the surface of the high capture layer (80) facing away from the buried oxide layer (40), thereby completing the preparation of the silicon-on-insulator device.

9. The method for preparing a silicon-on-insulator device according to claim 8, characterized in that: A high capture layer (80) having charge trap positions is prepared on a surface of the buried oxide layer (40) facing away from the active device layer (30), comprising: A polysilicon layer is epitaxially prepared on a surface of the buried oxide layer (40) facing away from the active device layer (30) to serve as the high capture layer (80).

10. The method for preparing a silicon-on-insulator device according to claim 7, characterized in that: Before preparing a second interconnect layer (50) and a pad (61) on the side of the buried oxide layer (40) facing away from the active device layer (30), the method further comprises: A first conductive through hole (71) structure is opened through the active device layer (30) and the buried oxide layer (40) by using a through silicon via process, so as to lead the conductive layer (21) in the first interconnect layer to a side of the buried oxide layer (40) facing away from the active device layer (30); Accordingly, a second interconnect layer (50) and a pad (61) are prepared on the side of the buried oxide layer (40) facing away from the active device layer (30), thereby completing the preparation of the silicon-on-insulator device, including: A second interconnection layer (50) and a pad (61) are prepared on the side of the buried oxide layer (40) facing away from the active device layer (30), and the conductive layer (51) in the second interconnection layer is conductively connected to the conductive layer in the first interconnection layer (20) via the first conductive through-hole (71) structure, thereby completing the preparation of the silicon-on-insulator device.

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