Wafer-level vacuum packaging sensing chip and preparation method thereof
By etching a blind hole structure on the capping wafer and forming a copper wall structure, electrical activation of the getter layer is achieved, which solves the problem of difficulty in thermal activation of the getter layer and improves wafer-level vacuum packaging of sensor chips. performance.
Patent Information
- Application Number
- CN202411515094.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-01-21
AI Technical Summary
In wafer-level vacuum packaging, thermal activation of the getter layer is difficult and may reduce the operating performance of the sensing chip.
The first and second copper walls are formed by etching a blind via structure on the capping wafer and filling the copper wall extension therein, and preparing a solder layer and a getter layer respectively. The capping wafer is then thinned to turn the blind hole into a through hole, and the copper wall extension is exposed as an excitation electrode to achieve electrical activation of the getter layer.
It reduces the difficulty of activation of the aspiration layer, avoids the effects of thermal activity on the performance of the chip, and improves the performance of the wafer -class vacuum packaging sensor chip.
Smart Images
Figure CN119342929A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a wafer-level vacuum packaged sensor core and a preparation method thereof. Background Art
[0002] Wafer Level Packaging (WLP) is an advanced packaging technology that has developed rapidly in recent years due to its advantages such as small size, excellent electrical performance, good heat dissipation and low cost. It meets the current demand for miniaturized chips in mobile devices and can effectively reduce the cost of devices.
[0003] The wafer-level packaging structure mainly includes a sensor wafer and a cover wafer. The sensor wafer and the cover wafer are combined together through bonding technology to form a vacuum closed space, thereby providing good protection for the sensing structure on the sensor wafer.
[0004] In order to ensure a high vacuum degree in the confined space where the sensing structure is located, a getter needs to be provided in the confined space where the sensing structure is located. However, it is relatively difficult to thermally activate the getter in the confined cavity, and this may reduce the working performance of the sensor chip. Summary of the invention
[0005] The purpose of the present invention is to provide a wafer-level vacuum packaged sensor chip and a preparation method thereof, which can reduce the difficulty of activating the getter in the vacuum packaged sensor chip to a certain extent and avoid the activation of the getter layer to reduce the working performance of the sensor chip.
[0006] In order to solve the above technical problems, the present invention provides a method for preparing a wafer-level vacuum packaged sensor chip, comprising:
[0007] Etching at least two blind hole structures at set positions corresponding to each sensing area on the capping wafer;
[0008] A first copper wall and a second copper wall and a copper wall extension portion filled in the blind hole structure are formed on the capping wafer; wherein the second copper wall is a copper wall that forms an annular wall corresponding to the edge of each sensing area; the first copper wall is a copper wall that extends at the inner edge of each annular wall, and the extension area of the first copper wall covers the location of the blind hole structure and is connected to the copper wall extension portion;
[0009] Forming a solder layer on the second copper wall;
[0010] preparing a getter layer on the first copper wall;
[0011] Thinning the capping wafer on the side away from the blind hole structure until the blind hole structure becomes a through hole structure, so that the end of the copper wall extension located at the bottom of the blind hole structure is exposed to form an excitation electrode for activating the getter layer;
[0012] The cover wafer and the sensor wafer are wafer-bonded via the solder layer to obtain a wafer-level vacuum packaged sensor chip.
[0013] In an optional embodiment of the present application, forming a first copper wall and a second copper wall and a copper wall extension filled in the blind hole structure on the capping wafer includes:
[0014] A seed layer is prepared on the capping wafer to cover the surface of the capping wafer and the hole wall and hole bottom of the blind hole structure;
[0015] coating a first photoresist layer on the seed layer;
[0016] Performing patterned etching on the first photoresist layer to form a first groove and a second groove not covered by the photoresist; wherein an extension area of the first groove covers the location of the blind hole structure and is connected to the blind hole structure;
[0017] The first copper wall, the copper wall extension and the second copper wall are respectively formed in the first groove, the blind hole structure and the second groove; wherein the first copper wall and the copper wall extension are integrally formed, and the height of the first copper wall is smaller than that of the second copper wall.
[0018] In an optional embodiment of the present application, the first groove is an L-shaped extending groove or an annular extending groove;
[0019] The first groove is a sawtooth linear groove or a city wall linear groove.
[0020] In an optional embodiment of the present application, forming a solder layer on the second copper wall; and forming a getter layer on the first copper wall, comprising:
[0021] Performing secondary etching on the first photoresist layer to remove the sidewall photoresist adhering to the first copper wall and the second copper wall, and forming gap grooves between the sidewalls of the first copper wall and the second copper wall and the first photoresist layer;
[0022] Filling the upper surfaces of the first copper wall and the second copper wall and the gap groove with a conductive protective layer that wraps the upper surfaces and side surfaces of the first copper wall and the second copper wall;
[0023] Forming the solder layer on the conductive protective layer covering the upper surface of the second copper wall;
[0024] The getter layer is formed on the conductive protection layer covering the first copper wall.
[0025] In an optional embodiment of the present application, the getter layer is prepared on the conductive protective layer covering the first copper wall, comprising:
[0026] Etching and removing the first photoresist layer and the seed layer located in the area covered by the patterned first photoresist layer on the capping wafer;
[0027] Performing secondary photoresist coating to form a second photoresist layer having a height greater than that of the solder layer, so that the second photoresist layer covers the solder layer;
[0028] According to the area where the first copper wall is located, the second photoresist layer is patterned and etched to remove the photoresist in the upper area and the side area of the first copper wall;
[0029] Prepare the getter layer on the first copper wall to wrap the conductive protective layer;
[0030] The patterned second photoresist layer is removed by etching.
[0031] In an optional embodiment of the present application, after wafer bonding the cover wafer and the sensor wafer, the method further includes:
[0032] The excitation electrode is energized using an activation probe to activate the getter layer.
[0033] A wafer-level vacuum packaged sensor chip, comprising a sensor wafer and a cover wafer;
[0034] The capping wafer is provided with a second annular copper wall, and a first copper wall provided at the inner edge of the second copper wall; a getter layer provided on the first copper wall; and a solder layer provided on the second copper wall;
[0035] The sensor wafer and the cover wafer are bonded to each other via the solder layer on the second copper wall;
[0036] At least two through-hole structures penetrating the thickness of the covering wafer are arranged on the covering wafer within the ring of the second copper wall, and the through-hole structure is filled with a copper wall extension connected to the first copper wall. The copper wall extension is exposed from the surface of the covering wafer on the side facing away from the sensor wafer, serving as an excitation electrode for exciting the getter layer.
[0037] In an optional embodiment of the present application, the surfaces of the first copper wall and the second copper wall are both provided with a conductive protective layer; the getter layer is provided on the conductive protective layer on the first copper wall; the solder layer is provided on the conductive protective layer on the second copper wall;
[0038] The conductive protection layer wraps the side surfaces of the first copper wall and the second copper wall and the upper surface facing away from the capping wafer.
[0039] In an optional embodiment of the present application, the getter layer extends from the upper surface of the first copper wall facing away from the capping wafer to the side surface of the first copper wall and wraps around it.
[0040] In an optional embodiment of the present application, the first copper wall is an L-shaped copper wall or a ring-shaped copper wall;
[0041] And / or, the first copper wall is a zigzag linear copper wall or a city wall linear copper wall.
[0042] The present invention provides a wafer-level vacuum packaged sensor chip and a preparation method thereof. The preparation method comprises: etching at least two blind hole structures at set positions corresponding to each sensing area on a cover wafer; forming a first copper wall, a second copper wall and a copper wall extension filled in the blind hole structure on the cover wafer; wherein the second copper wall is a copper wall forming an annular wall corresponding to the edge of each sensing area; the first copper wall is a copper wall extending at the inner edge of each annular wall, and the extension area of the first copper wall covers the position of the blind hole structure and is connected to the copper wall extension; forming a solder layer on the second copper wall; preparing a getter layer on the first copper wall; thinning the side of the cover wafer away from the blind hole structure until the blind hole structure becomes a through hole structure, so that the end of the copper wall extension located at the bottom of the hole of the blind hole structure is exposed to form an excitation electrode for activating the getter layer; wafer bonding the cover wafer and the sensor wafer through the solder layer to obtain a wafer-level vacuum packaged sensor chip.
[0043] In the present application, a blind hole structure is etched on a capping wafer, and a first copper wall corresponding to each sensing area is formed on the capping wafer, and a copper wall extension connected to the first copper wall is filled in the blind hole structure; a second copper wall for bonding and connecting the sensor wafer is prepared on the capping wafer, and a solder layer on the second copper wall is formed, and after a getter layer is prepared on the first copper wall, the surface of the capping wafer on the side away from the blind hole structure is further thinned, so that the blind hole structure is changed into a through-hole structure, so that the copper wall extension can be exposed from the surface of the capping wafer on the side away from the sensor wafer. Therefore, after the capping wafer and the sensor wafer are bonded to each other through the solder layer, although the getter layer is located in the cavity of each sensor chip unit, because the getter layer and the copper wall extension whose end is exposed from the outer surface of the capping wafer are electrically connected through the first copper wall, the getter layer can be electrically activated by applying an excitation voltage to the copper wall extension, thereby reducing the difficulty of activating the getter layer and avoiding the influence of thermal activation of the getter layer on the working performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0045] FIG1 is a schematic diagram of the first part of the process of preparing a wafer-level vacuum packaged sensor chip according to an embodiment of the present application;
[0046] FIG2 is a schematic diagram of the second part of the process of preparing a wafer-level vacuum packaged sensor chip according to an embodiment of the present application;
[0047] FIG3 is a schematic diagram of the third part of the process of preparing a wafer-level vacuum packaged sensor chip according to an embodiment of the present application;
[0048] FIG4 is a schematic diagram of the fourth part of the process of the method for preparing a wafer-level vacuum packaged sensor chip provided in an embodiment of the present application;
[0049] FIG5 is a schematic diagram of the fifth part of the process of the method for preparing a wafer-level vacuum packaged sensor chip provided in an embodiment of the present application;
[0050] FIG6 is a schematic diagram of the sixth part of the process of the method for preparing a wafer-level vacuum packaged sensor chip provided in an embodiment of the present application;
[0051] FIG7 is a schematic top view of the capping wafer in FIG1 ;
[0052] FIG8 is a schematic top view of a first type of groove formed in step S23 of the method for preparing a wafer-level vacuum packaged sensor chip provided in an embodiment of the present application;
[0053] FIG9 is a schematic top view of a second type of groove formed in step S23 of the method for preparing a wafer-level vacuum packaged sensor chip provided in an embodiment of the present application;
[0054] FIG10 is a schematic top view of a third type of groove formed in step S23 of the method for preparing a wafer-level vacuum packaged sensor chip provided in an embodiment of the present application;
[0055] In the accompanying drawings: 10 is a capping wafer, 100 is a blind hole structure, 11 is a seed layer, 12 is a first photoresist layer, 121 is a first groove, 122 is a second groove, 123 is a gap groove, 13 is a first copper wall, 131 is a copper wall extension, 14 is a second copper wall, 15 is a conductive protective layer, 16 is a solder layer, 17 is a second photoresist layer, 171 is a groove structure, 18 is an adsorbent layer, 20 is a sensor wafer, 21 is a sensing structure, and 22 is a bonding structure. DETAILED DESCRIPTION
[0056] The core of the present invention is to provide a photoelectric sensor chip and a preparation method thereof, which can realize the electrical activation of the getter layer in each sensor chip unit in the photoelectric sensor chip, reduce the difficulty of activating the getter layer, and avoid the influence of thermal activation of the getter layer on the working performance of the sensor chip.
[0057] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0058] As shown in Figures 1 to 10, Figure 1 is a schematic diagram of the first part of the process of preparing a wafer-level vacuum-packaged sensor chip provided in an embodiment of the present application; Figure 2 is a schematic diagram of the second part of the process of preparing a wafer-level vacuum-packaged sensor chip provided in an embodiment of the present application; Figure 3 is a schematic diagram of the third part of the process of preparing a wafer-level vacuum-packaged sensor chip provided in an embodiment of the present application; Figure 4 is a schematic diagram of the fourth part of the process of preparing a wafer-level vacuum-packaged sensor chip provided in an embodiment of the present application; Figure 5 is a schematic diagram of the fifth part of the process of preparing a wafer-level vacuum-packaged sensor chip provided in an embodiment of the present application; Figure 6 is a schematic diagram of the sixth part of the process of preparing a wafer-level vacuum-packaged sensor chip provided in an embodiment of the present application; Figure 7 is a top view schematic diagram of the capping wafer in Figure 1; Figures 8 to 10 are top view schematic diagrams of three different grooves formed in step S23 in Figure 2.
[0059] It should be noted that in the process of wafer-level packaging processing to form sensor chips, a plurality of sensor structures 21 arranged in an array, such as photosensitive units, are generally prepared on the sensor wafer 20. After the capping wafer 10 and the sensor wafer 20 are bonded to each other, a closed cavity can be formed for each sensor structure 21. Each sensor structure 21 and the closed cavity in which it is located is a sensor chip unit. After cutting each sensor chip unit, a plurality of sensor chips can be obtained, that is, a plurality of sensor chips can be prepared in batches at one time.
[0060] The wafer-level vacuum-packaged sensor chip processed and prepared in the present application can also be processed at one time to form sensor chip units corresponding to multiple sensor chips, and each sensor chip unit is the same; for the convenience of display and understanding, in the embodiments shown in Figures 1 to 6, only the structural processing flow diagram of two sensor chip units in the wafer-level vacuum-packaged sensor chip is shown, and the dotted lines in Figures 1 to 6 also roughly show the dividing line between the two sensor chip units, which will not be repeated later.
[0061] In a specific embodiment of the present application, the method for preparing the wafer-level vacuum packaged sensor chip may include:
[0062] S1: Etching at least two blind hole structures 100 at set positions in each sensing area on the capping wafer 10 .
[0063] In this embodiment, a sensing area corresponds to an area where a sensing chip unit is located after the cover wafer 10 and the sensor wafer 20 are bonded to each other.
[0064] S2 : forming a first copper wall 13 and a second copper wall 14 and a copper wall extension 131 filled in the blind via structure 100 on the capping wafer 10 .
[0065] Among them, the second copper wall 14 is a copper wall that forms an annular wall corresponding to the edge of each sensing area; the first copper wall 13 is a copper wall extending at the inner edge of each annular wall, and the extended area of the first copper wall 13 covers the location of the blind hole structure 100 and is connected to the copper wall extension part 131.
[0066] S3 : forming a solder layer 16 on the second copper wall 14 .
[0067] S4: preparing a getter layer 18 on the first copper wall 13 .
[0068] S5: Thinning the side of the capping wafer 10 away from the blind hole structure 100 until the blind hole structure 100 becomes a through hole structure, so that the end of the copper wall extension 131 located at the bottom of the blind hole structure 100 is exposed to form an excitation electrode for activating the getter layer 18.
[0069] S6: wafer bonding is performed on the cover wafer 10 and the sensor wafer 20 through the solder layer 16 to obtain a photoelectric sensor chip.
[0070] It should be noted that steps S1 to S6 in the process of the preparation method of this embodiment correspond to the processing steps shown in Figures 1 and 6, respectively. It can be determined that the preparation process of the wafer-level vacuum packaged sensor chip in this application is generally prepared and formed in sequence according to the process shown in Figures 1 to 6.
[0071] On this basis, the second copper wall 14 in this embodiment is used to realize the mutual bonding of the sensor wafer 20 and the cover wafer 10, therefore, it is necessary to form a solder layer 16 on the second copper wall 14; and the first copper wall 10 is used to carry the getter layer 18; and after the cover wafer 10 is thinned, the bottom of the blind hole structure 100 is removed, and the blind hole structure 100 forms a through hole structure, and the end of the copper wall extension portion 131 located in the through hole structure is exposed from the surface of the cover wafer 10 on the side away from the first copper wall 13, and the cover wafer 1 0 and the sensor wafer 20 are bonded to each other, the conductivity of the copper wall extension 131 can be used as an excitation electrode to electrically activate the getter layer 181. In practical applications, after the cover wafer 10 and the sensor wafer 20 are bonded to each other, the activation probe can be used to connect the excitation voltage to the copper wall extension 131, thereby realizing electrical activation of the getter layer 18, which can not only reduce the difficulty of activating the getter layer 18 to a certain extent, but also avoid the getter layer 18 from affecting the working performance of the sensor chip due to thermal activation.
[0072] To summarize, in the present application, a blind hole structure is etched on a capping wafer, and a first copper wall corresponding to each sensing area is formed on the capping wafer, and a copper wall extension connected to the first copper wall is filled in the blind hole structure; a second copper wall for bonding and connecting the sensor wafer is prepared on the capping wafer, and a solder layer on the second copper wall is formed, and after a getter layer is prepared on the first copper wall, the surface of the capping wafer on the side away from the blind hole structure is further thinned, so that the blind hole structure is changed into a through hole structure, so that the copper wall extension can be exposed from the surface of the capping wafer on the side away from the sensor wafer, and thus, after the capping wafer and the sensor wafer are bonded to each other through the solder layer, although the getter layer is located in the cavity of each sensor chip unit, because the getter layer and the copper wall extension exposed at the end are electrically connected through the first copper wall, the getter layer can be electrically activated by applying an excitation voltage to the copper wall extension, thereby reducing the difficulty of activating the getter layer and avoiding the influence of thermal activation of the getter layer on the working performance of the chip.
[0073] The following will further discuss in detail each step in the above preparation process with specific examples.
[0074] As shown in FIG1 , the capping wafer 10 of the present application is specifically a wafer, which needs to be bonded to the sensor wafer 20; at least two blind hole structures 100 are processed in the sensing area corresponding to each sensor chip unit on the wafer through the above step S1, which is equivalent to forming two excitation electrodes to ensure that a circuit path can be formed for the getter layer 18. In practical applications, it is not excluded to set more blind hole structures 100, as long as the copper wall extension 131 in the blind hole structure 100 can connect the getter layer 18 to the current path when the excitation voltage is turned on. Combined with FIG1 and FIG7 , FIG1 is a schematic diagram of the AA section in FIG7 , and FIG7 shows two sensing areas, in which the dotted line is the boundary line of the two sensing areas, and two blind hole structures 100 are processed in each sensing area. The depth of the blind hole structure 100 in this embodiment can be in the range of 50μm~500μm. In practical applications, the depth of the blind hole structure 100 can be selected appropriately based on the thickness of the capping wafer 10. The thicker the capping wafer 10 is, the deeper the depth of the blind hole structure 100 should be, thereby avoiding the subsequent thinning of the capping wafer 10, so that when the blind hole structure 100 is transformed into a through hole structure, the thickness of the capping wafer 10 needs to be reduced more.
[0075] After the blind hole structure 100 is formed on the capping wafer 10 in step S1, the first copper wall 13, the second copper wall 14 and the copper wall extension 131 may be further prepared in step S2; referring to FIG. 2 , in an optional implementation of the present embodiment, step S2 may further include:
[0076] S21 : preparing a seed layer 11 on the capping wafer 10 to cover the surface of the capping wafer 10 and the hole wall and hole bottom of the blind hole structure 100 .
[0077] The seed layer 11 in this embodiment may specifically be a stacked titanium layer and a copper layer; wherein the thickness of the titanium layer is 10 nm to 1000 nm, and the thickness of the copper layer is 10 nm to 1000 nm.
[0078] On the surface of the cover wafer 10 on which the blind hole structure 100 is provided, the hole wall and the hole bottom of the blind hole structure 100 are directly exposed to the outside, thereby, a continuous and complete seed layer 11 can be formed by deposition at one time on the upper surface of the cover wafer 10 (i.e., the surface on which the blind hole structure 100 is provided) and the hole wall and the hole bottom of the blind hole structure 100, so as to facilitate the subsequent electroplating of the first copper wall 13 and the second copper wall 14 on the surface of the seed layer 11 and the copper wall extension 131.
[0079] S22 : coating a first photoresist layer 12 on the seed layer 11 .
[0080] As shown in step S22 of FIG. 2 , the first photoresist layer 12 covers the entire surface of the capping wafer 10 . In practical applications, the thickness of the first photoresist layer 12 may be 10 μm to 200 μm.
[0081] S23: performing pattern etching on the first photoresist layer 12 to form a first groove 121 and a second groove 122 not covered by the photoresist;
[0082] The extension area of the first trench 121 covers the location of the blind hole structure 100 and is connected to the blind hole structure 100 .
[0083] It can be understood that a first photoresist layer 12 is formed on the surface of the seed layer 11 on the capping wafer 10, and the first photoresist layer 12 is patterned and etched so that the patterned first photoresist 12 serves as a mask for preparing the first copper wall 13, the second copper wall 14 and the copper wall extension 131.
[0084] Therefore, the position where the first groove 121 is etched on the first photoresist layer 12 is also the position where the first copper wall 13 needs to be formed, and the position of the second groove 122 is also the position where the second copper wall 14 needs to be formed; and when the first photoresist layer 12 is etched to form the first groove 121, the photoresist in the blind hole structure 100 should be removed at the same time, so as to subsequently form a copper wall extension 131 in the blind hole structure 100.
[0085] Obviously, the distribution shape and distribution position of the first grooves 121 correspond to the shape and position of the first copper wall 13 ; and the distribution shape and distribution position of the second grooves 122 determine the shape and position of the second copper wall 14 .
[0086] 8 to 10 show three different top views of the first photoresist layer 12 on the capping wafer 10 after patterning; each top view shows that the shape of the first groove 121 formed in step S23 is different.
[0087] The first groove 121 shown in FIG. 8 is an annular groove, and the blind hole structure 100 is located in the coverage area of the annular groove; the first groove 121 in FIG. 9 and FIG. 10 are both L-shaped grooves, and the blind hole structure 100 is also located in the area covered by the first groove 121; in addition, the first groove 121 in FIG. 9 is a wall linear groove, while the first groove 121 in FIG. 10 is a sawtooth linear groove.
[0088] S24: forming a first copper wall 13, a copper wall extension 131 and a second copper wall 14 in the first groove 121, the blind hole structure 100 and the second groove 122 respectively; wherein the first copper wall 13 and the copper wall extension 131 are integrally formed, and the height of the first copper wall 13 is smaller than that of the second copper wall 14.
[0089] Based on the masking effect of the patterned first photoresist layer 12, a copper wall structure is formed in the first groove 121 and the second groove 122. Because the area where the first groove 121 is located covers the area where the blind hole structure 100 is located, the first groove 121 and the blind hole structure 100 are interconnected. While the first copper wall 13 is formed in the first groove 121, a copper wall extension portion 131 integrally formed with the first copper wall 13 can be further filled in the blind hole structure 100; a second copper wall 14 with a ring structure is formed in the second groove 122.
[0090] It can be understood that, in the present embodiment, when the cover wafer 10 and the sensor wafer 20 are bonded to each other, they are bonded to each other through the second copper wall 14; the inner area of the ring formed by each second copper wall 14 is the inner area of the closed cavity corresponding to a sensor chip unit; and the first copper wall 13 is to support the formation of the getter layer 18 and needs to be located in each closed cavity. Therefore, the first copper wall 13 should be located in the ring of the second copper wall 14 and should extend as close as possible to the inner edge of the ring of the second copper wall 14, thereby avoiding mutual obstruction between the first copper wall 13 and the sensing structure 21 on the sensor wafer 20 when the sensor wafer 20 and the cover wafer 10 are bonded to each other.
[0091] In addition, because the second copper wall 14 is mainly used for bonding the cover wafer 10 and the sensor wafer 20, the height of the second copper wall 14 should be greater than the height of the first copper wall 13, so as to avoid the first copper wall 13 or the getter layer 18 on the first copper wall 13 from abutting against the sensor wafer 20 when the packaging wafer 10 and the sensor wafer 20 are bonded to each other.
[0092] In practical applications, the height of the first copper wall 13 can be 10μm~150μm; and the height of the second copper wall 14 can be 5μm~145μm. To facilitate subsequent processes, the height of the second copper wall 14 can be 5μm~50μm higher than that of the first copper wall 13.
[0093] As described above, the structural shape of the first groove 121 determines the structural shape of the first copper wall 13, thereby a first copper wall 13 with an annular structure or an L-shaped first copper wall 13 can be formed based on the first groove 121 shown in Figures 8 to 10, and the first copper wall 13 can also be a zigzag line copper wall or a city wall line copper wall.
[0094] Based on the above discussion, the main function of the second copper wall 14 is to achieve bonding between the capping wafer 10 and the sensor wafer 20. Therefore, it is necessary to further prepare a solder layer on the second copper wall 14, and a getter layer 18 needs to be prepared on the first copper wall 13; but in order to further protect the first copper wall 13 and the second copper wall 14, referring to FIG. 3, in an optional embodiment of the present embodiment, the above step S3 may further include:
[0095] S31 : performing secondary etching on the first photoresist layer 12 to remove the sidewall photoresist adhering to the first copper wall 13 and the second copper wall 14 , and forming a gap groove 123 between the sidewalls of the first copper wall 13 and the second copper wall 14 and the first photoresist layer 12 .
[0096] S32 : filling the upper surfaces of the first copper wall 13 and the second copper wall 14 and the gap groove 123 with a conductive protection layer 15 that wraps the upper surfaces and side surfaces of the first copper wall 13 and the second copper wall 14 .
[0097] S33 : forming a solder layer 16 on the conductive protection layer 15 covering the upper surface of the second copper wall 14 .
[0098] Correspondingly, the above step S4 may further include: preparing and forming a getter layer 18 on the conductive protection layer 15 covering the first copper wall 14 .
[0099] In this embodiment, in order to more comprehensively protect the first copper wall 13 and the second copper wall 14, the photoresist in the first photoresist layer 12 that is in contact with the side of the first copper wall 13 and the second copper wall 14 is further etched and removed, and a gap groove 123 is formed on the side of the first copper wall and the second copper wall. The width of the gap groove 123 can be 0.1μm~5μm, so that the upper surface (i.e., the surface away from the side of the capping wafer 10) and the side of the first copper wall 13 and the second copper wall 14 are exposed, so that when the conductive protective layer 15 is formed by electroplating, a conductive protective layer 15 covering the upper surface and side of the first copper wall 13 and the second copper wall 14 can be formed, so that the conductive protective layer 15 can wrap the first copper wall 13 and the second copper wall 14 in an all-round way, and improve the protection effect of the first copper wall 13 and the second copper wall 14. The thickness of the conductive protective layer 15 can be 0.1μm~6μm, and the conductive protective layer 15 can be a Ni metal layer or a Pt metal layer.
[0100] Referring to S33 shown in FIG3 , while preparing and forming the solder layer 16 on the conductive protective layer 15 of the second copper wall 14, because the conductive protective layer 15 on the first copper wall 13 does not have a mask structure, in general, a solder layer 16 will also be formed on the upper surface of the conductive protective layer 15 of the second copper wall 14; the solder layer 16 can be etched and removed before preparing the getter layer 18, or the getter layer 18 can be further formed directly on the surface of the solder layer 16, and no specific restrictions are made in this application. In addition, the solder layer 16 in this embodiment can be a SnAg layer or a Sn layer, and the thickness of the solder layer can be 3μm~20μm. Therefore, the conductive protective layer 15 in this embodiment can, on the one hand, wrap and protect the first copper wall 13 and the second copper wall 14, and can further isolate the first copper wall 13 and the second copper wall 14 from contacting each other with the solder layer 16.
[0101] On this basis, referring to FIG. 4 , in an optional embodiment of the present embodiment, the above step S4 may further include:
[0102] S41 : etching and removing the first photoresist layer 12 and the seed layer 11 located in the area covered by the patterned first photoresist layer 12 on the capping wafer 10 .
[0103] S42: performing secondary photoresist coating to form a second photoresist layer 17 having a height greater than that of the solder layer 16, so that the second photoresist layer 17 covers the solder layer 16;
[0104] S43: performing pattern etching on the second photoresist layer 17 according to the area where the first copper wall is located, and removing the photoresist in the upper area and the side area of the first copper wall 13;
[0105] S44: preparing a getter layer 18 on the first copper wall 13 to wrap the conductive protective layer 15;
[0106] S45: etching and removing the patterned second photoresist layer 17.
[0107] Because it is only necessary to prepare the getter layer 18 on the first copper wall 13, and the first photoresist layer 12 that has been etched and patterned cannot serve as a mask for the second copper wall 14, it is necessary to etch and remove the first photoresist layer 17 and the seed layer 11 to which it is attached at one time. At this time, only the lower surface of the first copper wall 13 and the second copper wall 14 (close to the surface of the capping wafer) and the seed layer 11 in the blind hole structure 100 are retained, while the seed layer 11 in other areas is etched and removed.
[0108] After the first photoresist layer 17 can be removed, the surface of the first copper wall 13 and the second copper wall 14 on the capping wafer 10 can be re-coated to form a second photoresist layer 17, so that the second photoresist layer 17 completely covers and wraps the first copper wall 13 and the second copper wall 14, and the conductive protective layer 15 and the solder layer 16 on the first copper wall 13 and the second copper wall 14 are also completely wrapped in the second photoresist layer 17; the second photoresist layer 17 is further patterned and etched, and at this time, the photoresist wrapping the first copper wall 13 is mainly etched and removed, so that the conductive protective layer 15 (or also including the solder layer 15) on the first copper wall 13 can be exposed, thereby forming a getter layer 18 on the conductive protective layer 15 of the first copper wall 13.
[0109] On this basis, in order to increase the coverage area of the getter layer 18 to a certain extent in the present embodiment, when the second photoresist layer 17 is patterned and etched, not only the photoresist located above the first copper wall 13 is etched away, but also the photoresist directly attached to the side of the first copper wall 13 The conductive protective layer 15 is further etched away, so that a gap is formed between the conductive protective layer 15 located on the side of the first copper wall 13 and the groove sidewall of the second photoresist layer 17, and the width of the gap can be 2μm~50μm, that is, the second photoresist layer 12 is etched at the position of the first copper wall 13 to form a groove structure 171, and the width of the groove structure 171 is greater than the width of the first copper wall 13 plus the sum of the thickness of the conductive protective layer 15 on both sides of the side of the first copper wall 13. Therefore, when the getter layer 18 is processed on the conductive protective layer 15 on the first copper wall 13, the getter layer 18 can be formed to fully wrap the entire conductive protective layer 15 on the first copper wall 13 from different directions of the side and upper surface of the first copper wall 13, which can further expand the coverage area of the getter layer 18 to a great extent, thereby improving the adsorption effect of the getter layer 18.
[0110] As described above, based on the first groove 121 shown in Figures 8 to 10, a first copper wall 13 with an annular structure or an L-shaped first copper wall 13 can be formed, and the first copper wall 13 can also be a zigzag line copper wall or a city wall line copper wall; this can also greatly increase the side area and the upper surface area of the first copper wall 13. Accordingly, when a wrapped getter layer 18 is formed on the side and upper surface of the first copper wall 13, the surface area of the getter layer 18 can also be greatly increased, thereby improving the adsorption effect of the getter layer 18.
[0111] Based on the above discussion, after the getter layer 18 is prepared on the first copper wall 13, as shown in Figure 5, the cover wafer 10 needs to be further thinned from the surface of the cover wafer 10 on the side away from the first copper wall 13, until the bottom of the blind hole structure 100 and the seed layer 11 at the bottom of the hole are thinned and removed, so that the blind hole structure 100 can be transformed into a through hole structure, and the copper wall extension portion 131 located in the through hole structure can also be exposed on the surface of the cover wafer 10 on the side away from the first copper wall 13, thereby serving as an excitation electrode for activating the getter layer 18.
[0112] In practical applications, after the cover wafer 10 is thinned, the cover wafer 10 and the sensor wafer 20 can be bonded; as shown in FIG6 , at a position on the sensor wafer 20 corresponding to the second copper wall 14 on the cover wafer 10 , a bonding structure 22 is also correspondingly provided on the sensor 20 , and the bonding structure 22 can be a material structure similar to the solder layer 16 , so that the bonding structure 22 can be bonded to the solder layer 16 on the second copper wall 14 .
[0113] It is understandable that, in practical applications, the cover wafer 10 is first thinned in the manner shown in FIG5 , and then the cover wafer 10 and the sensor wafer 20 are bonded in the manner shown in FIG6 . Alternatively, the cover wafer 10 and the sensor wafer 20 may be first bonded in the manner shown in FIG6 , and then the side of the cover wafer 10 away from the sensor wafer 20 is thinned until the end of the copper wall extension 131 is exposed. In addition, because the end of the copper wall extension 131 in this embodiment is exposed, if the activation of the adsorbent layer 18 is unsuccessful, the adsorbent layer 18 may be activated multiple times to ultimately ensure the working performance of the adsorbent layer 18 .
[0114] In practical applications, the sensor chip prepared according to the above-mentioned wafer-level vacuum packaging sensor chip preparation method in the present application can be a photoelectric detection chip. Therefore, after the adsorbent layer 18 is activated, an anti-reflection film layer can be further formed on the surface of the side of the cover wafer 10 away from the sensor wafer 20, thereby improving the light transmittance of the cover wafer in the photoelectric detection chip.
[0115] The present application further provides an embodiment of a wafer-level vacuum packaged sensor chip, which can be prepared based on any of the above-mentioned methods for preparing a wafer-level vacuum packaged sensor chip, and the structure of the wafer-level vacuum packaged sensor chip can refer to the chip structure of the final bonding formation in FIG6 . The wafer-level vacuum packaged sensor chip may include:
[0116] Sensor wafer 20 and cover wafer 10;
[0117] The capping wafer 10 is provided with an annular second copper wall 14, and a first copper wall 13 provided at the inner edge of the second copper wall 14; a getter layer 18 provided on the first copper wall 13; and a solder layer 15 provided on the second copper wall 14;
[0118] The sensor wafer 20 and the cover wafer 10 are bonded to each other via the solder layer 15 on the second copper wall 14;
[0119] At least two through-hole structures penetrating the thickness of the capping wafer 10 are arranged on the capping wafer 10 within the ring of the second copper wall 14, and the through-hole structure is filled with a copper wall extension 131 connected to the first copper wall 13. The copper wall extension 131 is exposed from the surface of the capping wafer 10 facing away from the sensor wafer 20, serving as an excitation electrode for exciting the getter layer 18.
[0120] The structure of the wafer-level vacuum packaged sensor chip in this embodiment can refer to the chip structure after the sensor wafer 20 and the cover wafer 10 are packaged with each other as shown in FIG6 . In addition, it is difficult to deposit and form the first copper wall 13, the second copper wall 14, and the copper wall extension 131 directly on the cover wafer 10 stably, so generally, a seed layer 11 is provided between the surfaces where the first copper wall 13, the second copper wall 14, and the copper wall extension 131 are respectively connected to the cover wafer 10, and the seed layer 11 can be a stacked titanium layer and a copper layer; wherein the thickness of the titanium layer is 10nm~1000nm, and the thickness of the copper layer is 10nm~1000nm.
[0121] It can be understood that the first copper wall 13 and the copper wall extension 131 in the present embodiment are both conductive structures. At the same time, the getter layer 18 located inside the closed cavity surrounded by the second copper wall 14, the sensor wafer 20 and the cover wafer 10 is arranged on the first copper wall 13, and the end of the copper wall extension 131 away from the first copper wall 13 is exposed on the outer surface of the cover wafer 10 through the through-hole structure. Therefore, the copper wall extension 131 can be used as an excitation electrode, and an excitation voltage is applied to the end of the copper wall extension 131 outside the closed cavity. The conductive properties of the copper wall extension 131 and the first copper wall 13 are used to electrically activate the getter layer 18. The activation method is simple and easy to operate, and will not affect the working performance of the sensing structure on the sensor wafer 20. On the basis of ensuring the working quality of the sensor chip, the difficulty of activating the getter layer 18 is reduced.
[0122] In addition, the height of the first copper wall 13 in this embodiment can be 10 μm to 150 μm, and the height of the second copper wall 14 can be 5 μm to 145 μm, and the height of the second copper wall 14 can be 5 μm to 50 μm lower than the height of the first copper wall 13. The thickness of the getter layer 18 disposed on the first copper wall 13 can be 0.5 μm to 5 μm, and the solder layer 15 disposed on the second copper wall 14 can be a SnAg layer or a Sn layer with a thickness of 3 μm to 20 μm.
[0123] In an optional embodiment of the present application, the surfaces of the first copper wall 13 and the second copper wall 14 are both provided with a conductive protective layer 15; the getter layer 18 is provided on the conductive protective layer 15 on the first copper wall 13; the solder layer 16 is provided on the conductive protective layer 15 on the second copper wall 14;
[0124] The conductive protection layer 15 wraps around the side surfaces of the first copper wall 13 and the second copper wall 14 and the upper surface facing away from the capping wafer 10 .
[0125] In order to avoid protecting the first copper wall 13 and the second copper wall 14, in this embodiment, on the basis of further wrapping the surface of the first copper wall 13 and the second copper wall 14 with a conductive protective layer 15, a getter layer 18 and a solder layer 16 are respectively prepared on the conductive protective layer 15 on the first copper wall 13 and the second copper wall 14.
[0126] The conductive protective layer 15 in this embodiment fully covers the first copper wall 13 and the second copper wall 14 from the upper surface (the surface close to the sensor wafer 20) and the side surface, thereby achieving more comprehensive protection for the first copper wall 13 and the second copper wall 14 and improving the protection effect.
[0127] In addition, it should be noted that, based on the preparation process flow, when preparing and forming the solder layer 15 on the conductive protective layer 15 of the second copper wall 14, a solder layer 16 may also be formed on the conductive protective layer 15 of the first copper wall 13, and the solder layer 16 can be removed or retained; when this part of the solder layer 16 is retained, the adsorbent layer 18 can be set on the surface of the solder layer 16.
[0128] In addition, the thickness of the conductive protection layer 15 can be 0.1 μm to 6 μm, and the conductive protection layer 15 can be a Ni metal layer or a Pt metal layer.
[0129] On this basis, in order to increase the area of the adsorbent layer 18 as much as possible, in an optional embodiment of the present embodiment, the getter layer 18 can be extended from the upper surface of the first copper wall 13 away from the cover wafer 10 to the side of the first copper wall 13 to wrap around it, thereby expanding the surface area of the getter layer 18 to the greatest extent, thereby improving the air absorption effect of the getter layer 18.
[0130] It can be understood that when the surface of the first copper wall 13 is wrapped with a conductive protective layer 15, the getter layer 18 also wraps and covers the entire conductive protective layer 15 from the upper surface and side of the first copper wall 13 in all directions, and a solder layer 16 is also provided on the conductive protective layer 15 of the first copper wall 13, then the getter layer 18 on the upper surface of the first copper wall 13 is covered on the surface of the solder layer 16, and on the side of the first copper wall 13 is covered on the surface of the conductive protective layer 15.
[0131] In order to further increase the surface area of the getter layer 18, in another optional embodiment of the present embodiment, the first copper wall 13 can also be an L-shaped copper wall or a ring-shaped copper wall; and / or, the first copper wall 13 is a zigzag copper wall or a city wall copper wall.
[0132] In the present embodiment, the first copper wall 13 adopts an L-shaped extended copper wall or a ring-shaped extended copper wall, which is equivalent to increasing the total length of the entire first copper wall 13 to a certain extent. The first copper wall 13 adopts a zigzag copper wall or a city wall copper wall, which can increase the side area of the first copper wall 13 to a certain extent. Therefore, the coverage area of the getter layer 18 wrapped around the first copper wall 13 can obviously also be increased accordingly, thereby further improving the air absorption effect of the getter layer 18.
[0133] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "includes", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements are inherent to the elements. In the absence of more restrictions, the elements limited by the sentence "comprising one..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. In addition, the above-mentioned technical solution provided in the embodiment of the present application is consistent with the corresponding technical solution in the prior art in principle, and the part is not described in detail, so as to avoid too much redundancy.
[0134] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A method for preparing a wafer-level vacuum packaged sensor chip, characterized in that: include: Etching at least two blind hole structures (100) at set positions corresponding to each sensing area on the cover wafer (10); A first copper wall (13) and a second copper wall (14) and a copper wall extension (131) filled in the blind hole structure (100) are formed on the cover wafer (10); wherein the second copper wall (14) is a copper wall that forms an annular wall corresponding to the edge of each sensing area; the first copper wall (13) is a copper wall that extends at the inner edge of each annular wall, and the extension area of the first copper wall (13) covers the location of the blind hole structure (100) and is connected to the copper wall extension (131); Preparing and forming a solder layer (16) on the second copper wall (14); Forming a getter layer (18) on the first copper wall (13); Thinning the side of the capping wafer (10) facing away from the blind hole structure (100) until the blind hole structure (100) becomes a through hole structure, so that the end of the copper wall extension (131) located at the bottom of the blind hole structure (100) is exposed to form an excitation electrode for activating the getter layer (18); The cover wafer (10) and the sensor wafer (20) are wafer-bonded via the solder layer (16) to obtain a wafer-level vacuum packaged sensor chip.
2. The method for preparing a wafer-level vacuum packaged sensor chip according to claim 1, characterized in that: A first copper wall (13) and a second copper wall (14) are formed on the capping wafer (10), as well as a copper wall extension (131) filled in the blind hole structure (100), comprising: A seed layer (11) is prepared on the cover wafer (10) to cover the surface of the cover wafer (10) and the hole wall and hole bottom of the blind hole structure (100); Coating a first photoresist layer (12) on the seed layer (11); The first photoresist layer (12) is pattern-etched to form a first groove (121) and a second groove (122) not covered by the photoresist; wherein an extension area of the first groove (121) covers the location of the blind hole structure (100) and is connected to the blind hole structure (100); The first copper wall (13), the copper wall extension (131) and the second copper wall (14) are respectively formed in the first groove (121), the blind hole structure (100) and the second groove (122); wherein the first copper wall (13) and the copper wall extension (131) are integrally formed, and the height of the first copper wall (13) is less than the height of the second copper wall (14).
3. The method for preparing a wafer-level vacuum packaged sensor chip according to claim 2, characterized in that: The first groove (121) is an L-shaped extending groove or a ring-shaped extending groove; The first groove (121) is a sawtooth linear groove or a city wall linear groove.
4. The method for preparing a wafer-level vacuum packaged sensor chip according to claim 2, characterized in that: Forming a solder layer (16) on the second copper wall (14); and forming a getter layer (18) on the first copper wall (13), comprising: Performing secondary etching on the first photoresist layer (12) to remove the sidewall photoresist adhering to the first copper wall (13) and the second copper wall (14), thereby forming a gap groove (123) between the sidewalls of the first copper wall (13) and the second copper wall (14) and the first photoresist layer (12); Filling the upper surfaces of the first copper wall (13) and the second copper wall (14) and the gap groove (123) with a conductive protective layer (15) that wraps the upper surfaces and side surfaces of the first copper wall (13) and the second copper wall (14); Forming the solder layer (16) on the conductive protective layer (15) covering the upper surface of the second copper wall (14); The getter layer (18) is formed on the conductive protective layer (15) covering the first copper wall (13).
5. The method for preparing a wafer-level vacuum packaged sensor chip according to claim 4, characterized in that: The getter layer (18) is prepared on the conductive protective layer (15) covering the first copper wall (13), comprising: Etching and removing the first photoresist layer (12) and the seed layer (11) located in the area covered by the patterned first photoresist layer (12) on the capping wafer (10); Performing secondary photoresist coating to form a second photoresist layer (17) having a height greater than that of the solder layer (16), so that the second photoresist layer (17) covers the solder layer (16); According to the area where the first copper wall (13) is located, the second photoresist layer (17) is patterned and etched to remove the photoresist in the area above and the side areas of the first copper wall (13); The getter layer (18) wrapping the conductive protective layer (15) is formed on the first copper wall (13); The patterned second photoresist layer (17) is removed by etching.
6. The method for preparing a wafer-level vacuum packaged sensor chip according to claim 1, characterized in that: After wafer bonding the cover wafer (10) and the sensor wafer (20), the method further comprises: The excitation electrode is energized using an activation probe to activate the getter layer (18).
7. A wafer-level vacuum packaged sensor chip, characterized in that: It comprises a sensor wafer (20) and a cover wafer (10); The cover wafer (10) is provided with an annular second copper wall (14), and a first copper wall (13) arranged at an inner edge of the second copper wall (14); a getter layer (18) arranged on the first copper wall (13); and a solder layer (16) arranged on the second copper wall (14); The sensor wafer (20) and the cover wafer (10) are bonded and connected to each other via the solder layer (16) on the second copper wall; At least two through-hole structures penetrating the thickness of the cover wafer (10) are arranged on the cover wafer (10) within the ring of the second copper wall (14), and the through-hole structures are filled with a copper wall extension (131) connected to the first copper wall (13); the copper wall extension (131) is exposed from the surface of the cover wafer (10) on the side facing away from the sensor wafer (20) and serves as an excitation electrode for exciting the getter layer (18).
8. The wafer-level vacuum packaged sensor chip according to claim 7, characterized in that: The surfaces of the first copper wall (13) and the second copper wall (14) are both provided with a conductive protective layer (15); the getter layer (18) is provided on the conductive protective layer (15) on the first copper wall (13); and the solder layer (16) is provided on the conductive protective layer (15) on the second copper wall (14); The conductive protective layer (15) wraps around the side surfaces of the first copper wall (13) and the second copper wall (14) as well as the upper surface facing away from the capping wafer (10).
9. The wafer-level vacuum packaged sensor chip according to claim 7, characterized in that: The getter layer (18) extends from the upper surface of the first copper wall (13) on a side facing away from the cover wafer (10) to the side surface of the first copper wall (13) and wraps around it.
10. The wafer-level vacuum packaged sensor chip according to claim 9, characterized in that: The first copper wall (13) is an L-shaped copper wall or a ring-shaped copper wall; And / or, the first copper wall (13) is a sawtooth line copper wall or a city wall line copper wall.