Semiconductor device and memory device

Abstract

A novel semiconductor device is provided. The first circuit is electrically connected with the second circuit through a first wire, the first circuit is electrically connected with the fourth circuit through a third wire and a fourth wire, and the second circuit is electrically connected with the third circuit through a fifth wire. The first circuit has a function of bringing the first wiring, the second wiring, the third wiring, and the fourth wiring into a conductive state or a non-conductive state, and the third circuit has a function of holding a potential corresponding to the first data. The second circuit has a function of supplying a potential corresponding to the first data from the first wiring to the fifth wiring, a function of holding a potential corresponding to the second data, and a function of amplifying a change in the potential of the fifth wiring and outputting the change to the first wiring. The fourth circuit has a function of outputting a potential corresponding to the first data or the second data in accordance with a potential difference between the third wiring and the fourth wiring.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a storage device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an object, a method, a driving method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product, or a composition of matter. Therefore, more specifically, as an example of the technical field of one embodiment of the present invention disclosed in this specification, etc., semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, camera devices, lighting devices, computing devices, control devices, storage devices, input devices, output devices, input-output devices, signal processing devices, electronic computers, electronic devices, their driving methods, or their manufacturing methods can be cited. Background Art

[0003] In recent years, semiconductor devices have been developed, and semiconductor devices are mainly used in, for example, LSI, CPU, memory, etc. The CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit formed by processing a semiconductor wafer into a chip and having electrodes formed thereon as connection terminals.

[0004] For example, semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards (eg, printed wiring boards) and are used as one of the components of various electronic devices.

[0005] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply recorded as display devices). As semiconductor thin films that can be used for transistors, silicon-based semiconductor materials are widely known, and as other materials, oxide semiconductors have attracted attention.

[0006] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely low in a non-conducting state. For example, Patent Document 1 has disclosed a low-power CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 has disclosed a storage device that can utilize the low leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0007] In recent years, as electronic devices have become smaller and lighter, there has been an increased demand for further high density of integrated circuits. In addition, it is required to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a plurality of memory cells are arranged in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit. [Prior technical literature] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0009] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 Summary of the invention Technical problem to be solved by the invention

[0010] One of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of achieving high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of reducing manufacturing costs. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of achieving low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of increasing operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of achieving miniaturization. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. In addition, one of the purposes of one embodiment of the present invention is to provide a storage device comprising any one or more of the semiconductor devices listed above.

[0011] Note that the description of these purposes does not prevent the existence of other purposes. Note that one embodiment of the present invention does not necessarily achieve all of the above purposes. Note that purposes other than the above can be known and extracted from the description of the specification, drawings, claims, etc. Solutions to technical problems (1) One embodiment of the present invention is a semiconductor device including: a first circuit; a second circuit; a third circuit; a fourth circuit; a first wiring; a second wiring; a third wiring; a fourth wiring; and a fifth wiring, wherein the first circuit is electrically connected to the second circuit via the first wiring, the first circuit is electrically connected to the fourth circuit via the third wiring and the fourth wiring, and the second circuit is electrically connected to the third circuit via the fifth wiring, the first circuit has a function of making the first wiring, the second wiring, the third wiring, and the fourth wiring mutually in a conductive state or a non-conductive state, the third circuit has a function of maintaining a potential corresponding to first data, the second circuit has a function of supplying a potential corresponding to the first data from the first wiring to the fifth wiring, a function of maintaining a potential corresponding to the second data, and a function of amplifying a change in the potential of the fifth wiring and outputting it to the first wiring, and the fourth circuit has a function of outputting a potential corresponding to the first data or the second data according to a potential difference between the third wiring and the fourth wiring. (2) In addition, in the above (1), the first circuit includes: a first transistor; a second transistor; a third transistor; a fourth transistor; and a fifth transistor, wherein the first transistor can have a function of making the first wiring and the second wiring in a conductive state or a non-conductive state, the second transistor can have a function of making the first wiring and the third wiring in a conductive state or a non-conductive state, the third transistor can have a function of making the second wiring and the fourth wiring in a conductive state or a non-conductive state, the fourth transistor can have a function of precharging the first wiring, and the fifth transistor can have a function of precharging the second wiring. (3) In addition, in the above (1), the first circuit includes: a first transistor; a second transistor; a third transistor; a first capacitor; and a second capacitor, wherein the first transistor can have a function of making the first wiring and the second wiring in a conductive state or a non-conductive state, the second transistor can have a function of making the first wiring and the third wiring in a conductive state or a non-conductive state, the third transistor can have a function of making the second wiring and the fourth wiring in a conductive state or a non-conductive state, the first capacitor can have a function of changing the potential of the first wiring, and the second capacitor can have a function of changing the potential of the second wiring. (4) In addition, in the above (1), the first circuit includes: a first transistor; a second transistor; and a third transistor, wherein the first transistor can have a function of making the first wiring and the second wiring in a conductive state or a non-conductive state, the second transistor can have a function of making the first wiring and the third wiring in a conductive state or a non-conductive state, the third transistor can have a function of making the second wiring and the fourth wiring in a conductive state or a non-conductive state, and the fourth circuit includes: a sixth transistor; and a seventh transistor, wherein the sixth transistor can have a function of pre-charging the third wiring, and the seventh transistor can have a function of pre-charging the fourth wiring. (5) In addition, in any one of the above (1) to (4), the fourth circuit can be set in the substrate, the first circuit and the second circuit can be set in the first layer configured on the substrate, the third circuit can be set in each of the multiple second layers configured on the substrate, the substrate can include a Si transistor, and the first layer and each of the multiple second layers can include an OS transistor. (6) In addition, one embodiment of the present invention is a storage device comprising: the semiconductor device described in (5) above; and a fifth circuit, wherein the fifth circuit is arranged in each of the plurality of second layers, and the fifth circuit has a function of outputting a signal for controlling the operation of the third circuit. Effects of the Invention

[0018] One embodiment of the present invention can provide a semiconductor device capable of achieving high integration. In addition, one embodiment of the present invention can provide a semiconductor device capable of reducing manufacturing costs. In addition, one embodiment of the present invention can provide a semiconductor device capable of achieving low power consumption. In addition, one embodiment of the present invention can provide a semiconductor device capable of increasing operating speed. In addition, one embodiment of the present invention can provide a semiconductor device capable of achieving miniaturization. In addition, one embodiment of the present invention can provide a novel semiconductor device. In addition, one embodiment of the present invention can provide a storage device including any one or more of the semiconductor devices listed above.

[0019] Note that the description of these effects does not prevent the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a circuit diagram illustrating a structural example of a semiconductor device. Figure 2 It is a schematic diagram for explaining a structural example of a semiconductor device. Figure 3AIt is a schematic diagram for explaining a structural example of a semiconductor device. Figure 3B is a circuit diagram illustrating a structural example of a semiconductor device. FIG. 4A to FIG. 4D is a circuit diagram illustrating a structural example of a semiconductor device. Figure 5A and Figure 5B is a circuit diagram illustrating a structural example of a semiconductor device. Figure 6 It is a timing chart for explaining an operation example of a semiconductor device. Figure 7 It is a timing chart for explaining an operation example of a semiconductor device. Figure 8 is a block diagram illustrating a structural example of a semiconductor device. Fig. 9A and Fig. 9B It is a schematic diagram for explaining a structural example of a semiconductor device. Fig.10 It is a schematic diagram illustrating an example of the structure of an electronic computer. Fig.11A This is a flowchart illustrating an example of the operation of an electronic computer. Fig. 11B and Fig. 11C This is a schematic diagram illustrating an example of the operation of an electronic computer. Fig.12 is a circuit diagram illustrating a structural example of a semiconductor device. Fig.13 It is a timing chart for explaining an operation example of a semiconductor device. Fig.14 It is a timing chart for explaining an operation example of a semiconductor device. Fig.15 is a circuit diagram illustrating a structural example of a semiconductor device. Fig.16A and Fig. 16B is a circuit diagram illustrating a structural example of a semiconductor device. Fig.17 It is a timing chart for explaining an operation example of a semiconductor device. Fig.18 It is a timing chart for explaining an operation example of a semiconductor device. Fig.19A and Fig.19B is a schematic diagram illustrating a configuration example of a storage device. Fig. 20A and Fig. 20B is a schematic diagram illustrating a configuration example of a storage device. Fig.21A is a circuit diagram illustrating a structural example of a storage device. Fig. 21B This is a timing chart illustrating an example of the operation of the storage device. FIG. 22A to FIG. 22E is a circuit diagram illustrating a configuration example of a memory circuit. Fig.23A and Fig. 23B It is a plan layout diagram illustrating a structural example of a storage device. Fig.24A is a plan view showing an example of a semiconductor device. FIG. 24B to FIG. 24D is a cross-sectional view showing an example of a semiconductor device. Fig.25A and Fig.25B It is a schematic diagram for explaining an example of a semiconductor device. Fig.26A and Fig.26B It is a diagram for explaining an example of an electronic device. FIG. 27A to FIG. 27E is a schematic diagram illustrating an example of a storage device. FIG. 28A to FIG. 28H is a diagram showing an example of an electronic device. Fig.29A and Fig.29B is a diagram showing an example of an electronic device. Fig.30 is a diagram showing an example of space equipment. Fig.31 is a diagram showing an example of a storage system that can be used in a data center. Fig.32 is a cross-sectional view showing an example of a semiconductor device. Fig.33 This is a diagram illustrating the characteristics of a transistor for estimating the operation of a semiconductor chip. Fig.34 This is a diagram illustrating the characteristics of a transistor for estimating the operation of a semiconductor chip. Fig.35 This is a diagram illustrating the characteristics of a transistor for estimating the operation of a semiconductor chip. Modes for Carrying Out the Invention

[0021] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, for example, a circuit including a semiconductor element (for example, a transistor, a diode, or a photodiode, etc.) or a device including the circuit, etc. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips including integrated circuits, or electronic components that contain chips in packages. In addition, for example, storage devices, display devices, light-emitting devices, lighting devices, or electronic devices themselves are semiconductor devices, and sometimes include semiconductor devices.

[0022] In addition, in this specification, when it is described that "X is connected to Y", it means that the following cases are disclosed in this specification, etc.: a case where X is electrically connected to Y; a case where X is functionally connected to Y; and a case where X is directly connected to Y. Therefore, the connection relationship is not limited to the connection relationship shown in the drawings or the text, and other connection relationships are also described within the scope described in the drawings or the text. X and Y are both objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films or layers, etc.).

[0023] As an example of a case where X and Y are electrically connected, one or more elements capable of electrically connecting X and Y (for example, switches, transistors, capacitors, inductors, resistors, diodes, display devices, light emitting devices, or loads) may be connected between X and Y.

[0024] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (for example, a logic circuit (for example, an inverter, a NAND circuit, or a NOR circuit), a signal conversion circuit (for example, a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, or a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit (for example, a step-up circuit or a step-down circuit) or a level shift circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifier circuit (for example, a circuit capable of increasing the signal amplitude or the amount of current, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit), a signal generation circuit, a storage circuit, or a control circuit) may be connected between X and Y. Note that, for example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y can be said to be functionally connected.

[0025] Furthermore, when it is clearly stated that “X is electrically connected to Y”, the following cases are included: a case where X is electrically connected to Y (in other words, a case where X and Y are connected with another element or another circuit interposed therebetween); and a case where X and Y are directly connected (in other words, a case where X and Y are connected without another element or another circuit interposed therebetween).

[0026] In addition, for example, it can be expressed as "X, Y, the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor and Y are electrically connected in sequence". Alternatively, it can be expressed as "the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor and Y are electrically connected in sequence". Alternatively, it can be expressed as "X is electrically connected to Y through the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are arranged in sequence". By specifying the connection order in the circuit structure using the same expression method as this example, the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that this expression method is an example and is not limited to the above expression method. Here, both X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films or layers, etc.).

[0027] In addition, even if independent components are electrically connected to each other on a circuit diagram, one component may have the functions of multiple components. For example, when a part of a wiring is used as an electrode, one conductive film has the functions of both wiring and electrode. Therefore, the category of "electrically connected" in this specification and the like also includes the case where one conductive film has the functions of multiple components.

[0028] In this specification, etc., as a "resistor", for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω can be used. Therefore, in this specification, etc., a "resistor" includes, for example, a wiring having a resistance value, a transistor, a diode, or a coil through which current flows between a source and a drain. Therefore, a "resistor" may also be referred to as a "resistor", "load", or "region having a resistance value", etc. On the contrary, for example, sometimes a "resistor", "load", or "region having a resistance value" may also be referred to as a "resistor", etc. The resistance value is, for example, preferably not less than 1 mΩ and not more than 10 Ω, more preferably not less than 5 mΩ and not more than 5 Ω, and even more preferably not less than 10 mΩ and not more than 1 Ω. In addition, for example, it may be not less than 1 Ω and not more than 1×10 9 Ω or less.

[0029] When a wiring is used for a resistor, the resistance value of the resistor sometimes depends on the length of the wiring. In addition, a conductor having a resistivity different from that of the conductor used as the wiring is sometimes used for the resistor. In addition, when a semiconductor is used for a resistor, the resistance value of the resistor is sometimes determined by doping the semiconductor with impurities.

[0030] In this specification, etc., "capacitor" may include, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of wiring having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor, etc. Therefore, in this specification, etc., "capacitor" is not limited to a circuit element including a pair of electrodes and a dielectric between the electrodes. "Capacitor" includes, for example, parasitic capacitance generated between wiring and wiring or gate capacitance generated between one of the source and drain of a transistor and the gate, etc. In addition, for example, "capacitor", "parasitic capacitance" or "gate capacitance" etc. may be referred to as "capacitor", etc. On the contrary, for example, "capacitor" may be referred to as "capacitor", "parasitic capacitance" or "gate capacitance", etc. In addition, for example, "a pair of electrodes" of "capacitor" may be referred to as "a pair of conductors", "a pair of conductive regions" or "a pair of regions", etc. The electrostatic capacitance value may be, for example, above 0.05fF and below 10pF. In addition, for example, it may also be above 1pF and below 10μF.

[0031] In addition, in this specification, etc., a transistor includes three terminals called a gate (also called a gate terminal, a gate region, or a gate electrode), a source (also called a source terminal, a source region, or a source electrode), and a drain (also called a drain terminal, a drain region, or a drain electrode). In addition, the transistor includes a region (also called a channel formation region) where a channel is formed between the drain and the source. In the transistor, current can flow between the source and the drain through the channel formation region. Note that the channel formation region is the region where the current mainly flows. The gate is a control terminal that controls the amount of current flowing in the channel formation region between the source and the drain. The two terminals used as the source or the drain are the input and output terminals of the transistor.

[0032] Depending on the conductivity type of the transistor (n-channel or p-channel) and the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as a source and the other as a drain. For example, when the direction of the current changes during circuit operation, the function as a source and the function as a drain are sometimes swapped. Therefore, in this specification, etc., "source" and "drain" can be interchanged. In this specification, etc., when describing the connection relationship of the transistor, the expression "one of the source and drain" (first electrode or first terminal) or "the other of the source and drain" (second electrode or second terminal) is used.

[0033] In addition, depending on the structure of the transistor, a back gate is sometimes included in addition to the above three terminals. In this case, in this specification, one of the gate and the back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and the back gate of the transistor is sometimes referred to as the second gate. Moreover, in the same transistor, the "gate" and the "back gate" can sometimes be interchanged. In addition, when the transistor includes more than three gates, in this specification, for example, each gate is sometimes referred to as the first gate, the second gate, or the third gate.

[0034] In this specification, etc., a transistor having a multi-gate structure with more than two gate electrodes can be used as a transistor. Since the channel forming region is connected in series, the transistor of the multi-gate structure has a structure in which multiple transistors are connected in series. Therefore, the transistor of the multi-gate structure can reduce the off-state current and can improve the voltage resistance of the transistor (improve reliability). Alternatively, in a transistor of the multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the change in the current between the drain and the source is not too large, so that a voltage-current characteristic with a flat tilt angle can be obtained. A transistor with a voltage-current characteristic with a flat tilt angle can realize an ideal current source circuit or an active load with an extremely high resistance value. As a result, a transistor with a voltage-current characteristic with a flat tilt angle can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0035] In addition, in this specification, etc., a case where a circuit diagram shows a circuit element sometimes includes a case where the circuit element has a plurality of circuit elements. For example, in a case where a circuit diagram shows a resistor, it includes a case where two or more resistors are electrically connected in series. In addition, for example, in a case where a circuit diagram shows a capacitor, it includes a case where two or more capacitors are electrically connected in parallel. In addition, for example, in a case where a circuit diagram shows a transistor, it includes a case where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Similarly, for example, in a case where a circuit diagram shows a switch, it includes a case where there are two or more transistors, two or more transistors are electrically connected in series or in parallel, and the gates of each transistor are electrically connected to each other.

[0036] In addition, in this specification, etc., a "node" may be referred to as a "terminal", "wiring", "electrode", "conductive layer", "conductor" or "impurity region", etc., for example, depending on a circuit structure or a device structure. In addition, for example, a "terminal" or "wiring" may be referred to as a "node".

[0037] In addition, in this specification, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from the reference potential. For example, when the reference potential is the ground potential (ground potential), "voltage" can also be referred to as "potential". The ground potential does not necessarily mean 0V. In addition, potential is relative. That is, for example, the potential supplied to the wiring, the potential applied to the circuit, or the potential output from the circuit also changes according to the change of the reference potential.

[0038] In addition, in this specification, etc., "high-level potential (also referred to as "H potential" or "H")" or "low-level potential (also referred to as "L potential" or "L")" does not mean a specific potential. For example, in the case where two wirings are both recorded as "wirings used to supply high-level potentials", the high-level potentials supplied by the two wirings may be different from each other. Similarly, in the case where two wirings are both recorded as "wirings used to supply low-level potentials", the low-level potentials supplied by the two wirings may be different from each other.

[0039] In addition, in this specification, "electric current" refers to the movement phenomenon of charge (conduction). For example, the record of "conduction of a positively charged body" can be replaced by the record of "conduction of a negatively charged body in the opposite direction". Therefore, in this specification, in the absence of special instructions, "electric current" refers to the movement phenomenon of charge when carriers move (conduction). Here, as carriers, for example, electrons, holes, anions, cations or complex ions can be cited. In addition, the carriers are different according to the system through which the current flows (for example, semiconductors, metals, electrolytes or vacuum, etc.). In addition, for example, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and is recorded as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is recorded as a negative current amount. Therefore, in this specification, in the absence of special instructions, about the positive and negative of the current (or the direction of the current), for example, the record of "current flows from element A to element B" can be replaced by the record of "current flows from element B to element A". In addition, for example, the description such as “current is input to element A” may be replaced with the description such as “current is output from element A”.

[0040] In addition, in this specification, etc., ordinal numbers such as "first", "second" or "third" are added to avoid confusion between constituent elements. Therefore, the ordinal numbers do not limit the number of constituent elements. In addition, the ordinal numbers do not limit the order of the constituent elements. For example, in this specification, etc., a constituent element with the number "first" in one embodiment may be attached with the number "second" in other embodiments or claims. In addition, for example, in this specification, etc., a constituent element with the number "first" in one embodiment may be omitted in other embodiments or claims.

[0041] In addition, in this specification, etc., for the sake of convenience, words such as "upper", "lower", "above" or "below" that indicate configuration are sometimes used to illustrate the positional relationship of components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases indicating configuration described in this specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the situation. For example, in the expression "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can also be referred to as "an insulator located on the bottom surface of the conductor". In addition, in the expression "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 90 degrees, it can also be referred to as "an insulator located on the left (or right) of the conductor".

[0042] In addition, the terms "above" or "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact, but may also include the case where other components are included between insulating layer A and electrode B.

[0043] In addition, in this specification, for example, sometimes, in order to explain the components configured in a matrix and their positional relationship, the words "row" or "column" are used. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, for example, the words "row" or "column" are not limited to the words described in this specification, and can be appropriately replaced according to the situation. For example, by rotating the direction of the drawing by 90 degrees, the expression of "row direction" can sometimes be replaced by "column direction".

[0044] In addition, in this specification, etc., terms such as "overlap" are not limited to the state of the stacking order of the components. For example, the expression "electrode B overlapping with the insulating layer A" does not necessarily mean that the electrode B is formed on the insulating layer A. The expression "electrode B overlapping with the insulating layer A" may also include, for example, the state in which the electrode B is formed under the insulating layer A or the state in which the electrode B is formed on the right side (or left side) of the insulating layer A.

[0045] In addition, in this specification, the terms "adjacent" or "close to" are not limited to the case where the components are in direct contact. For example, the expression "electrode B adjacent to insulating layer A" does not necessarily mean that insulating layer A and electrode B are formed in direct contact, and may also include the case where other components are included between insulating layer A and electrode B.

[0046] In addition, in this specification, etc., depending on the situation, for example, words such as "film" or "layer" may be interchanged with each other. For example, "conductive layer" may be replaced with "conductive film" sometimes. For example, "insulating film" may be replaced with "insulating layer" sometimes. In addition, depending on the situation, for example, other words may be used instead of "film" or "layer". For example, "conductive layer" or "conductive film" may be replaced with "conductor". In addition, "conductor" may be replaced with "conductive layer" or "conductive film". For example, "insulating layer" or "insulating film" may be replaced with "insulator". In addition, "insulator" may be replaced with "insulating layer" or "insulating film" sometimes.

[0047] Note that, for example, in this specification, the words "electrode", "wiring" or "terminal" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" or "wiring" also includes, for example, a case where a plurality of "electrodes" or "wirings" are formed as one. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or "electrode", and vice versa. Furthermore, the word "terminal" also includes, for example, a case where a plurality of "electrodes", "wiring" or "terminals" are formed as one. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal". In addition, for example, a "terminal" can be a part of a "wiring" or "electrode". In addition, for example, words such as "electrode", "wiring" or "terminal" are sometimes replaced with words such as "region".

[0048] In this specification, etc., depending on the situation, for example, the words "wiring", "signal line" or "power line" can sometimes be interchanged. For example, "wiring" can sometimes be converted to "signal line". In addition, for example, "wiring" can sometimes be converted to "power line". Vice versa, for example, "signal line" or "power line" can sometimes be converted to "wiring". In addition, for example, "power line" can sometimes be converted to "signal line". Vice versa, for example, "signal line" can sometimes be converted to "power line". In addition, depending on the situation, for example, the "potential" applied to the wiring can be converted to "signal". Vice versa, for example, "signal" can sometimes be converted to "potential".

[0049] In addition, in this specification, etc., a "switch" includes a plurality of terminals and has a function of switching (selecting) conduction or non-conduction between the terminals. For example, when a switch includes two terminals and conduction between the two terminals occurs, the switch is in a "conducting state" or "open state". In addition, when non-conduction between the two terminals occurs, the switch is in a "non-conducting state" or "closed state". Note that "the switch is switched to one of the conducting state and the non-conducting state" or "the switch maintains one of the conducting state and the non-conducting state" is sometimes referred to as "controlling the conducting state".

[0050] That is, a switch is a component that has the function of controlling whether or not to allow current to flow. Alternatively, a switch is a component that has the function of selecting and switching a current path. As a switch, for example, an electric switch or a mechanical switch can be used. In other words, a switch is not limited to a specific component as long as it can control current.

[0051] In addition, as a type of switch, there is a switch that is normally in a non-conducting state and becomes a conducting state by controlling the conducting state, and this switch is sometimes called an "A contact". In addition, there is a switch that is normally in a conducting state and becomes a non-conducting state by controlling the conducting state, and this switch is sometimes called a "B contact".

[0052] As an electric switch, there are, for example, a transistor (for example, a bipolar transistor or a MOS transistor), a diode (for example, a PN diode, a PIN diode, a Schottky diode, a metal-insulator-metal (MIM: Metal Insulator Metal) diode, a metal-insulator-semiconductor (MIS: Metal Insulator Semiconductor) diode, or a diode-connected transistor, or a logic circuit combining these elements. Note that when a transistor is used as a switch, the "on state" or "open state" of the transistor refers to, for example, a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited or a state in which current can flow between the source electrode and the drain electrode. In addition, the "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When the transistor is used only as a switch, there is no particular restriction on the polarity (conductivity type) of the transistor.

[0053] As a mechanical switch, for example, a switch using MEMS (micro-electromechanical system) technology can be cited. This switch has a mechanically movable electrode, and a conductive state or a non-conductive state is selected by moving the electrode.

[0054] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. In addition, "substantially parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Substantially perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0055] In addition, in this specification, etc., "high consistency or approximately consistency" means that the height from a reference plane (for example, a flat surface such as a substrate surface) is equal when viewed from a cross section. For example, in the manufacturing process of a semiconductor device, sometimes a single layer or a plurality of layers are exposed due to a flattening process (typically a CMP process). At this time, the processed surface treated by the CMP process has a structure with a height equal to that from the reference plane. However, depending on the processing device, processing method or material of the processed surface used in the CMP process, the heights of the plurality of layers of the processed surface are sometimes not completely equal. In this specification, etc., this situation is also regarded as "high consistency or approximately consistency". For example, the following situation is also referred to as "high consistency or approximately consistency": when including two layers (here, the first layer and the second layer) with different heights from the reference plane, the difference between the top surface height of the first layer and the top surface height of the second layer is less than 20nm.

[0056] In this specification, etc., "the ends are consistent or approximately consistent" means that at least a part of the outline of each layer in the stack overlaps when viewed from above. For example, it refers to the case where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern in the manufacturing process of the semiconductor device. However, strictly speaking, sometimes the outlines do not overlap and the outline of the upper layer is located inside the outline of the lower layer or the outline of the upper layer is located outside the outline of the lower layer. In this specification, etc., these cases are also included in the case of "the ends are approximately consistent".

[0057] In this specification, for example, regarding count values ​​and measurement values, or objects, methods, and phenomena converted into count values ​​and measurement values, when referring to "same", "identical", "equal", or "uniform" (including synonyms of these words), unless otherwise stated, an error of ±20% is included.

[0058] In this specification, etc., impurities of a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. When a semiconductor contains impurities, for example, the defect state density in the semiconductor may increase, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group I elements, Group II elements, Group XIII elements, Group XIV elements, Group XV elements, or transition metals other than the main components of the oxide semiconductor. In particular, for example, there are hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, or nitrogen. In oxide semiconductors, for example, the mixing of impurities sometimes leads to the formation of oxygen vacancies (also called V O When the semiconductor is a silicon layer, the impurities that change the characteristics of the semiconductor include oxygen, a first group element other than hydrogen, a second group element, a thirteenth group element, or a fifteenth group element.

[0059] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified, for example, into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide is used as a material capable of constituting a channel formation region of a transistor having at least one of an amplification function, a rectification function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, an OS transistor can be referred to as a transistor comprising a metal oxide or an oxide semiconductor.

[0060] In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0061] In this specification, etc., the structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one mode of the present invention. In addition, when a plurality of structural examples are described in one embodiment, these structural examples can be appropriately combined.

[0062] The embodiments described in this specification are described with reference to the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. Thus, a person skilled in the art can easily understand the fact that the methods and details can be transformed into various forms without departing from the purpose and scope thereof. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments. Note that with respect to the drawings illustrating the embodiments, in the structure of the invention, the same reference numerals are sometimes used in different drawings to represent the same parts or parts with the same functions, thereby omitting repeated descriptions. In addition, in the drawings, the same hatching is sometimes used when representing parts with the same functions, without specifically adding a reference numeral. For example, in a stereogram or a top view (also called a "plan view"), etc., for the sake of clarity, the illustration of some constituent elements is sometimes omitted. In addition, the illustration of some constituent elements is sometimes omitted in the drawings. In addition, the description of some hidden lines in the drawings is sometimes omitted. In addition, for example, hatching is sometimes omitted in the drawings.

[0063] In the drawings and the like of this specification, the size, thickness of a layer or region may be exaggerated for the sake of clarity. Therefore, the drawings are not limited to the dimensions or aspect ratios in the drawings. In addition, the drawings schematically show ideal examples, so the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0064] For example, the drawings and the like according to the present specification may include unevenness of signals, voltages, or currents caused by noise or timing deviations and the like.

[0065] For example, according to the drawings and the like in this specification, in an actual manufacturing process, a layer or a resist mask may be unintentionally thinned by a process such as etching, but this may not be reflected in the drawings for ease of understanding.

[0066] In addition, arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings and the like according to this specification. In this specification and the like, the "X direction" refers to the direction along the X axis, and sometimes the positive direction and the negative direction are not distinguished except for the cases clearly indicated. The same is true for the "Y direction" and the "Z direction". In addition, the X direction, the Y direction, and the Z direction are directions that intersect each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other. In this specification and the like, sometimes one of the X direction, the Y direction, and the Z direction is referred to as the "first direction". In addition, sometimes the other one is referred to as the "second direction". In addition, sometimes the remaining one is referred to as the "third direction".

[0067] In this specification, etc., when the same symbol is used for multiple components and it is necessary to distinguish them, a symbol for identification such as "A", "b", "_1", "[n]" or "[m, n]" is sometimes added to the symbol.

[0068] (Implementation Method 1) Reference Figure 1 A structural example of a semiconductor device according to one embodiment of the present invention is described through FIG. 5 .

[0069] Note that a semiconductor device is a device that utilizes semiconductor characteristics, and is also a circuit including a semiconductor element (for example, a transistor, a diode, or a photodiode, etc.) or a device including the circuit. The semiconductor device described in this embodiment and the like can be appropriately used as a storage device, for example. In addition, for example, it can be appropriately used as an electronic computer including the storage device.

[0070] <Structural Example of Semiconductor Device> Figure 1 : is a circuit diagram showing a structural example of a semiconductor device 10 according to one embodiment of the present invention.

[0071] The semiconductor device 10 includes a substrate 50 and a layer 20. The substrate 50 may be an insulating substrate or a semiconductor substrate including various materials. For example, the substrate 50 may be a substrate including silicon. For example, the substrate 50 may include a transistor including silicon in a channel formation region (Si transistor). The layer 20 includes various materials such as a conductor, a semiconductor, or an insulator, and is provided with various elements such as a capacitor or a transistor. For example, the layer 20 may include a transistor including an oxide semiconductor in a channel formation region (OS transistor).

[0072] The layer 20 includes the layer 30 and the layer 40. The layer 40 includes the layers 41[1] to 41[m]. Note that m is an integer greater than or equal to 2.

[0073] In each of the layers 41[1] to 41[m], the layer 40 includes a plurality of memory cells 42. Each of the plurality of memory cells 42 is electrically connected to a local bit line LBL. The memory cell 42 has a function of storing data by maintaining a potential corresponding to the data. The memory cell 42 can write or read data through the local bit line LBL.

[0074] The memory cell 42 includes a transistor and a capacitor (sometimes referred to as a capacitor) (see Figure 3B and Figure 4A ). One of the source and the drain of the transistor is electrically connected to one terminal of the capacitor. As the transistor in the memory cell 42, a transistor with extremely low off-state current is preferably used. For example, an OS transistor can be used as the transistor. The structure of the memory cell using this OS transistor can be called DOSRAM (registered trademark). DOSRAM is the abbreviation of Dynamic Oxide Semiconductor RAM (Random Access Memory). By using an OS transistor with extremely low off-state current, DOSRAM can store data for a long time. In addition, since DOSRAM can be composed of one OS transistor and one capacitor, high density of memory cells can be achieved.

[0075] The band gap of the oxide semiconductor forming the channel of the OS transistor is above 2eV, so the OS transistor has the characteristic of extremely low off-state current (the current flowing between the source and the drain when the transistor is in the off state). The off-state current value of the OS transistor with a channel width of 1μm at room temperature can be 1aA (1×10 -18 A) or less, 1zA(1×10 -21 A) or less or 1yA(1×10 -24 Note that the off-state current value of a Si transistor with a channel width of 1 μm at room temperature is 1 fA (1×10 -15 A) or more and 1pA (1×10 -12Therefore, it can be said that the off-state current of the OS transistor is about 10 bits lower than the off-state current of the Si transistor.

[0076] The semiconductor layer of the OS transistor preferably contains at least one of indium and zinc. In addition, the semiconductor layer of the OS transistor preferably contains, for example, indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and cobalt) and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium and tin.

[0077] In particular, as the semiconductor layer, it is preferable to use an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also recorded as IGZO). Alternatively, as the semiconductor layer, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also recorded as IAZO) may be used. Alternatively, as the semiconductor layer, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also recorded as IAGZO) may be used.

[0078] When In-M-Zn oxide is used for the semiconductor layer, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of the atomic ratio of metal elements in such an In-M-Zn oxide include a composition of In:M:Zn=1:1:1 or in the vicinity thereof, a composition of In:M:Zn=1:1:1.2 or in the vicinity thereof, a composition of In:M:Zn=2:1:3 or in the vicinity thereof, a composition of In:M:Zn=3:1:2 or in the vicinity thereof, a composition of In:M:Zn=4:2:3 or in the vicinity thereof, a composition of In:M:Zn=4:2:4.1 or in the vicinity thereof, a composition of In:M:Zn=5:1:3 or in the vicinity thereof, a composition of In:M:Zn=5:1:6 or in the vicinity thereof, a composition of In:M:Zn=5:1:7 or in the vicinity thereof, a composition of In:M:Zn=5:1:8 or in the vicinity thereof, a composition of In:M:Zn=6:1:6 or in the vicinity thereof, or a composition of In:M:Zn=5:2:5 or in the vicinity thereof. In addition, the atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M in some cases. Examples of the atomic ratio of metal elements in the In-M-Zn oxide include a composition of In:M:Zn=1:3:2 or in the vicinity thereof, and a composition of In:M:Zn=1:3:4 or in the vicinity thereof. Note that the vicinity of the composition includes a range of ±30% of the desired atomic ratio.

[0079] For example, when the atomic ratio of metal elements is described as In:Ga:Zn=4:2:3 or a composition in the vicinity thereof, the content ratio of each element includes the following cases: when In is 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. In addition, when the atomic ratio of metal elements is described as In:Ga:Zn=5:1:6 or a composition in the vicinity thereof, the content ratio of each element includes the following cases: when In is 5, Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. In addition, when the atomic ratio of metal elements is described as In:Ga:Zn=1:1:1 or a composition in the vicinity thereof, the content ratio of each element includes the following cases: when In is 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0080] Since the off-state current of the OS transistor is extremely low, the memory cell using the OS transistor can maintain the charge stored in the capacitor constituting the memory cell for a long time. Therefore, the memory cell can store the data for a long time by using the potential corresponding to the amount of charge maintained in the capacitor as data. In other words, the memory cell can store the written data for a long time, so the refresh frequency of the data can be reduced. Therefore, the memory cell can realize low power consumption of the semiconductor device or memory device using the memory cell.

[0081] In addition, the memory cell using the OS transistor writes or reads data by charging or discharging electric charge, thereby being able to write or read data countless times. In addition, the memory cell using the OS transistor has excellent rewrite resistance because it does not accompany atomic-level structural changes like magnetic memory or resistive memory. In addition, unlike flash memory, the memory cell using the OS transistor does not observe instability caused by the increase of electron capture centers even if it is repeatedly written, so it has excellent stability.

[0082] In addition, a memory cell using an OS transistor can be freely arranged on a silicon substrate provided with a Si transistor, for example, and thus can be easily integrated. In addition, a memory cell using an OS transistor can be manufactured using the same manufacturing equipment as a Si transistor, thereby enabling low-cost manufacturing.

[0083] The OS transistor can be a 4-terminal semiconductor element by including a back gate (back gate electrode) in addition to the gate (gate electrode), source (source electrode) and drain (drain electrode). The 4-terminal OS transistor can independently control the current flowing between the source and the drain according to the potential supplied to the gate or the back gate respectively. In addition, the OS transistor also has superior electrical characteristics than Si transistors in high temperature environments. Specifically, the OS transistor has a large ratio of on-state current to off-state current even at high temperatures above 125°C and below 150°C, so it can perform good switching operations.

[0084] The layer 30 includes a sensing circuit 35 , a sensing circuit 35_pre and a switching circuit 37 .

[0085] The sensing circuit 35 is electrically connected to a plurality of memory cells 42 included in the layer 40 through the local bit line LBL. In addition, the sensing circuit 35 is electrically connected to the switching circuit 37 through the global bit line GBL. When data is written to the memory cell 42, the sensing circuit 35 has a function of supplying a potential corresponding to the data from the global bit line GBL to the local bit line LBL. In addition, when data is read from the memory cell 42, the sensing circuit 35 has a function of amplifying a change in the potential of the local bit line LBL and outputting it to the global bit line GBL. In addition, the sensing circuit 35 can be configured using an OS transistor.

[0086] Note that, although not shown, the layer 30 includes a plurality of sensing circuits 35. The global bit line GBL is electrically connected to the plurality of local bit lines LBL via the plurality of sensing circuits 35. The semiconductor device 10 has a function of selecting any one of the plurality of sensing circuits 35 and writing or reading data to or from one of the plurality of memory cells 42 electrically connected to the sensing circuit 35.

[0087] In addition, among the transistors constituting the sensor circuit 35, the threshold voltage of each of the plurality of sensor circuits 35 may vary. In particular, the variation in the threshold voltage of the transistor having the function of converting a slight change in the potential of the local bit line LBL into a current has a great influence on the operation of the sensor circuit 35. Therefore, such variation in the threshold voltage affects the operation of the sensor circuit 35 and the semiconductor device 10 may not be able to accurately read the data from the memory cell 42. The sensor circuit 35 may also have a correction function to reduce the influence of such variation in the threshold voltage on the read data. Through such a correction function, the semiconductor device 10 can improve the reliability of the read data.

[0088] The sensor circuit 35_pre has the same structure as the sensor circuit 35. Therefore, in the description of the sensor circuit 35_pre, the global bit line GBL is replaced by global bit line GBLB, and the local bit line LBL is replaced by local bit line LBL_pre, and the description of the sensor circuit 35 mentioned above may be referred to as appropriate.

[0089] The sensing circuit 35, the global bit line GBL, the local bit line LBL and the plurality of memory cells 42 electrically connected to the local bit line LBL and the sensing circuit 35_pre, the global bit line GBLB, the local bit line LBL_pre and the plurality of memory cells 42 electrically connected to the local bit line LBL_pre form a pair.

[0090] The memory cell 42 connected to the local bit line LBL is written or read. The memory cell 42 connected to the local bit line LBL_pre is not written or read. The local bit line LBL_pre is precharged to a predetermined potential and the potential is maintained. Note that the memory cell 42 connected to the local bit line LBL_pre can be set as a memory cell for writing or reading data, and the memory cell 42 connected to the local bit line LBL can be set as a memory cell for not writing or reading data. In this case, the local bit line LBL is precharged to a predetermined potential and the potential is maintained.

[0091] The switching circuit 37 is electrically connected to the sensing circuit 35 through the global bit line GBL. In addition, the switching circuit 37 is electrically connected to the sensing circuit 35_pre through the global bit line GBLB. In addition, the switching circuit 37 is electrically connected to the driving circuit 51 included in the substrate 50 through the global bit line SA_GBL and the global bit line SA_GBLB. The switching circuit 37 has a function of making the global bit line GBL, the global bit line GBLB, the global bit line SA_GBL, and the global bit line SA_GBLB mutually conductive or non-conductive. In addition, the switching circuit 37 has a function of precharging the global bit line GBL and the global bit line GBLB to a specified potential.

[0092] The switching circuit 37 includes a transistor M0, a transistor M1, a transistor M2, a transistor M3, and a transistor M4. Note that it is preferable to use a transistor with an extremely low off-state current as the transistor constituting the switching circuit 37. For example, an OS transistor can be used as the transistor constituting the switching circuit 37.

[0093] One of the source and drain of transistor M0 is electrically connected to global bit line GBL. The other of the source and drain of transistor M0 is electrically connected to global bit line GBLB. Transistor M0 has a function of connecting or disconnecting global bit line GBL and global bit line GBLB according to signal SW0.

[0094] One of the source and drain of transistor M1 is electrically connected to global bit line GBL. The other of the source and drain of transistor M1 is electrically connected to global bit line SA_GBL. Transistor M1 has a function of conducting or non-conducting between global bit line GBL and global bit line SA_GBL according to signal SW1.

[0095] One of the source and drain of transistor M2 is electrically connected to global bit line GBLB. The other of the source and drain of transistor M2 is electrically connected to global bit line SA_GBLB. Transistor M2 has a function of conducting or non-conducting between global bit line GBLB and global bit line SA_GBLB according to signal SW2.

[0096] One of the source and drain of the transistor M3 is electrically connected to the global bit line GBL. The other of the source and drain of the transistor M3 is electrically connected to a terminal to which the potential VPRE2 is supplied. The transistor M3 has a function of precharging the global bit line GBL to the potential VPRE2 according to the signal SW3.

[0097] One of the source and drain of the transistor M4 is electrically connected to the global bit line GBLB. The other of the source and drain of the transistor M4 is electrically connected to a terminal to which the potential VPRE2 is supplied. The transistor M4 has a function of precharging the global bit line GBLB to the potential VPRE2 according to the signal SW.

[0098] The substrate 50 includes a driving circuit 51 .

[0099] The driving circuit 51 is electrically connected to the switching circuit 37 included in the layer 30 through the global bit line SA_GBL and the global bit line SA_GBLB. When writing data, the driving circuit 51 has a function of supplying a potential corresponding to the data to the global bit line SA_GBL and the global bit line SA_GBLB. In addition, when reading data, the driving circuit 51 has a function of outputting a potential corresponding to the data according to the potential difference between the global bit line SA_GBL and the global bit line SA_GBLB. In addition, the driving circuit 51 can be configured using a Si transistor in which a channel is formed in the substrate 50.

[0100] The operating speed of the Si transistor is faster than that of the OS transistor. In addition, the Si transistor can form a CMOS circuit (for example, a circuit that works complementarily, a CMOS logic gate, or a CMOS logic circuit, etc.) by electrically connecting the gate of the n-channel Si transistor to the gate of the p-channel Si transistor. Therefore, by using Si transistors to form the drive circuit 51 included in the substrate 50, the operating speed can be increased and the power consumption in the steady state can be reduced.

[0101] Figure 21 is a schematic diagram showing a structural example of a semiconductor device 10 according to one embodiment of the present invention.

[0102] like Figure 2 As shown, the semiconductor device 10 includes a substrate 50 and one or more layers 20 (layers 20[1] to 20[k]). Note that k is an integer greater than 2. The substrate 50 may be an insulating substrate or a semiconductor substrate made of various materials. For example, the substrate 50 may be a substrate made of silicon. Each of the layers 20[1] to 20[k] may include various materials such as a conductor, a semiconductor, or an insulator. For example, various elements such as a capacitor or a transistor may be provided for each of the layers 20[1] to 20[k].

[0103] Note that Figure 2 In the schematic diagram shown, in order to illustrate the configuration of each layer constituting the semiconductor device 10, the X direction, Y direction and Z direction are sometimes specified. The Z direction refers to a direction perpendicular to or approximately perpendicular to the surface of the substrate 50. "Approximately perpendicular" refers to a state in which the angle formed by the two constituent elements as the object is greater than 85° and less than 95°. In this embodiment, for ease of understanding, the Z direction is sometimes referred to as a vertical direction. In addition, the surface of the substrate 50 corresponds to the surface formed by the X direction and the Y direction, wherein the X direction is specified as a perpendicular direction or an approximately perpendicular direction relative to the Z direction, and the Y direction is specified as a perpendicular direction or an approximately perpendicular direction relative to both the X direction and the Z direction. In this embodiment, etc., for ease of understanding, the X direction is sometimes referred to as a depth direction and the Y direction is sometimes referred to as a horizontal direction.

[0104] Each of the layers 20 [ 1 ] to 20 [ k ] may be stacked in a vertical direction (Z direction) on the substrate 50 . The layers 20 [ 1 ] to 20 [ k ] each include a layer 30 and a layer 40 .

[0105] like Figure 2 As shown, each of the layers 41[1] to 41[m] included in the layer 40 can be stacked in the vertical direction. Therefore, the semiconductor device 10 according to one embodiment of the present invention can improve the density (storage density) of the plurality of memory cells 42. In addition, each of the layers 41[1] to 41[m] can be repeatedly manufactured using the same manufacturing process in the vertical direction. Therefore, the semiconductor device 10 according to one embodiment of the present invention can reduce the manufacturing cost of the plurality of memory cells 42.

[0106] In addition, if Figure 2As shown, the layer 30 and the layer 40 (layer 41[1] to layer 41[m]) can be stacked in the vertical direction on the substrate 50. Therefore, the semiconductor device 10 according to one embodiment of the present invention can shorten the length of the wiring such as the local bit line LBL and the global bit line SA_GBL. That is, the semiconductor device 10 according to one embodiment of the present invention can reduce the parasitic resistance and parasitic capacitance of the wiring by shortening the signal transmission distance between two circuits connected to the wiring. Therefore, the semiconductor device 10 according to one embodiment of the present invention can achieve reduced power consumption and signal delay.

[0107] In addition, the semiconductor device 10 according to one embodiment of the present invention can operate even if the electrostatic capacitance of the capacitor included in the memory cell 42 is reduced by reducing the parasitic capacitance of the local bit line LBL. Therefore, the memory cell 42 can reduce the occupied area. Therefore, the semiconductor device 10 according to one embodiment of the present invention can be miniaturized.

[0108] Furthermore, the semiconductor device 10 according to one embodiment of the present invention can amplify a small potential change of the local bit line LBL by including the sensing circuit 35 in the layer 30. Therefore, the sense amplifier 55 included in the substrate 50 can be miniaturized. Thus, the semiconductor device 10 according to one embodiment of the present invention can be miniaturized.

[0109] In the semiconductor device 10 according to one embodiment of the present invention, as the transistors provided in the layers 30 and 40, OS transistors with extremely low off-state current can be used. Therefore, the memory cell 42 can reduce the refresh frequency of the stored data. Thus, the semiconductor device 10 according to one embodiment of the present invention can achieve low power consumption. In addition, the semiconductor device 10 according to one embodiment of the present invention can stack the layers 41[1] to 41[m] provided with OS transistors in the vertical direction. Therefore, each of the layers 41[1] to 41[m] can be repeatedly manufactured using the same manufacturing process. Therefore, the semiconductor device 10 according to one embodiment of the present invention can reduce the manufacturing cost. In addition, the semiconductor device 10 according to one embodiment of the present invention can stack the layers 41[1] to 41[m] provided with the memory cell 42 in the vertical direction. Therefore, the memory cell 42 can increase the storage density. Therefore, the semiconductor device 10 according to one embodiment of the present invention can achieve miniaturization. In addition, the semiconductor device 10 according to one embodiment of the present invention can use OS transistors whose electrical characteristics change less than Si transistors in a high temperature environment. Therefore, according to the semiconductor device 10 of one embodiment of the present invention, a semiconductor device with excellent reliability can be realized.

[0110] Figure 3A is equivalent to Figure 2A schematic diagram of a layer 20 of any of layers 20 [ 1 ] to 20 [ k ] is shown.

[0111] Figure 3A The layer 20 shown includes layers 41[1] to 41[m] in which memory cells 42 are provided in the vertical direction (Z direction) on the layer 30. By adopting this structure, the distance between the layers 30 and the layers 41[1] to 41[m] can be shortened. Therefore, the length of the local bit line LBL can be shortened and the parasitic capacitance can be reduced. By repeatedly using the same manufacturing process in the vertical direction to manufacture the layers 41[1] to 41[m], the manufacturing cost can be reduced.

[0112] Figure 3B It is shown with circuit markings Figure 3A A diagram of the components in layer 20 is shown.

[0113] Layers 41[1] to 41[m] each include a plurality of memory cells 42. The memory cell 42 includes a transistor 43 and a capacitor 44. One of the source and the drain of the transistor 43 is electrically connected to one terminal (electrode) of the capacitor 44. The other of the source and the drain of the transistor 43 is electrically connected to the local bit line LBL. The gate of the transistor 43 is electrically connected to the word line WL. The other terminal (electrode) of the capacitor 44 is electrically connected to a wiring CSL to which an arbitrary fixed potential is supplied. Note that sometimes a region where one of the source and the drain of the transistor 43 is electrically connected to one terminal of the capacitor 44 is referred to as a node MND. The transistor 43 has a function of making the local bit line LBL and the node MND conductive or non-conductive according to the potential supplied to the word line WL.

[0114] As transistor 43, it is preferable to use a transistor with extremely low off-state current. For example, OS transistor can be used as transistor 43. Capacitor 44 has a structure in which an insulator is sandwiched between conductors used as electrodes. Note that as a conductor constituting an electrode, a semiconductor layer imparting conductivity can be used in addition to metal. In addition, regarding the structure of capacitor 44, for example, a structure in which a portion of a semiconductor layer or electrode constituting transistor 43 is used as an electrode of capacitor 44 can be cited.

[0115] The memory cell 42 can hold the charge stored in the capacitor 44 for a long time by making the transistor 43 in a non-conductive state. The memory cell 42 can store binary data by, for example, making the potential of the node MND corresponding to the amount of charge held in the capacitor 44 correspond to "1" or "0". In addition, when writing data, the memory cell 42 can supply the potential corresponding to the data from the local bit line LBL to the node MND by making the transistor 43 in a conductive state. In addition, when reading data, the memory cell 42 can extract the charge held in the node MND to the local bit line LBL by making the transistor 43 in a conductive state.

[0116] Note that when the memory cell 42 reads data, the charge held at the node MND is extracted to the local bit line LBL and the potential of the node MND changes. That is, when the memory cell 42 reads data, the stored data is destroyed. In other words, the data read by the memory cell 42 is a destructive read. Therefore, the memory cell 42 needs to write back (refresh) the data after reading the data.

[0117] Layer 30 includes a sensing circuit 35. The sensing circuit 35 includes a transistor 31, a transistor 32, a transistor 33, and a transistor 34. One of the source and the drain of the transistor 31 is electrically connected to one of the source and the drain of the transistor 33 and one of the source and the drain of the transistor 34. The other of the source and the drain of the transistor 31 is electrically connected to one of the source and the drain of the transistor 32. The gate of the transistor 31 is electrically connected to the other of the source and the drain of the transistor 33 and the local bit line LBL. The other of the source and the drain of the transistor 32 is electrically connected to the wiring SL. The other of the source and the drain of the transistor 34 is electrically connected to the global bit line GBL. The transistor 31 has a function of causing a current to flow between the source and the drain according to the potential of the local bit line LBL. The transistor 32 has a function of causing the source and the drain to be in a conducting state or a non-conducting state according to a signal RE supplied to the gate. The transistor 33 has a function of causing the source and the drain to be in a conducting state or a non-conducting state according to a signal WE supplied to the gate. The transistor 34 has a function of placing the source and the drain in a conducting state or a non-conducting state according to a signal MUX supplied to the gate.

[0118] Transistors with extremely low off-state current can be used as the transistors 31 to 34. For example, OS transistors can be used as the transistors 31 to 34.

[0119] The sensing circuit 35 has a function of causing a current corresponding to the potential of the local bit line LBL to flow from the global bit line GBL through the wiring SL via the transistor 34, the transistor 31, and the transistor 32, thereby changing the potential of the global bit line GBL. In addition, the sensing circuit 35 has a function of transmitting the potential of the global bit line GBL to the local bit line LBL via the transistor 34 and the transistor 33. In addition, the sensing circuit 35 has a function of causing the charge stored in the gate of the transistor 31 to be discharged to the wiring SL via the transistor 33, the transistor 31, and the transistor 32, thereby changing the gate potential of the transistor 31 to a potential corresponding to the threshold voltage of the transistor 31. Due to this function, the sensing circuit 35 can perform correction in a manner that reduces the influence of the threshold voltage of the transistor 31.

[0120] Note that the sensor circuit 35 may include a capacitor. In this case, it is preferable that one terminal of the capacitor is electrically connected to the local bit line LBL and the other terminal of the capacitor is electrically connected to a wiring to which an arbitrary fixed potential is supplied.

[0121] By using an OS transistor with an extremely low off-state current as the transistor 33 of the sensing circuit 35, when the transistor 33 is in a non-conducting state, the charge stored in the local bit line LBL can be maintained for a long time. Therefore, the sensing circuit 35 can store binary data by, for example, making the high or low potential corresponding to the amount of charge maintained in the local bit line LBL correspond to "1" or "0". That is, the sensing circuit 35 can be used as a memory. When the sensing circuit 35 used as a memory writes data to the local bit line LBL, by making the transistor 33 in a conducting state, the potential corresponding to the data can be supplied from the global bit line GBL to the local bit line LBL. In addition, when the sensing circuit 35 used as a memory reads the data stored in the local bit line LBL, by supplying the potential corresponding to the data to the gate of the transistor 31, the data can be read by utilizing the phenomenon that the current corresponding to the data flows between the source and the drain.

[0122] Note that the charge held in the local bit line LBL by the sensing circuit 35 used as a memory does not change when reading data. That is, the data stored in the sensing circuit 35 used as a memory is not destroyed when reading data. That is, the data reading performed by the sensing circuit 35 used as a memory is non-destructive reading.

[0123] Here, as a non-destructive read memory using an OS transistor, there is a memory called NOSRAM (registered trademark). NOSRAM is an abbreviation of Nonvolatile Oxide Semiconductor RAM (Random Access Memory). Therefore, the sensing circuit 35 can be regarded as a memory that operates like NOSRAM.

[0124] Figure 4A A circuit diagram of the storage unit 42 is shown, which corresponds to Figure 3B A circuit diagram of the storage unit 42 is shown. Figure 4B The circuit blocks corresponding to the circuit diagram are shown, which correspond to Figure 1 The circuit blocks of the memory cell 42 are shown.

[0125] Figure 4C A circuit diagram of the sensing circuit 35 is shown, which corresponds to Figure 3B A circuit diagram of the sensing circuit 35 is shown. Figure 4D The circuit blocks corresponding to the circuit diagram are shown, which correspond to Figure 1 Circuit blocks of the sensing circuit 35 are shown.

[0126] Figure 5A 1 is a circuit diagram showing a driver circuit 51 provided in a substrate 50 using circuit symbols. The driver circuit 51 includes a switch circuit 52, a precharge circuit 53, a precharge circuit 54, and a sense amplifier 55. Each of the switch circuit 52, the precharge circuit 53, the precharge circuit 54, and the sense amplifier 55 is electrically connected to the global bit line SA_GBL and the global bit line SA_GBLB. The switch circuit 52 is electrically connected to the bit line BL and the bit line BLB. The driver circuit 51 has a function of controlling the writing or reading of data to the memory cell 42.

[0127] The switch circuit 52 has a function of making the wiring pair of the global bit line SA_GBL and the global bit line SA_GBLB and the wiring pair of the bit line BL and the bit line BLB in a conductive state or a non-conductive state according to the signal CSEL. Specifically, the switch circuit 52 includes a transistor 52_1 and a transistor 52_2. The transistor 52_1 and the transistor 52_2 are both n-channel transistors. The transistor 52_1 has a function of making the global bit line SA_GBL and the bit line BL in a conductive state or a non-conductive state according to the signal CSEL. The transistor 52_2 has a function of making the global bit line SA_GBLB and the bit line BLB in a conductive state or a non-conductive state according to the signal CSEL.

[0128] The precharge circuit 53 has a function of precharging the global bit line SA_GBL and the global bit line SA_GBLB to the potential VPRE according to the signal EQ. Specifically, the precharge circuit 53 includes a transistor 53_1, a transistor 53_2, and a transistor 53_3. The transistor 53_1, the transistor 53_2, and the transistor 53_3 are all n-channel transistors. The transistor 53_1 has a function of making the global bit line SA_GBL and the global bit line SA_GBLB in a conductive state or a non-conductive state according to the signal EQ. The transistor 53_2 has a function of precharging the global bit line SA_GBL to the potential VPRE according to the signal EQ. The transistor 53_3 has a function of precharging the global bit line SA_GBLB to the potential VPRE according to the signal EQ.

[0129] The precharge circuit 54 has a function of precharging the global bit line SA_GBL and the global bit line SA_GBLB to the potential VPRE according to the signal EQB. Specifically, the precharge circuit 54 includes a transistor 54_1, a transistor 54_2, and a transistor 54_3. The transistor 54_1, the transistor 54_2, and the transistor 54_3 are all p-channel transistors. The transistor 54_1 has a function of making the global bit line SA_GBL and the global bit line SA_GBLB in a conductive state or a non-conductive state according to the signal EQB. The transistor 54_2 has a function of precharging the global bit line SA_GBL to the potential VPRE according to the signal EQB. The transistor 54_3 has a function of precharging the global bit line SA_GBLB to the potential VPRE according to the signal EQB.

[0130] The sense amplifier 55 has a function of outputting a potential corresponding to one of the binary data to the global bit line SA_GBL and outputting a potential corresponding to the other of the binary data to the global bit line SA_GBLB by supplying a predetermined potential to the wiring SAP and the wiring SAN. The sense amplifier 55 includes a transistor 55_1, a transistor 55_2, a transistor 55_3, and a transistor 55_4. The transistors 55_1 and 55_2 are both p-channel transistors. The transistors 55_3 and 55_4 are both n-channel transistors. The transistors 55_1 and 55_3 form an inverter that takes the global bit line SA_GBLB as an input, takes the global bit line SA_GBL as an output, takes the wiring SAP as a high potential power line, and takes the wiring SAN as a low potential power line. The transistors 55_2 and 55_4 form an inverter that takes the global bit line SA_GBL as an input, takes the global bit line SA_GBLB as an output, takes the wiring SAP as a high potential power line, and takes the wiring SAN as a low potential power line.

[0131] Figure 5B Shown corresponding to Figure 5AThe circuit blocks of the circuit diagram of the illustrated driving circuit 51 correspond to Figure 1 The circuit blocks of the driving circuit 51 are shown.

[0132] <Operation Example of Semiconductor Device> Next, refer to Figure 6 and Figure 7 An operation example of the semiconductor device 10 will be described.

[0133] As an example of a driving method, a semiconductor device 10 according to one embodiment of the present invention includes a read mode 1 (Readmode 1) and a read mode 2 (Readmode 2). Read mode 1 is a mode in which data stored in a memory cell 42 (the potential held at a node MND) is read using a read amplifier 55 included in a drive circuit 51 through a sensing circuit 35 and a switching circuit 37. Read mode 2 is a mode in which a potential stored in a local bit line LBL is read using a read amplifier 55 included in a drive circuit 51 through a sensing circuit 35 and a switching circuit 37. In other words, when the sensing circuit 35 is used as a memory, read mode 2 is a mode in which data stored in a local bit line LBL is read using a read amplifier 55 included in a drive circuit 51 through a sensing circuit 35 and a switching circuit 37.

[0134] Note that in the working example described below, as the potential corresponding to binary data, the potential corresponding to "1" of the binary data is the potential VDD of the high power supply potential (hereinafter sometimes referred to as VDD) and the potential corresponding to "0" of the binary data is the potential VSS of the low power supply potential (hereinafter referred to as VSS). Compared with VSS, VDD is at least higher than the threshold voltage of the transistor. Note that VSS can be, for example, the ground potential GND. In addition, in the working example described below, the potential of the signal is set to the H level or the L level. The H level refers to the potential at which the transistor becomes conductive when supplied to the gate of the n-channel transistor and the potential at which the transistor becomes non-conductive when supplied to the gate of the p-channel transistor. The L level refers to the potential at which the transistor becomes non-conductive when supplied to the gate of the n-channel transistor and the potential at which the transistor becomes conductive when supplied to the gate of the p-channel transistor. The H level can be, for example, the same potential as VDD or a potential higher than VDD. The L level can be, for example, the same potential as VSS or a potential lower than VSS.

[0135] Note that, in each of the plurality of signals supplied to the semiconductor device 10, the H level or L level does not need to be the same potential. Each of the plurality of signals supplied to the semiconductor device 10 may have a different potential at the H level or L level depending on the threshold voltage of the transistor to which the signal is supplied. For example, the potential of the H level or L level of the signal supplied to the gate of the Si transistor provided in the substrate 50 may be different from that of the signal supplied to the gate of the OS transistor provided in the layer 30 and the layer 40. For example, when the threshold voltage of the OS transistor is higher than the threshold voltage of the Si transistor, the potential of the H level of the signal supplied to the gate of the OS transistor may be higher than the H level of the signal supplied to the gate of the Si transistor. For example, in the present embodiment, the potential of the H level of each signal supplied to the word line WL, the signal MUX, the signal WE, the signal RE, the signal SW0, the signal SW1, the signal SW2, and the signal SW3 may be higher than the H level of each signal of the signal EQ, the signal EQB, and the signal CSEL. In addition, regarding the working example described below, in order to simplify the description, the potential of the signal in all signals is described as the H level or the L level.

[0136] The following reference Figure 6 and Figure 7 The timing chart shown here explains an operation example of read mode 1 and read mode 2. Figure 6 and Figure 7 The timing diagram shown shows the potentials (H level or L level) of the signal supplied to the word line WL, the signal MUX, the signal WE, the signal RE, the signal SW0, the signal SW1, the signal SW2, the signal SW3, the signal EQ, the signal EQB, and the signal CSEL at each operation time. In addition, the potentials supplied to the wiring SL, the wiring SAP, and the wiring SAN are shown. In addition, the potential changes of the node MND, the local bit line LBL, the local bit line LBL_pre, the global bit line GBL, the global bit line GBLB, the global bit line SA_GBL, and the global bit line SA_GBLB of the memory cell 42 when the data "1" is read (data 1) and when the data "0" is read (data 0).

[0137] Note that in this specification, for example, the statement "at time T11, the signal becomes an H level (or an L level)" does not necessarily mean that the potential of the signal becomes constant at the H level (or the L level) at the instant of that time. For example, even if the potential of the signal gradually changes due to the parasitic resistance and parasitic capacitance of the wiring and some signal delay occurs until the potential becomes constant at the H level (or the L level), it is expressed as "at time T11, the signal becomes an H level (or an L level)". Therefore, for example, the expression "time T11" can be replaced with "approximately time T11" or "substantially time T11". Note that the same is true for times other than time T11. In addition, in the accompanying drawings of the timing diagram, the situation where the potential of the signal gradually changes and a signal delay occurs until the potential becomes constant at the H level (or the L level) is indicated by a slash. Note that the time of the signal delay is, for example, less than 100 nanoseconds, preferably less than 10 nanoseconds, more preferably less than 1 nanosecond, and further preferably less than 0.1 nanosecond. In addition, the time of the signal delay may be different for each signal.

[0138] [Reading mode 1] Figure 6 1 is a timing chart for explaining an operation example of the semiconductor device 10 in read mode 1. The period from time T11 to time T13 is a period for correcting the threshold voltage. The period from time T13 to time T16 is a period for reading data. The period after time T16 is a period for writing back data (refreshing).

[0139] Just before entering time T11, the signal supplied to the word line WL, the signal MUX, the signal WE, and the signal RE are all at L level. In addition, the potential of the wiring SL is a specified potential (e.g., VSS). In addition, the signal SW0, the signal SW1, the signal SW2, and the signal SW3 are all at L level. In addition, the signal EQ is at H level and the signal EQB is at L level. In addition, the signal CSEL is at L level. In addition, the potential of the wiring SAP and the potential of the wiring SAN are VDD. Note that the potential VPRE and the potential VPRE2 are VDD. In addition, the potential of the wiring CSL is an arbitrary fixed potential (e.g., VSS). At this time, the global bit line SA_GBL and the global bit line SA_GBLB are both precharged to VDD. In addition, the global bit line GBL and the global bit line GBLB are both in an electrically floating state and their respective potentials are VDD or VSS. In addition, the local bit line LBL and the local bit line LBL_pre are both in an electrically floating state and maintain VDD or VSS. In addition, the node MND of the memory cell 42 holds VDD (potential corresponding to data "1") or VSS (potential corresponding to data "0"). Note that in the description of each operation from time T11 to time T16, when the potential of each wiring and each signal are not mentioned, it can be regarded that the potential at the immediately previous time is held.

[0140] At time T11, the signal SW1 and the signal SW2 become H level. In addition, the signal MUX and the signal WE become H level. Therefore, the global bit line GBL and the global bit line GBLB are precharged to VDD. And the local bit line LBL and the local bit line LBL_pre are precharged to VDD. In addition, the potential of the wiring SL becomes a predetermined potential between VDD and VSS. This predetermined potential affects the amount of current that will flow through the transistor 31 in the operation at time T14 described later. Therefore, the predetermined potential can be determined in such a way that the amount of current becomes an appropriate value.

[0141] At time T12, signal MUX becomes L level and signal RE becomes H level. Therefore, the potential of local bit line LBL and local bit line LBL_pre decreases to "the potential of wiring SL+the threshold voltage of transistor 31" due to discharge to wiring SL via transistor 31 included in sensor circuit 35 and sensor circuit 35_pre.

[0142] At time T13, the signal WE and the signal RE become L level. Therefore, the local bit line LBL and the local bit line LBL_pre are both in an electrically floating state. Therefore, the potential corresponding to the threshold voltage of the transistor 31 included in the sensing circuit 35 and the sensing circuit 35_pre is maintained at the local bit line LBL and the local bit line LBL_pre. Therefore, the amount of current flowing through the transistor 31 in the operation at time T14 described later is corrected in a manner not affected by the threshold voltage of the transistor 31. By performing such correction, the semiconductor device 10 according to one embodiment of the present invention can improve the reliability of the data read out.

[0143] At time T13, signal EQ becomes L level and signal EQB becomes H level. Therefore, precharging of global bit lines SA_GBL and GBL and precharging of global bit lines SA_GBLB and GBLB are stopped. As a result, global bit lines SA_GBL and GBL and global bit lines SA_GBLB and GBLB are both in an electrically floating state.

[0144] In addition, at time T13, the signal supplied to the word line WL on the side of the memory cell 42 electrically connected to the local bit line LBL becomes the H level. Therefore, charge sharing is performed between the local bit line LBL and the node MND. Therefore, the potential of the local bit line LBL changes according to the data stored in the memory cell 42 (that is, according to the potential held at the node MND). As a result, the potential of the local bit line LBL becomes the same as the potential of the node MND.

[0145] Specifically, for example, when the data stored in the memory cell 42 is "1" (data 1) (i.e., the potential of the node MND is maintained at VDD), the signal supplied to the word line WL becomes H level, the potential of the local bit line LBL rises and the potential of the node MND falls. As a result, the potential of the local bit line LBL becomes the same as the potential of the node MND. Alternatively, for example, when the data stored in the memory cell 42 is "0" (data0) (i.e., the potential of the node MND is maintained at VSS), the signal supplied to the word line WL becomes H level, the potential of the local bit line LBL falls and the potential of the node MND rises. As a result, the potential of the local bit line LBL becomes the same as the potential of the node MND.

[0146] On the other hand, at time T13, the signal supplied to the word line WL on the memory cell 42 side electrically connected to the local bit line LBL_pre is kept at L level. That is, charge sharing is not performed on the local bit line LBL_pre. Therefore, the potential of the local bit line LBL does not change.

[0147] Note that the potential of the node MND changes by performing charge sharing. In other words, the data stored in the memory cell 42 is destroyed. That is, the read mode 1 is a destructive read. Therefore, data is written back in the operation of time T16 described later.

[0148] At time T14, the signal MUX and the signal RE become H level. In addition, the potential of the wiring SL becomes the same as the potential immediately before entering time T11 (for example, VSS). Therefore, according to the potentials of the local bit line LBL and the local bit line LBL_pre, the current flows through the transistor 31 in the sensing circuit 35 and the transistor 31 in the sensing circuit 35_pre. As a result, the potentials of the global bit line SA_GBL and the global bit line GBL, and the global bit line SA_GBLB and the global bit line GBLB gradually decrease. At this time, due to the difference between the potential of the local bit line LBL and the potential of the local bit line LBL_pre, a difference occurs between the amount of current flowing through the transistor 31 included in the sensing circuit 35 and the amount of current flowing through the transistor 31 included in the sensing circuit 35_pre. The difference in the amount of current corresponds to the potential of the local bit line LBL that changes due to the charge sharing in the operation at the above-mentioned time T13. That is, the speed at which the potential of the global bit line SA_GBL and the global bit line GBL decreases varies according to the potential of the local bit line LBL. Therefore, the potential of the local bit line LBL can be converted into the potential difference between the global bit line SA_GBL and the global bit line SA_GBLB.

[0149] Specifically, for example, when the data stored in the memory cell 42 is "1" (data 1), the amount of current flowing through the transistor 31 included in the sensing circuit 35 is greater than the amount of current flowing through the transistor 31 included in the sensing circuit 35_pre. Therefore, the speed at which the potential of the global bit line SA_GBL and the global bit line GBL decreases is faster than the speed at which the potential of the global bit line SA_GBLB and the global bit line GBLB decreases. Therefore, the potential of the global bit line SA_GBL is lower than the potential of the global bit line SA_GBLB. Or, for example, when the data stored in the memory cell 42 is "0" (data 0), the amount of current flowing through the transistor 31 included in the sensing circuit 35 is less than the amount of current flowing through the transistor 31 included in the sensing circuit 35_pre. Therefore, the speed at which the potential of the global bit line SA_GBL and the global bit line GBL decreases is slower than the speed at which the potential of the global bit line SA_GBLB and the global bit line GBLB decreases. As a result, the potential of the global bit line SA_GBL is higher than the potential of the global bit line SA_GBLB.

[0150] At time T15, signal RE becomes L level. In addition, the potential of wiring SAN becomes VSS. Therefore, when sense amplifier 55 operates, the potential difference between global bit line SA_GBL and global bit line SA_GBLB generated by the operation at time T14 is amplified. Thus, the potential of global bit line SA_GBL and global bit line SA_GBLB is determined to be one of VDD and VSS. In other words, the reading of data stored in memory cell 42 is completed.

[0151] Specifically, for example, when the data stored in the memory cell 42 is "1" (data 1), the potential of the global bit line SA_GBL becomes VSS and the potential of the global bit line SA_GBLB becomes VDD. Alternatively, for example, when the data stored in the memory cell 42 is "0" (data0), the potential of the global bit line SA_GBL becomes VDD and the potential of the global bit line SA_GBLB becomes VSS.

[0152] At time T16, signal SW0 becomes H level and signal SW1 becomes L level. In addition, signal WE becomes H level. Therefore, based on the data read from memory cell 42, the operation of writing back data is performed on memory cell 42. That is, the potentials of global bit line GBL and local bit line LBL become the same as the potential of global bit line SA_GBLB determined by the operation at time T15. Furthermore, this potential is written back to memory cell 42.

[0153] Specifically, for example, when the data stored in the memory cell 42 is "1" (data 1), the potential of the global bit line SA_GBLB immediately before entering time T16 is VDD. Therefore, the potentials of the global bit line GBL and the local bit line LBL become VDD. Furthermore, VDD is written back to the memory cell 42. Or, for example, when the data stored in the memory cell 42 is "0" (data0), the potential of the global bit line SA_GBLB immediately before entering time T16 is VSS. Therefore, the potentials of the global bit line GBL and the local bit line LBL become VSS. Furthermore, VSS is written back to the memory cell 42.

[0154] Note that when writing data to the memory cell 42, for example, the semiconductor device 10 may operate in the same manner as at the time T16 described above. For example, when writing data "1" to the memory cell 42, VDD may be supplied to the global bit line SA_GBLB, and the operation may be performed in the same manner as at the time T16 described above. Alternatively, for example, when writing data "0" to the memory cell 42, VSS may be supplied to the global bit line SA_GBLB, and the operation may be performed in the same manner as at the time T16 described above.

[0155] [Reading mode 2] Figure 7 1 is a timing diagram for explaining an example of the operation of the semiconductor device 10 in read mode 2 (Readmode2). Time T21 to time T24 is the period for reading data. Note that in read mode 2, the data stored in the memory cell 42 is not involved in the reading of data. In addition, the potential of the local bit line LBL_pre is not involved in the reading of data. Therefore, Figure 7 The potentials of the node MND and the local bit line LBL_pre are not shown in the figure. In addition, the potential of the global bit line GBLB is also omitted in the figure.

[0156] Just before entering time T21, the signal supplied to the word line WL, the signal MUX, the signal WE, and the signal RE are all at L level. In addition, the potential of the wiring SL is a specified potential (e.g., VSS). In addition, the signal SW0, the signal SW1, the signal SW2, and the signal SW3 are all at L level. In addition, the signal EQ is at H level and the signal EQB is at L level. In addition, the signal CSEL is at L level. In addition, the potential of the wiring SAP and the potential of the wiring SAN are (VDD-VSS) / 2. Note that the potential VPRE is (VDD-VSS) / 2, and the potential VPRE2 is a potential that exceeds (VDD-VSS) / 2 and does not exceed VDD (e.g., VDD). In addition, the potential of the wiring CSL is an arbitrary fixed potential (e.g., VSS). At this time, the global bit line SA_GBL and the global bit line SA_GBLB are precharged to (VDD-VSS) / 2. In addition, the global bit line GBL and the global bit line GBLB are both in an electrically floating state and their respective potentials are VDD or VSS. In addition, the local bit line LBL is in an electrically floating state and holds VDD (potential corresponding to data "1") or VSS (potential corresponding to data "0"). Note that in the description of each operation from time T21 to time T24, when the potential of each wiring and each signal are not mentioned, it can be regarded that the potential at the immediately previous time is held.

[0157] At time T21, signal EQ becomes L level and signal EQB becomes H level. Therefore, precharging of global bit lines SA_GBL and SA_GBLB is stopped. As a result, global bit lines SA_GBL and SA_GBLB are both in an electrically floating state.

[0158] At time T22, the signals SW1 and SW3 become H level. Therefore, the global bit lines SA_GBL and GBL are precharged to a potential between VDD and (VDD-VSS) / 2. That is, the potential of the global bit line SA_GBL is higher than the potential of the global bit line SA_GBLB.

[0159] At time T23, signal SW3 becomes L level. Therefore, precharging of global bit line SA_GBL and global bit line GBL stops. In addition, signal MUX and signal RE become H level. Thus, the potential of global bit line SA_GBL and global bit line GBL changes according to the potential of local bit line LBL. Therefore, the potential of local bit line LBL can be converted into the potential difference between global bit line SA_GBL and global bit line SA_GBLB.

[0160] Specifically, for example, when the data stored in the sensing circuit 35 used as a memory is "1" (data 1) (i.e., the potential of the local bit line LBL is maintained at VDD), the potentials of the global bit line SA_GBL and the global bit line GBL gradually decrease due to the flow of current through the transistor 31 included in the sensing circuit 35. Therefore, the potential of the global bit line SA_GBL is lower than the potential of the global bit line SA_GBLB. Or, for example, when the data stored in the sensing circuit 35 used as a memory is "0" (data0) (i.e., the potential of the local bit line LBL is maintained at VSS), the potentials of the global bit line SA_GBL and the global bit line GBL are maintained due to the transistor 31 included in the sensing circuit 35 being in a non-conductive state. Therefore, the potential of the global bit line SA_GBL continues to be higher than the potential of the global bit line SA_GBLB.

[0161] Note that the potential of the local bit line LBL does not change by the operation of time T23. That is, the data stored in the sensing circuit 35 used as a memory is not destroyed. In other words, the read mode 2 is non-destructive read.

[0162] At time T24, the signal MUX and the signal RE become L level. In addition, the potential of the wiring SAN becomes VSS and the potential of the wiring SAP becomes VDD. Therefore, when the sense amplifier 55 operates, the potential difference between the global bit line SA_GBL and the global bit line SA_GBLB generated by the operation at time T23 is amplified. Thus, the potential of the global bit line SA_GBL and the global bit line SA_GBLB is determined to be one of VDD and VSS. In other words, the reading of the data stored in the sensing circuit 35 used as a memory is completed.

[0163] Specifically, for example, when the data stored in the sensing circuit 35 used as a memory is "1" (data 1), the potential of the global bit line SA_GBL becomes VSS and the potential of the global bit line SA_GBLB becomes VDD. Alternatively, for example, when the data stored in the sensing circuit 35 used as a memory is "0" (data 0), the potential of the global bit line SA_GBL becomes VDD and the potential of the global bit line SA_GBLB becomes VSS.

[0164] Note that when writing data to the sensing circuit 35 used as a memory, the semiconductor device 10 may, for example, make the signal supplied to the word line WL become L level and operate in the same manner as the above-mentioned time T16. For example, when writing data "1" to the sensing circuit 35 used as a memory, the signal supplied to the word line WL may become L level, VDD may be supplied to the global bit line SA_GBLB, and the operation may be performed in the same manner as the above-mentioned time T16. Alternatively, when writing data "0" to the sensing circuit 35 used as a memory, the signal supplied to the word line WL may become L level, VSS may be supplied to the global bit line SA_GBLB, and the operation may be performed in the same manner as the above-mentioned time T16.

[0165] Read mode 1 is a mode for reading data stored in the storage cell 42. The storage cell 42 occupies a smaller area than the sensing circuit 35 used as a memory. In addition, the storage density is high because it can be stacked. Read mode 2 is a mode for reading data stored in the sensing circuit 35 used as a memory. Data mode 2 does not require a period for correcting the threshold voltage and a period for writing back the data, so data can be read faster than read mode 1. In addition, the energy required for reading (access energy) is low. A semiconductor device 10 according to one embodiment of the present invention can achieve high-speed data reading and reduced power consumption by appropriately using read mode 1 and read mode 2 respectively according to the situation or purpose.

[0166] After the semiconductor device 10 according to one embodiment of the present invention finishes reading in read mode 1, the potential corresponding to the data read from the memory cell 42 is maintained at the local bit line LBL. That is, the sensing circuit 35 used as a memory stores the data previously read from the memory cell 42. Therefore, when reading data from the same memory cell 42 again, the data can be read using read mode 2. Therefore, the speed of reading data can be made faster. In addition, the energy required for reading (access energy) can be reduced. Therefore, the semiconductor device 10 can achieve high-speed data reading and reduced power consumption.

[0167] As a driving method, the semiconductor device 10 according to one embodiment of the present invention can be suitably used in, for example, an electronic computer by having the read mode 1 and the read mode 2 as described above. For example, the plurality of storage cells 42 provided in each of the layers 41[1] to 41[m] can be used as a main memory included in the electronic computer, and the plurality of sensor circuits 35 provided in the layer 30 can be used as a cache memory included in the electronic computer. In this case, the read mode 1 corresponds to a mode for accessing the main memory, and the read mode 2 corresponds to a mode for accessing the cache memory.

[0168] An example in which the semiconductor device 10 according to one embodiment of the present invention is used in an electronic computer will be described in detail later.

[0169] <Configuration Example of Storage Device> A semiconductor device according to one embodiment of the present invention can be used appropriately in a storage device. Here, a storage device according to one embodiment of the present invention using the semiconductor device 10 described above is described. Note that in the storage device described below, since the portion using the semiconductor device 10 can refer to the above description as appropriate, the same reference numerals may be used in the drawings and the like to omit the description.

[0170] Figure 8 A block diagram showing a configuration example of a storage device 300 according to one embodiment of the present invention. Figure 8 The memory device 300 using the semiconductor device 10 shown includes a memory array 21 and a driving circuit 22. The memory array 21 includes a plurality of sensing circuits 35 and a switching circuit 37 disposed in a layer 30 and a plurality of memory cells 42 disposed in layers 41[1] to 41[m]. The driving circuit 22 is disposed on a substrate 50 (not shown).

[0171] As an example, Figure 8 The memory array 21 shown has m×n memory cells 42 arranged in a matrix of m rows and n columns. Note that m and n are integers greater than 2. In addition, as an example, the memory array 21 has n sensor circuits 35 arranged in each column.

[0172] exist Figure 8 , the first first column storage unit 42 is represented as storage unit 42[1,1], and the m-th row and n-th column storage unit 42 is represented as storage unit 42[m,n]. In addition, in the present embodiment, etc., sometimes "row i" is written to represent an arbitrary row. In addition, sometimes "column j" is written to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the i-th row and j-th column storage unit 42 is represented as storage unit 42[i,j]. In the present embodiment, etc., when expressed as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when expressed as "j+α", "j+α" is not less than 1 and not greater than n.

[0173] In addition, Figure 8 In the figure, the sensor circuit 35 arranged in the first column is represented as sensor circuit [1], the sensor circuit 35 arranged in the jth column is represented as sensor circuit [j], and the sensor circuit 35 arranged in the nth column is represented as sensor circuit [n].

[0174] In addition, the memory array 21 includes m word lines WL extending in the row direction, m wirings CSL extending in the row direction, and n local bit lines LBL extending in the column direction. In the present embodiment, the first word line WL (in the first row) is represented as word line WL[1], and the m-th word line WL (in the m-th row) is represented as word line WL[m]. Similarly, the first wiring CSL (in the first row) is represented as wiring CSL[1], and the m-th wiring CSL (in the m-th row) is represented as wiring CSL[m]. Similarly, the first local bit line LBL (in the first column) is represented as local bit line LBL[1], and the n-th local bit line LBL (in the n-th column) is represented as local bit line LBL[n].

[0175] The n memory cells 42 arranged in the i-th row are electrically connected to the i-th word line WL (word line WL[i]) and the i-th wiring CSL (wiring CSL[i]). The m memory cells 42 arranged in the j-th column are electrically connected to the j-th local bit line LBL (local bit line LBL[j]).

[0176] The sensing circuit 35 (sensing circuit 35[j]) provided in the j-th column is electrically connected to the j-th column local bit line LBL (local bit line LBL[j]). The switching circuit 37 is electrically connected to the n sensing circuits 35 via the global bit line GBL (not shown). In addition, the switching circuit 37 is electrically connected to the driving circuit 51 having the sense amplifier 55 included in the driving circuit 22 via the global bit line SA_GBL.

[0177] The drive circuit 22 includes a PSW 62 (power switch), a PSW 63 and a peripheral circuit 71 . The peripheral circuit 71 includes a peripheral circuit 81 , a control circuit 72 (control circuit) and a voltage generation circuit 73 .

[0178] Note that a portion of peripheral circuit 71 may be provided in layer 30 .

[0179] In the storage device 300, the above-mentioned circuits, signals and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside. Signal RDA is a signal output to the outside.

[0180] Signal CLK is a clock signal. In addition, signal BW, signal CE and signal GW are control signals. Signal CE is a chip enable signal. Signal GW is a global write enable signal. Signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data. Signal RDA is read data. Signal PON1 and signal PON2 are power gating control signals. In addition, signal PON1 and signal PON2 can also be generated in control circuit 72.

[0181] The control circuit 72 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation or reading operation (for example, reading mode 1 or reading mode 2)) of the storage device 300. Alternatively, the control circuit 72 generates a control signal for the peripheral circuit 81 to execute the above operation mode.

[0182] The voltage generating circuit 73 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 73. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 73, and the voltage generating circuit 73 generates a negative voltage.

[0183] The peripheral circuit 81 is a circuit for writing or reading data to the memory cell 42. In addition, the peripheral circuit 81 is a circuit for outputting various signals for controlling the sensing circuit 35 and the switching circuit 37. The peripheral circuit 81 includes a driving circuit 51 having a row decoder 82 (RowDecoder), a column decoder 84 (ColumnDecoder), a row driver 83 (RowDriver), a column driver 85 (ColumnDriver), an input circuit 87 (InputCir.), an output circuit 88 (OutputCir.), and a sense amplifier 55 (SenseAmplifier).

[0184] The row decoder 82 and the column decoder 84 have the function of decoding the signal ADDR. The row decoder 82 is a circuit for specifying a row to be accessed. The column decoder 84 is a circuit for specifying a column to be accessed. The row driver 83 has the function of selecting the word line WL specified by the row decoder 82. The column driver 85 has the following functions, for example: a function of writing data to the memory cell 42; a function of reading data from the memory cell 42; a function of holding the read data; etc.

[0185] The input circuit 87 has a function of holding a signal WDA. The data held in the input circuit 87 is output to the column driver 85. The output data of the input circuit 87 is the data (data Din) written to the memory cell 42. The data (data Dout) read from the memory cell 42 by the column driver 85 is output to the output circuit 88. The output circuit 88 has a function of holding the data Dout. In addition, the output circuit 88 has a function of outputting the data Dout to the outside of the memory device 300. The data output from the output circuit 88 is a signal RDA.

[0186] PSW62 has a function of controlling the supply of VDD to the peripheral circuit 71. PSW63 has a function of controlling the supply of potential VHM to the row driver 83. Here, the high power supply potential of the storage device 300 is VDD, and the low power supply potential is the ground potential GND (or VSS). In addition, the potential VHM is a high power supply potential used to make the word line H level, which is higher than VDD. The on / off state of PSW62 is controlled by the signal PON1. The on / off state of PSW63 is controlled by the signal PON2. Figure 8 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 71 is one, but it may be more than one. In this case, the driving circuit 22 may provide a power switch for each power domain.

[0187] As in the above description of the semiconductor device 10 , the layer 30 and each of the layers 41 [ 1 ] to 41 [ m ] may be stacked in a vertical direction on the substrate 50 .

[0188] As an example, Fig. 9A A perspective view of a memory device 300 is shown in which a layer 30 and layers 41 [ 1 ] to 41 [ 5 ] consisting of five layers (m=5) are stacked in a vertical direction on a substrate 50 . Fig. 9A A plurality of memory cells 42 arranged in each of the layers 41[1] to 41[5] are shown. In addition, a plurality of sensor circuits 35 arranged in the layer 30 are shown. In addition, word lines WL and wirings CSL extending in the X direction and local bit lines LBL extending in the Z direction (a vertical direction on the substrate 50 on which the drive circuit 22 is provided) are shown. Note that in order to make the drawings easier to understand, part of the word lines WL and wirings CSL are omitted.

[0189] Fig. 9B is shown with Fig. 9A A schematic diagram of a configuration example of a sensing circuit 35 and a plurality of memory cells 42 electrically connected to one of the plurality of local bit lines LBL shown. Fig. 9B2 shows a switching circuit 37 and a driving circuit 51 provided in the driving circuit 22. The switching circuit 37 is electrically connected to the sensing circuit 35 via the global bit line GBL. In addition, the switching circuit 37 is electrically connected to the driving circuit 51 via the global bit line SA_GBL. Fig. 9B As shown, a structure in which one local bit line LBL is electrically connected to a plurality of memory cells 42 is referred to as a "memory string".

[0190] In addition, the local bit line LBL is provided in a manner of contacting the semiconductor layer of the transistor included in the memory cell 42. Alternatively, the local bit line LBL is provided in a manner of contacting a region of the semiconductor layer of the transistor included in the memory cell 42 that functions as a source or a drain. Alternatively, the local bit line LBL is provided in a manner of contacting a conductor provided in a manner of contacting a region of the semiconductor layer of the transistor included in the memory cell 42 that functions as a source or a drain. That is, the local bit line LBL is a wiring for electrically connecting the other of the source and the drain of the transistor included in each of the plurality of memory cells 42 provided in the layers 41[1] to 41[5] to the sensing circuit 35 in the vertical direction.

[0191] In addition, the memory device 300 according to one embodiment of the present invention can stack a plurality of sensor circuits 35 and switching circuits 37 and a plurality of memory cells 42 in a vertical direction on the drive circuit 22 including the sense amplifier 55 by using the semiconductor device 10 described above. Thus, the memory device 300 according to one embodiment of the present invention can achieve, for example, an increase in storage density, a reduction in manufacturing cost, a reduction in power consumption, a reduction in signal delay, and miniaturization.

[0192] In addition, the memory device 300 according to one embodiment of the present invention can have a drive method including read mode 1 and read mode 2 by using the semiconductor device 10 described above. The memory device 300 according to one embodiment of the present invention can be suitably used in, for example, a computer by having the read mode 1 and read mode 2 described above.

[0193] <Structure example of electronic computer> A semiconductor device according to one embodiment of the present invention can be suitably used in an electronic computer. In addition, a storage device according to one embodiment of the present invention can be suitably used in an electronic computer. Here, an example in which the semiconductor device 10 described above is used in an electronic computer is described. Note that in the electronic computer described below, since the part using the semiconductor device 10 can refer to the above description as appropriate, the same symbols are sometimes used in the drawings and the like to omit the description.

[0194] Fig.10Schematic diagram showing an electronic computer 90 according to one embodiment of the present invention. The electronic computer 90 includes a processor 91 (CPU) and a main memory 92 (Main memory). The processor 91 has a core 93 (Core), a cache memory 94 (Cache memory), and an interface 95 (I / F).

[0195] The processor 91 has a function of accessing the cache memory 94 and storing (also referred to as loading) the command or data stored in the cache memory 94 in a register (not shown) included in the core 93 through the interface 95. In addition, the processor 91 has a function of performing a predetermined operation based on the command or data stored in the register. In addition, when the command or data stored in the register by loading is not the command or data desired by the core 93 (also referred to as a cache miss), the processor 91 has a function of accessing the main memory 92 and reading the desired command or data stored in the main memory 92 to the cache memory 94.

[0196] As an example of using the semiconductor device 10 described above, the electronic computer 90 can use multiple storage units 42 included in the semiconductor device 10 for the main memory 92, use the sensor circuit 35 used as the multiple memories included in the semiconductor device 10 for the main memory 94, and use the driving circuit 51 included in the semiconductor device 10 for the interface 95.

[0197] Therefore, if Fig.10 As shown, the core 93 and the interface 95 are provided on the substrate 50, the cache memory 94 is provided in the layer 30, and the main memory 92 is provided in each of the layers 41[1] to 41[m]. Furthermore, the layer 30 provided with the cache memory 94 and the layers 41[1] to 41[m] provided with the main memory 92 are stacked in the vertical direction on the substrate 50 provided with the core 93 and the interface 95.

[0198] As described above, the structure of the storage unit 42 can be called DOSRAM. DOSRAM can be used for main memory instead of DRAM (Dynamic Random Access Memory) which is widely used for main memory. Like DRAM, DOSRAM is composed of a transistor and a capacitor, and by using an OS transistor with extremely low off-state current as the transistor, data can be stored for a long time. Therefore, compared with DRAM, DOSRAM can greatly reduce the refresh cycle. For example, the refresh cycle of DRAM is less than 10 milliseconds, but the refresh cycle of DOSRAM is about one hour to one year. In addition, DOSRAM can be configured in multiple layers on a silicon substrate provided with a read amplifier. Due to these characteristics, compared with DRAM, DOSRAM can operate at high speed and can reduce access energy (energy consumed by writing or reading data).

[0199] In addition, as described above, by using the sensing circuit 35 as a memory, it can be regarded as a NOSRAM. NOSRAM is a non-volatile memory that stores data by maintaining a charge for a long time by utilizing the characteristics of the OS transistor with extremely low off-state current. In addition, NOSRAM has the advantages that there is no limit on the number of rewrites in principle and that multi-valued data can be written. NOSRAM can be used for a cache memory instead of SRAM (Static Random Access Memory) widely used in a cache memory. NOSRAM can be freely configured in a layer on a silicon substrate on which a core of a processor is provided, for example, and integration is easy.

[0200] That is, the electronic computer 90 may have a structure in which a layer of NOSRAM (sensing circuit 35) used as a cache memory is arranged on a silicon substrate having a core of a processor; and multiple layers of DOSRAM (storage unit 42) used as a main memory are arranged.

[0201] <Working example of electronic computer> Next, an operation example of the electronic computer 90 according to one embodiment of the present invention will be described. As a driving method of the electronic computer 90, the driving method of the semiconductor device 10 described above can be used.

[0202] Fig.11A 2 is a flowchart showing an example of the operation of the electronic computer 90. In order for the electronic computer 90 to perform a predetermined operation, it is necessary to load a desired command or data into a register included in the core 93. Fig.11A The flowchart shown in FIG. 1 shows a method for driving the electronic computer 90 when loading a desired command or data to a register included in the core 93. Fig.11AAs shown, the electronic computer 90 includes steps S01, S02 and S03. When the loading of the desired command or data is started (START), step S01 is first performed.

[0203] Step S01 accesses the cache memory 94 using access mode 1. Fig. 11B 1 is a diagram schematically showing the operation of the electronic computer 90 in access mode 1. That is, the electronic computer 90 loads the command or data stored in the cache memory 94 into the register of the core 93 through the interface 95. Note that access mode 1 corresponds to the read mode 2 (Read mode 2) included in the semiconductor device 10 described above (see as appropriate). Figure 7 ). That is, the electronic computer 90 reads out the data stored in the sensor circuit 35 used as a memory. Next, step S02 is performed.

[0204] Step S02 determines whether the command or data loaded in the register of the core 93 in step S01 is a cache miss (Determination of cache miss). When the determination in step S02 is "YES", that is, when the command or data stored in the register of the core 93 is not the command or data desired by the core 93 (cache miss), step S03 is performed. Or when the determination in step S02 is "NO", that is, when the command or data stored in the register of the core 93 is the command or data desired by the core 93 (cache hit), the loading of the command or data is terminated (END). After that, although not shown in the figure, a predetermined operation is performed according to the command or data stored in the register.

[0205] In step S03, the main memory 92 is accessed using access mode 2. Fig. 11C 1 is a diagram schematically showing the operation of the electronic computer 90 in access mode 2. That is, the electronic computer 90 loads the desired command or data stored in the main memory 92 into the register of the core 93 through the cache memory 94 and the interface 95, and ends (END) the loading of the command or data. After that, although not shown in the figure, the specified operation is performed according to the command or data stored in the register. Note that access mode 2 is equivalent to the read mode 1 (Read mode 1) included in the semiconductor device 10 described above (refer to the Figure 6 ). That is, the electronic computer 90 reads out the data stored in the storage unit 42.

[0206] Note that the electronic computer 90 according to one embodiment of the present invention is not limited to the above-described structural example. For example, the electronic computer 90 may include a primary cache memory provided on the substrate 50 and a secondary cache memory provided on the layer 30 instead of the cache memory 94. In this case, the electronic computer 90 may use, for example, an SRAM for the primary cache memory, use the sensor circuit 35 used as a plurality of memories included in the semiconductor device 10 for the secondary cache memory, and may appropriately use the above-described working example. In addition, for example, the electronic computer 90 may include a primary cache memory to a p-level cache memory (p is an integer greater than or equal to 2) provided on the substrate 50, and a p+1-level cache memory provided on the layer 30. In this case, the electronic computer may use, for example, an SRAM for each of the primary cache memory to the p-level cache memory, and may use the sensor circuit 35 used as a plurality of memories included in the semiconductor device 10 for the p-level cache memory, and may appropriately use the above-described working example. In addition, for example, the electronic computer 90 may include an external storage class memory in addition to the above-described structure. In this case, the electronic computer 90 may use the plurality of storage units 42 included in the semiconductor device as an external storage level memory, or may appropriately use the above-mentioned working example.

[0207] According to one embodiment of the present invention, an electronic computer 90 adopts the structure of the semiconductor device 10 and the driving method of the semiconductor device 10 described above, which can achieve, for example, improved storage density, reduced manufacturing costs, reduced power consumption, reduced signal delay and miniaturization.

[0208] Note that a semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device 10 described above. Furthermore, a storage device according to one embodiment of the present invention is not limited to the storage device 300 described above. Furthermore, an electronic computer according to one embodiment of the present invention is not limited to the electronic computer 90 described above. At least a part of the configuration examples, operation examples, and drawings corresponding to these examples illustrated in this embodiment mode may be appropriately combined with other configuration examples, operation examples, other drawings, and other embodiments or other examples described in this specification and the like.

[0209] (Implementation Method 2) In this embodiment, a semiconductor device 10A according to one embodiment of the present invention is described. The semiconductor device 10A is a modified example of the semiconductor device 10 described in the above embodiment 1. Therefore, in order to reduce repeated descriptions, the differences between the semiconductor device 10A and the semiconductor device 10 are mainly described. Note that the description of the semiconductor device 10 described above can be appropriately referred to.

[0210] <Structural Example of Semiconductor Device> Fig.12 1 is a circuit diagram showing a configuration example of a semiconductor device 10A according to one embodiment of the present invention.

[0211] The semiconductor device 10A is different from the semiconductor device 10 in that the former has a switching circuit 37A instead of the switching circuit 37. The switching circuit 37A is different from the switching circuit 37 in that the former has capacitors C1 and C2 instead of the transistors M3 and M4.

[0212] The switching circuit 37A is electrically connected to the sensing circuit 35 through the global bit line GBL. In addition, the switching circuit 37A is electrically connected to the sensing circuit 35_pre through the global bit line GBLB. In addition, the switching circuit 37A is electrically connected to the driving circuit 51 included in the substrate 50 through the global bit line SA_GBL and the global bit line SA_GBLB. In addition, the switching circuit 37A has a function of making the global bit line GBL, the global bit line GBLB, the global bit line SA_GBL, and the global bit line SA_GBLB in a conductive state or a non-conductive state. In addition, the switching circuit 37A has a function of changing the potential of the global bit line GBL and the global bit line GBLB.

[0213] The switching circuit 37A includes a transistor M0, a transistor M1, a transistor M2, a capacitor C1, and a capacitor C2. Note that it is preferable to use a transistor with a very low off-state current as the transistor constituting the switching circuit 37A. For example, an OS transistor can be used as the transistor constituting the switching circuit 37A.

[0214] One of the source and drain of transistor M0 is electrically connected to global bit line GBL. The other of the source and drain of transistor M0 is electrically connected to global bit line GBLB. Transistor M0 has a function of connecting or disconnecting global bit line GBL and global bit line GBLB according to signal SW0.

[0215] One of the source and drain of transistor M1 is electrically connected to global bit line GBL. The other of the source and drain of transistor M1 is electrically connected to global bit line SA_GBL. Transistor M1 has a function of conducting or non-conducting between global bit line GBL and global bit line SA_GBL according to signal SW1.

[0216] One of the source and drain of transistor M2 is electrically connected to global bit line GBLB. The other of the source and drain of transistor M2 is electrically connected to global bit line SA_GBLB. Transistor M2 has a function of conducting or non-conducting between global bit line GBLB and global bit line SA_GBLB according to signal SW2.

[0217] One terminal of the capacitor C1 is electrically connected to the global bit line GBL. The other terminal of the capacitor C1 is electrically connected to a terminal to which the signal BOOT1 is supplied. The capacitor C1 has a function of changing the potential of the global bit line GBL according to the signal BOOT1.

[0218] One terminal of capacitor C2 is electrically connected to global bit line GBLB. The other terminal of capacitor C2 is electrically connected to a terminal to which signal BOOT2 is supplied. Capacitor C2 has a function of changing the potential of global bit line GBLB according to signal BOOT2.

[0219] <Operation Example of Semiconductor Device> Next, refer to Fig.13 and Fig.14 An operation example of the semiconductor device 10A will be described.

[0220] Similar to the semiconductor device 10 described above, the semiconductor device 10A according to one embodiment of the present invention includes a read mode 1 (Read mode 1) and a read mode 2 (Read mode 2) as an example of a driving method.

[0221] The following reference Fig.13 and Fig.14 The timing chart shown in the figure explains the operation examples of the read mode 1 and the read mode 2. Fig.13 and Fig.14 The timing diagram shown is similar to Figure 6 and Figure 7 The timing chart shown is different in that the former shows the potentials (H level or L level) of the signal BOOT1 and the signal BOOT2 instead of the signal SW3.

[0222] [Reading mode 1] Fig.13 1 is a timing chart for explaining an operation example of the semiconductor device 10A in the read mode 1 (Read mode 1).

[0223] Before and during the period from T11 to T13, the signals BOOT1 and BOOT2 are at L level. Figure 6 Therefore, the description of the read mode 1 of the semiconductor device 10A can be referred to the description of the read mode 1 of the semiconductor device 10, and the description thereof will be omitted.

[0224] [Reading mode 2] Fig.141 is a timing diagram for explaining an example of the operation of the semiconductor device 10A in read mode 2 (Readmode2). Time T21 to time T24 is the period for reading data. Note that in read mode 2, the data stored in the memory cell 42 is not involved in the reading of data. In addition, the potential of the local bit line LBL_pre is not involved in the reading of data. Therefore, Fig.14 The potentials of the node MND and the local bit line LBL_pre are not shown in the figure. In addition, the potential of the global bit line GBLB is also omitted in the figure.

[0225] Immediately before entering time T21, the signal supplied to the word line WL, the signal MUX, the signal WE, and the signal RE are all at L level. In addition, the potential of the wiring SL is a specified potential (e.g., VSS). In addition, the signal SW0 is at L level and the signal SW1 and the signal SW2 are at H level. In addition, the signal BOOT1 and the signal BOOT2 are at L level. In addition, the signal EQ is at H level and the signal EQB is at L level. In addition, the signal CSEL is at L level. In addition, the potential of the wiring SAP and the potential of the wiring SAN are (VDD-VSS) / 2. Note that the potential VPRE is (VDD-VSS) / 2. In addition, the potential of the wiring CSL is an arbitrary fixed potential (e.g., VSS). At this time, the global bit line SA_GBL and the global bit line GBL and the global bit line SA_GBLB and the global bit line GBLB are precharged to (VDD-VSS) / 2, respectively. In addition, the local bit line LBL is in an electrically floating state and maintains VDD (the potential corresponding to data "1") or VSS (the potential corresponding to data "0"). Note that in the description of the operations at each time T21 to time T24 , when the potential of each wiring and each signal are not mentioned, it can be regarded that the potential at the immediately previous time is maintained.

[0226] At time T21, signal EQ becomes L level and signal EQB becomes H level. Therefore, precharging of global bit lines SA_GBL and GBL and precharging of global bit lines SA_GBLB and GBLB are stopped. As a result, global bit lines SA_GBL and GBL and global bit lines SA_GBLB and GBLB are both in an electrically floating state.

[0227] At time T22, signal BOOT1 is at H level. Due to capacitive coupling via capacitor C1, the potentials of global bit line SA_GBL and global bit line GBL rise. That is, the potential of global bit line SA_GBL is higher than the potential of global bit line SA_GBLB.

[0228] At time T23, signals MUX and RE become H level. Thus, the potentials of global bit lines SA_GBL and GBL change according to the potential of local bit line LBL. Therefore, the potential of local bit line LBL can be converted into the potential difference between global bit line SA_GBL and global bit line SA_GBLB.

[0229] At time T24, the signal MUX and the signal RE become L level. In addition, the potential of the wiring SAN becomes VSS and the potential of the wiring SAP becomes VDD. Thus, when the sense amplifier 55 operates, the potential difference between the global bit line SA_GBL and the global bit line SA_GBLB generated by the operation at time T23 is amplified. Thus, the potential of the global bit line SA_GBL and the global bit line SA_GBLB is determined to be one of VDD and VSS. In other words, the reading of the data stored in the sensing circuit 35 used as a memory is completed.

[0230] The semiconductor device 10A is a structure in which the transistor M3 and the transistor M4 in the semiconductor device 10 are replaced with the capacitor C1 and the capacitor C2. Thus, the area efficiency of the semiconductor device 10A can be improved. In addition, at time T22, the semiconductor device 10A changes the potential of the global bit line SA_GBL and the global bit line GBL by capacitive coupling without using precharging. Therefore, in the semiconductor device 10A, it is not necessary to generate the potential VPRE2 as in the semiconductor device 10. Thus, low power consumption and miniaturization of the circuit (such as a voltage generating circuit, etc.) that supplies the potential to the semiconductor device 10A can be achieved.

[0231] The semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device 10A described above. At least a part of the structural examples, working examples, and drawings corresponding to these examples illustrated in this embodiment can be appropriately combined with other structural examples, working examples, other drawings, other embodiments or other examples described in this specification, etc.

[0232] (Implementation 3) In this embodiment, a semiconductor device 10B according to one embodiment of the present invention is described. The semiconductor device 10B is a modified example of the semiconductor device 10 described in the above embodiment 1. Therefore, in order to reduce repeated descriptions, the differences between the semiconductor device 10B and the semiconductor device 10 are mainly described. Note that the description of the semiconductor device 10 described above can be appropriately referred to.

[0233] <Structural Example of Semiconductor Device> Fig.15 1 is a circuit diagram showing a configuration example of a semiconductor device 10B according to one embodiment of the present invention.

[0234] The semiconductor device 10B is different from the semiconductor device 10 in that the former has a switching circuit 37B instead of the switching circuit 37. The switching circuit 37B is different from the switching circuit 37 in that the former does not have the transistor M3 and the transistor M4. The semiconductor device 10B is different from the semiconductor device 10 in that the former has a driving circuit 51B instead of the driving circuit 51.

[0235] Fig.16A 1 is a circuit diagram showing a drive circuit 51B provided on a substrate 50 using circuit symbols. In addition to the structure of the drive circuit 51 described above, the drive circuit 51B further includes a precharge circuit 56. The precharge circuit 56 is electrically connected to the global bit line SA_GBL and the global bit line SA_GBLB. In addition to the functions of the drive circuit 51 described above, the drive circuit 51B further has the function of precharging the global bit line SA_GBL and the global bit line SA_GBLB to a predetermined potential.

[0236] The precharge circuit 56 has a function of precharging the global bit line SA_GBL to the potential VPRE3 in accordance with the signal SW5. In addition, the precharge circuit 56 has a function of precharging the global bit line SA_GBLB to the potential VPRE3 in accordance with the signal SW6.

[0237] Specifically, the precharge circuit 56 includes a transistor M5 and a transistor M6. The transistor M5 and the transistor M6 are p-channel transistors.

[0238] One of the source and drain of the transistor M5 is electrically connected to the global bit line SA_GBL. The other of the source and drain of the transistor M5 is electrically connected to a terminal to which the potential VPRE3 is supplied. The transistor M5 has a function of precharging the global bit line SA_GBL to the potential VPRE3 according to the signal SW5.

[0239] One of the source and drain of the transistor M6 is electrically connected to the global bit line SA_GBLB. The other of the source and drain of the transistor M6 is electrically connected to a terminal to which the potential VPRE3 is supplied. The transistor M6 has a function of precharging the global bit line SA_GBLB to the potential VPRE3 according to the signal SW6.

[0240] Fig. 16B Shown corresponding to Fig.16A The circuit blocks of the circuit diagram of the illustrated driving circuit 51B correspond to Fig.15 The circuit blocks of the driving circuit 51B are shown.

[0241] <Operation Example of Semiconductor Device> Next, refer to Fig.17 and Fig.18 An operation example of the semiconductor device 10B will be described.

[0242] Similar to the semiconductor device 10 described above, the semiconductor device 10B according to one embodiment of the present invention includes a read mode 1 (Read mode 1) and a read mode 2 (Read mode 2) as an example of a driving method.

[0243] The following reference Fig.17 and Fig.18 The timing chart shown in the figure explains the operation examples of the read mode 1 and the read mode 2. Fig.17 and Fig.18 The timing diagram shown is similar to Figure 6 and Figure 7 The timing chart shown is different in that the former shows the potentials (H level or L level) of the signal SW5 and the signal SW6 instead of the signal SW3.

[0244] [Reading mode 1] Fig.17 1 is a timing chart for explaining an operation example of the semiconductor device 10B in the read mode 1 (Read mode 1).

[0245] Before and during the period from time T11 to time T13, the signals SW5 and SW6 are at the H level. Figure 6 Therefore, the description of the read mode 1 of the semiconductor device 10B can be referred to the description of the read mode 1 of the semiconductor device 10, and the description thereof will be omitted.

[0246] [Reading mode 2] Fig.18 1 is a timing diagram for explaining an example of the operation of the semiconductor device 10B in read mode 2 (Readmode2). Time T21 to time T24 is the period for reading data. Note that in read mode 2, the data stored in the memory cell 42 is not involved in the reading of data. In addition, the potential of the local bit line LBL_pre is not involved in the reading of data. Therefore, Fig.18 The potentials of the node MND and the local bit line LBL_pre are not shown in the figure. In addition, the potential of the global bit line GBLB is also omitted in the figure.

[0247] Before entering time T21, the signal supplied to the word line WL, the signal MUX, the signal WE, and the signal RE are all at L level. In addition, the potential of the wiring SL is a specified potential (e.g., VSS). In addition, the signal SW0, the signal SW1, and the signal SW2 are all at L level. In addition, the signal SW5 and the signal SW6 are at H level. In addition, the signal EQ is at H level and the signal EQB is at L level. In addition, the signal CSEL is at L level. In addition, the potential of the wiring SAP and the potential of the wiring SAN are (VDD-VSS) / 2. Note that the potential VPRE is (VDD-VSS) / 2, and the potential VPRE3 is a potential (e.g., VDD) that exceeds (VDD-VSS) / 2 and does not exceed VDD. In addition, the potential of the wiring CSL is an arbitrary fixed potential (e.g., VSS). At this time, the global bit line SA_GBL and the global bit line SA_GBLB are precharged to (VDD-VSS) / 2. In addition, the global bit line GBL and the global bit line GBLB are both in an electrically floating state and their respective potentials are VDD or VSS. In addition, the local bit line LBL is in an electrically floating state and holds VDD (potential corresponding to data "1") or VSS (potential corresponding to data "0"). Note that in the description of each operation from time T21 to time T24, when the potential of each wiring and each signal are not mentioned, it can be regarded that the potential at the immediately previous time is held.

[0248] At time T21, signal EQ becomes L level and signal EQB becomes H level. Thus, precharging of global bit lines SA_GBL and SA_GBLB is stopped. Therefore, global bit lines SA_GBL and SA_GBLB are in an electrically floating state.

[0249] At time T22, signal SW1 becomes H level. Also, signal SW5 becomes L level. Thus, global bit line SA_GBL and global bit line GBL are precharged to a potential between VDD and (VDD-VSS) / 2. That is, the potential of global bit line SA_GBL is higher than the potential of global bit line SA_GBLB.

[0250] At time T23, signal SW5 becomes H level. Thus, precharging of global bit line SA_GBL and global bit line GBL stops. Also, signal MUX and signal RE become H level. Thus, the potential of global bit line SA_GBL and global bit line GBL changes according to the potential of local bit line LBL. Therefore, the potential of local bit line LBL can be converted into the potential difference between global bit line SA_GBL and global bit line SA_GBLB.

[0251] At time T24, the signal MUX and the signal RE become L level. In addition, the potential of the wiring SAN becomes VSS and the potential of the wiring SAP becomes VDD. Thus, when the sense amplifier 55 operates, the potential difference between the global bit line SA_GBL and the global bit line SA_GBLB generated by the operation at time T23 is amplified. Thus, the potential of the global bit line SA_GBL and the global bit line SA_GBLB is determined to be one of VDD and VSS. In other words, the reading of the data stored in the sensing circuit 35 used as a memory is completed.

[0252] The semiconductor device 10B can be said to have a structure in which the transistors M3 and M4 using OS transistors provided in the layer 30 of the semiconductor device 10 are replaced with the transistors M5 and M6 using Si transistors provided in the substrate 50. Thus, the area efficiency of the semiconductor device 10B can be improved.

[0253] In addition, the semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device 10B described above. At least a part of the structural examples, working examples, and drawings corresponding to these examples illustrated in this embodiment can be appropriately combined with other structural examples, working examples, other drawings, other embodiments or other examples described in this specification, etc.

[0254] (Implementation 4) In this embodiment, a storage device according to one embodiment of the present invention is described. At least a portion of the semiconductor device 10, the semiconductor device 10A, the semiconductor device 10B, or the storage device 300 described in the above-mentioned Embodiments 1 to 3 can be appropriately used for the storage device described in this embodiment. Therefore, the above description can be appropriately referred to.

[0255] <Storage Device Configuration Example A> Fig.19A and Fig.19B 1 is a schematic diagram for explaining a configuration example of a storage device 370A according to one embodiment of the present invention.

[0256] Note that Fig.19A In the schematic diagram shown, in order to explain the arrangement of the components constituting the storage device 370A, the X direction, the Y direction, and the Z direction are set. The X direction, the Y direction, and the Z direction are each perpendicular or substantially perpendicular to each other. In addition, in order to facilitate understanding of the arrangement of the components constituting the storage device 370A, the components are shown separately.

[0257] The storage device 370A may have one or more memory array sections 371. Note that, as an example, Fig.19AFIG. 4 shows a state where four memory array units 371 are arranged in the X direction in the memory device 370A.

[0258] The memory array section 371 may have one or more memory sections 372. Note that, as an example, Fig.19A 3 shows a state where a plurality of memory units 372 are arranged in the Y direction within the memory array unit 371 .

[0259] Note that the above-mentioned storage device 300 (see Fig. 9A In this case, the semiconductor device 10 described above may be appropriately provided in the memory unit 372 (see Figure 1 )、Semiconductor device 10A (refer to Fig.12 ) or semiconductor device 10B (refer to Fig.15 ) at least a portion of.

[0260] That is, the memory unit 372 uses, for example, Figure 1 The semiconductor device 10 shown in FIG. 5 may include a sense amplifier 55 provided in a substrate 50, a sensor circuit 35 provided in a layer 30 stacked in the Z direction on the substrate 50, and a memory cell 42 provided in each of a plurality of layers (layers 41[1] to 41[m] (m is an integer greater than or equal to 2)) stacked in the Z direction on the layer 30. In other words, in the memory unit 372, in each of the layers 41[1] to 41[m] stacked in the Z direction, a plurality of memory cells 42 are arranged in a matrix in the X direction and the Y direction. Note that, as an example, Fig.19A The case where the layers in which the storage cells 42 are provided are four layers (layer 41 [ 1 ] to layer 41 [ 4 ]) is shown.

[0261] Note that the memory section 372 may or may not be provided with the switching circuit 37 in the layer 30. When the switching circuit 37 is not provided in the memory section 372, for example, Figure 1 In the semiconductor device 10 shown, the global bit line SA_GBL is short-circuited to the global bit line GBL, and the global bit line SA_GBLB is short-circuited to the global bit line GBLB.

[0262] In addition, the sensor circuit 35 may not be provided in the memory section 372. When the sensor circuit 35 is not provided in the memory section 372, for example, Figure 1 In the semiconductor device 10 shown, the global bit line GBL is short-circuited to the local bit line LBL, and the global bit line GBLB is short-circuited to the local bit line LBL_pre.

[0263] In addition, if Fig.19AAs shown, the memory device 370A includes a word line driver section 373, a column driver section 374, a sense amplifier section 375, a sensor circuit driver section 376, a data sense amplifier section 377, and a memory controller section 378 around a memory array section 371. Fig.19A 3 shows a case where four word line driver sections 373, four sense amplifier driver sections 375, four sensor circuit driver sections 376, and four data sense amplifier sections 377 are arranged for each of the four memory array sections 371. Note that, for example, one word line driver section 373, one sense amplifier driver section 375, one sensor circuit driver section 376, and one data sense amplifier section 377 may be arranged for each of the four memory array sections 371.

[0264] The word line driver unit 373 , the column driver unit 374 , the sense amplifier unit 375 , the sensor circuit driver unit 376 , the data sense amplifier unit 377 and the memory controller unit 378 may all be provided on the substrate 50 and may be formed using Si transistors whose channels are formed on the substrate 50 .

[0265] The word line driver unit 373 has a function of selecting any one of the layers 41[1] to 41[m] stacked in the Z direction and any one of the plurality of memory cells 42 arranged in the X direction, and supplying a signal to the word line WL corresponding to the selected memory cell 42. The writing or reading of data to or from the memory cell 42 is controlled by the signal supplied to the word line WL.

[0266] exist Fig.19A In FIG. 1 , a situation where the word line driver section 373 supplies a signal to the word line WL corresponding to the memory cell 42 provided in each of the layers 41 [ 1 ] to 41 [ 4 ] is indicated by a dotted arrow. Fig.19B In FIG. 1 , the word line driver unit 373 supplies a signal to the word line WL corresponding to the memory cell 42 provided in each of the layers 41[1] to 41[4] by attaching symbols of the word lines WL[1] to WL[4] and using solid arrows to indicate that the word line driver unit 373 supplies a signal to the word line WL corresponding to the memory cell 42 provided in each of the layers 41[1] to 41[4]. That is, the word line driver unit 373 selects any one of the layers 41[1] to 41[4] and supplies a signal to any one of the corresponding word lines WL[1] to WL[4]. For example, when the layer 41[1] is selected, the signal can be supplied to the word line WL[1] corresponding thereto. Similarly, when the layer 41[4] is selected, the signal can be supplied to the word line WL[4] corresponding thereto.

[0267] The column driver unit 374 has a function of selecting any one of the plurality of semiconductor devices 10 arranged in the Y direction. For example, the column driver unit 374 can output the signal CSEL in the semiconductor device 10. That is, the column driver unit 374 can select the corresponding semiconductor device 10 by supplying the signal CSEL to any one of the plurality of semiconductor devices 10 arranged in the Y direction.

[0268] The sense amplifier driver section 375 has a function of controlling the operation of the sense amplifier 55. For example, the sense amplifier driver section 375 can output the signal EQ and the signal EQB in the semiconductor device 10. In addition, the sense amplifier driver section 375 can control the potential supplied to the wiring SAP and the wiring SAN.

[0269] The sensor circuit driver section 376 has a function of controlling the operation of the sensor circuit 35. For example, the sensor circuit driver section 376 can output the signal MUX, the signal WE, and the signal RE in the semiconductor device 10. In addition, the sensor circuit driver section 376 can control the potential supplied to the wiring SL.

[0270] The data sense amplifier section 377 has a function of writing or reading data from or to the memory cell 42 selected by the word line driver section 373 or the column driver section 374 .

[0271] The memory controller section 378 has a function of controlling the operations of the word line driver section 373 , the column driver section 374 , the sense amplifier section 375 , the sensor circuit driver section 376 , the data sense amplifier section 377 , and the memory controller section 378 .

[0272] <Storage Device Configuration Example B> Fig. 20A and Fig. 20B 1 is a schematic diagram illustrating a configuration example of a storage device 370B according to one embodiment of the present invention. The storage device 370B is a modified example of the above-mentioned storage device 370A. Therefore, in order to reduce repeated descriptions, the differences between the storage device 370B and the storage device 370A are mainly described. Note that the description of the above-mentioned storage device 370A can be appropriately referred to.

[0273] In addition to the structure of the above-described storage device 370A, the storage device 370B is provided with each of the layer selection driver sections 373L[1] to 373L[m] in each of the layers 41[1] to 41[m]. Each of the layer selection driver sections 373L[1] to 373L[m] is arranged so as to overlap in the Z direction on the word line driver section 373. Note that, as an example, in Fig. 20A and Fig. 20B2 shows a case where each of the layer selection driver units 373L[1] to 373L[4] is provided in each of the layers 41[1] to 41[4].

[0274] The word line driver unit 373 has the function of selecting any one of the layers 41[1] to 41[m] stacked in the Z direction and any one of the multiple memory cells 42 arranged in the X direction through the layer selection driver unit 373L[1] to the layer selection driver unit 373L[m], and supplying a signal to the word line WL corresponding to the selected memory cell 42.

[0275] That is, a signal for selecting any one of the plurality of memory cells 42 arranged in the X direction is output from the word line driver section 373 and input to each of the layer selection driver section 373L[1] to the layer selection driver section 373L[m]. And, the signal is output from any one of the layer selection driver section 373L[1] to the layer selection driver section 373L[m].

[0276] exist Fig. 20A In FIG. 1 , a solid arrow is used to indicate that the word line driver unit 373 supplies a signal to each of the layer selection driver units 373L[1] to 373L[4] provided in each of the layers 41[1] to 41[4]. Fig. 20B In FIG. 1 , the symbols of the word lines WLout[1] to WLout[4] are attached and the solid arrows are used to indicate that each of the layer selection driver sections 373L[1] to 373L[4] supplies a signal to the word line WL of the memory cell 42 provided in each of the layers 41[1] to 41[4]. That is, the word line driver section 373 can supply a signal to any one of the word lines WLout[1] to WLout[4] through any one of the layer selection driver sections 373L[1] to 373L[4] provided in each of the layers 41[1] to 41[4].

[0277] [Layer selection driver] Fig.21A 2 is a circuit diagram illustrating a configuration example of the layer selection driver 373Lbuf. The layer selection driver sections 373L[1] to 373L[m] each have one or more layer selection drivers 373Lbuf.

[0278] The layer selection driver 373Lbuf includes a transistor ML1, a transistor ML2, a transistor ML3 and a capacitor CL1. The transistors ML1 to ML3 are all OS transistors.

[0279] The gate of transistor ML2 is electrically connected to one of the source and drain of transistor ML1 and one terminal of capacitor CL1. One of the source and drain of transistor ML2 is electrically connected to one of the source and drain of transistor ML3, the other terminal of capacitor CL1 and word line WLout. The other of the source and drain of transistor ML2 is electrically connected to word line WLin. The gate of transistor ML1 is electrically connected to a wiring supplied with potential VLD. The other of the source and drain of transistor ML1 is electrically connected to a wiring supplied with signal LSEL. The gate of transistor ML3 is electrically connected to a wiring supplied with signal LSELB. The other of the source and drain of transistor ML3 is electrically connected to a wiring supplied with potential VLS. Note that the region where the gate of transistor ML2, one of the source and drain of transistor ML1 and one terminal of capacitor CL1 are electrically connected is sometimes referred to as node BL1.

[0280] Note that the structure of the layer selection driver 373Lbuf is not limited to Fig.21A The structure example shown. For example, the other terminal of the capacitor CL1 may be electrically connected to the other of the source and drain of the transistor ML2. Alternatively, for example, the layer selection driver 373Lbuf may not include the capacitor CL1. In this case, the parasitic capacitance between the gate of the transistor ML2 and one of the source and drain may be used as the capacitor CL1.

[0281] The layer selection driver 373Lbuf may have a function of outputting any one of the signal or the potential VLS supplied to the word line WLin to the word line WLout according to the signal LSEL and the signal LSELB.

[0282] Fig. 21B 373 is a timing chart illustrating an example of the operation of the layer selection driver 373Lbuf.

[0283] Fig. 21B The timing chart shows the potentials (H level or L level) of the signal LSEL, the signal LSELB, and the signal supplied to the word line WLin at each operation time, and also shows the potential changes of the node B1 and the word line WLout.

[0284] Note that in the following description of the operation example, the potential VLD is set to the same potential as the H level of the signal LSEL and the signal LSELB. Also, the potential VLS is set to the same potential as the L level of the signal LSEL and the signal LSELB.

[0285] Just before entering time TL1, the signal LSEL is set to L level and the signal LSELB is set to H level. At this time, since the transistor ML1 is in the on state, the potential of the node BL1 becomes L level. Therefore, the transistor ML2 is in the non-conducting state and the transistor ML3 is in the on state. Therefore, regardless of whether the signal supplied to the word line WLin is H level or L level, the potential of the word line WLout becomes L level (potential VLS).

[0286] At time TL1, the signal LSEL becomes H level, and the signal LSELB becomes L level. At this time, the potential of the node BL1 rises to a potential obtained by subtracting the threshold voltage of the transistor ML1 from the H level (potential VLD), and the transistor ML1 becomes non-conductive. As a result, the transistor ML2 becomes conductive, and the transistor ML3 becomes non-conductive. Therefore, the potential of the word line WLout becomes L level (signal supplied to the word line WLin at time TL1).

[0287] At time TL2, the signal supplied to the word line WLin becomes H level. As a result, the current flows from the word line Wlin to the word line WLout through the transistor ML2, and the potential of the word line WLout rises. At this time, because the transistor ML1 is in a non-conductive state, the potential of the node BL1 also rises due to the capacitive coupling of the capacitor CL1. Therefore, the potential difference between the gate and the source of the transistor ML2 is maintained, that is, the conductive state of the transistor ML2 is maintained. As a result, the potential of the word line WLout becomes H level (at time TL2, the signal supplied to the word line WLin).

[0288] In this way, in the layer selection driver 373Lbuf, by configuring a bootstrap circuit in which the capacitor CL1 is provided between the gate and source of the transistor ML2, when the signal supplied to the word line WLin becomes an H level, the on state of the transistor ML2 is maintained, and an H level can be output to the word line WLout. Note that the capacitor CL1 is sometimes referred to as a "bootstrap capacitor".

[0289] The storage device 370B can select any one of the layer selection driver units 373L[1] to the layer selection driver unit 373L[m] and output the signal supplied to the word line WLin to the word line WLout by controlling the signal LSEL and the signal LSELB supplied to the layer selection driver 373Lbuf respectively possessed by the layer selection driver unit 373L[1] to the layer selection driver unit 373L[m].

[0290] For example, by making the signal LSEL and the signal LSELB supplied to the layer selection driver 373Lbuf included in the layer selection driver unit 373L[1] respectively at the H level and the signal LSELB supplied to the layer selection driver 373Lbuf included in the layer selection driver unit 373L[2] to the layer selection driver unit 373L[m] respectively at the L level and the H level, the signal supplied from the word line driver unit 373 to the word line WLin is output to the word line WLout[1] through the layer selection driver 373Lbuf included in the layer selection driver unit 373L[1].

[0291] The storage device 370B has superior effects to the storage device 370A in, for example, the following aspects.

[0292] In the memory device 370A, m word lines need to be provided from the substrate 50 to the layers 41[1] to 41[m], respectively. However, in the memory device 370B, only one word line needs to be provided from the substrate 50 to the layers 41[1] to 41[m]. In addition, in the memory device 370A, m buffers need to be provided in the substrate 50 in order to supply signals to each of the m word lines. However, in the memory device 370B, only buffers need to be provided in each of the layer selection driver units 373L[1] to 373L[m], respectively, of the layers 41[1] to 41[m]. For example, in the layer selection driver 373Lbuf of each of the layer selection driver units 373L[1] to 373L[m], the transistors ML2 and ML3 may have a buffering function.

[0293] Therefore, the memory device 370B can suppress the increase in the area of ​​the word line driver section 373 caused by increasing the number of layers 41[1] to 41[m] in which the memory cells 42 are provided. That is, the memory device 370B can increase the number of layers 41[1] to 41[m] in which the memory cells 42 are provided without increasing the area cost. In other words, the memory device 370B can increase the density (storage density) of the memory cells 42 without increasing the area cost.

[0294] <Structure example of storage unit> A storage device according to one embodiment of the present invention may include storage cells having various structures.

[0295] FIG. 22A to FIG. 22E 1 is a diagram for explaining a configuration example of a circuit that can be adopted in the memory cell 42 of the memory device that can be applied to one embodiment of the present invention.

[0296] Fig.22AThe memory cell 42a shown includes a transistor Ma and a capacitor Ca. One of the source and drain of the transistor Ma is electrically connected to one terminal of the capacitor Ca. The other of the source and drain of the transistor Ma is electrically connected to the bit line BL. The gate of the transistor Ma is electrically connected to the word line WL. The other terminal of the capacitor Ca is electrically connected to the wiring CSL. The transistor Ma is an OS transistor. The OS transistor has a characteristic of extremely low off-state current. Therefore, by making the transistor Ma in a non-conducting state, the charge corresponding to the data can be maintained in the charge holding node FN. Therefore, the refresh rate of the data corresponding to the charge maintained in the charge holding node FN can be reduced.

[0297] Fig. 22B The storage unit 42b shown is Fig.22A A modified example of the storage unit 42a is shown. Fig. 22B and Fig.22A The difference between the transistor Ma of the embodiment of the present invention is that the former includes a back gate, and the potential of the word line WL is applied from both the back gate and the gate by electrically connecting the back gate to the gate. By adopting this structure, the amount of current flowing between the source and the drain when the transistor Ma is turned on can be increased.

[0298] Fig. 22C The storage unit 42c shown is Fig.22A A modified example of the storage unit 42a is shown. Fig. 22C and Fig.22A The difference between the transistor Ma of the embodiment of the present invention is that the former includes a back gate, and a potential different from that of the gate is applied to the back gate by electrically connecting the back gate to the back gate line BGL. By adopting the above structure, the threshold voltage of the transistor Ma can be controlled. Therefore, the amount of current flowing between the source and the drain of the transistor Ma can be changed.

[0299] Fig.22D The memory cell 42d shown includes a transistor Ma, a transistor Mb, and a capacitor Ca. One of the source and the drain of the transistor Ma is electrically connected to the gate of the transistor Mb and one terminal of the capacitor Ca. The other of the source and the drain of the transistor Ma is electrically connected to the bit line WBL for writing. The gate of the transistor Ma is electrically connected to the word line WWL for writing. The other terminal of the capacitor Ca is electrically connected to the word line RWL for reading. One of the source and the drain of the transistor Mb is electrically connected to the bit line RBL for reading. The other of the source and the drain of the transistor Mb is electrically connected to the wiring SL. Although an n-channel transistor is used as the transistor Mb in the drawings, a p-channel transistor may also be used. By making the transistor Ma non-conductive, the charge corresponding to the data can be maintained in the charge holding node FN. The transistor Mb is an OS transistor. In addition, the transistor Mb may also be a Si transistor. Note that the transistor Ma may adopt the same configuration as described above. Fig. 22B or Fig. 22C The transistor Ma shown has the same structure.

[0300] Fig.22E The memory cell 42e shown includes a transistor Ma, a transistor Mb, a transistor Mc, and a capacitor Ca. One of the source and drain of the transistor Ma is electrically connected to the gate of the transistor Mb and one terminal of the capacitor Ca. The other of the source and drain of the transistor Ma is electrically connected to the bit line WBL for writing. The gate of the transistor Ma is electrically connected to the word line WWL for writing. The other terminal of the capacitor Ca is electrically connected to the wiring CSL. One of the source and drain of the transistor Mb is electrically connected to one of the source and drain of the transistor Mc. The other of the source and drain of the transistor Mb is electrically connected to the wiring SL. The gate of the transistor Mc is electrically connected to the word line RWL for reading. The other of the source and drain of the transistor Mc is electrically connected to the bit line RBL for reading. Although an n-channel transistor is used as the transistor Mc in the drawings, a p-channel transistor may also be used. By making the transistor Ma non-conductive, the charge corresponding to the data can be maintained in the charge holding node FN. The transistor Mb and the transistor Mc are both OS transistors. Note that at least one of the transistor Mb and the transistor Mc may be a Si transistor. Note that the transistor Ma may be a Si transistor similar to the above-mentioned Fig. 22B or Fig. 22C The transistor Ma shown has the same structure.

[0301] in addition, FIG. 22A to FIG. 22C The structure of the memory cell shown is called DOSRAM (registered trademark). DOSRAM is the abbreviation of Dynamic Oxide Semiconductor RAM (Random Access Memory). The structure using DOSRAM can maintain the charge stored in one terminal of the capacitor when the OS transistor is in a non-conductive state by electrically connecting one of the source and drain of the OS transistor to one terminal of the capacitor. The structure using DOSRAM is particularly effective when the amount of stored data increases. For example, compared with the case where the memory cell of the memory circuit is composed of SRAM (Static RAM), DOSRAM can suppress the increase in circuit area. In particular, FIG. 22A to FIG. 22C The structure of the memory cell shown is effective from the viewpoint of suppressing an increase in circuit area.

[0302] Fig.22D and Fig.22EThe structure of the memory cell shown is called NOSRAM (registered trademark). NOSRAM is the abbreviation of Nonvolatile Oxide SemiconductorRAM. The structure using NOSRAM can maintain the charge stored in the gate of the read transistor when the OS transistor for writing is in a non-conductive state by electrically connecting one of the source and drain of the OS transistor for writing to the gate of the read transistor. The structure using NOSRAM can be used as a non-volatile memory. For example, NOSRAM can continuously store data even in a power-gated state by making the OS transistor for writing in a non-conductive state.

[0303] Notice, FIG. 22A to FIG. 22E The circuit configuration shown is merely an example, and any configuration may be employed as long as one embodiment of the present invention can be implemented.

[0304] <Layout Example> Fig.23A and Fig. 23B FIG. 1 is a plan layout diagram illustrating a configuration example of a storage device according to one embodiment of the present invention.

[0305] exist Fig.23A In the planar layout diagram shown, as an example, a module 381 is provided in a chip 380 having a 4 mm corner. The module 381 may include, for example, a storage device 370A or a storage device 370B. An interface for exchanging signals between the module 381 and the outside of the chip 380 is provided around the module 381. The interface is, for example, I2C (Inter-Integrated Circuit) or LVDS (Low voltage differential signaling).

[0306] exist Fig. 23B In the planar layout diagram shown, as an example of a module 381 including a memory device 370A or a memory device 370B, a region 382, ​​a region 383, a region 384, a region 385, and a region 386 are arranged in the module 381. In the region 382, ​​for example, a memory array section 371 including a memory cell 42, a sensor circuit 35, and a sense amplifier 55 is arranged. In the region 383, for example, a word line driver section 373, a sense amplifier driver section 375, and a sense circuit driver section 376 are arranged. In addition, a layer selection driver 373Lbuf is arranged in the region 383 of the memory device 370B. A column driver section 374 is arranged in the region 384. A data sense amplifier section 377 is arranged in the region 385. A memory controller section 378 is arranged in the region 386.

[0307] The memory device 370A or the memory device 370B can stack a plurality of memory cells 42 in the region 382. Therefore, the memory device 370A or the memory device 370B can increase the density of the memory cells 42 (storage density).

[0308] The storage device according to one embodiment of the present invention is not limited to the above-mentioned storage device 370A and storage device 370B. At least a part of the structural examples, working examples, and drawings corresponding to these examples illustrated in this embodiment can be appropriately combined with other structural examples, working examples, other drawings, other embodiments or other embodiments illustrated in this specification, etc.

[0309] (Implementation 5) In this embodiment, an example of a semiconductor device which is one embodiment of the present invention is described with reference to Fig. 24. The semiconductor device which is one embodiment of the present invention includes a transistor and a capacitor.

[0310] Note that the semiconductor device described in this embodiment can be used as appropriate for the memory cell 42 described in Embodiment 1. That is, the transistor and the capacitor included in the semiconductor device correspond to the transistor 43 and the capacitor 44 included in the memory cell 42, respectively.

[0311] The structure of a semiconductor device including a transistor and a capacitor will be described with reference to FIG. 24 . FIG. 24A to FIG. 24D 1 and 2 are a top view and a cross-sectional view of a semiconductor device including a transistor 200 a , a transistor 200 b , a capacitor 100 a , and a capacitor 100 b . Fig.24A is a top view of the semiconductor device. FIG. 24B to FIG. 24D is a cross-sectional view of the semiconductor device. Fig. 24B It is along Fig.24A The cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. 1 is also a cross-sectional view of the transistor 200a, the transistor 200b, the capacitor 100a, and the capacitor 100b in the channel length direction. Fig.24C It is along Fig.24A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. 1 is also a cross-sectional view of the transistor 200a in the channel width direction. Fig.24D It is along Fig.24A The cross-sectional view of the portion along the dotted line A5-A6 in FIG. 1 is also a cross-sectional view of the capacitor 100a in the channel width direction. Fig.24A In the top view, some components are omitted for clarity.

[0312] in addition, Fig.24A The X direction shown is parallel to the channel length direction of transistor 200a and the channel length direction of transistor 200b, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X direction and the Y direction. FIG. 24B to FIG. 24DIt is also shown in Fig.24A The X direction, Y direction and Z direction are shown.

[0313] A semiconductor device according to one embodiment of the present invention includes an insulator 214 on a substrate (not shown), a transistor 200a, a transistor 200b, a capacitor 100a, and a capacitor 100b on the insulator 214, an insulator 280 on an insulator 275 provided in the transistor 200a and the transistor 200b, an insulator 282 on the insulator 280, an insulator 285 on the capacitor 100a, the capacitor 100b, and the insulator 282, and a conductor 240 (conductor 240a and conductor 240b). The insulator 214, the insulator 280, the insulator 282, and the insulator 285 are used as interlayer films. Fig. 24B As shown, the transistor 200 a , the transistor 200 b , the capacitor 100 a , and the capacitor 100 b are configured in such a way that at least a portion of them is embedded in the insulator 280 .

[0314] Here, both transistor 200a and transistor 200b include oxide 230 used as a semiconductor layer, conductor 260 used as a first gate (also called top gate) electrode, conductor 205 used as a second gate (also called back gate) electrode, conductor 242b used as one of the source electrode and the drain electrode, and conductor 242a used as the other of the source electrode and the drain electrode. In addition, insulator 253 and insulator 254 used as a first gate insulator are included. In addition, insulator 222 and insulator 224 used as a second gate insulator are included. In addition, the gate insulator is sometimes referred to as a gate insulating layer or a gate insulating film.

[0315] Note that the insulator 282 and the insulator 222 preferably have a function of capturing or fixing hydrogen. Thus, for example, hydrogen contained in the insulator 280, the insulator 224, the insulator 253, and the insulator 254 is captured or fixed in the insulator 282 or the insulator 222.

[0316] Note that the transistor 200 a and the transistor 200 b have the same structure, and therefore, when describing the common contents between the transistor 200 a and the transistor 200 b hereinafter, the reference numerals are omitted and the transistor 200 is described as the transistor 200 .

[0317] The first gate electrode and the first gate insulating film are arranged in the opening 258 formed in the insulator 280 and the insulator 275. In other words, the conductor 260, the insulator 254, and the insulator 253 are arranged in the opening 258.

[0318] The capacitor 100a and the capacitor 100b both include a conductor 156 serving as a lower electrode, an insulator 153 serving as a dielectric, and a conductor 160 serving as an upper electrode. In other words, the capacitor 100a and the capacitor 100b both constitute MIM (Metal-Insulator-Metal) capacitors.

[0319] Note that capacitor 100 a and capacitor 100 b have the same structure, and therefore, when describing the common contents between capacitor 100 a and capacitor 100 b below, the reference numerals are omitted and capacitor 100 is described.

[0320] The upper electrode, dielectric and a portion of the lower electrode of the capacitor 100 are disposed in the opening 158 formed in the insulators 282 , 280 and 275 . In other words, the conductor 160 , the insulator 153 and the conductor 156 are disposed in the opening 158 .

[0321] The semiconductor device of one embodiment of the present invention includes a conductor 240 (conductor 240a and conductor 240b) which is used as a plug (may also be referred to as a connection electrode) by being electrically connected to the transistor 200. The conductor 240 is, for example, arranged in the opening 206 formed in the insulator 280 or the like. The conductor 240 has a region in contact with a portion of the top surface and a portion of the side surface of the conductor 242a.

[0322] The semiconductor device of one embodiment of the present invention includes an insulator 210 and a conductor 209 between a substrate (not shown) and an insulator 214. The conductor 209 is disposed so as to be embedded in the insulator 210. The conductor 209 has a region in contact with the conductor 240.

[0323] Furthermore, the semiconductor device according to one embodiment of the present invention may include the insulator 210 and an insulator 212 between the conductor 209 and the insulator 214 .

[0324] The semiconductor device including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device. In this case, the conductor 240 is sometimes electrically connected to a sense amplifier, and the conductor 240 is used as a bit line. Fig.24A As shown, the capacitor 100 is provided so that at least a portion thereof overlaps with the conductor 242b in the transistor 200. Therefore, the capacitor 100 can be provided without significantly increasing the occupied area when viewed from a plane, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated.

[0325] Note that the semiconductor device described in this embodiment can be used as appropriate for the semiconductor device 10 or the memory device 300 described in Embodiment 1. That is, the transistor 200, the capacitor 100, and the conductor 240 included in the semiconductor device correspond to the transistor 43, the capacitor 44, and the local bit line LBL, respectively. In addition, the sense amplifier electrically connected to the conductor 240 corresponds to the sensor circuit 35.

[0326] The semiconductor device described in this embodiment has Fig.24A The dotted line A7-A8 shown is an axisymmetric structure with an axis of symmetry. In other words, it can be said that the transistor 200b is configured at a position symmetrical to the transistor 200a with the conductor 240 as the axis of symmetry. In addition, it can be said that the capacitor 100b is configured at a position symmetrical to the capacitor 100a with the conductor 240 as the axis of symmetry. Here, the conductor 242a of the semiconductor device shown in this embodiment also serves as the other of the source electrode and the drain electrode of the transistor 200a and the other of the source electrode and the drain electrode of the transistor 200b. In addition, the transistor 200a and the transistor 200b also serve as the conductor 240 of the plug. In this way, by adopting the above structure as the connection relationship between the two transistors, the two capacitors and the plug, the semiconductor device shown in one embodiment of the present invention can be miniaturized or highly integrated.

[0327] 〔Transistor 200〕 like FIG. 24A to FIG. 24C As shown, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) arranged in a manner of being embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and a conductor 242a (conductor 242a1 and conductor 242a2) on the oxide 230b. and conductor 242b (conductor 242b1 and conductor 242b2), insulator 253 on oxide 230b, insulator 254 on insulator 253, conductor 260 (conductor 260a and conductor 260b) located on insulator 254 and overlapping with a portion of oxide 230b, and insulator 275 arranged on insulator 222, on insulator 224, on oxide 230a, on oxide 230b, on conductor 242a, and on conductor 242b.

[0328] Note that in this specification and the like, the oxide 230 a and the oxide 230 b may be collectively referred to as the oxide 230 . Also, the conductor 242 a and the conductor 242 b may be collectively referred to as the conductor 242 .

[0329] An opening 258 that reaches the oxide 230b is provided in the insulator 280 and the insulator 275. That is, the opening 258 can be said to have a region overlapping with the oxide 230b. In addition, the insulator 275 can be said to have an opening that overlaps with the opening included in the insulator 280. That is, the opening 258 has an opening in the insulator 280 and an opening in the insulator 275. In addition, the insulator 253, the insulator 254, and the conductor 260 are provided in the opening 258. That is, the conductor 260 has a region overlapping with the oxide 230b via the insulator 253 and the insulator 254. In addition, in the channel length direction of the transistor 200, the conductor 260, the insulator 253, and the insulator 254 are provided between the conductor 242a and the conductor 242b. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. Note that, as Fig.24C As shown, the top surface of insulator 222 is exposed in the area of ​​opening 258 that does not overlap oxide 230 .

[0330] Note that a material having a high ability to capture or fix hydrogen, such as aluminum oxide, is preferably used as the insulator 253, and a material having a high hydrogen barrier property, such as silicon nitride, is preferably used as the insulator 254. This can prevent impurities such as water and hydrogen from diffusing into the oxide 230.

[0331] The oxide 230 preferably includes an oxide 230a on the insulator 224 and an oxide 230b on the oxide 230a. When the oxide 230a is provided below the oxide 230b, diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b can be suppressed.

[0332] Note that in transistor 200, oxide 230 has a two-layer stacked structure of oxide 230a and oxide 230b, but one embodiment of the present invention is not limited to this. For example, oxide 230 may have a single-layer structure of oxide 230b. Alternatively, it may have a stacked structure of three or more layers. Alternatively, it may have a structure in which oxide 230a and oxide 230b each have a stacked structure.

[0333] As an example of the stacked structure, a three-layer stacked structure can be cited, in which a semiconductor layer having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used as the first layer, a semiconductor layer having an atomic ratio of metal elements of In:Zn=4:1 is used as the second layer, and a semiconductor layer having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used as the third layer. In addition, the band gap of the semiconductor layer of the first layer and the third layer is preferably larger than the band gap of the semiconductor layer of the second layer. By adopting this structure, the semiconductor layer of the second layer can be used as the main current path, so the so-called buried channel structure can be realized.

[0334] The conductor 260 is used as a first gate electrode, and the conductor 205 is used as a second gate electrode. In addition, the insulators 253 and 254 are used as first gate insulators, and the insulators 222 and 224 are used as second gate insulators. In addition, the conductor 242b is used as one of the source electrode and the drain electrode, and the conductor 242a is used as the other of the source electrode and the drain electrode. In addition, at least a portion of the region of the oxide 230 that overlaps with the conductor 260 is used as a channel formation region.

[0335] 〔Capacitor 100〕 like Fig.24A , Fig. 24B and Fig.24D As shown, capacitor 100 includes conductor 156, insulator 153 and conductor 160 (conductor 160a and conductor 160b). Conductor 156 is used as one of a pair of electrodes of capacitor 100 (also called lower electrode), conductor 160 is used as the other of a pair of electrodes of capacitor 100 (also called upper electrode), and insulator 153 is used as the dielectric of capacitor 100.

[0336] At least a portion of the conductor 156, the insulator 153, the conductor 160a, and the conductor 160b are disposed in the opening 158 provided in the insulators 275, 280, and 282. The conductor 156 is provided on the conductor 242b, the insulator 153 is provided on the conductor 156, the conductor 160a is provided on the insulator 153, and the conductor 160b is provided on the conductor 160a.

[0337] The conductor 156 is arranged along the opening 158 formed in the insulator 275, the insulator 280, and the insulator 282. The height of a portion of the top surface of the conductor 156 is preferably higher than the height of the top surface of the insulator 282. In addition, the bottom surface of the conductor 156 is in contact with the top surface of the conductor 242b. The conductor 156 is preferably deposited by a deposition method with good coverage, such as the ALD method or the CVD method. The conductor 156 can use a conductor that can be used for the conductor 205, the conductor 260, or the conductor 242. For example, by using the same conductive material as the conductor 242b as the conductor 156, the contact resistance between the conductor 156 and the conductor 242b can be reduced. For example, titanium nitride or tantalum nitride deposited by the ALD method can be used as the conductor 156.

[0338] The insulator 153 is arranged to cover the conductor 156 and a part of the insulator 282. A high-k material (a material with a high relative dielectric constant) is preferably used for the insulator 153. The insulator 153 is preferably deposited by a deposition method with high coverage, such as ALD or CVD.

[0339] As an insulator of a high dielectric constant material, for example, an oxide, an oxynitride, an oxynitride or a nitride containing one or more metal elements selected from aluminum, hafnium, zirconium and gallium can be used. In addition, the above oxide, oxynitride, oxynitride or nitride can also contain silicon. In addition, as an insulator of a high dielectric constant material, an insulating layer formed of the above materials can also be stacked and used.

[0340] In addition, for example, as an insulator of a high dielectric constant material, aluminum oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, an oxide containing silicon and zirconium, an oxynitride containing silicon and zirconium, an oxide containing hafnium and zirconium, or an oxynitride containing hafnium and zirconium, etc. can be used. By using such a high dielectric constant material, the insulator 153 can be thickened to a degree that can suppress leakage current and the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0341] In addition, it is preferred to stack an insulating layer formed by the above-mentioned materials, and it is preferred to use a laminated structure of a high dielectric constant material and a material whose dielectric strength is greater than that of the high dielectric constant material. For example, as the insulator 153, an insulating film of zirconium oxide, aluminum oxide and zirconium oxide can be used in sequence. In addition, for example, an insulating film of zirconium oxide, aluminum oxide, zirconium oxide and aluminum oxide can be used in sequence. In addition, for example, an insulating film of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide and aluminum oxide can be used in sequence. By using a laminate of an insulator with a larger dielectric strength such as aluminum oxide as the insulator 153, the dielectric strength is improved, and thus the electrostatic destruction of the capacitor 100 can be suppressed.

[0342] The conductor 160 is arranged so as to be embedded in the opening 158 formed in the insulator 275, the insulator 280, and the insulator 282. The conductor 160 is preferably deposited by, for example, the ALD method or the CVD method. The conductor 160 can use a conductor that can be used for the conductor 205 or the conductor 260. For example, as the conductor 160a, titanium nitride deposited by the ALD method can be used, and as the conductor 160b, tungsten deposited by the CVD method can be used. In addition, when the adhesion of tungsten to the insulator 153 is sufficiently high, a single layer of tungsten deposited by the CVD method can also be used as the conductor 160.

[0343] The opening 158 is provided so as to reach the conductor 242 b. In other words, it can be said that the opening 158 has a region overlapping with the conductor 242 b. The conductor 242 b is one of the source electrode and the drain electrode of the transistor 200, and by contacting the bottom surface of the conductor 156 provided in the opening 158, the transistor 200 and the capacitor 100 can be electrically connected.

[0344] Preferably, the distance between the opening 158 and the oxide 230 is close when viewed from a plane. By adopting such a structure, the occupied area of ​​the memory cell including the capacitor 100 and the transistor 200 can be reduced. In addition, the shape of the opening 158 when viewed from a plane can be a quadrangle, a polygon other than a quadrangle, a polygon with curved corners, or a circular shape including an ellipse.

[0345] like Fig. 24B and Fig.24D As shown, the conductor 156 is provided in contact with the bottom surface and inner wall of the opening 158. Therefore, the conductor 156 is in contact with the side surfaces of the insulators 275, 280, and 282, the side surfaces of the conductor 242b1, the side surfaces and the top surface of the conductor 242b2, and the top surface of the insulator 222. In addition, the insulator 153 is provided in contact with the top surface of the conductor 156, the conductor 160a is provided in contact with the top surface of the insulator 153, and the conductor 160b is provided in contact with the top surface of the conductor 160a.

[0346] By making the capacitor 100 have the above structure, as Fig. 24B and Fig.24D As shown, the capacitor 100 can be formed on the bottom and side surfaces of the opening 158 so that the conductor 156 and the conductor 160 are opposite to each other via the insulator 153. Therefore, by deepening the depth of the opening 158 (or the thickness of the insulator 280), the electrostatic capacitance of the capacitor 100 can be increased. In this way, by increasing the electrostatic capacitance of the capacitor 100 per unit area, the read operation of the storage device can be stabilized.

[0347] like Fig. 24B As shown, a portion of the conductor 156, a portion of the insulator 153, and a portion of the conductor 160 are disposed so as to be exposed from the opening 158. In other words, a portion of the conductor 156, a portion of the insulator 153, and a portion of the conductor 160 are formed above the top surface of the conductor 260 or above the top surface of the insulator 282.

[0348] Part of the conductor 156 and part of the insulator 153 are in contact with the top surface of the insulator 282. That is, the side end of the conductor 156 is covered by the insulator 153. Furthermore, the conductor 160 preferably has a region overlapping with the insulator 282 via the insulator 153. Fig. 24B As shown, the side end of the conductor 160 is substantially aligned with the side end of the insulator 153. By adopting this structure, the conductor 160 and the conductor 156 can be separated by the insulator 153, so the short circuit between the conductor 160 and the conductor 156 can be suppressed.

[0349] Alternatively, the portion of the conductor 160 above the insulator 282 may be routed in a wiring pattern. Fig.24C As shown in FIG. 1 , the conductor 160 may be extended in the channel width direction of the transistor 200. Thus, when a plurality of transistors 200 and capacitors 100 are provided, the conductor 160 may be used as wiring. In this case, the insulator 153 may be extended together with the conductor 160.

[0350] Fig.32 Yes Description Fig. 24B The semiconductor device shown in FIG. 1 is a cross-sectional view of another structural example of a transistor 200a and a capacitor 100a. Fig.32 The semiconductor device shown is Fig. 24B The semiconductor devices shown are different.

[0351] Fig.32 The semiconductor device shown is Fig. 24B The semiconductor device shown is different in that the former is formed so that the side ends of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a1, and the conductor 242a2 are substantially aligned.

[0352] In addition, if Fig.32 The semiconductor device shown in FIG. 24 further includes an insulator 271 a , an insulator 271 b , an insulator 255 , an insulator 241 , an insulator 221 , an insulator 283 , and an insulator 284 .

[0353] like Fig.32 As shown, an insulator 271a is provided between the conductor 242a2 and the insulator 275. In addition, an insulator 271b is provided between the conductor 242b2 and the insulator 275. Here, the insulators 271a and 271b preferably have the function of an etching stop layer to protect the conductor 242a2 and the conductor 242b2 when the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a1, the conductor 242a2, the insulator 271a, and the insulator 271b are processed at one time.

[0354] In addition, if Fig.32As shown, in the opening 258, the insulator 255 is provided between the insulator 253 and the conductors 242a2, 242b2, the insulators 271a, 271b, 275, and 280 and in contact with a portion of the top surface of the conductor 242a1 and a portion of the top surface of the conductor 242b1. In other words, it can be said that the insulator 255 is formed in a side wall shape so as to be in contact with the side wall of the opening 258. Here, when the conductors 242a1 and 242b1 are separated and heat treated in an atmosphere containing oxygen, the insulator 255 preferably has a protective film function to prevent the conductors 242a2 and 242b2 from being excessively oxidized.

[0355] In addition, if Fig.32 As shown in FIG. 2 , an insulator 221 is provided in contact with the bottom surface of the insulator 222. In addition, an insulator 283 is provided in contact with the top surface of the insulator 282. Here, the insulator 221 preferably has a function of suppressing impurities such as water or hydrogen from diffusing from an interlayer insulating film arranged below the insulator 221 to the transistor 200a. In addition, the insulator 283 preferably has a function of suppressing impurities such as water or hydrogen from diffusing from an interlayer insulating film arranged above the insulator 283 to the transistor 200a.

[0356] In addition, if Fig.32 The insulator 284 shown is disposed between the insulator 283 and the insulator 285. Here, the insulator 284 has a function of changing the electrostatic capacitance of the capacitor 100a according to the thickness. That is, the capacitor 100a can increase the electrostatic capacitance of the capacitor 100a by deepening the depth of the opening 158 (for example, increasing the thickness of the insulator 284).

[0357] In addition, if Fig.32 As shown, an insulator 241 is provided in a manner of contacting the side surface of the conductor 240. Specifically, the insulator 241 is provided in a manner of contacting the openings (equivalent to the openings of the insulators 216, 221, 222, 275, 280, 282, 283, 284, and 285) of the insulators 216, 221, 222, 275, 280, 282, 283, 284, and 285. Fig. 24B In addition, the insulator 241 formed in a protruding manner in the opening is also formed on the side of the insulator 224, the oxide 230 and the conductor 242a. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and contacts the conductor 240. In other words, the conductor 240 is formed in a manner embedded in the above-mentioned opening via the insulator 241.

[0358] The uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the top surface of the conductor 242a. By adopting this structure, the conductor 240 can be in contact with at least a portion of the side end portion of the conductor 242a. In addition, the insulator 241 formed below the conductor 242a preferably has a region in contact with the side surface of the oxide 230. By adopting this structure, for example, impurities such as water or hydrogen contained in the insulator 280 can be suppressed from mixing into the oxide 230 through the conductor 240. In addition, the insulator 241 may also have a stacked structure of two or more layers.

[0359] Note that the semiconductor device of one embodiment of the present invention can be formed by appropriately combining Fig. 24B The semiconductor device and Fig.32 The structure of the semiconductor device shown.

[0360] At least a part of the structure or method described in the above-mentioned embodiment can be implemented in combination with other embodiment or other examples described in this specification etc. as appropriate.

[0361] (Implementation 6) In this embodiment, refer to Fig.25A and Fig.25B An example of a chip 1200 on which the semiconductor device of the present invention is mounted will be described. A plurality of circuits (systems) are mounted on the chip 1200. In this way, a technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC).

[0362] like Fig.25A As shown, the chip 1200 includes, for example, a CPU 1211, a GPU 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, and one or more network circuits 1216.

[0363] Bumps (not shown) are provided on the chip 1200. Fig.25B As shown in the figure, the first surface of the package substrate 1201 is connected to the package substrate 1201 through the bumps. In addition, a plurality of bumps 1202 are provided on the back of the first surface of the package substrate 1201, and the package substrate 1201 is connected to the motherboard 1203 through the plurality of bumps 1202.

[0364] For example, a storage device such as DRAM 1221 or flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM described in the above embodiment may be applied to DRAM 1221. Thus, low power consumption, high speed, and large capacity of DRAM 1221 can be achieved.

[0365] CPU1211 preferably has a plurality of CPU cores. In addition, GPU1212 preferably has a plurality of GPU cores. In addition, CPU1211 and GPU1212 may each have a memory for temporarily storing data. Alternatively, a memory commonly used by CPU1211 and GPU1212 may be provided on chip 1200. The above-mentioned DOSRAM may be applied to the memory. In addition, GPU1212 is suitable for parallel calculation of a plurality of data, and it may perform image processing or product-sum operation. By providing an image processing circuit or product-sum operation circuit using the oxide semiconductor of the present invention as GPU1212, image processing or product-sum operation can be performed with low power consumption.

[0366] Furthermore, since the CPU 1211 and the GPU 1212 are provided on the same chip, the chip can shorten the wiring between the CPU 1211 and the GPU 1212. Therefore, the chip can perform data transfer from the CPU 1211 to the GPU 1212, data transfer between memories of the CPU 1211 and the GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 at high speed after the calculation in the GPU 1212 is completed.

[0367] The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. In addition, the analog operation unit 1213 may also include the above-mentioned product-sum operation circuit.

[0368] The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0369] The interface 1215 includes, for example, an interface circuit with an external connection device such as a display device, a speaker, a microphone, an image capture device, or a controller. The controller includes, for example, a mouse, a keyboard, or a game console controller. As the above-mentioned interface, for example, USB (Universal Serial Bus) or HDMI (High-Definition Multimedia Interface) (registered trademark) can be used.

[0370] The network circuit 1216 includes, for example, a LAN (Local Area Network) or other network circuits, and may also include a network security circuit.

[0371] The above-mentioned multiple circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process. Therefore, the chip 1200 can be manufactured at a low cost.

[0372] The motherboard 1203 including the package substrate 1201 provided with the chip 1200 having the GPU 1212 , the DRAM 1221 , and the flash memory 1222 may be collectively referred to as a GPU module 1204 .

[0373] The GPU module 1204 can be reduced in size because it has a chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop personal computers, or portable (portable) game consoles due to its high image processing capabilities. In addition, the GPU module 1204 can perform methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), or deep belief networks (DBNs) by utilizing a product-sum operation circuit using the GPU 1212. Thus, the chip 1200 can be used as an AI chip. Alternatively, the GPU module 1204 can be used as an AI system module.

[0374] At least a part of the structure or method described in the above-mentioned embodiment can be implemented in combination with other embodiment or other examples described in this specification etc. as appropriate.

[0375] (Implementation 7) This embodiment mode describes an example of an electronic component and an electronic device incorporating the storage device described in the above embodiment mode, etc. By using the storage device described in the above embodiment mode for the following electronic component and electronic device, low power consumption and high speed of the electronic component and electronic device can be achieved.

[0376] <Electronic components> First, use Fig.26A and Fig.26B An example of an electronic component in which the storage device 720 is incorporated will be described.

[0377] Fig.26A The electronic component 700 and a perspective view of a substrate (circuit board 704 ) on which the electronic component 700 is mounted are shown. Fig.26A The electronic component 700 shown includes a storage device 720 within a mold 711. Fig.26A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713. The electrode pad 713 is electrically connected to the storage device 720 via a lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of the electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0378] The storage device 720 includes a driving circuit layer 721 and a storage circuit layer 722 .

[0379] Note that the memory circuit layer 722 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the drive circuit layer 721 and the memory circuit layer 722 are stacked can be a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the drive circuit layer 721 and the memory circuit layer 722 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be realized.

[0380] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to a technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0381] In addition, it is preferred that multiple memory cell arrays in the memory circuit layer 722 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, one or both of the bandwidth of the memory and the access delay of the memory can be improved. Note that bandwidth refers to the amount of data transmission per unit time. In addition, access delay refers to the time between access and the start of data exchange. When Si transistors are used in the memory circuit layer 722, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0382] That is, compared with Si transistors, OS transistors have excellent effects such as being able to achieve wider memory bandwidth.

[0383] Note that the memory device 720 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip, and cutting it into rectangular pieces. Examples of semiconductor materials that can be used for bare chips include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a bare chip obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon chip.

[0384] then, Fig.26B7 is a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.

[0385] In the electronic component 730, the storage device 720 can be used as a high bandwidth memory (HBM), for example. In addition, the semiconductor device 735 can be used in an integrated circuit (semiconductor device) such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0386] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The interposer 731 may be, for example, a silicon interposer or a resin interposer, etc.

[0387] The plug board 731 has a plurality of wirings and has the function of electrically connecting each of a plurality of integrated circuits having different terminal spacings through each of the plurality of wirings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit disposed on the plug board 731 to the electrode disposed on the package substrate 732. Therefore, the plug board 731 is sometimes also referred to as a "rewiring substrate" or an "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon plug board is used as the plug board 731, TSV can also be used as the through electrode.

[0388] A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. In addition, the wiring formation of the silicon interposer can be performed in a semiconductor process, so it is easy to form fine wiring that is difficult to form when using a resin interposer.

[0389] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0390] In addition, for example, in SiP or MCM using a silicon interposer, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, poor connection between the integrated circuit disposed on the silicon interposer and the silicon interposer is not likely to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0391] On the other hand, for example, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0392] The substrate on which the electronic component 730 is mounted may be provided with a heat sink (heat sink) overlapping the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the storage device 720 and the semiconductor device 735 consistent.

[0393] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig.26B An example of forming the electrode 733 using solder balls is shown. The electronic component 730 can be mounted in a BGA (Ball Grid Array) by arranging solder balls in a matrix on the bottom of the package substrate 732. Alternatively, the electrode 733 can be formed using conductive pins. The electronic component 730 can be mounted in a PGA (Pin Grid Array) by arranging conductive pins in a matrix on the bottom of the package substrate 732.

[0394] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA or PGA. For example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package) or QFN (Quad Flat Non-leaded package) can be used as mounting methods.

[0395] Note that by using a storage device of one embodiment of the present invention in an electronic component, power consumption can be reduced. Therefore, it is currently believed that as the energy demand of storage devices increases with high performance or high integration, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a storage device of one embodiment of the present invention. In addition, a storage device of one embodiment of the present invention has low power consumption and is therefore also effective as a measure against global warming.

[0396] The configuration or method described in the above-mentioned embodiment mode can be used in combination with other configurations or methods described in the embodiment mode or configurations or methods described in other embodiments or other examples as appropriate.

[0397] (Implementation 8) In this embodiment, an application example of a storage device using the storage device shown in the above embodiment, etc. is described. The storage device shown in the above embodiment, etc. can be applied to the storage device of various electronic devices (for example, information terminals, computers, smart phones, e-book readers, digital cameras (including video cameras), video playback devices or navigation systems, etc.). By using the storage device shown in the above embodiment, etc. for the storage device of the above electronic device, low power consumption and high speed of the electronic device can be achieved. Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. In addition, the storage device shown in the above embodiment, etc. is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory or an SSD (solid state drive). FIG. 27A to FIG. 27E Schematically showing some structural examples of a removable storage device. For example, the storage device shown in the above-mentioned embodiment etc. is processed into a packaged memory chip and used in various storage devices or removable memories.

[0398] Fig.27A 11 is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. For example, the storage device shown in the above-mentioned embodiment and the like can be assembled to the memory chip 1105 and the like.

[0399] Fig.27B This is a schematic diagram of the appearance of an SD card. Fig.27C11 is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also arranging the memory chip 1114 on the back side of the surface of the substrate 1113 on which the control chip 1115 is assembled, the capacity of the SD card 1110 can be increased. In addition, the SD card 1110 can also arrange a wireless chip with a wireless communication function on the substrate 1113. Thus, data of the memory chip 1114 can be read or written through wireless communication between the host device and the SD card 1110. For example, the storage device shown in the above-mentioned embodiment can be assembled on the memory chip 1114, etc.

[0400] Fig.27D This is a schematic diagram of the appearance of an SSD. Fig.27E 1150 is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and for example, a DOSRAM chip can be used. By also providing a memory chip 1154 on the back side of the surface of the substrate 1153 on which the control chip 1156 is assembled, the capacity of the SSD 1150 can be increased. For example, the storage device shown in the above-mentioned embodiment can be assembled on the memory chip 1154, etc.

[0401] At least a part of the structure or method described in the above-mentioned embodiment can be implemented in combination with other embodiment or other examples described in this specification etc. as appropriate.

[0402] (Implementation method 9) The storage device according to one embodiment of the present invention can be applied to a processor or chip such as a CPU or a GPU, for example. By using a processor or chip such as a CPU or a GPU using the storage device according to one embodiment of the present invention in an electronic component, the electronic component can achieve low power consumption and high speed. FIG. 28A to FIG. 28H A specific example of an electronic device including a processor or a chip such as a CPU or a GPU using the storage device is shown.

[0403] <Electronic equipment and systems> A GPU or chip according to one embodiment of the present invention can be installed in a variety of electronic devices. Examples of electronic devices include television devices, electronic devices with larger screens such as desktop or notebook information terminals, digital signage, or large game consoles such as pinball machines. In addition, examples include digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, or sound reproduction devices. In addition, by setting a GPU or chip according to one embodiment of the present invention in an electronic device, the electronic device can have artificial intelligence.

[0404] An electronic device according to one embodiment of the present invention may also include an antenna. The electronic device may receive a signal using the antenna, and may display an image or information on a display unit, for example. In addition, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0405] An electronic device of one embodiment of the present invention may also include a sensor (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared, etc.).

[0406] An electronic device of one embodiment of the present invention may have various functions. For example, the electronic device may have the following functions: a function of displaying various information (e.g., static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc. FIG. 28A to FIG. 28H An example of an electronic device is shown.

[0407] 〔Information Terminal〕 Fig.28A The figure shows a mobile phone (smartphone) which is one of the information terminals. The information terminal 5100 includes a housing 5101 and a display portion 5102 . The display portion 5102 is provided with a touch panel as an input interface, and buttons are provided on the housing 5101 .

[0408] Note that the information terminal 5100 may include, for example, a power button, an operation button, a speaker, a microphone, a camera, a light source, and a control device. Note that the control device may include, for example, one or more selected from a CPU, a GPU, and a storage device. By using a storage device of one embodiment of the present invention for the control device, power consumption can be reduced, which is preferred.

[0409] By applying a chip of one embodiment of the present invention to the information terminal 5100, an application program utilizing artificial intelligence can be executed. Examples of the application program utilizing artificial intelligence include an application program that recognizes a conversation and displays the content of the conversation on the display unit 5102, an application program that recognizes text or graphics input by a user to a touch panel provided on the display unit 5102 and displays the text or graphics on the display unit 5102, and an application program that performs biometric recognition such as fingerprints or voiceprints.

[0410] Fig.28B 1 and 2. The notebook information terminal 5200 is shown. The notebook information terminal 5200 includes an information terminal body 5201, a display portion 5202, and a keyboard 5203.

[0411] Note that the notebook information terminal 5200 may include, for example, a pointing device, an external connection port, and a control device. Note that the control device may include, for example, one or more selected from a CPU, a GPU, and a storage device. By using a storage device of one embodiment of the present invention for the control device, power consumption can be reduced, which is preferred.

[0412] As with the above-mentioned information terminal 5100, by applying a chip of one embodiment of the present invention to the notebook information terminal 5200, an application program utilizing artificial intelligence can be executed. Examples of applications utilizing artificial intelligence include design support software, article proofreading software, and menu automatic generation software. In addition, a user using the notebook information terminal 5200 can develop novel artificial intelligence.

[0413] Note that in the above example, Fig.28A and Fig.28B A smartphone and a notebook information terminal are shown as examples of electronic devices, but information terminals other than smartphones and notebook information terminals may also be used. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0414] 〔Game console〕 Fig.28CA portable game console 5300 is shown as an example of a game console. The portable game console 5300 includes, for example, a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, and an operation key 5306. The housing 5302 and the housing 5303 can be detached from the housing 5301. The portable game console 5300 can output the image output to the display unit 5304 to other video devices (not shown) by installing the connection unit 5305 provided in the housing 5301 to another housing (not shown). At this time, the housing 5302 and the housing 5303 can be used as an operation unit respectively. Thus, multiple game players of the portable game console 5300 can play games at the same time. For example, the chip shown in the above-mentioned embodiment can be assembled to a chip provided on a substrate of the housing 5301, the housing 5302, and the housing 5303.

[0415] in addition, Fig.28D A stationary gaming machine 5400, which is one of the gaming machines, is shown. The stationary gaming machine 5400 is connected to a controller 5402 by wireless or wired connection.

[0416] For example, by applying a GPU or chip of one embodiment of the present invention to a gaming machine such as a portable gaming machine 5300 or a fixed gaming machine 5400, a low-power gaming machine can be realized. In addition, the gaming machine can reduce heat generated by the circuit due to low power consumption, thereby reducing the negative effects of heat on the circuit itself, peripheral circuits, or modules.

[0417] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, a portable game console 5300 equipped with artificial intelligence can be realized.

[0418] The performance of the progress of the game, the words and deeds of creatures appearing in the game, or the phenomena occurring in the game is originally specified by the program of the game, but by applying artificial intelligence to the portable game console 5300, it is possible to achieve performance not limited to the game program. The portable game console 5300 can achieve the performance of the changes in the words and deeds of characters appearing in the game, for example, based on the content of the game player's questions, the progress of the game, or the time.

[0419] In addition, when the portable game console 5300 plays a game that requires multiple game players, artificial intelligence can be used to form an anthropomorphic game player, whereby the artificial intelligence game player can be used as an opponent, and one person can play a game that can be played by multiple people.

[0420] Although Fig.28C and Fig.28DPortable game consoles and stationary game consoles are shown as examples of game consoles, but game consoles to which a GPU or chip according to one embodiment of the present invention is applied are not limited thereto. Game consoles to which a GPU or chip according to one embodiment of the present invention is applied include, for example, arcade game consoles installed in entertainment facilities (e.g., game centers or amusement parks) or pitching machines for batting practice installed in sports facilities.

[0421] 〔Mainframe computer〕 The GPU or chip according to one embodiment of the present invention can be applied to large computers.

[0422] Fig.28E A supercomputer 5500 is shown as an example of a large-scale computer. Fig.28F A rack mount computer 5502 included in the supercomputer 5500 is shown.

[0423] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that the plurality of computers 5502 are housed in the rack 5501. In addition, the computer 5502 is provided with a plurality of substrates 5504. On the substrate 5504, the GPU or chip described in the above embodiment and the like can be mounted.

[0424] The supercomputer 5500 is a large computer mainly used for scientific computing. When the supercomputer 5500 is used for scientific computing, it needs to perform huge calculations at high speed, so the power consumption is large and the heat generation of the chip is high. By applying the GPU or chip of one embodiment of the present invention to the supercomputer 5500, a low-power supercomputer can be realized. In addition, the supercomputer 5500 can reduce the heat generated by the circuit by means of low power consumption, thereby reducing the negative impact caused by heat to the circuit itself, peripheral circuits or modules.

[0425] The supercomputer 5500 can also be used as a parallel computer. By using the supercomputer 5500 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0426] exist Fig.28E and Fig.28F In the embodiment, a supercomputer is shown as an example of a large computer, but a large computer to which a GPU or chip of one embodiment of the present invention is applied is not limited to this. As a large computer to which a GPU or chip of one embodiment of the present invention is applied, for example, a computer (server) providing a service or a large general-purpose computer (host) can be cited.

[0427] Fig.29A 1 is a perspective view illustrating a specific structural example of the computer 5502. Fig.29AIn the embodiment, the computer 5502 includes a motherboard 5630. The motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals (not shown). A personal computer card 5621 is inserted into the slots 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0428] Fig.29B The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.29B Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0429] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe (Peripheral Component Interconnect Express) and the like.

[0430] Each of the connection terminals 5623, 5624, and 5625 can be used as an interface for supplying power to the personal computer card 5621 or inputting a signal, for example. In addition, for example, it can be used as an interface for outputting a signal calculated by the personal computer card 5621. As examples of the specifications of each of the connection terminals 5623, 5624, and 5625, USB (Universal Serial Bus), SATA (Serial ATA), or SCSI (Small Computer System Interface) can be cited. In addition, when the connection terminals 5623, 5624, and 5625 each output a video signal, as examples of the specifications, HDMI (registered trademark) (High-Definition Multimedia Interface) can be cited.

[0431] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622, the semiconductor device 5626 and the board 5622 can be electrically connected.

[0432] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5627, for example, an FPGA, a GPU, or a CPU can be cited. As the semiconductor device 5627, for example, the above-mentioned electronic component 730 can be used.

[0433] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 described above can be used.

[0434] 〔Mobile body〕 The GPU or chip according to one embodiment of the present invention can be applied to a vehicle as a mobile object and the vicinity of a driver's seat of the vehicle.

[0435] Figure 28G This is a diagram showing the periphery of a front windshield in an automobile as an example of a moving object. Figure 28G Display panels 5701, 5702, and 5703 installed on the instrument panel and display panel 5704 installed on the pillar are shown.

[0436] For example, the display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a driving distance, a fuel gauge, a gear status, an air conditioning setting, etc. In addition, the user can appropriately change the display content or layout displayed by the display panel according to his or her preferences. Therefore, the display device can improve the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0437] By displaying the image captured by the camera device (not shown) installed in the car on the display panel 5704, the field of view (blind spot) blocked by the pillar can be compensated. That is, the display panel 5704 can compensate for the blind spot by displaying the image captured by the camera device installed outside the car, thereby improving safety. In addition, the display panel 5704 can confirm safety more naturally and comfortably by displaying the image that supplements the invisible part. The display panel 5704 can also be used as a lighting device.

[0438] Because the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of a car. In addition, the chip can also be used in a system for navigation, danger prediction, etc. In addition, the display panels 5701 to 5704 can also have a structure for displaying information such as navigation or danger prediction, for example.

[0439] Although a car is described as an example of a mobile body in the above example, the mobile body is not limited to a car. For example, a tram, a monorail, a ship, or a flying object (a helicopter, an unmanned aircraft (drone), an airplane, or a rocket) etc. can also be cited as a mobile body. By applying a chip of one embodiment of the present invention to these mobile bodies, a system using artificial intelligence can be provided.

[0440] 〔Electrical products〕 Fig.28H An electric refrigerator-freezer 5800 is shown as an example of an electric appliance. The electric refrigerator-freezer 5800 includes, for example, a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0441] By applying a chip of one embodiment of the present invention to an electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 can, for example, have a function of automatically generating a menu based on the food stored in the electric refrigerator-freezer 5800 or the expiration date of the food, or a function of automatically adjusting the temperature of the electric refrigerator-freezer 5800 according to the stored food.

[0442] An electric refrigerator-freezer is described as an example of an electrical appliance, but other electrical appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, an electric rice cooker, a water heater, an IH cooker, a water dispenser, an air conditioner including a heating and cooling air conditioner, a washing machine, a dryer, or audio-visual equipment.

[0443] Note that by using a storage device of one embodiment of the present invention for one or more selected from electronic devices, information terminals, game consoles, large computers, mobile bodies, and electrical products, power consumption can be reduced. Therefore, it is currently believed that as the energy demand for storage devices increases with high performance or high integration, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a storage device of one embodiment of the present invention. In addition, a storage device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0444] For example, the electronic device, the function of the electronic device, the application example of artificial intelligence or its effect, etc. described in this embodiment can be implemented in combination with the description of other electronic devices as appropriate.

[0445] At least a part of the structure or method described in the above-mentioned embodiment can be implemented in combination with other embodiment or other examples described in this specification and the like as appropriate.

[0446] (Implementation 10) A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, the OS transistor has high resistance to radiation and can be appropriately used even in an environment where radiation may be incident. For example, the OS transistor can be appropriately used when used in outer space. In this embodiment, the OS transistor is used Fig.30 A specific example in which a semiconductor device according to one embodiment of the present invention is applied to space equipment will be described.

[0447] exist Fig.30 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.30 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification and the like may also include the thermosphere, mesosphere, and stratosphere.

[0448] In addition, although Fig.30 Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0449] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays or gamma rays; or particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, or muon rays.

[0450] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel 6802 or when the amount of sunlight shining on the solar cell panel 6802 is small, the amount of power generated by the solar cell panel 6802 decreases. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the power generated by the solar cell panel 6802 is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel 6802 is sometimes referred to as a solar cell module.

[0451] The artificial satellite 6800 may generate a signal. The signal is transmitted via the antenna 6803. In addition, a receiver on the ground or another artificial satellite may receive the signal. For example, by receiving the signal transmitted by the artificial satellite 6800, the receiver may measure the position of the receiver receiving the signal. Thus, the artificial satellite 6800 may constitute a satellite positioning system.

[0452] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, it is preferable to use a semiconductor device including an OS transistor of one embodiment of the present invention. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change less. That is, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0453] That is, the OS transistor has excellent effects such as high resistance to radiation compared to the Si transistor.

[0454] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. In addition, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0455] Note that by using a semiconductor device of one embodiment of the present invention in space equipment, power consumption can be reduced. Therefore, it is currently believed that as the energy demand for semiconductor devices increases with the performance or high integration of semiconductor devices, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a semiconductor device of one embodiment of the present invention. In addition, a semiconductor device of one embodiment of the present invention has low power consumption and is therefore also effective as a measure against global warming.

[0456] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, or a space probe.

[0457] At least a part of the structure or method described in the above-mentioned embodiment can be implemented in combination with other embodiment or other examples described in this specification etc. as appropriate.

[0458] (Implementation 11) In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. In addition, in the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) is briefly described.

[0459] 〔OS transistor〕 It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor, the impurity concentration in the oxide semiconductor can be reduced to reduce the defect state density in the oxide semiconductor. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0460] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0461] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0462] In an OS transistor, when impurities or oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), electrons that become carriers may be generated. In addition, in the OS transistor, when V O When the gate voltage is 0V, the donor concentration in the channel formation region may increase. Therefore, in the OS transistor, as the donor concentration in the channel formation region increases, the threshold voltage may be uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the OS transistor may have a normally-on characteristic (a characteristic in which the drain current flows when the gate voltage is 0V). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H.

[0463] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0464] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (also called SCE: Short Channel Effect) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the appearance of the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with a large band gap, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0465] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0466] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0467] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0468] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junctionless transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are both n + Type area.

[0469] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if miniaturization or high integration is performed. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, because of the short channel effect, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm. Therefore, compared with Si transistors, OS transistors can be appropriately used as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is the width of the bottom surface of the gate electrode in the plan view of the transistor.

[0470] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0471] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0472] The configuration, structure, method, or the like described in this embodiment mode can be used in combination with the configuration, structure, method, or the like described in other embodiments or other examples as appropriate.

[0473] (Implementation 12) In this embodiment, a data center (DC) using the semiconductor device described in the above embodiment is described. A data center using the semiconductor device of one embodiment of the present invention is effective in achieving high performance such as low power consumption.

[0474] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. For example, a data center is required to ensure data invariance and to perform long-term data management. When performing long-term data management, for example, it is necessary to set up storage and servers for storing large amounts of data, ensure a stable power supply to maintain data, or ensure cooling equipment required for maintaining data. Therefore, for example, it is necessary to enlarge the facilities of a data center.

[0475] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and to miniaturize the semiconductor device for retaining data. Therefore, for example, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the size of the cooling equipment. As a result, it is possible to save space in the data center.

[0476] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the peripheral modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0477] Fig.31 A storage system that may be used in a data center is shown. Fig.31The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as storage 7003 (shown as storage). In addition, the host 7001 and the storage 7003 are shown to be connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0478] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0479] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for writing or reading data is shortened, but this time is much longer than the time required for a DRAM that can be used as a cache memory in the storage. In order to solve the problem of the long access speed of the storage 7003 in the storage system, a cache memory is generally provided in the storage to shorten the time required for writing or reading data.

[0480] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0481] When an OS transistor is used as a transistor for storing data of the cache memory to hold a potential corresponding to the data, the refresh frequency of the cache memory can be reduced and the power consumption of the cache memory can be reduced. In addition, the cache memory can be miniaturized by stacking memory cell arrays.

[0482] Note that by using a semiconductor device of one embodiment of the present invention in a data center, power consumption can be reduced. Therefore, it is currently believed that as the energy demand of semiconductor devices increases with the high performance or high integration, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a semiconductor device of one embodiment of the present invention. In addition, the power consumption of a semiconductor device of one embodiment of the present invention is low, so it is also effective as a measure against global warming.

[0483] The configuration, structure, method, or the like described in this embodiment mode can be used in combination with the configuration, structure, method, or the like described in other embodiments or other examples as appropriate. [Example]

[0484] In this embodiment, the results of estimating the write time, read time, storage density, and retention time of a storage device according to one embodiment of the present invention are described.

[0485] like Figure 3B , Fig.19A and Fig.19B As shown, a memory device for estimating write time, read time, storage density, and retention time has a memory array in which four layers (corresponding to layers 41[1] to 41[4]) having memory cells (corresponding to memory cells 42) formed of OS transistors are stacked on a layer (corresponding to layer 30) having a read circuit (corresponding to sensor circuit 35) formed of OS transistors. In addition, a driving circuit (corresponding to, for example, read amplifier 55) such as a driver, a read amplifier, and a controller is provided on a substrate including Si transistors.

[0486] Note that the memory device evaluated in this embodiment has a structure in which memory cells of DOSRAM are stacked, which is sometimes referred to as 3D DOSRAM.

[0487] Table 1 shows the results of estimating the write time, read time, storage density, and retention time of the 3D DOSRAM (hereinafter sometimes simply referred to as DOSRAM) constructed as described above and the DRAM composed of Si transistors.

[0488] [Table 1]

[0489] As shown in Table 1, in the estimation of DOSRAM, the design rule of the OS transistor is 30 nm. In addition, in the estimation of DRAM, the design rule of the Si transistor is 14 nm.

[0490] Table 1 shows the results of estimation for three cases (condition A, condition B, and condition C) with different DOSRAM structures.

[0491] In condition A, the memory cell of DOSRAM has Fig. 24B In the structure shown, the atomic ratio of metal elements in the semiconductor layer (equivalent to the oxide 230 ) of the OS transistor (equivalent to the transistor 200 ) is In:Ga:Zn=1:1:1.

[0492] In condition B, the memory cell of DOSRAM has Fig.32 In the structure shown, the atomic ratio of metal elements in the semiconductor layer of the OS transistor is In:Ga:Zn=1:1:1.

[0493] In condition C, the memory cell of DOSRAM has Fig. 24BThe structure shown and the semiconductor layer of the OS transistor have a three-layer stacked structure, wherein a semiconductor layer whose atomic ratio of metal elements is In:Ga:Zn=1:1:1 is used as the first layer, a semiconductor layer whose atomic ratio of metal elements is In:Zn=4:1 is used as the second layer, and a semiconductor layer whose atomic ratio of metal elements is In:Ga:Zn=1:1:1 is used as the third layer.

[0494] In the estimation of DOSRAM shown in Table 1, the design value of the channel length of the OS transistor is 30 nm, and the design value of the channel width is 30 nm. In addition, the cell capacitance (equivalent to capacitance 100) is 1.5 fF.

[0495] Fig.33 , Fig.34 and Fig.35 Id-Vg characteristics of the OS transistor used for estimation in conditions A, B, and C, respectively. Fig.33 , Fig.34 and Fig.35 Each shows the drain current Id (current flowing between the source and the drain) in the range of -1V to 4V when the gate voltage Vg (voltage between the source and the gate) is 1.2V and the back gate voltage Vb (voltage between the source and the back gate) is 0V under an environment of 27°C. In addition, the Id-Vg characteristics (measurement results) represented by the solid line are the Id-Vg characteristics of the actually manufactured OS transistor, and the Id-Vg characteristics (simulation) represented by the dotted line are the Id-Vg characteristics for estimating the OS transistor. Note that Fig.35 Only the Id-Vg characteristics indicated by the dotted line are shown (simulation).

[0496] Note that the on-state current Ion of the OS transistor (in the Id-Vg characteristics (measurement results) shown by the solid line in this embodiment, the drain current Id per channel width of 1 μm when the source voltage Vg is 3.3 V) is Fig.33 The condition A is 272.6μA / μm. Fig.34 In the case of condition B shown, it is 297.8 μA / μm.

[0497] As shown in Table 1, the estimated write time of DOSRAM is 7ns, 6ns and 3ns in conditions A, B and C, respectively, which is shorter than the estimated write time of DRAM, 20ns, under all conditions. In addition, the estimated read time of DOSRAM is 48ns, 24ns and 16ns in conditions A, B and C, respectively, which is shorter than the estimated read time of DRAM, 20ns, under condition C. In other words, it can be seen that DOSRAM may obtain higher performance than DRAM in write time and read time depending on the conditions.

[0498] In addition, it can be seen that in the estimated storage density item, the storage density of each layer of DOSRAM is estimated to be 77 cell / μm 2 , for example, by stacking five memory cells, exceeding the estimated 383 cell / μm of DRAM storage density 2 In other words, it can be seen that in terms of storage density, DOSRAM has the potential to surpass the performance of DRAM by achieving multi-layering.

[0499] In addition, in the retention item of estimating the retention time of data, DOSRAM is estimated to need to be refreshed once more than every 6.4s, and DRAM is estimated to need to refresh all storage cells once every 64ms. As a result, it is known that the power required for refreshing DOSRAM may be reduced to 1 / 100 of the power required when refreshing DRAM.

[0500] At least a part of this embodiment can be implemented in combination with other embodiment modes and the like described in this specification and the like as appropriate. [Explanation of symbols]

[0501] 10: semiconductor device, 20: layer, 30: layer, 40: layer, 41: layer, 50: substrate, 35: sensing circuit, 35_pre sensing circuit, 37: switching circuit, 42: memory cell, 51: driving circuit, LBL: local bit line, LBL_pre: local bit line, GBL: global bit line, GBLB: global bit line, SA_GBL: global bit line, SA_GBLB: global bit line, BL: bit line, BLB: bit line, M0: transistor, M1: transistor, M2: transistor, M3: transistor, M4: transistor, SW0: signal, SW1: signal, SW2: signal, SW3: signal, VPRE2: potential, MUX: signal, WE: signal, RE: signal, SL: wiring, WL: word line, CSL: wiring, EQ: signal, EQB: signal, CSEL: signal, VPRE: potential, SAP: wiring, SAN: wiring, 31: transistor, 32: transistor, 33: transistor, 34: transistor, 43: transistor, 44: capacitor, MND: node, 52: switch circuit, 53: precharge circuit, 54: precharge circuit, 55: sense amplifier, 52_1: transistor, 52_2: transistor, 53_1: transistor, 53_2: transistor, 53_3: transistor, 54_1: transistor, 54_2: transistor, 54_3: transistor, 55_1: transistor, 55_2: transistor, 55_3: transistor, 55_4 : transistor, T11: time, T12: time, T13: time, T14: time, T15: time, T16: time, T21: time, T22: time, T23: time, T24: time, 300: storage device, 21: memory array, 22: drive circuit, 62: PSW, 63: PSW, 71: peripheral circuit, 72: control circuit, 73: voltage generation circuit, 81: peripheral circuit, 82: row decoder, 83: row driver, 84: column decoder, 85: column driver, 87: input circuit, 88: output circuit, BW: signal, CE: signal, GW: signal, CLK: signal, WAKE: signal, ADDR: signal, WDA: signal, RDA : signal, PON1: signal, PON2: signal, VDD: potential, VHM: potential, GND: ground potential, Din: data, Dout: data, 90: electronic computer, 91: processor, 92: main memory, 93: core, 94: cache memory, 95: interface, S01: step, S02: step, S03: step, 10A: semiconductor device, 37A: switching circuit, C1: capacitor, C2: capacitor, BOOT1: signal, BOOT2: signal, 10B: semiconductor device, 37B: switching circuit, 51B: drive circuit, 56: precharge circuit, M5: transistor, M6: transistor, SW5: signal, SW6: signal, VPRE3: potential,370A: storage device, 371: memory array unit, 372: memory unit, 373: word line driver unit, 374: column driver unit, 375: sense amplifier driver unit, 376: sensor circuit driver unit, 377: data sense amplifier unit, 378: storage controller unit, 370B: storage device, 373L: layer selection driver unit, 373Lbuf: layer selection driver, ML1: transistor, ML2: transistor, ML3: transistor, CL1: capacitor, BL1: node, LSEL: signal, LSELB: signal, VLD: potential, VLS: potential, WLin: word line, WLout: word line, TL1: time, TL2: time, 42a: storage cell, 42b: storage cell, 42c: storage cell, 42d: storage cell, 42 e: memory cell, Ma: transistor, Mb: transistor, Mc: transistor, Ca: capacitor, FN: node, BGL: back gate line, WWL: word line, RWL: word line, WBL: bit line, RBL: bit line, 380: chip, 381: module, 382: region, 383: region, 384: region, 385: region, 386: region, 735: semiconductor device, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 1104: substrate, 1113: substrate, 1153: substrate, 5504: substrate, 200: transistor, 200a: transistor, 200b: transistor, 100: capacitor, 100a: capacitor, 100b: capacitor, 1200: chip, 720: memory device, 7003md: memory device,

Claims

1. A semiconductor device comprising: First Circuit; Second Circuit; Third Circuit; Fourth Circuit; first wiring; Second wiring; The third wiring; Fourth wiring; as well as The fifth wiring, wherein the first circuit is electrically connected to the second circuit via the first wiring, The first circuit is electrically connected to the fourth circuit via the third wiring and the fourth wiring, The second circuit is electrically connected to the third circuit via the fifth wiring. The first circuit has a function of making the first wiring, the second wiring, the third wiring, and the fourth wiring conductive or non-conductive with each other. The third circuit has a function of holding a potential corresponding to the first data, The second circuit has a function of supplying a potential corresponding to the first data from the first wiring to the fifth wiring, a function of holding a potential corresponding to the second data, and a function of amplifying a change in the potential of the fifth wiring and outputting it to the first wiring. Furthermore, the fourth circuit has a function of outputting a potential corresponding to the first data or the second data according to a potential difference between the third wiring and the fourth wiring.

2. The semiconductor device according to claim 1, The first circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor, The first transistor has a function of making the first wiring and the second wiring conductive or non-conductive. The second transistor has a function of making the first wiring and the third wiring conductive or non-conductive. The third transistor has a function of making the second wiring and the fourth wiring conductive or non-conductive. The fourth transistor has a function of precharging the first wiring. And the fifth transistor has a function of precharging the second wiring.

3. The semiconductor device according to claim 1, The first circuit includes a first transistor, a second transistor, a third transistor, a first capacitor and a second capacitor, The first transistor has a function of making the first wiring and the second wiring conductive or non-conductive. The second transistor has a function of making the first wiring and the third wiring conductive or non-conductive. The third transistor has a function of making the second wiring and the fourth wiring conductive or non-conductive. The first capacitor has a function of changing the potential of the first wiring. And the second capacitor has a function of changing the potential of the second wiring.

4. The semiconductor device according to claim 1, The first circuit includes a first transistor, a second transistor and a third transistor, The first transistor has a function of making the first wiring and the second wiring conductive or non-conductive. The second transistor has a function of making the first wiring and the third wiring conductive or non-conductive. The third transistor has a function of making the second wiring and the fourth wiring conductive or non-conductive. The fourth circuit includes a sixth transistor and a seventh transistor, The sixth transistor has a function of precharging the third wiring. And the seventh transistor has a function of precharging the fourth wiring.

5. The semiconductor device according to any one of claims 1 to 4, wherein the fourth circuit is disposed on the substrate, The first circuit and the second circuit are arranged in a first layer configured on the substrate, The third circuit is provided in each of a plurality of second layers arranged on the substrate, The substrate includes a Si transistor, And each of the first layer and the plurality of second layers includes an OS transistor.

6. A storage device, comprising: The semiconductor device according to claim 5; as well as Fifth Circuit, wherein the fifth circuit is disposed in each of the plurality of second layers, Furthermore, the fifth circuit has a function of outputting a signal for controlling the operation of the third circuit.

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