Dual in-line power module

Abstract

A power module is provided with a substrate, a power device and a housing. The power device is mounted on the device pad of the substrate and is arranged to provide a power circuit having a first input, a second input, and at least one output. The first and second power terminals provide first and second inputs for the power circuit. The at least one output power terminal provides at least one output. The housing surrounds the substrate, the power device, and portions of the first and second input power terminals and the at least one output power terminal.

Description

[0001] Related Applications

[0002] This application is based upon and claims the benefit of priority to U.S. Patent Application No. 17 / 736,487, filed on May 4, 2022. This application claims the benefit of priority to, and is incorporated by reference in its entirety to, the entire contents of that application. Technical Field

[0003] The present disclosure relates to power modules for high power applications. Background Art

[0004] In high power applications, multiple components for all or part of a circuit are often packaged in electronic modules. These modules are often referred to as power modules and are housed in a thermoplastic, epoxy, or similar molded housing that encapsulates the components and a circuit board or substrate to which they are mounted. Input / output connections for the power module are provided by terminal assemblies extending from the housing to facilitate incorporation and connection to other systems. Such systems may include electric vehicles, power conversion and control, etc. Summary of the invention

[0005] The power module has a substrate, a power device and a housing. The power device is mounted on a device pad of the substrate and is arranged to provide a power circuit having a first input, a second input and at least one output. The first and second power terminals provide the first and second inputs for the power circuit. At least one output power terminal provides at least one output. The housing surrounds the substrate, the power device, and portions of the first and second input power terminals and at least one output power terminal.

[0006] In one embodiment, the housing surrounds a substrate, a plurality of power devices, and a portion of a first input power terminal, a second input power terminal, and at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing. The at least one first input power terminal may provide a first V-terminal and a second V-terminal extending from the first side of the housing. The at least one second input power terminal may provide a first V+ terminal and a second V+ terminal extending from the first side of the housing. The first V+ terminal and the second V+ terminal may be between the first V-terminal and the second V-terminal. The at least one output power terminal may be between the first V+ terminal and the second V+ terminal.

[0007] The at least one output power terminal may provide: a first output power terminal providing a first output of the power circuit, a second output power terminal providing a second output of the power circuit, and a third output power terminal providing a third output of the power circuit.

[0008] The plurality of signal terminals may provide a plurality of control signals for the power circuit, wherein portions of the plurality of signal terminals extend from a second side of the housing, the second side being opposite to the first side thereof. The plurality of signal terminals may include a first plurality of gate signal terminals providing gate control signals to gates of a first group of the plurality of power devices and a second plurality of gate signal terminals providing gate control signals to gates of a second group of the plurality of power devices.

[0009] The plurality of signal terminals may also include a first plurality of source-Kelvin signal terminals that provide source-Kelvin control signals to sources of a first group of the plurality of power devices and a second plurality of source-Kelvin signal terminals that provide source-Kelvin control signals to sources of a second group of the plurality of power devices. Each gate signal terminal in the first plurality of gate signal terminals may be adjacent to a corresponding source-Kelvin signal terminal in the first plurality of source-Kelvin signal terminals, and each gate signal terminal in the second plurality of gate signal terminals may be adjacent to a corresponding source-Kelvin signal terminal in the second plurality of source-Kelvin signal terminals. Additional terminals may be used for various types of sensors to monitor temperature, current, voltage, etc.

[0010] The pin headers for adjacent pairs of the first and second pluralities of gate terminals and the first and second pairs of source-Kelvin signal terminals may be staggered from one another. Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal may have a first pin header and a second pin header staggered from the first pin header.

[0011] The substrate may provide at least one jumper pad, a first bonding wire, and a second bonding wire. The first bonding wire may extend from at least one of the plurality of signal terminals to the at least one jumper pad, and the second bonding wire may extend from the at least one jumper pad to the power circuit.

[0012] The at least one first input power terminal and / or the at least one second input power terminal are directly mechanically coupled to the substrate. The at least one output power terminal may not be directly mechanically coupled to the substrate, wherein a bonding wire couples the at least one output power terminal to the power circuit. At least one of the plurality of signal terminals may be directly mechanically coupled to the substrate, and at least another of the plurality of signal terminals may be directly coupled to the power circuit via a bonding wire, while other signal terminals are not.

[0013] In selected embodiments, the thermal pad is arranged on the bottom side of the substrate, wherein the thermal pad is exposed through the housing. The power circuit is a three-phase circuit, a full bridge, a half bridge, etc. A temperature circuit may be arranged on the substrate.

[0014] The notches may be recessed into one or more sides of the housing for attaching the power module to another device. A creepage extender may be provided on at least one of the top side and the bottom side of the housing. One or more notches may be provided in the first side of the housing between adjacent ones of at least one first input power terminal, at least one second input power terminal, or at least one output power terminal to reduce creepage.

[0015] In one embodiment, a power module is provided with a substrate, a power device and a housing. The power device is mounted on a device pad of the substrate and is arranged to provide a power circuit having a first input, a second input and at least one output. The first and second power terminals provide the first and second inputs for the power circuit. At least one output power terminal provides at least one output. The housing surrounds the substrate, the power device, and portions of the first and second input power terminals and at least one output power terminal, wherein at least one of the at least one first input power terminal and / or the at least one second input power terminal is directly mechanically coupled to the substrate. At least one first input power terminal and at least one second input power terminal are directly mechanically coupled to the substrate.

[0016] At least one of the plurality of signal terminals may also be directly mechanically coupled to the substrate, and at least another one of the plurality of signal terminals may be coupled to the power circuit via a bonding wire.

[0017] Based on the above, the present disclosure relates to a compact, high voltage, high current, low inductance power module designed for next generation silicon carbide (SiC) and other material system power devices and power electronics applications. It utilizes a novel layout combining size and cost optimized power substrates.

[0018] The design is characterized by scalability and modularity. The layout can be made wider and longer to (1) accommodate larger devices or (2) place more devices in parallel. Basically, the package concept can be scaled up or down to meet power handling needs without losing any performance benefits provided by the package. It is also possible to arrange these packages in parallel directly, increasing the current of the converter and / or forming topologies such as half-bridge and full-bridge (often used in DC-DC power conversion) and three-phase circuits (used in motor drives and inverters).

[0019] Those skilled in the art will understand the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0021] Figure 1A A schematic diagram of a three-phase circuit is shown.

[0022] Figure 1B The temperature circuit is shown.

[0023] Figure 2 is an isometric view of the top side of a power module according to a first embodiment of the present disclosure.

[0024] Figure 3 is an isometric view of the bottom side of a power module according to a first embodiment of the present disclosure.

[0025] Figure 4 is a top plan view of a power module according to a first embodiment of the present disclosure.

[0026] Figure 5 , Figure 6 and Figure 7 is a corresponding side view of the power module according to the first embodiment of the present disclosure.

[0027] Figure 8 is a bottom plan view of a power module according to a first embodiment of the present disclosure.

[0028] Fig. 9 , Fig.10 and Fig.11 are top plan, top isometric, and side plan views of a power module without a housing or bond wires according to a first embodiment of the present disclosure.

[0029] Fig.12 , Fig.13 and Fig.14 are a top plan view, a top isometric view, and a side plan view of a power module without a housing but with bonding wires according to a first embodiment of the present disclosure.

[0030] Fig.15 and Fig.16 Terminal pins according to two embodiments of the present disclosure are shown.

[0031] Fig.17 and Fig.18 are a bottom plan view and a bottom isometric view of a power module without a housing according to a first embodiment of the present disclosure.

[0032] Fig.19 is an exploded view of the first embodiment of the present disclosure.

[0033] Fig. 20 An exemplary power loop for a first embodiment of the present disclosure is shown.

[0034] Fig.21 An exemplary signal loop according to the first embodiment of the present disclosure is shown.

[0035] Fig. 22 An exemplary implementation of a power module when used with a larger power device is shown.

[0036] Fig.23 An exemplary implementation of a power module when used with smaller power devices is shown.

[0037] Fig.24 An exemplary embodiment of a power module when used with parallel power devices is shown.

[0038] Fig.25 An exemplary embodiment of a power module is shown in which certain available locations for power devices are not used. DETAILED DESCRIPTION

[0039] The embodiments set forth below represent necessary information to enable those skilled in the art to practice the embodiments and illustrate the best way to practice the embodiments. When reading the following description according to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize that the application of these concepts is not specifically described herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0040] It will be understood that although the terms first, second, etc. may be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used in this article, the term "and / or" includes any and all combinations of one or more related listed items.

[0041] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element or extending "on" another element, the element may be directly on another element or directly extend to another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly on another element" or "extending directly to another element", there is no intermediate element. Similarly, it will be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element or extending "on" another element, the element may be directly on another element or extend directly on another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly on another element" or extending "directly on another element", there is no intermediate element. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to another element, or there may be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0042] Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical", may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms and those described above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0043] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" also include plural forms. It should be further understood that when used herein, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of described features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or increase of one or more other features, wholes, steps, operations, elements, parts and / or combinations thereof.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should be further understood that the terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined in this article.

[0045] The present disclosure relates to power modules used in high power applications. The power module may include one or more power semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), diodes, etc., arranged in various circuit topologies. Typical circuit topologies include, but are not limited to, a single switch, a half H-bridge circuit, a full H-bridge circuit, and a three-phase switch circuit, which is often referred to as a six-pack.

[0046] For the following discussion, a three-phase circuit is used to facilitate understanding of the packaging concepts disclosed herein. Figure 1A An exemplary three-phase circuit according to an embodiment of the present disclosure is shown in . Those skilled in the art will recognize that other circuits may be employed, such as a half-bridge circuit, a full-bridge circuit, etc. For this example, it is assumed that transistors Q1-Q6 are power silicon carbide (SiC) MOSFETs, each having a drain (D), a gate (GX), a source (S), and a source-Kelvin (KX) terminal. For the embodiments described below, transistors Q1-Q6 are vertical N-channel MOSFETs, wherein the drain contact is at the bottom of the device, and the source, gate, and source-Kelvin contacts are at the top of the device.

[0047] Each high-side transistor Q1, Q3, Q5 is coupled in series with the corresponding low-side transistor Q2, Q4, Q6. The drain D of the high-side transistors Q1, Q3, Q5 is coupled to the V+ terminal, and the source S of the low-side transistors Q2, Q4, Q6 is coupled to the V- terminal. For the first branch of the three-phase circuit, the source S of the high-side transistor Q1 is coupled to the drain D of the low-side transistor Q2 to provide a first output, referred to as terminal U. For the second branch of the three-phase circuit, the source S of the high-side transistor Q3 is coupled to the drain D of the low-side transistor Q4 to provide a second output, referred to as terminal V. For the third branch of the three-phase circuit, the source S of the high-side transistor Q5 is coupled to the drain D of the low-side transistor Q6 to provide a third output, referred to as terminal W. Each of the transistors Q1-Q6 also has an independent gate terminal G1-G6 (usually GX) and a source-Kelvin signal terminal K1-K6 (usually KX).

[0048] Diodes D1-D6 may be coupled between the drain and source of the respective transistors Q1-Q6. In each case, the anode of diodes D1-D6 is coupled to the source of the respective transistors Q1-Q6, and the cathode of diodes D1-D6 is coupled to the drain of transistors Q1-Q6. Diodes D1-D6 may be separate devices or integrated into the packages of transistors Q1-Q6.

[0049] like Figure 1B As shown in , additional circuitry (e.g., a temperature circuit 16 for sensing internal device temperature) may be provided in association with the three-phase circuit and may be as simple as a thermistor, a negative temperature coefficient (NTC) device, or a resistance temperature detector (RTD) having terminals TEMP1 and TEMP2. In such an embodiment, the resistance of the thermistor or RTD will vary with temperature and be measurable across terminals TEMP1 and TEMP2. A thermistor will typically have a negative temperature coefficient because its resistance has a negative correlation with temperature, while an RTD will typically have a positive temperature coefficient because its resistance has a positive correlation with temperature. Additional circuitry, such as current sensing, may be introduced using functional elements and dedicated pins.

[0050] Figures 2 to 8 1 are different isometric views and plan views of a power module 10 according to a first embodiment, the power module providing a method for implementing different power circuits (such as Figure 1A and Figure 1B The electronic devices required for the three-phase circuit and temperature circuit 16). Figure 2 and Figure 3 are the top isometric view and the bottom isometric view. Figure 4 It is the top floor plan. Figure 5 , Figure 6 and Figure 7 Relative side and end views, respectively. Figure 8 The power module 10 has a housing 12, which may include a thermal pad 14, which is located at Figure 3 and Figures 5 to 8 1. Although housing 12 may be molded as described below, other types of housings are also contemplated, such as housings having one or more fabricated or preformed components. Thermal pad 14 is electrically isolated from any internal circuitry and facilitates heat transfer from power module 10 to an unillustrated environment, heat sink structure, or the like. Other reference features in these figures are further described below after the internal architecture of power module 10 is described.

[0051] Figures 9 to 11 Various isometric and plan views of the internal architecture of the power module 10 are shown, with the housing 12 and bond wires BW (or similar interconnects) removed to more clearly illustrate various components of the internal architecture. Figure 12 to Figure 14 Different isometric and plan views of the internal architecture of the power module 10 are shown, wherein the bonding wires BW are in place for the implementation of a three-phase circuit. The following description is initially directed to Figures 9 to 11 , which does not show the bond wires BW, and then transitions to when discussing the connections provided by the bond wires BW Figure 12 to Figure 14 The bond wires BW are generically labeled, but care is taken to clearly describe the connections provided by all shown bond wires BW. Fig.17 and Fig.18 is a plan and isometric view of the top side of the power module 10 with the housing 12 removed.

[0052] refer to Figures 9 to 11 The core of the internal structure is a substrate S, on one side of which a plurality of conductive device pads 18, 20, 22, 24, 26, 28 are formed. A thermal pad 14 is formed on the opposite side, such as Fig.11 The device pads 18-28 and the thermal pad 14 may be formed of any conductive material such as copper. Figure 1A The three-phase circuit of FIG. 1 is shown in FIG. 1 , wherein high-side transistors Q1, Q3, and Q5 are mounted on an elongated device pad 18 that extends along a side adjacent to power terminals V-, V+, U, V, and W. Low-side transistor Q2 is located on device pad 20. Low-side transistor Q6 is located on device pad 24. Low-side transistor Q4 is located on device pad 22. Temperature circuit 16 is located on device pad 26 that is formed on the substrate and, in this embodiment, is located between device pads 20 and 22. Each of device pads 18-26 is electrically isolated from the other device pads.

[0053] In one embodiment, drains D of respective transistors Q1-Q6 are directly attached to respective device pads 18-24 to mechanically and electrically connect transistors Q1-Q6 to device pads 18-24. Temperature circuit 16 may be mechanically and electrically connected to device pad 26 in a similar manner.

[0054] Each terminal can be separated into a power terminal and a signal terminal. As described above, the power terminal includes power terminals V+, V-, U, V and W. The signal terminal includes signal terminals G1-G6, K1-K6, TEMP1, TEMP2. Although each of these terminals can take any shape required to work with the intended application, those terminals shown are suitable for being welded, pressed or snapped into corresponding holes in a printed circuit board (not shown). As shown, direct current (DC) input power terminals V- and V+ and alternating current (AC) output power terminals U, V, W extend from a first side of the power module 10. Signal terminals G1-G6, K1-K6, TEMP1, TEMP2 extend from a second side of the power module 10, wherein the first side of the power module 10 is opposite to the second side of the power module 10.

[0055] There are two power terminals V- at opposite ends of the first side of the power module 10. Each of the power terminals V- extends to opposite ends of the elongated jumper pad J9. The power terminals V- each have a pair of power pins P- and branches L- extending from the power pins P- to the jumper pad J9. In the present embodiment, the power terminals V- are mechanically attached directly to the substrate via the jumper pad J9. Most (if not all) of the branches L- of the power terminals V- are provided with the housing 12, wherein the power pins P- extend to the outside of the housing 12 and are rotated approximately 90 degrees toward the top side of the power module 10.

[0056] The power terminal V+ is between the power terminals V- along a first side of the power module 10, wherein each power terminal V+ is adjacent to a corresponding one of the power terminals V-. The power terminal V+ extends to opposite ends of the device pad 18, such that the transistors Q1, Q3, Q5 and the diodes D1, D3 and D5 are located between the power terminals V+ on the device pad 18. The power terminals V+ each have a pair of power pins P+ and branches L+ extending from the power pins P+ to the device pad 18. Most, if not all, of the branches L+ of the power terminal V+ are disposed with the housing 12, wherein the power pins P+ extend to the exterior of the housing 12 and are rotated approximately 90 degrees toward the top side of the power module 10. In this embodiment, the power terminal V+ is mechanically attached directly to the substrate via the device pad 18.

[0057] Each power terminal U, V, W is located between the power terminal V+ along the first side of the power module 10. Each power terminal U, V, W has a pair of power pins PU, PV, PW and branches LU, LV, LW, respectively. The branches LU, LV, LW do not directly contact any pads on the substrate S. Instead, a set of bonding wires BW is used to facilitate electrical connection.

[0058] Reference now Figure 12 to Figure 14 , which includes bonding wires BW. For power terminal U, a first set of bonding wires BW extends from branch LU of power terminal U to source pad SP on top of transistor Q1 and to jumper pad J3, which is an extension of device pad 20 and is electrically connected to device pad 20. A second set of bonding wires BW extends from branch LU to the anode on top of diode D1 and to jumper pad J3. In this way, the first and second sets of bonding wires BW connect the source of transistor Q1 to the drain of transistor Q2, the anode of diode D1, and power terminal U.

[0059] For the power terminal V, the second set of bonding wires BW extends from the branch LV of the power terminal V to the source pad SP on the top of the transistor Q3 and to the jumper pad J4, which is an extension of the device pad 22 and is electrically connected to the device pad 22. The second set of bonding wires BW extends from the branch LU to the anode on the top of the diode D3 and to the jumper pad J4. Thus, the first and second sets of bonding wires BW connect the source of the transistor Q3 to the drain of the transistor Q4, the anode of the diode D3, and the power terminal V.

[0060] For power terminal W, a third set of bonding wires BW extends from branch LW of power terminal W to source pad SP on top of transistor Q5 and to jumper pad J6, which is an extension of device pad 24 and electrically connected to device pad 24. A second set of bonding wires BW extends from branch LU to the anode on top of diode D5 and to jumper pad J6. In this way, the first and second sets of bonding wires BW connect the source of transistor Q5 to the drain of transistor Q6, the anode of diode D3, and power terminal W.

[0061] The signal terminal G1 is electrically coupled to the gate pad GP of the transistor Q1 through a first bonding wire BW extending from the signal terminal G1 to the jumper pad J1 and a second bonding wire BW extending from the jumper pad J1 to the gate pad GP of the transistor Q1. The first bonding wire BW is coupled to the branch LG1 of the signal terminal G1 at a point opposite to the point of the signal pin PG1.

[0062] The signal terminal K1 is electrically coupled to the source pad SP of the transistor Q1 through a first bonding wire BW extending from the signal terminal K1 to the jumper pad J2 and a second bonding wire BW extending from the jumper pad J2 to the source pad SP of the transistor Q1. The first bonding wire BW is coupled to the branch LK1 of the signal terminal K1 at a point opposite to the point of the signal pin PK1.

[0063] The signal terminal K2 is coupled to the source pad SP of the transistor Q2 via a first bonding wire BW. Additional bonding wires BW are used to couple the source pad SP of the transistor Q2 to a jumper pad J9, which is coupled to the V-terminal. In this embodiment, these additional bonding wires BW may have an intermediate connection to the anode of the diode D2, which is located on the device pad 20, so that the cathode is electrically coupled to the device pad 20. The first bonding wire BW is coupled to the branch LK2 of the signal terminal K2 at a point opposite to the point of the signal pin PK2. The signal terminal G2 is coupled to the gate pad GP of the transistor Q2 via a second bonding wire BW. The second bonding wire BW is coupled to the branch LG2 of the signal terminal G2 at a point opposite to the point of the signal pin PG2.

[0064] As shown, the temperature circuit 16 can be a vertically oriented semiconductor mounted on and in electrical contact with the device pad 26. The signal terminal TEMP1 is coupled to the top contact of the temperature circuit 16 by a first bonding wire BW. The first bonding wire BW is coupled to the branch LT1 of the signal terminal TEMP1 at a point opposite to the point of the signal pin PT1. The signal terminal TEMP2 extends to the device pad 26 and is directly coupled to the device pad 26 without using the bonding wire BW. Therefore, the signal terminal TEMP2 is directly mechanically attached to the substrate via the device pad 26.

[0065] The signal terminal G3 extends to the device pad 26 and is directly coupled to the device pad 26 without using a bonding wire BW. Therefore, the signal terminal G3 is directly mechanically attached to the substrate via the device pad 28. The bonding wire is used to couple the device pad 28 to the gate pad GP of the transistor Q3. The signal terminal K3 is electrically coupled to the source pad SP of the transistor Q3 by a first bonding wire BW extending from the signal terminal K3 to the jumper pad J5 and a second bonding wire BW extending from the jumper pad J5 to the source pad SP of the transistor Q3. The first bonding wire BW is coupled to the branch LK3 of the signal terminal K3 at a point opposite to the point of the signal pin PK3.

[0066] Signal terminal K4 is coupled to source pad SP of transistor Q4 via a first bonding wire BW. Additional bonding wires BW are used to couple source pad SP of transistor Q4 to jumper pad J9, which is coupled to V-terminal. In this embodiment, these additional bonding wires may have an intermediate connection to the anode of diode D4, which is located on device pad 22, so that the cathode is electrically coupled to device pad 22. The first bonding wire BW is coupled to branch LK4 of signal terminal K4 at a point opposite to the point of signal pin PK4. Signal terminal G4 is coupled to gate pad GP of transistor Q4 via a second bonding wire BW. The second bonding wire BW is coupled to branch LG4 of signal terminal G4 at a point opposite to the point of signal pin PG4.

[0067] The signal terminal G5 is electrically coupled to the gate pad GP of the transistor Q5 through a first bonding wire BW extending from the signal terminal G5 to the jumper pad J8 and a second bonding wire BW extending from the jumper pad J8 to the gate pad GP of the transistor Q5. The first bonding wire BW is coupled to the branch LG5 of the signal terminal G5 at a point opposite to the point of the signal pin PG5.

[0068] The signal terminal K5 is electrically coupled to the source pad SP of the transistor Q5 through a first bonding wire BW extending from the signal terminal K5 to the jumper pad J7 and a second bonding wire BW extending from the jumper pad J7 to the source pad SP of the transistor Q5. The first bonding wire BW is coupled to the branch LK5 of the signal terminal K5 at a point opposite to the point of the signal pin PK5.

[0069] Signal terminal K6 is coupled to source pad SP of transistor Q6 via first bonding wire BW. Additional bonding wires BW are used to couple source pad SP of transistor Q6 to jumper pad J9, which is directly coupled to V-terminal. In this embodiment, these additional bonding wires may have an intermediate connection to the anode of diode D6, which is located on device pad 24 so that the cathode is electrically coupled to device pad 24. The first bonding wire BW is coupled to branch LK6 of signal terminal K6 at a point opposite to the point of signal pin PK6. Signal terminal G6 is coupled to gate pad GP of transistor Q6 via first bonding wire BW. The first bonding wire BW is coupled to branch LG6 of signal terminal G6 at a point opposite to the point of signal pin PG6.

[0070] In the illustrated embodiment, the pins P-, P+, U, V, W of the corresponding power terminals V-, V+, U, V, W each have dual pin headers that are staggered with each other. For higher power devices, additional power terminals may be used for the power terminals V-, V+, U, V, W. The first pin header of each power terminal V-, V+, U, V, W is linearly aligned with the first pin headers of the other power terminals V-, V+, U, V, W, and the second pin header of each terminal is linearly aligned with the second pin headers of the other power terminals V-, V+, U, V, W.

[0071] Unlike power terminals V-, V+, U, V, W, in the illustrated embodiment, signal terminals G1-G6, K1-K6, TEMP1, TEMP2 are all terminated with a single pin head. Adjacent pairs of signal terminals are configured so that the pin heads for these signal terminals are staggered. As shown, the pin heads for signal terminals G1, K2, TEMP1, K4, G3, G6, K5 are linearly aligned with each other, while signal terminals K1, G2, TEMP2, G4, K3, K6, G5 are linearly aligned with each other, but staggered with signal terminals G1, K2, TEMP1, K4, G3, G6, K5. Staggering is defined as meaning falling into at least two different planes that are parallel to the side of the housing 12 from which the various terminals extend. In alternative embodiments, the pin heads may all be aligned or staggered in a manner different from that shown in the figure.

[0072] Fig.15 and Fig.16 Two exemplary pin configurations are shown for any of the various pins described above (P+, P-, PU, ​​PV, PW, PG1-PG6, PK1-PK6). Fig.15 The pin P1 has a linear body B that narrows into a linear head H1 that is configured to be inserted into a corresponding hole of a printed circuit board or the like and to be soldered to facilitate mechanical and electrical connection between the printed circuit board and the head H1. Fig.16 Pin P2 of the linear body B has a press-fit head H2 at the end of the linear body B. The press-fit head H2 is designed to compress radially when inserted into the corresponding hole of the printed circuit board to provide a solderless mechanical connection and electrical connection between the printed circuit board and the head H1. Once inserted, the press-fit head will apply an outward radial pressure to fix the press-fit head H2 in the corresponding hole. Depending on the thickness of the metal and the insertion process, a variety of press-fit head styles can be used. Figures 9 to 14 As shown, pin P1 will typically have a bend of approximately 90 degrees (i.e., 80-100 degrees). Fig.15 and Fig.16 2 is shown in order to better illustrate the linear body and configuration of the heads H1, H2.

[0073] like Fig.17 and Fig.18, the lower surface of the substrate S includes a large thermal pad 14 that covers a large portion of the substrate S and is intended to be directly attached to a heat sink, cold plate, or similar heat removal device. Such attachment may be made by bolting with thermal interface materials, metal sintering (silver, copper or other metals), welding, conductive adhesives, welding, or other thermally conductive attachments. Other embodiments of the design may be attached in a similar manner to a gap base plate, which may then be bolted or welded to a cold plate.

[0074] Reference now Fig.19 1-14 is an exploded view of the power module 10 in FIG. Starting from the bottom of the figure, the drain pads of the transistors Q1-Q6 and the temperature circuit 16 are electrically and mechanically attached to the device pads 18-26 on the substrate S using a device attachment material 40. The device attachment material 40 can be a solder, adhesive, sintered metal, laser welding, ultrasonic welding, etc. that provides mechanical structure, high current interconnection and high thermal conductivity. The power terminals V+, V-, U, V, W, the signal terminals G1-G6, K1-K6 and the temperature circuit signal terminals TEMP1, TEMP2 can be formed by a single lead frame 44. As detailed above, the bonding wires BW are used to enable Figure 1A and Figure 1B The lead frame 44 is typically a metal contact strip for high current external connection and internal interconnection. Any contacts are bonded together on a single sheet, usually with multiple products per sheet, and processed as an array before forming and segmenting. The bonding wire BW can be a large diameter wire for ultrasonic or thermoelectric bonding, capable of supporting relatively high current electrical interconnection.

[0075] The housing 12 may be formed using a transfer or injection molding process to provide mechanical structure, high voltage isolation. The housing 12 encapsulates the internal parts of the power module 10. The molding compound used for the housing 12 may be a transfer or compression molded epoxy molding compound (EMC) that can provide mechanical structure, high voltage isolation, coefficient of thermal expansion (CTE) matching, and low moisture absorption.

[0076] like Figure 3 and Figure 8As shown, the thermal pad 14 on the back side of the power module 10 is exposed without covering the housing material. During manufacturing, the epoxy resin used for the housing 12 may penetrate the thermal pad 14 and leave a small amount of flash on the thermal pad 14. In order to ensure that the molding compound or other sealant does not cover the outer surface of the thermal pad 14, a pressing pin can be used to apply pressure to the edge or other surface of the substrate S to enhance the seal to the molding tool. These pins retract as the material solidifies and may leave marks 42 in the compound. The ejector pins are used to release the product from the mold and will also leave small marks. The number and location of the pressing pins and ejector pins will vary based on the design implementation, because more or less of these components may be required as the width of the module changes.

[0077] Clearance and creepage are important aspects of high voltage products. Between conductors at different voltage potentials, clearance is the shortest direct path between them in the air. Creepage is the shortest direct path between them along the surface. Meeting safety standards is challenging and often inconsistent with manufacturing (tooling, epoxy flow, etc.) and product size (footprint and power density). For small transfer molded packages, especially low profile and high voltage SiC-based products, it is necessary to achieve the right balance between module size and voltage safety.

[0078] For creepage, notches 46 and / or ridges 48 may be formed in the housing 12 to increase the surface distance between the various voltage nodes provided by the various signal and power terminals, such as Figure 2 , Figure 3 and Figure 4 and Figure 8 As shown in . Creepage between signal terminals G1-G6, K1-K6, power terminals V+, V-, U, V, W and / or thermal pad 14 can be addressed in a first manner by adding elongated edges 48 and ridges on the surface of the compound or placing elongated grooves between voltage nodes. The specific features will depend on the size and voltage level of a given implementation of the design.

[0079] like Figure 8As shown, notches 46 can be placed between each group of adjacent signal terminals G1 / K1 to G6 / K6 and on either side of a pair of TEMP1 / TEMP2 signal terminals. Additional notches 46 can be placed between adjacent power terminals in power terminals V1-, V+, U, V, W. Mounting notches 52 on the opposite non-terminal side of the housing are also shown. These mounting notches 52 allow the power module 10 to be securely attached to a PCB or other structure using bolts, screws or other fasteners. The mounting notches 52 can also be used as creepage extenders. In the illustrated embodiment, transistors Q1-Q6 are placed in a row on corresponding device pads 18, 20, 22, 24 based on the switch position. The overall layout, length, width, aspect ratio and number of transistors for each switch position can be parametrically changed to scale up or down to the desired output power of the power module 10. Transistors Q1-Q6 and any other devices may be attached by: (1) metal sintering (silver, copper or other metal), (2) soldering, (3) conductive adhesive, or (4) other electrically and thermally conductive attachments. Depending on the sensor technology or nature of the temperature circuit 16, a temperature sensor (represented by the temperature circuit 16) may be included and placed on the isolated device pad 26 shown or directly adjacent to one of the transistors Q1-Q6. The temperature sensor shown is generally attached to transistors Q1-Q6 in a similar manner. Depending on the attachment method, the substrate metal used for the device pads 18-26 may be completely or partially plated with silver, nickel, nickel / gold, or the like, depending on material compatibility.

[0080] Fiducials may be added to aid in automated pick and place of transistors Q1-Q6 and / or any other included components, as well as for subsequent process steps where relative positions need to be determined. Fiducials may be provided by partial plating, etched features or edges, laser marked symbols, or other visually distinguishing features that can be recognized by a machine vision system.

[0081] Typically, there are two types of electrical loops in a power module: a power loop and a signal loop. The power loop is a high voltage, high current path between power terminals V+, V- and through transistors Q1-Q6, for delivering power to a load via the drain (or collector) and source (or emitter) of transistors Q1-Q6, wherein the load is connected to terminals U, V, W of a three-phase circuit. The signal loop is a low voltage, low current path through the gate G1-G6 (or base) and source (or emitter) of transistors Q1-Q6. The gate-source (or base-emitter) signal path actuates transistors Q1-Q6 to effectively turn on or off transistors Q1-Q6. The signal loop may also require source-Kelvin connections K1-K6 of transistors Q1-Q6.

[0082] The power loop effectively runs between power terminals V+, V-. The power terminals V+, V- are typically connected in parallel with a large capacitor across a DC power source such as a battery. Fig. 20 An exemplary power loop for the illustrated power module 10 is shown in FIG. Fig. 20 An exemplary power commutation loop for the three-phase embodiment described above is shown. The internal and external layouts allow power to efficiently enter and leave the power module 10 with effective flux cancellation. Power (1) flows in through the power terminal V+, (2) flows downward to the device pad 18 of the substrate S, (3) flows to the drain D of the high-side transistors Q1, Q3, Q5, (4) flows upward through the high-side transistors Q1, Q3, Q5 to the corresponding source pads SP, (5) flows via the bonding wires BW and the jumper pads J3, J4, J6 to the corresponding device pads 20, 22, 24 of the substrate S, (6) flows to the drain D of the corresponding low-side transistors Q2, Q4, Q6, (7) flows upward through the low-side transistors Q2, Q4, Q6 to the corresponding source pads SP, (8) flows via the bonding wires BW to the jumper pads J9, and (9) flows directly to the power terminal V-. For various outputs, daisy-chain bond wires BW are used to couple power terminals U, V, W to source pads SP of high-side transistors Q1, Q3, Q5, respectively. For each parallel device, the loop is well balanced. The low profile, compact module size, flux cancellation, and balanced loops of the power module 10 result in very low loop inductance and clean, efficient switching.

[0083] The signal loop at each transistor location preferably provides low impedance to minimize voltage stress on the device gate during switching. Although these can be buffered or reduced by adding resistors, this is usually at the expense of increased complexity, higher cost and slower switching speeds. To improve switching performance, the power loop and signal loop can be substantially (if not completely) independent of each other to achieve low switching losses with fast, well-controlled dynamic characteristics.

[0084] In some embodiments, any drain-source (or collector-emitter) and gate-source (or gate-emitter) loops share the same connection at the source (or emitter) of each transistor Q1-Q6. If the power path is coupled into the signal path, additional power is introduced through positive or negative feedback. Typically, negative feedback introduces additional losses when the power path coupling conflicts with the control signal. In essence, the power path coupling attempts to turn off the transistor when the control signal attempts to turn on the transistor. Positive feedback typically causes instability because the power path coupling amplifies the control signal until the transistor is destroyed. Ultimately, any significant coupling of the power and signal paths results in reduced switching quality, slower switching speeds, increased losses, and possible damage.

[0085] Thus, one way to improve switching quality is to ensure independent power and control loops. The power source connection has a separate path from the signal source (called source Kelvin) so that one does not overlap or interfere with the other. The closer the individual connections to transistors Q1-Q6 are, the better the switching performance.

[0086] Fig.21 The internal signal loop of the high side position and the low side position is shown. Here, the gate signal adopts one of two general paths. The first is a straight-through path, which is used for the signal loop associated with the signal terminals G2, G4, and G6, wherein a single bonding wire is used to connect the corresponding signal terminals G2, G4, and G6 to the gate pads GP of transistors Q2, Q4, and Q6. The second path uses a jumper and multiple bonding wires to jump. The signal terminal G1 is connected to the gate pad GP via the jumper pad J1 through two bonding wires. The signal terminal G5 is connected to the gate pad GP via the jumper pad J8 through two bonding wires. The signal terminal G3 is slightly different in that it is directly connected to the device pad 26 and the bonding wire BW connects the device pad 26 to the gate pad GP of the transistor Q3.

[0087] The return Kelvin-source signal takes a similar path. The first is a straight-through path, which is used for the signal loop associated with the signal terminals K2, K4, and K6, where a single bonding wire is used to connect the corresponding signal terminals K2, K4, and K6 to the source pads SP of the transistors Q2, Q4, and Q6. The second path uses jumpers and multiple bonding wire jumps. The signal terminal K1 is connected to the gate pad GP via the jumper pad J1 through two bonding wires. The signal terminal K3 is connected to the source pad SP via the jumper pad J5 using two bonding wires. The signal terminal K5 is connected to the source pad SP via the jumper pad J7 using two bonding wires.

[0088] In the illustrated embodiment, a true Kelvin-source implementation is provided, in which the power and signal loops are completely independent. In some embodiments, transistor devices can be connected in parallel to increase the output current. When connected in parallel, further problems arise in terms of transconductance mismatch between transistor devices. Transconductance is actually the relationship between the current gain of the device - the output current and the input voltage. During the switching process, the input voltage rises and causes a related increase in the output current. If there is a transconductance difference between parallel transistor devices (common in silicon carbide, SiC, power devices), they will each have slightly different conduction characteristics. In the case of different currents flowing through each device, they will have slightly different voltages at both ends of themselves. This voltage mismatch will result in a 'balanced current' flowing between the devices during switching.

[0089] This balancing current will prefer the path of least impedance, which can be through the signal loop rather than the power loop. If the balancing current flows through the signal loop, it will affect the switching quality. Introducing such high, uncontrolled currents through the signal loop may also bring reliability issues because the signal loop is not designed to carry high currents. For these parallel devices, jumper bond wires BW can be connected between their source pads SP to create a very low impedance path for these balancing currents.

[0090] Modularity is a beneficial feature of the concepts described herein. Fig. 22 and Fig.23 As shown, within a given footprint, transistors Q1-Q6 and / or other devices of different sizes may be combined. For a given footprint, Fig. 22 The ratio of transistors Q1-Q6 Fig.23 The smaller and lower power transistors Q1-Q6 are much larger and have higher power. This flexibility allows the designer to optimize the device size and operating parameters for a given system and operating conditions. Because the size of the device is generally related to the overall cost of the power module 10, using the appropriately sized device is key to reducing cost.

[0091] In some embodiments, the substrate S may be widened to accommodate multiple parallel devices, thereby increasing power handling capabilities. Fig.24 and Fig.25 A full fill (where all possible locations are filled) is shown ( Fig.24 ) or fill down ( Fig.25 ) (wherein selected possible locations are not populated). This is a useful technique for tuning the device area for a given application, with the added benefit of not having to develop or manufacture new custom devices. Further embodiments and combinations with different device rotations are envisioned, depending on the bond pad layout, different device sizes, and a greater or smaller number of devices in parallel.

[0092] In addition to being highly modular, the layout of power module 10 can be easily scaled to be as compact as possible for the desired device size and count. Parametric scalability gives product designers many variables to adjust to streamline thermal performance and product size to achieve desired electrical performance parameters.

[0093] As the power module 10 is scaled up or down, the internal layout also scales with it. Since the current will vary based on the total device area, the wider electrical paths are dynamically scaled to appropriately carry the current without excessive resistive losses. Scaling the electrical paths helps ensure that the effective current paths to each device are actually balanced. In some cases, as the size is scaled, the width of the power terminals and the number of power bonding wires can be scaled up or down as needed or desired.

[0094] The concepts disclosed herein provide an optimized three-phase package design for the next generation power module 10. A modular layout is possible, where multiple device areas can be fully or partially populated in the same structure. A scalable layout supports multiple optimized products by simply increasing or decreasing the length and width to achieve the desired power device area and / or size. The layout can be optimized for high current by grouping the power and signal terminals. A straight edge can be used for the power terminal area instead of relying on voltage isolation.

[0095] The architecture provides a logic flow of power with minimal or reduced power loop inductance, which results in clean, efficient switching. The architecture provides a low inductance structure with minimal voltage overshoot to facilitate higher bus voltage and higher voltage operation. The layout also supports paralleling two or more power devices per switch position while providing nearly identical power loop inductance for each power device.

[0096] The signal and power terminals can be arranged and organized by using DC input connections (on one side), AC output connections (on the other side), and signal contacts (by potential grouping). The dual DC input terminal arrangement enables uniform power distribution and low inductance connection to the external bus. The internal layout can be configured to minimize the bond wire distance by direct bonding from the terminals to the device pads.

[0097] The concepts herein also provide the option of forming electrical connections from the power terminals to the power substrate by wire bonding or by direct soldering. Staggered power terminals and signal terminals can provide voltage isolation gaps between different signal terminals and power terminals. Direct plug-in power and signal terminals allow for regularly spaced pin pitches for headers, PCBs, etc.

[0098] The architecture provides a true Kelvin implementation for the signal loop, resulting in clean, efficient switching. Integrated temperature sensors, etc. can be placed close to the power device. The temperature sensor or similar circuit can be placed on an isolated substrate trace (for non-isolated vertical sensors) or on the same trace as the device (for lateral isolated sensors). There is an option for the overcurrent / desaturation signal pin to detect overcurrent events.

[0099] The architecture can reduce costs by minimizing the number of unique parts used, minimizing the area of ​​the power substrate, maximizing the utilization of the semiconductor area, and using volume processing of lead frames, transfer molding, and production automation.

[0100] The power module 10 may have molded voltage creepage extenders on the top and bottom sides of the package. The power module 10 may also have power terminals that may be configured for welding, connection to a header, clamping or welding to a wire, laser welding, or integration with press-fit contacts for solderless connections. The signal terminals may be configured for welding, connection to a header, clamping or welding to a wire, laser welding, or integration with press-fit contacts for solderless connections. The exposed thermal pads on the back of the power module 10 may be configured for permanent silver sintering, copper sintering, or direct welding to a cold plate or heat sink. The edge notches of the molding compound for the housing 14 may act as bolt holes, allowing direct non-permanent bolting to a cold plate or heat sink using thermal interface materials, thermal clearance pads, phase change materials, or the like.

[0101] The concepts provided above solve one, some or all of the above problems to provide a unique and novel power module 10. Those skilled in the art will recognize improvements and modifications to the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein.

Claims

1. A power module, comprising: a substrate comprising a bottom side and a top side, the top side comprising a plurality of device pads; a plurality of power devices mounted on the plurality of device pads and arranged to provide a power circuit having a first input, a second input, and at least one output; at least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; at least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; at least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; as well as A housing is provided for the substrate, the plurality of power devices, and portions of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing.

2. The power module according to claim 1, wherein: The at least one first input power terminal includes a first V-terminal and a second V-terminal extending from the first side of the housing, and the at least one second input power terminal includes a first V+ terminal and a second V+ terminal extending from the first side of the housing.

3. The power module according to claim 2, wherein: The first V+ terminal and the second V+ terminal are between the first V- terminal and the second V- terminal.

4. The power module according to claim 3, wherein: The at least one output power terminal is between the first V+ terminal and the second V+ terminal.

5. The power module according to claim 4, wherein: The at least one output power terminal includes a first output power terminal providing a first output of the power circuit, a second output power terminal providing a second output of the power circuit, and a third output power terminal providing a third output of the power circuit.

6. The power module according to claim 4, further comprising: A plurality of signal terminals are provided to provide a plurality of control signals for the power circuit, wherein portions of the plurality of signal terminals extend from a second side of the housing, the second side being opposite to the first side of the housing.

7. The power module according to claim 6, wherein: The plurality of signal terminals include: a first plurality of gate signal terminals providing gate control signals to gates of a first group of the plurality of power devices and a second plurality of gate signal terminals providing gate control signals to gates of a second group of the plurality of power devices.

8. The power module according to claim 7, wherein: The multiple signal terminals also include: a first plurality of source-Kelvin signal terminals and a second plurality of source-Kelvin signal terminals, the first plurality of source-Kelvin signal terminals providing source-Kelvin control signals to the sources of the first group of the multiple power devices, and the second plurality of source-Kelvin signal terminals providing source-Kelvin control signals to the sources of the second group of the multiple power devices.

9. The power module according to claim 8, wherein: Each gate signal terminal of the first plurality of gate signal terminals is adjacent to a corresponding source-Kelvin signal terminal of the first plurality of source-Kelvin signal terminals, and each gate signal terminal of the second plurality of gate signal terminals is adjacent to a corresponding source-Kelvin signal terminal of the second plurality of source-Kelvin signal terminals.

10. The power module according to claim 9, wherein: The pin headers for the first plurality of gate signal terminals and the second plurality of gate signal terminals and adjacent pairs of first source-Kelvin signal terminals and second source-Kelvin signal terminals are staggered from one another.

11. The power module according to claim 10, wherein: Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin header and a second pin header offset from the first pin header.

12. The power module according to claim 6, wherein: The substrate includes at least one jumper pad, a first bonding wire, and a second bonding wire; and The first bonding wire extends from at least one of the plurality of signal terminals to the at least one jumper pad, and the second bonding wire extends from the at least one jumper pad to the power circuit.

13. The power module according to claim 1, wherein: The at least one first input power terminal or the at least one second input power terminal is directly mechanically coupled to the substrate.

14. The power module according to claim 1, wherein: The at least one first input power terminal and the at least one second input power terminal are directly mechanically coupled to the substrate.

15. The power module according to claim 14, wherein: The at least one output power terminal is not directly mechanically coupled to the substrate, and a bond wire couples the at least one output power terminal to the power circuit.

16. The power module according to claim 15, wherein: At least one of the plurality of signal terminals is directly mechanically coupled to the substrate, and at least another of the plurality of signal terminals is coupled to the power circuit via a bonding wire.

17. The power module according to claim 1, further comprising: A plurality of signal terminals are provided to provide a plurality of control signals for the power circuit, wherein portions of the plurality of signal terminals extend from a second side of the housing opposite to the first side.

18. The power module according to claim 17, wherein: At least one of the plurality of signal terminals is directly mechanically coupled to the substrate, and at least another one of the plurality of signal terminals is coupled to the power circuit via a bonding wire.

19. The power module according to claim 1, further comprising: A thermal pad is located on the bottom side of the substrate, wherein the thermal pad is exposed through the housing.

20. The power module according to claim 1, wherein: The power circuit is a three-phase circuit.

21. The power module according to claim 1, wherein: Notches are recessed into one or more sides of the housing for attaching the power module to another device.

22. The power module according to claim 1, wherein: Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal is terminated with at least one linear pin configured for soldering to another device.

23. The power module according to claim 1, wherein: A creepage extender is disposed on at least one of the top side and the bottom side of the housing.

24. The power module according to claim 1, wherein: In the first side of the housing, at least one notch is provided between adjacent ones of the at least one first input power terminal, the at least one second input power terminal, or the at least one output power terminal.

25. The power module according to claim 1, wherein: The temperature circuit is disposed on the substrate.

26. The power module according to claim 1, wherein: Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin header and a second pin header offset from the first pin header.

27. A power module comprising: a substrate comprising a bottom side and a top side, the top side having a plurality of device pads; a plurality of power devices mounted on the plurality of device pads and arranged to provide a power circuit having a first input, a second input, and at least one output; at least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; at least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; at least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; as well as A housing for the substrate, the plurality of power devices, and portions of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal or the at least one second input power terminal is directly mechanically coupled to the substrate.

28. The power module according to claim 27, wherein: The at least one first input power terminal and the at least one second input power terminal are directly mechanically coupled to the substrate.

29. The power module according to claim 28, wherein: The at least one output power terminal is not directly mechanically coupled to the substrate, and a bond wire couples the at least one output power terminal to the power circuit.

30. The power module according to claim 29, wherein: At least one of the plurality of signal terminals is directly mechanically coupled to the substrate, and at least another of the plurality of signal terminals is coupled to the power circuit via a bonding wire.

31. The power module according to claim 27, further comprising: a plurality of signal terminals, the plurality of signal terminals providing a plurality of control signals for the power circuit, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing, and portions of the plurality of signal terminals extend from a second side of the housing, the second side being opposite to the first side of the housing.

32. The power module according to claim 31, wherein: At least one of the plurality of signal terminals is directly mechanically coupled to the substrate, and at least another one of the plurality of signal terminals is coupled to the power circuit via a bonding wire.

33. A power module comprising: a substrate comprising a bottom side and a top side, the top side having a plurality of device pads; a plurality of power devices mounted on the plurality of device pads and arranged to provide a power circuit having a first input, a second input, and at least one output; at least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; at least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; at least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; as well as A shell, the shell is used for the substrate, the multiple power devices and the at least one first input power terminal, the at least one second input power terminal and the at least one output power terminal, wherein each of the at least one first input power terminal, the at least one second input power terminal and the at least one output power terminal has a first pin head and a second pin head staggered with the first pin head.

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