Triangular-trapezoidal dual-channel shaping algorithm based resistive anode single photon camera

Abstract

The application provides a resistance anode single photon camera based on a triangle-trapezoid dual-channel shaping algorithm, and aims at solving the technical problem that the trapezoidal shaping signal flat top part of the existing resistance anode single photon camera based on a trapezoidal filter shaping algorithm will appear signal superposition phenomenon, which causes the tail wave of the previous pulse to affect the amplitude of the next pulse, and even when the signal superposition is too much, the amplitude extraction and position signal calculation will be affected, and then the imaging resolution of the resistance anode single photon camera is reduced. The resistance anode single photon camera provided by the application digitizes the analog part in the traditional electronics, and introduces a triangle shaping algorithm on the basis of the traditional trapezoidal shaping algorithm, determines the pulse position through the triangle shaping algorithm, and then determines the pulse amplitude through the trapezoidal shaping algorithm, so that the effective pulse peak value under the pulse superposition condition can be more accurately identified, and the spatial resolution of the resistance anode single photon camera is greatly improved.

Description

Technical Field

[0001] This invention relates to single-photon cameras, and more particularly to a resistive anode single-photon camera based on a triangular-trapezoidal dual-channel shaping algorithm. Background Technology

[0002] In research fields such as high-energy particle tracking, aerospace exploration, and biomedical development, optical signals carrying event information contain only a finite number of photons. Therefore, single-photon cameras with photon counting capabilities have become a research hotspot and are widely used in nuclear and particle physics experiments as well as in particle position measurement in X-ray imaging. A single-photon camera mainly consists of an anode detector and an electron readout system. The anode detector mainly includes a photocathode, a microchannel plate (MCP), and a position-sensitive detector (PSD). Its principle is as follows: the photocathode converts the single-photon signal into an electrical signal. When an electron strikes the surface of the MCP, the signal is multiplied to generate an electron cloud. The position-sensitive detector acquires the position information of the electron cloud.

[0003] Position-sensitive detectors can be delay line anodes, wedge-shaped anodes, or resistive anodes, each employing different techniques to determine the position of incident particles. Among these, resistive anodes are widely used in low-light imaging due to their ability to provide good spatial resolution while reducing the number of required electron channels. However, the performance of existing resistive anode-based single-photon cameras is limited by two main components: the front-end resistive anode plate and the back-end electronic readout system. Resistive anode plates have been around for a long time, and their design structure is relatively stable, making further improvements difficult. Therefore, current research on resistive anode single-photon cameras primarily focuses on improving the electronic readout system. Compared to resistive anode plates, the development of electronic readout systems has been slower. Early electronic readout systems directly read the detector output signal and extracted peak values ​​before position decoding. With the development of analog circuit technology, discrete components are now primarily used to construct the filtering and shaping circuits in the electronic readout system to improve the position calculation accuracy of the output signal. However, when a large number of single-photon signals reach the resistive anode plate, pulse accumulation occurs in the output signal of the analog shaping circuit, leading to a decrease in the system count rate and consequently, a reduction in image resolution, failing to meet the ever-increasing detection demands.

[0004] In 2001, Cosimo Imperiale proposed a trapezoidal filter shaping algorithm based on the Z-domain. This algorithm uses the Z-domain expressions of the input and output signals to calculate the system function, thereby suppressing high-frequency noise and achieving system filtering. Pulse signals acquired by an ADC have short rise times, long fall times, and low ballistic loss. Compared to traditional analog shaping circuits, the trapezoidal shaping algorithm offers better energy resolution and a higher count rate. However, due to the randomness of single-photon signals and the tailing effect produced by the preamplifier circuit output, signal superposition occurs in the flat-top portion of the trapezoidal-shaped signal. When this signal superposition occurs, the tail of the previous pulse affects the amplitude of the next pulse. Excessive signal superposition can even affect amplitude extraction and position signal calculation, ultimately reducing the imaging resolution of the resistive anode single-photon camera. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problem that existing resistive anode single-photon cameras based on trapezoidal filter shaping algorithms suffer from signal superposition at the top of the trapezoidal shaped signal, which causes the tail of the previous pulse to affect the amplitude of the next pulse. In some cases, excessive signal superposition can even affect amplitude extraction and position signal calculation, thereby reducing the imaging resolution of the resistive anode single-photon camera. The invention provides a resistive anode single-photon camera based on a triangular-trapezoidal dual-channel shaping algorithm.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] A resistive anode single-photon camera based on a triangular-trapezoidal dual-channel shaping algorithm is characterized by including a resistive anode detector, an electronic readout system, and a host computer; the electronic readout system includes four charge-sensitive amplifier circuits, an ADC module, and a signal processing unit.

[0008] The input terminals of the four charge-sensitive amplifier circuits are respectively connected to the output terminals of the resistive anode detector, which are used to convert the four charge signals output by the resistive anode detector into corresponding voltage signals and amplify them;

[0009] The four input terminals of the ADC module are respectively connected to the output terminals of four charge-sensitive amplifier circuits, which are used to acquire four amplified voltage signals and convert them into corresponding digital signals for output.

[0010] The signal processing unit includes four identical signal processing modules and a position calculation module; the signal processing modules include a trapezoidal shaping module, a triangular shaping module, a baseline recovery module, a trapezoidal peak finding module, a triangular peak finding module, a signal delay module, and a peak output channel;

[0011] The input terminals of the trapezoidal shaping module and the triangular shaping module in each signal processing module are connected to one output terminal of the ADC module, respectively, to perform trapezoidal shaping and triangular shaping on the digital signal output by the ADC module to obtain the corresponding trapezoidal shaped signal and triangular shaped signal.

[0012] The two input terminals of the baseline recovery module are respectively connected to the output terminals of the trapezoidal shaping module and the triangular shaping module, and are used to recover the baseline deviation of the trapezoidal shaped signal and the triangular shaped signal;

[0013] The input of the triangular peak finding module is connected to the first output of the baseline recovery module, and is used to extract the peak value and position of the triangular-shaped signal; the first input of the trapezoidal peak finding module is connected to the second output of the baseline recovery module, and its second input is connected to the position output of the triangular peak finding module, and is used to extract the peak value of the trapezoidal-shaped signal based on the position information of the triangular-shaped signal.

[0014] The three input terminals of the signal delay module are respectively connected to the position output terminal, peak output terminal of the triangular peak finding module, and peak output terminal of the trapezoidal peak finding module for signal synchronization.

[0015] The three input terminals of the peak output channel are respectively connected to the peak output terminal, position output terminal and trapezoidal shape signal of the triangular-shaped signal in the signal delay module. They are used to determine the pulse accumulation situation based on the position information of the triangular-shaped signal, and select to output the peak value of the triangular-shaped signal, the peak value of the trapezoidal shape signal or discard the current signal based on the pulse accumulation situation.

[0016] The four input terminals of the position calculation module are respectively connected to the output terminals of the four peak output channels, and are used to calculate the position coordinates of a single photon based on the four peak values; the input terminal of the host computer is connected to the output terminal of the position calculation module, and is used to complete single-photon imaging based on the position coordinates of the single photon.

[0017] Furthermore, the peak output channel includes a pulse interval calculation module, a first comparison module, a second comparison module, and a decision output module;

[0018] The input terminal of the pulse interval calculation module is connected to the position output terminal of the triangular shaping signal of the signal delay module, and is used to calculate the adjacent pulse interval ΔT based on the position information of two adjacent triangular shaping pulses.

[0019] The first input terminal of the first comparison module is connected to the output terminal of the pulse interval calculation module, and the second input terminal is used to input the sum of the rise time and the flat-top time t of the set trapezoidal shaping signal. b ;

[0020] The first input terminal of the second comparison module is connected to the first output terminal of the first comparison module, and the second input terminal is used to input the set rise time t of the trapezoidal shaping signal. a ;

[0021] The four input terminals of the decision output module are respectively connected to the peak output terminal of the triangular-shaped signal of the signal delay module, the peak output terminal of the trapezoidal-shaped signal, the second output terminal of the first comparison module, and the output terminal of the second comparison module, for use when ΔT≥t b At time t, the peak value of the output trapezoidal shaped signal is at time t a ≤ΔT<t b When the peak value of the output triangular-shaped signal is less than t, a When this happens, discard the current signal;

[0022] The four input terminals of the position calculation module are respectively connected to the output terminals of the corresponding decision output modules in the four signal processing modules.

[0023] Furthermore, the four peak output channels corresponding to the four signal processing modules are defined as channel A, channel B, channel C and channel D, with channel A located at the upper left of the signal processing unit, and channels B, C and D arranged clockwise at 90-degree intervals.

[0024] The position calculation module uses the following formula to calculate the position coordinates (x, y) of a single photon:

[0025]

[0026] In the above formula, V A V B V C V D These represent the peak values ​​of the outputs for channels A, B, C, and D, respectively.

[0027] Furthermore, the trapezoidal shaping module is a high-order IIR filter, and its Z-domain-based system function H(z) is:

[0028]

[0029] in, This indicates that the signal is delayed by n. a Each sampling period, This indicates that the signal is delayed by n. b Each sampling period, z -1 This indicates that the signal is delayed by one sampling period, n a =t a / T s n b =t b / T s Ts The sampling period; τ1 is the fast time constant, and τ2 is the slow time constant;

[0030] The triangular shaping module is a high-order IIR filter, and its Z-domain-based system function H(z)′ is:

[0031]

[0032] Furthermore, the high-order IIR filter of the trapezoidal shaping module is constructed using a four-stage cascade method, including a first-stage subsystem H1(z), a second-stage subsystem H2(z), a third-stage subsystem H3(z), and a fourth-stage subsystem H4(z), whose expressions are as follows:

[0033]

[0034] Where, n c =t c / T s , t c Indicates the duration of the pulse signal;

[0035] The high-order IIR filter of the triangular shaping module is constructed using a four-stage cascade method, including a first-stage subsystem H1(z)′, a second-stage subsystem H2(z)′, a third-stage subsystem H3(z)′, and a fourth-stage subsystem H4(z)′, whose expressions are as follows:

[0036]

[0037] Furthermore, the first-level subsystem H1(z) includes delay1, delay2, delay3, subtractor sub1, subtractor sub2, and adder add1;

[0038] The input terminals of delay units delay1, delay2, and delay3 are all connected to the corresponding output terminals of the ADC module, and are used to delay one digital signal output by the ADC module by n respectively. a n b n c Each sampling period; the first input of subtractor sub1 is connected to the corresponding output of the ADC module, and its second input is connected to the output of delayer delay1; the first input of subtractor sub2 is connected to the output of subtractor sub1, and its second input is connected to the output of delayer delay2; the first input of adder add1 is connected to the output of subtractor sub2, and its second input is connected to the output of delayer delay3, used to enable the first-level subsystem

[0039] The second-level subsystem H2(z) includes a multiplier mux1, a delay unit delay4, and a subtractor sub3;

[0040] The input of the multiplier mux1 is connected to the first output of the adder add1, and its output is connected to the input of the delay unit delay4. The output of the delay unit delay4 is connected to the first input of the subtractor sub3, and the second input of the subtractor sub3 is connected to the second output of the adder add1, so that the second-stage subsystem H2(z) = 1 - α1 -1 ;

[0041] The third-level subsystem H3(z) includes a multiplier mux2, a delay unit delay5, and a subtractor sub4;

[0042] The input of multiplier mux2 is connected to the first output of subtractor sub3, and its output is connected to the input of delay unit delay5. The output of delay unit delay5 is connected to the first input of subtractor sub4, and the second input of subtractor sub4 is connected to the second output of subtractor sub3. This is used to make the third-level subsystem H3(z) = 1 - α2. -1 ;

[0043] The fourth-level subsystem H4(z) includes adder add2, adder add3, multiplier mux3, delayer delay6, and delayer delay7;

[0044] Adders add2, add3, and multiplier mux3 are connected sequentially in input-output order. One input of adder add2 is connected to the output of subtractor sub4. The input of delay unit delay6 is connected to the other output of adder add2, and its output is connected to the other input of adder add2. The input of delay unit delay7 is connected to the other output of adder add3, and its output is connected to the other input of add3. This is used to enable the fourth-level subsystem...

[0045] The first-level subsystem H1(z)′ includes delay1′, delay2′, delay3′, subtractor sub1′, subtractor sub2′, and adder add1′;

[0046] The input terminals of delay1′, delay2′, and delay3′ are all connected to the corresponding output terminals of the ADC module, and are used to delay one digital signal output by the ADC module by n respectively. a n a n cEach sampling period; the first input of the subtractor sub1′ is connected to the corresponding output of the ADC module, and its second input is connected to the output of the delay unit delay1′; the first input of the subtractor sub2′ is connected to the output of the subtractor sub1′, and its second input is connected to the output of the delay unit delay2′; the first input of the adder add1′ is connected to the output of the subtractor sub2′, and its second input is connected to the output of the delay unit delay3′, used to enable the first-stage subsystem

[0047] The second-level subsystem H2(z)′ includes a multiplier mux1′, a delay unit delay4′, and a subtractor sub3′.

[0048] The input of the multiplier mux1′ is connected to the first output of the adder add1′, and its output is connected to the input of the delay unit delay4′. The output of the delay unit delay4′ is connected to the first input of the subtractor sub3′, and the second input of the subtractor sub3′ is connected to the second output of the adder add1′, so as to make the second-stage subsystem H2(z)′=1-α1 -1 ;

[0049] The third-level subsystem H3(z)′ includes a multiplier mux2′, a delayer delay5′, and a subtractor sub4′.

[0050] The input of the multiplier mux2′ is connected to the first output of the subtractor sub3′, and its output is connected to the input of the delay unit delay5′. The output of the delay unit delay5′ is connected to the first input of the subtractor sub4′, and the second input of the subtractor sub4′ is connected to the second output of the subtractor sub3′. This is used to make the third-level subsystem H3(z)′ = 1 - α2. -1 ;

[0051] The fourth-level subsystem H4(z)′ includes adder add2′, adder add3′, multiplier mux3′, delayer delay6′ and delay7′;

[0052] The adders add2', add3', and multiplier mux3' are connected sequentially in input-output order. The input of add2' is connected to the output of subtractor sub4'. The input of delay6' is connected to another output of add2', and its output is connected to another input of add2'. The input of delay7' is connected to another output of add3', and its output is connected to another input of add3'. This is used to enable the fourth-level subsystem...

[0053] Furthermore, the ADC module includes two ADC acquisition circuits;

[0054] The two input terminals of an ADC acquisition circuit are respectively connected to the output terminals of two charge-sensitive amplifier circuits. Its first output terminal is respectively connected to the input terminals of delay1, delay2, delay3, sub1, delay1′, delay2′, delay3′, and sub1′ in the first signal processing module. Its second output terminal is respectively connected to the input terminals of delay1, delay2, delay3, sub1, delay1′, delay2′, delay3′, and sub1′ in the second signal processing module.

[0055] The two input terminals of another ADC acquisition circuit are respectively connected to the output terminals of two other charge-sensitive amplifier circuits. Its first output terminal is respectively connected to the input terminals of delay1, delay2, delay3, sub1, delay1′, delay2′, delay3′, and sub1′ in the third signal processing module. Its second output terminal is respectively connected to the input terminals of delay1, delay2, delay3, sub1, delay1′, delay2′, delay3′, and sub1′ in the fourth signal processing module.

[0056] Furthermore, the signal processing unit is built on an FPGA.

[0057] Furthermore, both the trapezoidal shaping module and the triangular shaping module are implemented using System Generator software.

[0058] The advantages of this invention compared to the prior art are as follows:

[0059] 1. This invention provides a resistive anode single-photon camera based on a triangular-trapezoidal dual-channel shaping algorithm. It digitizes the analog portion of traditional electronics and introduces a triangular shaping algorithm on the basis of the traditional trapezoidal shaping algorithm to form a triangular-trapezoidal dual-channel shaping algorithm. This algorithm first uses the triangular shaping algorithm to determine the pulse position and then uses the trapezoidal shaping algorithm to determine the pulse amplitude. It can more accurately identify the effective pulse peak value under pulse superposition, that is, it can more accurately retain a large number of effective pulse values ​​under pulse superposition, alleviate the decrease in count rate caused by pulse accumulation, greatly improve the spatial resolution of the resistive anode single-photon camera, and improve image quality.

[0060] 2. The triangular-trapezoidal dual-channel shaping algorithm proposed in this invention has good real-time performance, can reduce system latency and improve imaging speed. It can be applied to other electronic readout systems to improve the performance of the corresponding detectors.

[0061] 3. The signal processing unit of this invention is built on FPGA, which can effectively improve system stability and reduce the size of the single-photon camera. Attached Figure Description

[0062] Figure 1 This is a structural block diagram of an embodiment of a resistive anode single-photon camera based on a triangular-trapezoidal dual-channel shaping algorithm according to the present invention;

[0063] Figure 2 This is a structural block diagram of the signal processing module in an embodiment of the present invention;

[0064] Figure 3 The diagrams show the signal waveforms before and after trapezoidal shaping, where (a) is the input signal waveform and (b) is the output trapezoidal shaped signal waveform.

[0065] Figure 4 This is a circuit topology diagram of the four subsystems of the trapezoidal shaping module constructed using a cascaded method in an embodiment of the present invention;

[0066] Figure 5 This is a structural block diagram of the peak output channel in an embodiment of the present invention;

[0067] Figure 6 The following are waveform diagrams of the data processing process of the signal processing module based on the triangular-trapezoidal dual-channel shaping algorithm in this embodiment of the invention: (a) is the waveform diagram of the input signal when pulses are piled up; (b) is the waveform diagram of the signal after pulse piled up is processed by the triangular-trapezoidal dual-channel shaping algorithm; and (c) is the waveform diagram of the extracted peak signal.

[0068] Figure 7 The test image input during the test experiment;

[0069] Figure 8 The waveforms of the input signals from channels A, B, C, and D during the test experiment are shown.

[0070] Figure 9 The images shown are the original input images used in the test experiment and the imaging results processed by different algorithms. (a) is the original input image, (b) is the imaging result of the original input signal, (c) is the imaging result after being shaped by the traditional trapezoidal shaping algorithm, and (d) is the imaging result after being shaped by the triangular-trapezoidal dual-channel shaping algorithm of the present invention.

[0071] Figure 10The images are a comparison diagram of the imaging of a traditional electronic readout system and the electronic readout system based on the triangular-trapezoidal dual-channel shaping algorithm of the present invention. In (a), the left side is the imaging diagram of the traditional electronic readout system and the right side is the corresponding grayscale curve. In (b), the left side is the imaging diagram of the electronic readout system based on the triangular-trapezoidal dual-channel shaping algorithm and the right side is the corresponding grayscale curve.

[0072] The specific reference numerals in the attached figures are as follows:

[0073] 1-Resistor anode detector; 2-Electronic readout system; 21-Call-sensitive amplifier circuit; 22-ADC acquisition circuit; 23-Signal processing module; 231-Trapezoidal shaping module; 232-Triangular shaping module; 233-Baseline recovery module; 234-Trapezoidal peak finding module; 235-Triangular peak finding module; 236-Signal delay module; 237-Peak output channel; 2371-Pulse interval calculation module; 2372-First comparison module; 2373-Second comparison module; 2374-Decision output module; 238-Oscilloscope; 24-Position calculation module; 3-Host computer. Detailed Implementation

[0074] To make the advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0075] like Figure 1 As shown, a resistive anode single-photon camera based on a triangular-trapezoidal dual-channel shaping algorithm includes a resistive anode detector 1, an electronic readout system 2, and a host computer 3. The electronic readout system 2 includes four charge-sensitive amplifier circuits 21, an ADC module, and a signal processing unit. The input terminals of the four charge-sensitive amplifier circuits 21 are respectively connected to the output terminals of the resistive anode detector 1, and are used to convert the four charge signals output by the resistive anode detector 1 into corresponding voltage signals and amplify them.

[0076] The four input terminals of the ADC module are respectively connected to the output terminals of four charge-sensitive amplifier circuits 21, used to acquire four amplified voltage signals and convert them into corresponding digital signals for output. In this embodiment, the ADC module includes two ADC acquisition circuits 22. Specifically, the two input terminals of one ADC acquisition circuit 22 are respectively connected to the output terminals of two of the charge-sensitive amplifier circuits 21, and the two input terminals of the other ADC acquisition circuit 22 are respectively connected to the output terminals of the other two charge-sensitive amplifier circuits 21. In other embodiments of the present invention, the ADC module can also be configured as four ADC acquisition circuits, each corresponding to one charge-sensitive amplifier circuit.

[0077] The signal processing unit, as the core of the single-photon camera, includes four identical signal processing modules 23 and a position calculation module 24. Considering that signal superposition occurs at the top of the trapezoidal-shaped signal, causing the tail of the previous pulse to affect the amplitude of the next pulse, and even affecting amplitude extraction and position signal calculation when there is too much signal superposition, while the triangular shaping algorithm can better determine the position of the pulse amplitude during pulse accumulation, this invention proposes a new triangular-trapezoidal dual-channel shaping algorithm. This algorithm divides the input signal into two paths for processing: one path executes the trapezoidal shaping algorithm, and the other path executes the triangular shaping algorithm.

[0078] like Figure 2 As shown, each signal processing module 23 includes a trapezoidal shaping module 231, a triangular shaping module 232, a baseline recovery module 233, a trapezoidal peak finding module 234, a triangular peak finding module 235, a signal delay module 236, and a peak output channel 237.

[0079] The trapezoidal shaping module 231 and the triangular shaping module 232 are used to shape the digital signal input from the corresponding ADC acquisition circuit 22 through two channels, namely the trapezoidal shaping channel and the triangular shaping channel, respectively, to obtain the corresponding trapezoidal shaped signal and triangular shaped signal.

[0080] The trapezoidal shaping module 231 calculates the system function of the trapezoidal shaping algorithm using the Z-domain expressions of the input and output signals. Define A as the pulse height of the charge-sensitive amplifier circuit 21, which is proportional to the energy of the input signal. τ1 is the fast time constant, and τ2 is the slow time constant. The time constants are affected by the charge-sensitive amplifier circuit 21, and their specific values ​​are obtained by curve fitting and averaging multiple signal acquisitions. For the input signal, T... s Sampling is performed for a sampling period and the Z-transform is implemented, where

[0081] like Figure 3 The image shows the signal waveforms before and after shaping using the trapezoidal shaping algorithm. Figure 3 (a) in the diagram is the waveform of the input signal, which is a bilateral negative exponential signal. Figure 3 (b) in the diagram shows the waveform of the output trapezoidal-shaped signal. The Z-domain expression of the input signal is then:

[0082]

[0083] The time-domain expression of the output trapezoidal-shaped signal is:

[0084]

[0085] Where A is the amplitude of the trapezoidal shaped signal. This indicates that the signal is delayed by n.a Each sampling period, This indicates that the signal is delayed by n. b Each sampling period, z -1 This indicates that the signal is delayed by one sampling period, t c n represents the duration of the pulse signal. a =t a / T s n b =t b / T s , t a The rise time t represents the trapezoidal-shaped signal. b This represents the sum of the rise time and the flat top time of the shaped signal.

[0086] The system function of the trapezoidal shaping algorithm can be expressed as H(z) = V out (z) / V in (z) is used for calculation, resulting in formula (3):

[0087]

[0088] The trapezoidal shaping algorithm is essentially a high-order IIR filter that can effectively suppress high-frequency noise and achieve system filtering. This embodiment uses a four-stage cascade method to construct the high-order IIR filter of the trapezoidal shaping module 231, that is, it is decomposed into four subsystems in a cascaded manner, including a first-stage subsystem H1(z), a second-stage subsystem H2(z), a third-stage subsystem H3(z), and a fourth-stage subsystem H4(z), whose expressions are as follows:

[0089]

[0090] Where, n c =t c / T s , t c This indicates the flat-top time of the trapezoidal shaping signal.

[0091] The signal processing unit of this invention is built on an FPGA, using Xilinx's Artix7 FPGA for the design of the overall trapezoidal and triangular shaping algorithms, and implementing the overall trapezoidal and triangular shaping algorithms using System Generator software. Figure 4The diagram shows the circuit topology of the four subsystems of a trapezoidal shaping module constructed using a cascaded method. The first-stage subsystem H1(z) includes delay units delay1, delay2, delay3, subtractors sub1 and sub2, and adder add1. The inputs of delay units delay1, delay2, and delay3 are all connected to the corresponding outputs of the respective ADC sampling circuits, used to delay one digital signal output from the ADC sampling circuit by n respectively. a n b n c Each sampling period; the first input of subtractor sub1 is connected to the corresponding output of the ADC sampling circuit, and its second input is connected to the output of delay unit delay1; the first input of subtractor sub2 is connected to the output of subtractor sub1, and its second input is connected to the output of delay unit delay2; the first input of adder add1 is connected to the output of subtractor sub2, and its second input is connected to the output of delay unit delay3, used to enable the first-stage subsystem The second-level subsystem H2(z) includes a multiplier mux1, a delay unit delay4, and a subtractor sub3. The input of multiplier mux1 is connected to the first output of adder add1, and its output is connected to the input of delay unit delay4. The output of delay unit delay4 is connected to the first input of subtractor sub3, and the second input of subtractor sub3 is connected to the second output of adder add1. This is used to make the second-level subsystem H2(z) = 1 - α1. -1 The third-level subsystem H3(z) includes a multiplier mux2, a delay unit delay5, and a subtractor sub4. The input of multiplier mux2 is connected to the first output of subtractor sub3, and its output is connected to the input of delay unit delay5. The output of delay unit delay5 is connected to the first input of subtractor sub4, and the second input of subtractor sub4 is connected to the second output of subtractor sub3. This is used to make the third-level subsystem H3(z) = 1 - α2. -1 The fourth-level subsystem H4(z) includes adder add2, adder add3, multiplier mux3, delay unit delay6, and delay unit delay7. Adder add2, add3, and multiplier mux3 are connected sequentially in the order of input and output. One input of adder add2 is connected to the output of subtractor sub4. The input of delay unit delay6 is connected to the other output of adder add2, and its output is connected to the other input of adder add2. The input of delay unit delay7 is connected to the other output of adder add3, and its output is connected to the other input of add3. This is used to enable the fourth-level subsystem... Ultimately, trapezoidal shaping of the input signal is achieved to obtain the corresponding trapezoidal shaped signal.

[0092] The construction ideas of the triangular shaping module 232 and the trapezoidal shaping module 231 are similar. When t in the trapezoidal shaping algorithm a =t b When this happens, the output is a triangular-shaped signal (a special trapezoidal-shaped signal). Correspondingly, the triangular-shaped module 232 is a high-order IIR filter, and its Z-domain-based system function H(z)′ is:

[0093]

[0094] The triangular shaping module 232 is decomposed into four subsystems for a high-order IIR filter using a cascaded approach: the first-stage subsystem H1(z)′, the second-stage subsystem H2(z)′, the third-stage subsystem H3(z)′, and the fourth-stage subsystem H4(z)′, whose expressions are as follows:

[0095]

[0096] The circuit topology of the four subsystems of the triangular shaping module differs from that of the four subsystems of the trapezoidal shaping module only in the first-level subsystem H1(z)′. Specifically, the first-level subsystem H1(z)′ of the triangular shaping module includes delay units delay1′, delay2′, delay3′, subtractors sub1′, subtractors sub2′, and adder add1′. The input terminals of delay units delay1′, delay2′, and delay3′ are all connected to the corresponding output terminals of the ADC module, used to delay one digital signal output by the ADC module by n respectively. a n a n c Each sampling period; the first input of subtractor sub1′ is connected to the corresponding output of the ADC module, and its second input is connected to the output of delayer delay1′; the first input of subtractor sub2′ is connected to the output of subtractor sub1′, and its second input is connected to the output of delayer delay2′; the first input of adder add1′ is connected to the output of subtractor sub2′, and its second input is connected to the output of delayer delay3′, used to enable the first-stage subsystem

[0097] The first input terminal of the baseline recovery module 233 is connected to the output terminal of the trapezoidal shaping module 231, and its second input terminal is connected to the output terminal of the triangular shaping module 232, which is used to recover the baseline deviation of the trapezoidal shaping signal and the triangular shaping signal.

[0098] The input terminal of the triangular peak finding module 235 is connected to the first output terminal of the baseline recovery module 233, and is used to extract the peak value and position of the triangular-shaped signal. The first input terminal of the trapezoidal peak finding module 234 is connected to the second output terminal of the baseline recovery module 233, and its second input terminal is connected to the position output terminal of the triangular peak finding module 235, and is used to extract the peak value of the trapezoidal-shaped signal based on the position information of the triangular-shaped signal input to the triangular peak finding module 235.

[0099] The three input terminals of the signal delay module 236 are respectively connected to the position output terminal, peak output terminal of the triangular peak finding module 235 and the peak output terminal of the trapezoidal peak finding module 234, and are used to synchronize the triangular shaped signal and the trapezoidal shaped signal.

[0100] Peak output channel 237 is used to determine pulse accumulation based on the position information of the triangular-shaped signal, and selects to output the peak value of the triangular-shaped signal, the peak value of the trapezoidal-shaped signal, or discard the current signal based on the pulse accumulation. For example... Figure 5 As shown, the peak output channel 237 includes a pulse interval calculation module 2371, a first comparison module 2372, a second comparison module 2373, and a decision output module 2374. The input terminal of the pulse interval calculation module 2371 is connected to the position output terminal of the triangular-shaped signal of the signal delay module 236, and is used to calculate the adjacent pulse interval ΔT based on the position information of two adjacent triangular-shaped pulses. The first input terminal of the first comparison module 2372 is connected to the output terminal of the pulse interval calculation module 2371, and the second input terminal is used to input the sum t of the rise time and the flat-top time of the set trapezoidal-shaped signal. b The first input terminal of the second comparison module 2373 is connected to the first output terminal of the first comparison module 2372, and the second input terminal is used to input the rise time t of the set trapezoidal shaping signal. a The four input terminals of the decision output module 2374 are respectively connected to the peak output terminal of the triangular-shaped signal, the peak output terminal of the trapezoidal-shaped signal of the signal delay module 236, the second output terminal of the first comparison module 2372, and the output terminal of the second comparison module 2373, for use in cases where ΔT≥t b At time t, the peak value of the output trapezoidal shaped signal is at time t a ≤ΔT<t b When the peak value of the output triangular-shaped signal is less than t, a When that happens, discard the current signal.

[0101] like Figure 6 The diagram shown is a schematic of the signal processing module based on a triangular-trapezoidal dual-channel shaping algorithm. Figure 6 (a) in the figure is the waveform of the input signal when pulses are piled up. Figure 6(b) in the figure shows the signal waveform after pulse stacking is processed using the triangular-trapezoidal dual-channel shaping algorithm. Figure 6 (c) in the figure is the waveform of the extracted peak signal.

[0102] For ease of observation, this embodiment also includes a built-in oscilloscope 238 in each signal processing module, used to acquire the output signals of the ADC sampling circuit, baseline recovery module 233 and peak output channel 237 respectively.

[0103] The four input terminals of the position calculation module 24 are respectively connected to the output terminals of the corresponding decision output modules 2374 in the four signal processing modules, and are used to calculate the position coordinates of a single photon based on the four peak values. The four peak output channels 237 in the four signal processing modules 23 are defined as channel A, channel B, channel C, and channel D, with channel A located at the upper left of the signal processing unit, and channels B, C, and D arranged clockwise at 90-degree intervals. The formula for calculating the position coordinates (x, y) of the single photon is as follows:

[0104]

[0105]

[0106] In the above formula, V A V B V C V D These represent the peak values ​​of the outputs for channels A, B, C, and D, respectively.

[0107] The single-photon position coordinates (x, y) output by the position calculation module 24 are stored in DDR3 (double-data-rate three synchronous dynamic random access memory) via the AXI (Advanced Extensible Interface) bus. Then, the single-photon position coordinate information stored in DDR3 is transmitted to the host computer 3 via Ethernet, where the coordinates are visualized to complete single-photon imaging.

[0108] The following specific tests further illustrate the shaping effect of the present invention based on the triangular-trapezoidal dual-channel shaping algorithm. For example... Figure 7 As shown, the input test image is a 256*256 pixel grayscale image. The input grayscale image is converted into a matrix for data storage. Then, the data is binarized. White areas are considered valid regions, with pixels set to 1, while black areas have pixels set to 0. The location information (x, y, y) of pixels with a value of 1 is recorded. i ,y i ).

[0109] The electronic readout system determines the position coordinates of a single photon using peak information from four channels, converting these coordinates into amplitude data for four channels (A, B, C, and D). During algorithm testing, the position coordinates of the single photons are known, and the amplitude information corresponding to each single photon's position coordinate is inferred by using the single photon position coordinate calculation formula. The input test image consists of 2551 valid pixels, such as... Figure 8 The figure shows the input signal waveforms for channels A, B, C, and D. Each channel contains 2551 bilateral negative exponential signals. The bilateral negative exponential signals in each channel are then randomly superimposed to construct the input signals for the four channels based on the amplitude information.

[0110] To evaluate the applicability of the triangular-trapezoidal dual-channel shaping algorithm of this invention in processing pulse accumulation, signals exhibiting pulse accumulation were shaped using both the traditional trapezoidal shaping algorithm and the triangular-trapezoidal dual-channel shaping algorithm. The peak values ​​of the unprocessed original input signal, the trapezoidal-shaped signal after traditional trapezoidal shaping, and the triangular-trapezoidal-shaped signal after triangular-trapezoidal dual-channel shaping were extracted. The number of peak signals extracted for each group of signals is shown in Table 1.

[0111] Table 1 Peak Extraction Comparison Table

[0112]

[0113] As can be seen, due to pulse accumulation, the number of peak signals extracted from the unprocessed raw input signal is relatively small, with only 69.38% of the peak signals being identified. A large number of pulses carrying positional information are not identified and are therefore discarded, resulting in severe degradation of image quality. In contrast, the extraction rates using the traditional trapezoidal shaping algorithm and the triangular-trapezoidal dual-channel shaping algorithm of this invention are 77.81% and 83.38%, respectively. The triangular-trapezoidal dual-channel shaping algorithm effectively improves the counting rate of accumulated pulses. Compared to using no algorithm or relying solely on the trapezoidal shaping algorithm, the counting rate of the triangular-trapezoidal dual-channel shaping algorithm is increased by 12.15% and 20.17%, respectively, effectively shortening the imaging time and improving image quality.

[0114] Figure 9 (a) is the original input image. Figure 9 (b) shows the imaging result of the original input signal. Figure 9 (c) is the imaging result after shaping using the traditional trapezoidal shaping algorithm. Figure 9(d) shows the imaging result after being shaped using the triangular-trapezoidal dual-channel shaping algorithm of this invention. It can be seen that the original input signal can only recover 1216 pixels, accounting for 47% of the total pixels, resulting in an unsatisfactory imaging effect. Traditional trapezoidal shaping algorithms effectively improve the counting rate, but errors exist in amplitude extraction when the trapezoidal-shaped signal accumulates, leading to a large number of noise points in the image. Only 1472 pixels (57% of the total pixels) are recovered, resulting in unsatisfactory imaging quality. In contrast, the triangular-trapezoidal shaping algorithm of this invention accurately extracts peak data while effectively improving the counting rate and reducing positioning errors, ultimately recovering 1852 pixels, accounting for 72.6% of the total pixels. Compared to unprocessed signals and signals processed solely using the trapezoidal shaping algorithm, the pixel recovery of the triangular-trapezoidal shaping algorithm is improved by 52.3% and 20.5% respectively, achieving excellent image restoration results and significantly improving image quality.

[0115] like Figure 10 As shown, the imaging images of the conventional electronic readout system and the electronic readout system based on the triangular-trapezoidal dual-channel shaping algorithm of this invention are compared. Using the commonly used USAF 1951 resolution test target to measure the imaging resolution of the single-photon camera, the imaging resolution of the single-photon camera with the conventional electronic readout system can reach 12.7 LinePairs / mm. The electronic readout circuit of this invention can effectively improve the imaging resolution of the single-photon camera to 20.1 LinePairs / mm. Figure 10 The graph on the right shows the grayscale distribution of a selected region (rows 221, columns 137-159) and its effect on image contrast. Traditional electronic readout systems have low contrast, with a measured value of 61.5%. The electronic readout circuit of this invention significantly improves contrast, reaching 90.9%, enhancing the visual effect and detail of the image. In summary, incorporating the triangular-trapezoidal dual-channel shaping algorithm into the electronic readout system effectively improves the resolution and contrast of the final image, thereby enhancing image quality.

[0116] The above description is only used to illustrate the technical solutions of the present invention, and is not intended to limit them. For those skilled in the art, modifications can be made to the specific technical solutions described in the above embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions protected by the present invention.

Claims

1. A resistive anode single-photon camera based on a triangular-trapezoidal dual-channel shaping algorithm, characterized in that: It includes a resistive anode detector (1), an electronic readout system (2), and a host computer (3); the electronic readout system (2) includes four charge-sensitive amplifier circuits (21), an ADC module, and a signal processing unit; The input terminals of the four charge-sensitive amplifier circuits (21) are respectively connected to the output terminals of the resistive anode detector (1) to convert the four charge signals output by the resistive anode detector (1) into corresponding voltage signals and amplify them. The four input terminals of the ADC module are respectively connected to the output terminals of four charge-sensitive amplifier circuits (21) to collect the four amplified voltage signals and convert them into corresponding digital signals for output. The signal processing unit includes four identical signal processing modules (23) and a position calculation module (24); the signal processing module (23) includes a trapezoidal shaping module (231), a triangular shaping module (232), a baseline recovery module (233), a trapezoidal peak finding module (234), a triangular peak finding module (235), a signal delay module (236), and a peak output channel (237); The input terminals of the trapezoidal shaping module (231) and the triangular shaping module (232) in each signal processing module (23) are connected to one of the output terminals of the ADC module, respectively, to perform trapezoidal shaping and triangular shaping on the digital signal output by the ADC module to obtain the corresponding trapezoidal shaped signal and triangular shaped signal. The baseline recovery module (233) has two input terminals connected to the output terminals of the trapezoidal shaping module (231) and the triangular shaping module (232), respectively, for baseline deviation recovery of the trapezoidal and triangular shaped signals; The input of the triangular peak finding module (235) is connected to the first output of the baseline recovery module (233) and is used to extract the peak value and position of the triangular-shaped signal; the first input of the trapezoidal peak finding module (234) is connected to the second output of the baseline recovery module (233), and its second input is connected to the position output of the triangular peak finding module (235) and is used to extract the peak value of the trapezoidal-shaped signal based on the position information of the triangular-shaped signal. The three input terminals of the signal delay module (236) are respectively connected to the position output terminal, peak output terminal of the triangular peak finding module (235) and the peak output terminal of the trapezoidal peak finding module (234) for signal synchronization; The three input terminals of the peak output channel (237) are respectively connected to the peak output terminal of the triangular-shaped signal, the position output terminal and the peak output terminal of the trapezoidal-shaped signal in the signal delay module (236), and are used to determine the pulse accumulation situation according to the position information of the triangular-shaped signal, and select to output the peak value of the triangular-shaped signal, output the peak value of the trapezoidal-shaped signal or discard the current signal according to the pulse accumulation situation. The four input terminals of the position calculation module (24) are respectively connected to the output terminals of the four peak output channels (237) for calculating the position coordinates of a single photon based on the four peak values; the input terminal of the host computer (3) is connected to the output terminal of the position calculation module (24) for completing single-photon imaging based on the position coordinates of the single photon. The trapezoidal shaping module (231) is a high-order IIR filter, which is constructed using a four-stage cascade method, including a first-stage subsystem H1(z), a second-stage subsystem H2(z), a third-stage subsystem H3(z), and a fourth-stage subsystem H4(z), the expressions of which are as follows: Where, n c =t c / T s , t c Indicates the duration of the pulse signal; The first-level subsystem H1(z) includes delay1, delay2, delay3, subtractor sub1, subtractor sub2, and adder add1; The input terminals of delay units delay1, delay2, and delay3 are all connected to the corresponding output terminals of the ADC module, and are used to delay one digital signal output by the ADC module by n respectively. a n b n c Each sampling period; the first input of subtractor sub1 is connected to the corresponding output of the ADC module, and its second input is connected to the output of delayer delay1; the first input of subtractor sub2 is connected to the output of subtractor sub1, and its second input is connected to the output of delayer delay2; the first input of adder add1 is connected to the output of subtractor sub2, and its second input is connected to the output of delayer delay3, used to enable the first-level subsystem The second-level subsystem H2(z) includes a multiplier mux1, a delay unit delay4, and a subtractor sub3; The input of the multiplier mux1 is connected to the first output of the adder add1, and its output is connected to the input of the delay unit delay4. The output of the delay unit delay4 is connected to the first input of the subtractor sub3, and the second input of the subtractor sub3 is connected to the second output of the adder add1, so that the second-stage subsystem H2(z) = 1 - α1 -1 ; The third-level subsystem H3(z) includes a multiplier mux2, a delay unit delay5, and a subtractor sub4; The input of multiplier mux2 is connected to the first output of subtractor sub3, and its output is connected to the input of delay unit delay5. The output of delay unit delay5 is connected to the first input of subtractor sub4, and the second input of subtractor sub4 is connected to the second output of subtractor sub3. This is used to make the third-level subsystem H3(z) = 1 - α2. -1 ; The fourth-level subsystem H4(z) includes adder add2, adder add3, multiplier mux3, delayer delay6, and delayer delay7; Adders add2, add3, and multiplier mux3 are connected sequentially in input-output order. One input of adder add2 is connected to the output of subtractor sub4. The input of delay unit delay6 is connected to the other output of adder add2, and its output is connected to the other input of adder add2. The input of delay unit delay7 is connected to the other output of adder add3, and its output is connected to the other input of add3. This is used to enable the fourth-level subsystem...

2. The resistive anode single-photon camera based on the triangular-trapezoidal dual-channel shaping algorithm according to claim 1, characterized in that: The peak output channel (237) includes a pulse interval calculation module (2371), a first comparison module (2372), a second comparison module (2373), and a decision output module (2374); The input terminal of the pulse interval calculation module (2371) is connected to the position output terminal of the triangular shaping signal of the signal delay module (236), and is used to calculate the adjacent pulse interval ΔT based on the position information of two adjacent triangular shaping pulses. The first input terminal of the first comparison module (2372) is connected to the output terminal of the pulse interval calculation module (2371), and the second input terminal is used to input the sum of the rise time and the flat-top time t of the set trapezoidal shaping signal. b ; The first input terminal of the second comparison module (2373) is connected to the first output terminal of the first comparison module (2372), and the second input terminal is used to input the rise time t of the set trapezoidal shaping signal. a ; The four input terminals of the decision output module (2374) are respectively connected to the peak output terminal of the triangular-shaped signal, the peak output terminal of the trapezoidal-shaped signal of the signal delay module (236), the second output terminal of the first comparison module (2372), and the output terminal of the second comparison module (2373), for use in cases where ΔT≥t b At time t, the peak value of the output trapezoidal shaped signal is at time t a ≤ΔT<t b When the peak value of the output triangular-shaped signal is less than t, a When this happens, discard the current signal; The four input terminals of the position calculation module (24) are respectively connected to the output terminals of the corresponding decision output modules (2374) in the four signal processing modules (23).

3. The resistive anode single-photon camera based on the triangular-trapezoidal dual-channel shaping algorithm according to claim 2, characterized in that: The four peak output channels (237) in the four signal processing modules (23) are defined as channel A, channel B, channel C and channel D, respectively. Channel A is located in the upper left position of the signal processing unit, and channels B, C and D are arranged in a clockwise direction with a 90-degree interval between them. The position calculation module (24) calculates the position coordinates (x, y) of a single photon using the following formula: In the above formula, V A V B V C V D These represent the peak values ​​of the outputs for channels A, B, C, and D, respectively.

4. The resistive anode single-photon camera based on the triangular-trapezoidal dual-channel shaping algorithm according to claim 3, characterized in that: The trapezoidal shaping module (231) has the following system function H(z) based on the Z-domain: in, This indicates that the signal is delayed by n. a Each sampling period, This indicates that the signal is delayed by n. b Each sampling period, z -1 This indicates that the signal is delayed by one sampling period, n a =t a / T s n b =t b / T s T s The sampling period; τ1 is the fast time constant, and τ2 is the slow time constant; The triangular shaping module (232) is a high-order IIR filter, and its Z-domain-based system function H(z)′ is:

5. The resistive anode single-photon camera based on the triangular-trapezoidal dual-channel shaping algorithm according to claim 4, characterized in that: The high-order IIR filter of the triangular shaping module (232) is constructed using a four-stage cascade method, including a first-stage subsystem H1(z)′, a second-stage subsystem H2(z)′, a third-stage subsystem H3(z)′, and a fourth-stage subsystem H4(z)′, whose expressions are as follows:

6. The resistive anode single-photon camera based on the triangular-trapezoidal dual-channel shaping algorithm according to claim 5, characterized in that: The first-level subsystem H1(z)′ includes delay1′, delay2′, delay3′, subtractor sub1′, subtractor sub2′, and adder add1′; The input terminals of delay1′, delay2′, and delay3′ are all connected to the corresponding output terminals of the ADC module, and are used to delay one digital signal output by the ADC module by n respectively. a n a n c Each sampling period; the first input of the subtractor sub1′ is connected to the corresponding output of the ADC module, and its second input is connected to the output of the delay unit delay1′; the first input of the subtractor sub2′ is connected to the output of the subtractor sub1′, and its second input is connected to the output of the delay unit delay2′; the first input of the adder add1′ is connected to the output of the subtractor sub2′, and its second input is connected to the output of the delay unit delay3′, used to enable the first-stage subsystem The second-level subsystem H2(z)′ includes a multiplier mux1′, a delay unit delay4′, and a subtractor sub3′. The input of the multiplier mux1′ is connected to the first output of the adder add1′, and its output is connected to the input of the delay unit delay4′. The output of the delay unit delay4′ is connected to the first input of the subtractor sub3′, and the second input of the subtractor sub3′ is connected to the second output of the adder add1′, so as to make the second-stage subsystem H2(z)′=1-α1 -1 ; The third-level subsystem H3(z)′ includes a multiplier mux2′, a delayer delay5′, and a subtractor sub4′. The input of the multiplier mux2′ is connected to the first output of the subtractor sub3′, and its output is connected to the input of the delay unit delay5′. The output of the delay unit delay5′ is connected to the first input of the subtractor sub4′, and the second input of the subtractor sub4′ is connected to the second output of the subtractor sub3′. This is used to make the third-level subsystem H3(z)′ = 1 - α2. -1 ; The fourth-level subsystem H4(z)′ includes adder add2′, adder add3′, multiplier mux3′, delayer delay6′, and delayer delay7′. The adders add2', add3', and multiplier mux3' are connected sequentially in input-output order. The input of add2' is connected to the output of subtractor sub4'. The input of delay6' is connected to another output of add2', and its output is connected to another input of add2'. The input of delay7' is connected to another output of add3', and its output is connected to another input of add3'. This is used to enable the fourth-level subsystem...

7. The resistive anode single-photon camera based on the triangular-trapezoidal dual-channel shaping algorithm according to claim 6, characterized in that: The ADC module includes two ADC acquisition circuits (22); The two input terminals of an ADC acquisition circuit (22) are respectively connected to the output terminals of two charge-sensitive amplifier circuits (21). Its first output terminal is respectively connected to the input terminals of delay1, delay2, delay3, sub1, delay1′, delay2′, delay3′, and sub1′ in the first signal processing module (23). Its second output terminal is respectively connected to the input terminals of delay1, delay2, delay3, sub1, delay1′, delay2′, delay3′, and sub1′ in the second signal processing module. The two input terminals of another ADC acquisition circuit (22) are respectively connected to the output terminals of two other charge-sensitive amplifier circuits (21). Its first output terminal is respectively connected to the input terminals of delay1, delay2, delay3, sub1, delay1′, delay2′, delay3′, and sub1′ in the third signal processing module (23). Its second output terminal is respectively connected to the input terminals of delay1, delay2, delay3, sub1, delay1′, delay2′, delay3′, and sub1′ in the fourth signal processing module.

8. The resistive anode single-photon camera based on the triangular-trapezoidal dual-channel shaping algorithm according to claim 1, characterized in that: The signal processing unit is built on an FPGA.

9. The resistive anode single-photon camera based on the triangular-trapezoidal dual-channel shaping algorithm according to claim 8, characterized in that: Both the trapezoidal shaping module (231) and the triangular shaping module (232) are implemented using System Generator software.

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