Channel PI Calibration Device and Testing Machine
The channel PI calibration apparatus addresses the challenge of reliable PI calibration in semiconductor testing by using internal feedback loops to adjust and measure phase changes, ensuring accurate channel alignment without external instruments, thus reducing costs and enabling simultaneous multi-channel calibration.
Patent Information
- Application Number
- CN202411932769.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2044-12-26
AI Technical Summary
In the prior art, the calibration of channel PI has reliability problems, especially under the influence of temperature, clock deviation, voltage fluctuation and other factors between the chip batch and the channel, it is difficult to achieve accurate phase adjustment and calibration.
A channel PI calibration device is designed, including a waveform control module, a PI control module, a transceiver module, a PI measurement module and a protocol analysis module. Through the internal calibration process, square wave pattern data and phase adjustment are used to realize reliable calibration of PI and avoid errors introduced by external instruments and instruments.
Reliable calibration of channel PI is achieved, reducing calibration costs, improving calibration reliability, and supporting simultaneous calibration of multiple test channels, simplifying the calibration process.
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Figure CN119355501B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor testing technologies, and particularly to a channel PI calibration device and a tester. Background Art
[0002] Semiconductor automatic testing refers to using automatic test equipment (ATE) to detect various parameter indicators of a device under test (DUT), and rejecting defective products to control the ex-factory quality of semiconductors. In the resource board of a tester, a phase interpolator (PI) is provided on the transmitting side. Its main function is to perform phase adjustment on the data transmitted within the resource board and align the phases between channels, so that each channel can transmit data according to a set phase at the starting stage of data transmission. Especially during the process of transmitting high-speed signal pattern data, it is necessary to adjust the phase relationship between two channels, and at this time, PI is required to perform fine phase adjustment on the channels. Due to chip batches, different channels of the same chip, as well as temperature, clock deviation, and voltage fluctuation, all will cause deviations from the theoretical value of PI, and it is necessary to calibrate the theoretical values between each channel. Therefore, how to achieve reliable calibration of channel PI is an urgent problem to be solved. Summary of the Invention
[0003] Based on this, in view of the above problems, it is necessary to provide a channel PI calibration device and a tester that can improve the reliability of calibration.
[0004] A first aspect of this application provides a channel PI calibration device, including:
[0005] A waveform control module, connected to a transceiver module, generating square wave pattern data according to a configuration command issued by a host computer and sending it to the transceiver module;
[0006] A PI control module, connected to the transceiver module, configuring a PI adjustment value for the transceiver module according to a configuration command issued by a host computer;
[0007] The transceiver module, connected to a pin circuit module, performing phase adjustment on the received transmission clock according to the configured PI adjustment value, and sending the square wave pattern data to the pin circuit module according to the clock after phase adjustment;
[0008] A PI measurement module, connected to the pin circuit module, receiving the signal returned by the pin circuit module for continuous sampling to obtain sampling result data; the sampling result data is used to analyze the change amount of PI.
[0009] In one embodiment, the waveform control module generates square wave pattern data according to the configuration command issued by the host computer and stores it in the internal buffer unit. After receiving the transmission command issued by the host computer, the waveform control module sends the square wave pattern data in the internal buffer unit to the transceiver module. The transmission command is that the host computer issues a configuration command to the PI control module, configures the PI adjustment value for the transceiver module, and then issues it.
[0010] In one embodiment, the transceiver module performs parallel-to-serial conversion on the square wave pattern data according to the phase-adjusted clock and outputs a differential signal to the pin circuit module.
[0011] In one embodiment, the PI measurement module converts the differential signal returned by the pin circuit module into a single-ended signal, performs multi-level sampling on the single-ended signal according to the sampling clock and starts timing according to the reference clock, generates a rising edge according to two consecutive sampled signals, stops sampling until the timing reaches the set sampling preset value, and counts the number of rising edges obtained by sampling to obtain the sampling value. The change amount of PI is calculated according to the sampling value, the period of the sampling clock, and the sampling preset value.
[0012] In one embodiment, the channel PI calibration device further includes:
[0013] A clock processing module, connected to the transceiver module and the PI measurement module, receives an external initial clock signal for processing, outputs the transmission clock to the transceiver module, and outputs the sampling clock and the reference clock to the PI measurement module.
[0014] In one embodiment, the PI measurement module performs an AND operation on the non-signal of the latter-stage signal and the former-stage signal among two consecutive sampled signals of non-first stage to obtain a rising edge.
[0015] In one embodiment, the calculation formula for the change amount of PI is: 。
[0016] In one embodiment, the channel PI calibration device further includes:
[0017] A protocol analysis module, connected to the pin circuit module, configures the register parameters of the pin circuit module according to the configuration command issued by the host computer.
[0018] In one embodiment, the tester includes a plurality of test channels, and each of the test channels is provided with the waveform control module, the PI control module, the transceiver module, the PI measurement module, the protocol analysis module, and the pin circuit module.
[0019] The second aspect of the present application provides a testing machine, including a host computer and the above-mentioned channel PI calibration device.
[0020] For the above-mentioned channel PI calibration device and the testing machine, the waveform control module generates square wave pattern data according to the configuration command issued by the host computer and sends it to the transceiver module; the PI control module configures the PI adjustment value for the transceiver module according to the configuration command issued by the host computer; the transceiver module adjusts the phase of the received transmission clock according to the configured PI adjustment value, and sends the square wave pattern data to the pin circuit module according to the clock after phase adjustment; the PI measurement module receives the signal returned by the pin circuit module for continuous sampling to obtain sampling result data for analyzing the change amount of PI. It can realize the calibration of different channels of PI, and uses internal calibration of the testing machine, without the need to rely on external instruments, avoiding the introduction of new errors due to the access of external instruments, improving the calibration reliability and reducing the calibration cost. Description of the Drawings
[0021] Figure 1 It is a structural block diagram of the channel PI calibration device in an embodiment;
[0022] Figure 2 It is a structural schematic diagram of the channel PI calibration device in an embodiment;
[0023] Figure 3 It is a timing diagram of the PI measurement module for continuous sampling of signals in an embodiment. Detailed Embodiments
[0024] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0026] It can be understood that "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is an electrical signal or data transmission between the connected circuits, modules, units, etc.
[0027] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
[0028] In one embodiment, as Figure 1 shown, a channel PI calibration device is provided, including a waveform control module 110, a PI control module 120, a transceiver module 130, and a PI measurement module 140. The waveform control module 110 is connected to the transceiver module 130 and generates square wave pattern data according to the configuration command issued by the host computer and sends it to the transceiver module 130; the PI control module 120 is connected to the transceiver module 130 and configures the PI adjustment value for the transceiver module 130 according to the configuration command issued by the host computer; the transceiver module 130 is connected to the pin circuit module (Pin Electronics Driver / Comparator, PE) 200, adjusts the phase of the received transmission clock according to the configured PI adjustment value, and sends the square wave pattern data to the pin circuit module 200 according to the clock after phase adjustment; the PI measurement module 140 is connected to the pin circuit module 200, receives the signal returned by the pin circuit module 200 for continuous sampling, and obtains the sampled result data; the sampled result data is used to analyze the change amount of PI. Among them, the PI measurement module 140 may return the change amount of PI analyzed from the sampled result data to the host computer, or upload the sampled result data to the host computer, and the host computer analyzes the change amount of PI according to the sampled result data. In addition, as Figure 2 shown, the channel PI calibration device further includes a protocol parsing module 150. The protocol parsing module 150 is connected to the pin circuit module 200 and configures the register parameters of the pin circuit module 200 according to the configuration command issued by the host computer.
[0029] Among them, the waveform control module 110, the PI control module 120, the transceiver module 130, the PI measurement module 140, and the protocol parsing module 150 can be set on the same FPGA (Field Programmable Gate Array). The tester includes multiple test channels. For each test channel, a waveform control module 110, a PI control module 120, a transceiver module 130, a protocol parsing module 150, and a pin circuit module 200 can be set. One PI measurement module 140 can be configured for each test channel, or one can be shared by some or all of the test channels. The host computer can be connected to the waveform control module 110, the PI control module 120, and the protocol parsing module 150 through the HBUS bus, issue configuration commands to perform waveform configuration, PI adjustment value configuration, and register parameter configuration of the pin circuit module 200 respectively, and receive the analysis of the sampling result data returned by the PI measurement module 140 to obtain the change amount of PI. The host computer only needs to issue configuration commands and receive sampling result data, and PI calibration can be performed simultaneously between test channels.
[0030] Specifically, as Figure 2 shown, after the host computer issues a configuration command to the protocol parsing module 150 through the HBUS bus, the protocol parsing module 150 performs protocol parsing, restores the HBUS bus data into SPI (Serial Peripheral Interface) bus data, and sends it to the register inside the pin circuit module 200 through the SPI interface to configure the comparison voltage, level mode, and compare channel mode of the pin circuit module 200.
[0031] In one embodiment, the waveform control module 110 generates square wave pattern data according to the configuration command issued by the host computer and stores it in the internal cache unit. After receiving the send command issued by the host computer, the waveform control module 110 sends the square wave pattern data in the internal cache unit to the transceiver module 130; the send command is that the host computer issues a configuration command to the PI control module 120, configures the PI adjustment value for the transceiver module 130, and then issues it.
[0032] Specifically, the internal cache unit can be a FIFO (First In First Out) unit or other storage units. The host computer sends configuration commands through the HBUS bus to cause the waveform control module 110 to generate square wave pattern data and store it in the internal FIFO unit. Then, the host computer sends a configuration command to the PI control module 120 through the HBUS bus again to control the PI control module 120 to configure the adjustment value of the phase regulator in the transceiver module 130 (normally, the PI adjustment value is 0). Finally, the host computer sends a transmission command to the waveform control module 110 through the HUBS bus to send the square wave pattern data in the FIFO unit to the transceiver module 130.
[0033] Specifically, the transceiver module 130 can be a gigabit transceiver. After the PI adjustment value is configured, the transceiver module 130 can perform a phase-locked loop process on the incoming transmission clock and adjust the phase of the clock after the phase-locked loop process according to the PI adjustment value, or directly adjust the phase of the incoming transmission clock according to the PI adjustment value. After the transceiver module 130 performs parallel-to-serial conversion on the square wave pattern data according to the phase-adjusted clock, it outputs differential signals to the pin circuit module 200. The pin circuit module 200 converts the received differential signals into single-ended signals, performs a voltage comparison on the single-ended signals according to the configured comparison voltage, then compares the comparison result signals according to the configured register parameters through the compare channel, converts the obtained square wave signals into differential signals, and returns them to the PI measurement module 140 through the LVDS (Low-Voltage Differential Signaling) interface. After the square wave pattern data sent by the transceiver module 130 reaches the pin circuit module 200, it is not sent outwards but looped back to the PI measurement module 140 inside the FPGA for data sampling.
[0034] Furthermore, the PI measurement module 140 converts the differential signals returned by the pin circuit module 200 into single-ended signals, performs multi-level sampling on the single-ended signals according to the sampling clock and starts timing according to the reference clock, generates rising edges according to two consecutive sampled signals until the timing reaches the set sampling preset value and then stops sampling, and counts the number of rising edges obtained from the acquisition to obtain the sampling value; among them, the change amount of the PI is calculated according to the sampling value, the period of the sampling clock, and the sampling preset value.
[0035] Specifically, the PI measurement module 140 can access the differential signal through the internal IBUFDS (input buffer) primitive block to convert it into a single-ended signal, and then continuously perform multi-level sampling using the sampling clock and start timing according to the reference clock. The rising edge is generated using every two adjacent levels of signals until the sampling stops after the timing reaches the set sampling preset value. The number of rising edges collected is counted to obtain the sampling value, which is uploaded to the host computer as the sampling result data. The frequencies of the sampling clock and the reference clock are not unique. For example, the sampling clock can be a 400M clock, and the reference clock can be a 200M clock. The reference clock can be the same as or different from the transmission clock used by the transceiver module 130. In this embodiment, the signals obtained by multi-level sampling are all rectangular wave signals. The PI measurement module 140 samples the rising edge of the first-level rectangular wave signal according to the sampling clock and counts according to the reference clock at the same time. When the count reaches the sampling preset value according to the reference clock, the sampling according to the sampling clock stops, and the sampling value is determined.
[0036] Further, the PI measurement module 140 performs an AND operation on the non-signal of the latter-level signal and the former-level signal among two continuously sampled levels of non-first-level signals to obtain the rising edge. As Figure 3 shown, the PI measurement module 140 continuously performs multi-level sampling according to the sampling clock. To avoid interference with signal acquisition due to fluctuations in the first-level signal, starting from the second-level signal, the non-signal of the latter-level signal and the former-level signal among every two adjacent levels of signals are AND-operated to obtain the signal rising edge. After the count reaches the sampling preset value (for example, counting 20,000 times) according to the reference clock, the PI measurement module 140 stops signal acquisition, and the number of signal rising edges collected is used as the sampling value and uploaded to the host computer for calculating the change amount of PI. It can be understood that in other embodiments, the PI measurement module 140 can also directly calculate the change amount of PI based on the sampling value and then upload it to the host computer. Specifically, the change amount of PI, that is, the phase change amount of each PI calibration, is calculated by the formula:
[0037]
[0038] For example, the transceiver module 130 sends a 150M square wave, and the actual rate of the transceiver module 130 is 4.8G. After continuously configuring the PI adjustment value to 1, the 150M square wave becomes a 149.96345M square wave, and the cycle parameter after adjustment has a slight change. If sampled 20,000 times, this slight change amount will be amplified, and the amplified amount is divided by 20,000 times, thereby averaging the slight amount to obtain the change amount of PI.
[0039] After calculating the change amount of PI once, the host computer can also send a configuration command again to change the PI adjustment value configured in the transceiver module 130, perform multiple PI calibrations on each test channel. For example, the PI adjustment value is configured as 1, 2, 3, ……, etc. in sequence, gradually change the PI adjustment value, and control the phase adjustment amplitude of the transceiver module 130. Continuously sample the continuous signal using the PI measurement module 140 under different PI adjustment values to obtain the change amount corresponding to the new PI adjustment value, and finally determine the change amount corresponding to each PI adjustment value.
[0040] In addition, the channel PI calibration device may further include a clock processing module. The clock processing module is connected to the transceiver module 130 and the PI measurement module 140, receives an external initial clock signal for processing, outputs a transmission clock to the transceiver module 130, and outputs a sampling clock and a reference clock to the PI measurement module 140. Among them, the clock processing module can be set inside the FPGA or outside the FPGA. Specifically, the clock processing module can be connected to the waveform generation device, receive the initial clock signal sent by the waveform generation device, divide the frequency of the initial clock signal, and send the required different frequency clocks to the transceiver module 130 and the PI measurement module 140.
[0041] In one embodiment, a channel PI calibration method is also provided, including: the waveform control module generates square wave pattern data according to the configuration command issued by the host computer and sends it to the transceiver module; the PI control module configures the PI adjustment value for the transceiver module according to the configuration command issued by the host computer; the transceiver module adjusts the phase of the received transmission clock according to the configured PI adjustment value, and sends the square wave pattern data to the pin circuit module according to the clock after phase adjustment; the PI measurement module receives the signal returned by the pin circuit module for continuous sampling to obtain sampling result data; the sampling result data is used to analyze the change amount of PI.
[0042] In one embodiment, the method further includes: after the waveform control module generates square wave pattern data according to the configuration command issued by the host computer, it stores the data in the internal cache unit, and after receiving the transmission command issued by the host computer, it sends the square wave pattern data in the internal cache unit to the transceiver module; the transmission command is issued by the host computer after issuing the configuration command to the PI control module to configure the PI adjustment value for the transceiver module.
[0043] In one embodiment, the method further includes: after the transceiver module performs parallel-to-serial conversion on the square wave pattern data according to the clock after phase adjustment, it outputs a differential signal to the pin circuit module.
[0044] In one embodiment, the method further includes: the PI measurement module converts the differential signal returned by the pin circuit module into a single-ended signal, performs multi-level sampling on the single-ended signal according to the sampling clock and starts timing according to the reference clock, generates a rising edge based on two consecutively sampled signals, and stops sampling until the timing reaches the set sampling preset value, and counts the number of rising edges obtained by sampling to obtain the sampling value; wherein, the change amount of PI is calculated according to the sampling value, the period of the sampling clock, and the sampling preset value.
[0045] In one embodiment, the method further includes: the PI measurement module performs an AND operation on the non-signal of the latter-stage signal and the former-stage signal among two consecutively sampled signals of non-first stage to obtain a rising edge.
[0046] In one embodiment, the method further includes: the clock processing module receives an external initial clock signal for processing, outputs a transmission clock to the transceiver module, and outputs a sampling clock and a reference clock to the PI measurement module.
[0047] In one embodiment, the method further includes: the protocol parsing module configures the register parameters of the pin circuit module according to the configuration command issued by the host computer.
[0048] It can be understood that the specific embodiments of the above channel PI calibration method have been explained in detail in the above channel PI calibration device, and will not be repeated here.
[0049] In one embodiment, a tester is further provided, which includes a host computer and the above channel PI calibration device. The host computer can be but is not limited to various personal computers, laptop computers, smart phones, tablet computers, and portable wearable devices, and the portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, etc. In addition, the tester may further include a waveform generating device for providing an initial clock signal. The waveform generating device can specifically be a direct digital synthesizer (DDS), or can be an arbitrary waveform generator (AWG) or other devices.
[0050] The above channel PI calibration device, method, and tester continuously configure the PI adjustment value, causing the transmitted square wave code pattern data to have a continuous phase change, indicating that the signal period changes. By continuously sampling the change amount of the period, the tiny change amount is amplified, and then the change amounts are accumulated and divided by the accumulated amount, and finally the tiny phase change amount of each PI adjustment is deduced. This solution has the following advantages:
[0051] 1. Internal calibration is adopted, eliminating the need for additional instruments and meters, saving costs and avoiding introducing new errors due to the connection of instruments and meters.
[0052] 2. The calibration time is fast, allowing multiple test channels to be calibrated together.
[0053] 3. The calibration process is simple, only requiring register configuration and not relying on auxiliary devices such as other test boards.
[0054] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.
[0055] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A channel PI calibration device, characterized in that, Comprising: A waveform control module, connected to the transceiver module, generating square wave pattern data according to the configuration command issued by the host computer and sending it to the transceiver module; A PI control module, connected to the transceiver module, configuring the PI adjustment value for the transceiver module according to the configuration command issued by the host computer; The transceiver module, connected to the pin circuit module, performing phase adjustment on the received transmission clock according to the configured PI adjustment value, and sending the square wave pattern data to the pin circuit module according to the clock after phase adjustment; A PI measurement module, connected to the pin circuit module, receiving the signal returned by the pin circuit module for continuous sampling, and obtaining the sampled result data after the small change in PI adjustment is amplified; the sampled result data is used to analyze the change amount of PI and determine the change amount corresponding to different PI adjustment values; Wherein, the PI measurement module converts the differential signal returned by the pin circuit module into a single-ended signal, performs multi-level sampling on the single-ended signal according to the sampling clock and starts timing according to the reference clock, generates a rising edge according to two consecutive sampled signals, and stops sampling until the timing reaches the set sampling preset value, and counts the number of rising edges obtained by sampling to obtain the sampled value; Wherein, the change amount of PI is calculated according to the sampled value, the period of the sampling clock, and the sampling preset value.
2. The device according to claim 1, wherein The waveform control module generates square wave pattern data according to the configuration command issued by the host computer and stores it in the internal buffer unit, and after receiving the transmission command issued by the host computer, sends the square wave pattern data in the internal buffer unit to the transceiver module; the transmission command is issued by the host computer after configuring the PI adjustment value for the transceiver module by issuing the configuration command to the PI control module.
3. The device according to claim 1, characterized in that, The transceiver module performs parallel-to-serial conversion on the square wave pattern data according to the clock after phase adjustment, and outputs a differential signal to the pin circuit module.
4. The device according to claim 1, characterized in that, The transceiver module is a gigabit transceiver.
5. The device according to claim 4, characterized in that, Further comprising: A clock processing module, connected to the transceiver module and the PI measurement module, receiving an external initial clock signal for processing, outputting the transmission clock to the transceiver module, and outputting the sampling clock and the reference clock to the PI measurement module.
6. The device according to claim 4, characterized in that, The PI measurement module performs an AND operation on the non-signal of the latter-stage signal and the former-stage signal among two consecutive sampled signals of non-first stage to obtain a rising edge.
7. The device according to claim 4, characterized in that, The calculation formula for the change in PI is as follows: .
8. The device according to any one of claims 1-7, characterized in that, Further comprising: A protocol parsing module, connected to the pin circuit module, configuring the register parameters for the pin circuit module according to the configuration command issued by the host computer.
9. The device according to claim 8, characterized in that, The test machine includes a plurality of test channels, and each of the test channels is provided with the waveform control module, the PI control module, the transceiver module, the PI measurement module, the protocol parsing module, and the pin circuit module.
10. A testing machine, characterized in that, Including a host computer and the channel PI calibration device according to any one of claims 1-9.
Citation Information
Patent Citations
Multi-channel synchronizing signal generator
CN102129269A
Interchannel delay deviation measuring device
CN222070764U