A test circuit

Abstract

A test circuit includes: a module to be isolated; a scan register module including a scan chain formed by cascading N scan registers; a data selection module including a first input end and a second input end, wherein the N scan registers select an input signal or a scan signal from the input end of the module to be isolated to the first input end of the data selection module under the control of a scan enable signal; the second input end of the data selection module is connected to the output end of the module to be isolated, and the data selection module selects one of the input data for output under the control of a test mode signal; and a peripheral circuit connected to the input end of the module to be isolated and / or the output end of the data selection module. The present application isolates the module to be isolated by scanning the register module, and the output circuit can directly receive the input signal instead of the X-state output signal output by the module to be isolated, thereby improving the accuracy of circuit testing.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and particularly relates to a test circuit. Background Art

[0002] With the development of the integrated circuit industry, the chip integration degree is getting higher and higher, the logic scale is getting larger and larger, and the working mode is getting more and more complex. There are problems such as long test time and low test coverage. Therefore, DFT (Design for Testability) testing is required.

[0003] In the existing DFT test solutions, there are usually some off-the-shelf IPs in chip design, such as various PHY (Physical Layer) chips. When performing DFT digital logic testing, since these IPs are in black box structures, the input and output signals will be in the X state, and the propagation of the X state will affect the test coverage of the surrounding circuits.

[0004] For example Figure 1 As shown, the values of the input signals in0 / in1 / in2 of the PHY chip cannot be observed, so the input circuits AND0 / XOR / OR of the PHY chip are all unobservable, and the previous-stage drivers of AND0 / XOR / OR are also unobservable; in addition, since the outputs out0 / out1 / out2 of the PHY are in the X state, the outputs of the next-stage logic circuits Gating0 / BUF0 / AND1 driven by it may also be in the X state, and the next-stage circuits driven by Gating0 / BUF0 / AND1 are also unmeasurable due to the influence of the X state; this will lead to a large number of unmeasurable risks in the logic around the PHY chip, greatly affecting the test quality.

[0005] In the prior art, to solve the above problems, mostly a single flip-flop or multiple separate flip-flops are used to cache signals. However, a single flip-flop cannot cache and output multiple input signals simultaneously, and multiple separate flip-flops cannot be compressed, which requires a large circuit design area. Moreover, neither a single flip-flop nor multiple separate flip-flops can avoid the situation of mixing and chaining with the registers of other modules in the circuit; in addition, neither a single flip-flop nor multiple separate flip-flops can output the cached input signals completely independently. If the complete input signals cannot be observed separately, the defects in the circuit design process cannot be discovered and repaired in time, greatly increasing the uncontrollability and unobservability of the circuit design. Summary of the Invention

[0006] In this application, the module to be isolated is isolated by a scan register module. A scan chain formed by cascading N scan registers selects the input signal at the input end of the module to be isolated to a data selection module under the control of a scan enable signal, and directly outputs it to an output circuit through the data selection module. The output circuit can directly receive the input signal at the input end of the module to be isolated instead of the X-state output signal output by the module to be isolated, improving the correct rate of circuit testing.

[0007] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or part or all of the above objects or other objects, the present invention provides a test circuit.

[0009] A test circuit includes:

[0010] A module to be isolated;

[0011] A scan register module including a scan chain formed by cascading N scan registers;

[0012] A data selection module including a first input end and a second input end. The N scan registers select the input signal or the scan signal at the input end of the module to be isolated to the first input end of the data selection module under the control of a scan enable signal; the second input end of the data selection module is connected to the output end of the module to be isolated, and the data selection module selects one of the input data for output under the control of a test mode signal; and a peripheral circuit connected to the input end of the module to be isolated and / or the output end of the data selection module;

[0013] Wherein, N is a positive integer not less than 1.

[0014] The multiple input signals of the module to be isolated are sequentially connected to the data input ends of each of the scan registers in sequence;

[0015] The data output ends of each of the scan registers are correspondingly output to the first input end of the data selection module according to the input signal of the module to be isolated received by the scan register.

[0016] The input signal at the input end of the module to be isolated is subjected to combinational logic processing and then sequentially input into the data input ends of the N scan registers in sequence.

[0017] The scan register module further includes:

[0018] A scan signal input end electrically connected to the scan input end of the first-stage scan register to provide a scan signal;

[0019] The scan enable signal input terminal is electrically connected to the scan enable terminals of N scan registers, and controls the scan registers to select the input signal or the scan signal of the module to be isolated for input;

[0020] The scan clock signal input terminal is electrically connected to the scan clock terminals of N scan registers, and provides a scan clock signal;

[0021] The scan output terminal is electrically connected to the data output terminal of the last-stage scan register, and shifts and outputs the input signal of the module to be isolated captured.

[0022] The scan register includes a multiplexer controlled by the scan enable signal, and a D flip-flop connected to the output terminal of the multiplexer;

[0023] The scan clock signal is connected to the clock signal interface of the D flip-flop.

[0024] The working process of the scan register module includes:

[0025] In the shift input stage, the scan enable signal controls the multiplexer to select the scan signal and shift it into the N scan registers of the scan register module one by one;

[0026] In the capture stage, the multiplexers in the N scan registers select the input signal of the module to be isolated for input under the control of the scan enable signal and output it to the corresponding D flip-flop;

[0027] In the shift output stage, under the control of the scan clock signal, the input signal of the module to be isolated cached in the D flip-flops in the N scan registers is output to the data selection module through the data output terminals, and at the same time, it is output bit by bit to the scan output terminal.

[0028] The scan signal is a signal sequence corresponding to the scan clock signal.

[0029] The working process of the scan register module further includes:

[0030] The shift input stage of the next scan cycle is carried out simultaneously with the shift output stage of the previous scan cycle.

[0031] The data selection module includes N data selection units, and the data selection unit is a multiplexer;

[0032] The test mode signal controls the multiplexer to select the data at the first input terminal or the second input terminal for output.

[0033] The peripheral circuit includes,

[0034] An input circuit connected to the input end of the module to be isolated, and / or an output circuit connected to the output end of the data selection module;

[0035] The input circuit is electrically connected to the input signal interface of the module to be isolated, and different input signals are input to the module to be isolated. The different input signals are transmitted to the data selection module through the scan register module;

[0036] The output end of the data selection module is electrically connected to the output circuit, and under the control of the test mode signal, the data at the first input end or the second input end is selected and output to the output circuit.

[0037] Compared with the prior art, the beneficial effects of the present invention mainly include:

[0038] 1. In this application, the N scan registers select the input signal or the scan signal at the input end of the module to be isolated to the first input end of the data selection module under the control of the scan enable signal; the data selection module selects one of the input data for output under the control of the test mode signal. In this way, the scan chain formed by cascading N scan registers in this application selects the input signal at the input end of the module to be isolated to the data selection module under the control of the scan enable signal. The input signal at the input end of the module to be isolated can be directly output to the output circuit through the data selection module, and the output circuit can directly receive the input signal at the input end of the module to be isolated, so as to isolate the module to be isolated through the scan register module, shield the influence of the X-state output signal, and improve the accuracy of circuit testing.

[0039] Since the output end of the module to be isolated is connected to the second input end of the data selection module, the data selection module can directly propagate the output of the module to be isolated to the peripheral circuit under the control of the test mode signal without affecting the realization of the original logic function of the circuit.

[0040] 2. This application increases the scanning function of the input signal of the module to be isolated by designing a scan chain formed by cascading N scan registers, and can realize the individual observation of the input signal. The designer can quickly and effectively detect and repair the defects in the circuit design process through the observed input signal, reduce the dependence on external test equipment, reduce the circuit design cost, and can avoid the problem that the input signal X-state cannot be observed, shorten the test time, and improve the observability of the circuit; on the basis of observation, the scan chain can realize the control input of the input signal under the control of the scan enable signal, not only realizing the isolation of the module to be isolated, but also realizing the controllability of the design, greatly improving the flexibility and effectiveness of the test; in addition, the scan register module also supports the automatic test mode. Since all scan registers can be accessed through the scan chain, it is convenient for the application of test vectors, and the test coverage of the peripheral circuit is improved on the basis of isolating the X-state signal.

[0041] 3. This application connects N scan registers in series to form a scan chain, which is isolated from other modules of the circuit. Users can add or delete scan registers in the scan chain according to the actual situation of the input signal. While the circuit design is more flexible, there is no need to consider the impact on other modules of the circuit design. It can also be selected to compress or not compress according to the actual design requirements. The integration method is very flexible, greatly reducing the circuit design area and avoiding the situation of mixed serial chains with registers of other modules, reducing the impact brought by other modules in the circuit design.

[0042] 4. The scan signal output by the scan register module of this application enters the data selection module, and the data selection module outputs the scan signal to the peripheral circuit. The test vector of the scan signal will be used as the test excitation for the registers in the peripheral circuit, ensuring that the registers and their related circuits in the peripheral circuit can be effectively tested, improving the testability of the registers in the peripheral circuit at the output port of the data selection module, and further increasing the test coverage rate.

[0043] To make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0045] Figure 1 It is a schematic diagram of the input / output circuit of the PHY chip.

[0046] Figure 2 It is a schematic diagram of a test circuit provided by an embodiment of this application Figure 1 .

[0047] Figure 3 It is a schematic diagram of a test circuit provided by an embodiment of this application Figure 2 .

[0048] Figure 4 It is a timing diagram of a test circuit provided by an embodiment of this application.

[0049] Among them, D is the data input terminal of the SDFF, SI is the scan input terminal of the SDFF, SE is the scan enable terminal of the SDFF, CP is the scan clock terminal of the SDFF, and Q is the data output terminal of the SDFF. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or rear, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0051] In this application, the module to be isolated is isolated by the scan register module. The scan chain formed by cascading N scan registers selects the input signal at the input end of the module to be isolated to the data selection module under the control of the scan enable signal, and directly outputs it to the output circuit through the data selection module. The output circuit can directly receive the input signal at the input end of the module to be isolated instead of the X-state output signal output by the module to be isolated, improving the correct rate of circuit testing.

[0052] However, those of ordinary skill in the art can understand that in various embodiments of this application, many technical details are proposed to help readers better understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0053] Embodiment:

[0054] As Figure 2 shown, a test circuit includes: a module to be isolated, a scan register module connected to the module to be isolated, a data selection module, and a peripheral circuit.

[0055] Specifically, as Figure 3 shown, the peripheral circuit includes an input circuit connected to the input end of the module to be isolated, and / or an output circuit connected to the output end of the data selection module.

[0056] In this embodiment, the module to be isolated is a black box module in the circuit, and its input and output signals are in the X state (unknown state) (such as Figure 3 the PHY chip in), the input circuit AND0 / XOR / OR in the peripheral circuit is the previous-stage driver of the module to be isolated and cannot be observed; the output circuit Gating0 / BUF0 / AND1 in the peripheral circuit is the next-stage logic circuit driven by the module to be isolated, and is affected by the output signals Out0 / Out1 / Out2 of the module to be isolated which may be in the X state and cannot be observed either; therefore, there are a large number of unmeasurable risks in the upper and lower logic circuits of the module to be isolated, and the module to be isolated needs to be isolated.

[0057] In this embodiment, the input end of the module to be isolated is connected to the input circuits AND0 / XOR / OR and the scan register module in the peripheral circuit, and the output end is connected to the data selection module. The output end of the data selection module is connected to the output circuits Gating0 / BUF0 / AND1 in the peripheral circuit.

[0058] Specifically, the input circuits AND0 / XOR / OR in the peripheral circuit are electrically connected to the input signal interface of the module to be isolated, and different input signals In0 / In1 / In2 are input to the module to be isolated. The different input signals In0 / In1 / In2 are transmitted to the first input end of the data selection module through the scan register module.

[0059] The output end of the module to be isolated is connected to the second input end of the data selection module, and different output signals Out0 / Out1 / Out2 are transmitted to the second input end of the data selection module.

[0060] The output end of the data selection module is electrically connected to the output circuits Gating0 / BUF0 / AND1 in the peripheral circuit, and under the control of the test mode signal, the data at the first input end or the second input end is selected and output to the output circuits Gating0 / BUF0 / AND1.

[0061] The scan register module includes a scan chain formed by cascading N scan registers. The data input ends of each scan register are sequentially connected to multiple input signals of the module to be isolated in order, and the output ends are connected to the first input end of the data selection module. By transmitting the signals In0 / In1 / In2 input to the module to be isolated by the input circuit through the scan register module to the data selection module and then to the output circuit through the data selection module, the problem that the signal X state causes unobservable is avoided.

[0062] Among them, the cascading relationship of the N scan registers in the scan chain is in series, and N is a positive integer not less than 1.

[0063] The scan register module further includes: a scan signal input end, a scan enable signal input end, a scan clock signal input end, and a scan output end.

[0064] The scan signal input end is electrically connected to the scan input end of the first-stage scan register in the scan chain to provide a scan signal for the scan chain; the scan enable signal input end is electrically connected to the scan enable ends of the N scan registers in the scan chain to control the scan registers in the scan chain to select the input signals or scan signals of the module to be isolated for input; the scan clock signal input end is electrically connected to the scan clock ends of the N scan registers to provide a scan clock signal for the scan chain; the scan output end is electrically connected to the data output end of the last-stage scan register in the scan chain to shift and output the captured input signals of the module to be isolated.

[0065] The present application adds a scanning function for the input signals of the module to be isolated by designing a scan chain formed by cascading N scan registers, enabling separate observation of the input signals. Designers can quickly and effectively detect and repair defects in the circuit design process by observing the input signals, reducing dependence on external test equipment, lowering the circuit design cost, and avoiding the problem of unobservability caused by the X state of the input signals, shortening the test time, and improving the observability of the circuit. On the basis of observation, the scan chain can control the input of the input signals under the control of the scan enable signal, not only isolating the module to be isolated but also achieving the controllability of the design, greatly improving the flexibility and effectiveness of testing. In addition, the scan register module also supports the automatic test mode. Since all scan registers can be accessed through the scan chain, it is convenient to apply test vectors, improving the test coverage of the peripheral circuit on the basis of isolating the X state signals.

[0066] The present application connects N scan registers in series to form a scan chain, which is isolated from other modules of the circuit. Users can add or delete scan registers in the scan chain according to the actual situation of the input signals. While the circuit design is more flexible, there is no need to consider the impact on other modules of the circuit design. It can also be selected to be compressed or not compressed according to the actual design requirements, and the integration method is very flexible, greatly reducing the circuit design area and avoiding the situation of mixed serial chains of registers with other modules, reducing the impact brought by other modules in the circuit design.

[0067] The data selection module includes a first input terminal and a second input terminal. Under the control of the scan enable signal, N scan registers select the input signal or the scan signal at the input terminal of the module to be isolated to the first input terminal of the data selection module; the second input terminal of the data selection module is connected to the output terminal of the module to be isolated, and the data selection module selects one of the input data for output under the control of the test mode signal.

[0068] Specifically, as Figure 3 shown, the input circuit is electrically connected to the input signal interface of the module to be isolated, inputting different input signals to the module to be isolated. Different input signals are transmitted to the data selection module through the scan register module; the output terminal of the data selection module is electrically connected to the output circuit, and under the control of the test mode signal, it selects the data at the first input terminal or the second input terminal and outputs it to the output circuit.

[0069] The data selection module includes N data selection units. The data selection unit is a 2-to-1 multiplexer (abbreviated as 2:1 MUX), including two input lines, one selection line, and one output line; the two input lines respectively correspond to the two input terminals, and according to the state of the selection line, the output line selects the data at one of the input terminals for output.

[0070] It should be noted that in other embodiments, the data selection module can be determined according to actual situations. In other embodiments, the data selection module can also be implemented by a switch matrix, a programmable logic device or a logic circuit, which is not limited herein.

[0071] Specifically, as Figure 3 shown, the test mode signal is connected to the selection line of the multiplexer, and controls the output line of the multiplexer to output the data of the first input end or the second input end;

[0072] When the level of the test mode signal is the first level, the multiplexer selects the data transmitted by the scan register module for output; when the level of the test mode signal is the second level, the multiplexer selects the output signal of the module to be isolated for output.

[0073] As Figure 3 shown, multiple input signals of the module to be isolated are sequentially connected to the data input ends of each scan register in sequence; the data output ends of each scan register are correspondingly output to the first input end of the data selection module according to the input signals of the module to be isolated received by the scan register.

[0074] Specifically, the input signals In0 / In1 / In2 of the module to be isolated are respectively connected to the data input ends of the scan registers SDFF1 / SDFF2 / SDFF3. After the scan registers capture the input signals In0 / In1 / In2, the input signals In0 / In1 / In2 are simultaneously output to the first input ends of the corresponding multiplexers MUX1 / MUX2 / MUX3 through the Q ends; since the Q end of SDFF1 is respectively connected to the first input end of MUX1 and the SI end of SDFF2, the Q end of SDFF2 is respectively connected to the first input end of MUX2 and the SI end of SDFF3, and the Q end of SDFF3 is respectively connected to the first input end of MUX3 and the scan output end; therefore, the transmission paths corresponding to the In0 signal, the In1 signal and the In2 signal are isolated from each other. The user can add or delete scan registers in the scan chain according to the actual situation of the input signal, without affecting each other while taking into account the design flexibility.

[0075] It should be noted that the input signal at the input end of the module to be isolated can first be processed by a combinational logic circuit and then sequentially input to the data input ends of N scan registers. Whether it is a common gate circuit (basic logic gates such as AND, OR, NOT, NAND, NOR, XOR...), an adder for performing binary addition operations, a decoder, an encoder, or a multiplexer, the output of the combinational logic circuit depends only on the current input and is not affected by previous inputs. Therefore, the output of a stable input signal after being processed by the combinational logic circuit is also stable. Moreover, adding the design of the combinational logic circuit can better preprocess the input signal according to actual needs (such as compressing or not compressing), making the circuit design more flexible.

[0076] As a preferred embodiment of the present invention, in this embodiment, the output of the combinational logic circuit immediately responds to changes in the input and has no storage unit. The output depends only on the current input. When the input is stable, the output is also stable.

[0077] As a preferred embodiment of the present invention, the scan register in this embodiment is a scan D flip-flop (Scan D Flip-Flop, abbreviated as SDFF). The scan D flip-flop is a special D flip-flop that adds a scan function on the basis of a register, including a multiplexer controlled by a scan enable signal and a D flip-flop that takes the output signal of the multiplexer as the signal input. The scan clock signal is connected to the clock signal interface of the D flip-flop.

[0078] As Figure 3 shown, the input signals In0 / In1 / In2 are respectively connected to the D terminals of SDFF1 / SDFF2 / SDFF3 and captured through the D terminals of the SDFF to achieve the observability of the In0 / In1 / In2 signals. The 1 terminals of MUX1 / MUX2 / MUX3 of the data selection module are respectively connected to the Q terminals of SDFF1 / SDFF2 / SDFF3 through net1 / net2 / net3, and the 0 terminals of MUX1 / MUX2 / MUX3 are connected to the output signals Out0 / Out1 / Out2 of the module to be isolated. When the test mode signal test_mode is 0, MUX1 / MUX2 / MUX3 routes through the 0 terminal and outputs the output signals Out0 / Out1 / Out2 of the module to be isolated to the output circuit. When the test mode signal test_mode is 1, MUX1 / MUX2 / MUX3 routes through the 1 terminal and outputs the output signals at the Q terminals of sdff1 / sdff2 / sdff3 to the output circuit, and no longer outputs the signals Out0 / Out1 / Out2 to the output circuit, achieving the purpose of isolating the X-state output signals.

[0079] As Figure 4As shown, when the level of the scan enable signal is the first level, the scan register selects the scan signal as the input signal; when the level of the scan enable signal is the second level, the scan register selects the input signal of the module to be isolated for input.

[0080] The specific working process includes:

[0081] Shift shift input stage: The scan enable signal controls the multiplexer to select the scan signal and shift it into the scan chain composed of N series-connected scan registers bit by bit; specifically, at the first clock pulse, the first bit of the scan signal enters the first scan register SDFF1, and at the second clock pulse, the first bit of the scan signal enters the second scan register SDFF2, and at the same time the second bit of the scan signal enters the first scan register SDFF1, until all the scan signals are shifted into the scan chain, and the shifted scan signals are used as the input or initial state of the N scan registers;

[0082] Capture capture stage: Under the control of the scan enable signal, the multiplexer inputs the input signals In0 / In1 / In2 of the module to be isolated into the scan registers SDFF1 / SDFF2 / SDFF3 correspondingly. The D flip-flop in the scan register SDFF1 captures the input signal In0, the D flip-flop in the scan register SDFF2 captures the input signal In1, and the D flip-flop in the scan register SDFF3 captures the input signal In2; and since the input signals In0 / In1 / In2 are input into the scan registers SDFF1 / SDFF2 / SDFF3 at the same time, when the D flip-flop in the scan register SDFF1 captures the input signal In0, the D flip-flops in the scan registers SDFF2 / SDFF3 will capture the input signals In1 / In2 at the same time;

[0083] Shift shift output stage: Under the control of the scan clock signal, the signals In0 buffered by the D flip-flop in the scan register SDFF1, the signal In1 buffered by the D flip-flop in the scan register SDFF2, and the signal In2 buffered by the D flip-flop in the scan register SDFF3 will be output to MUX1 / MUX2 / MUX3 in the data selection module at the same time, that is, when the signal In0 is output from the Q end of the scan register SDFF1 to the 1 end of MUX1 through net1, the signals In1 / In2 are output from the Q ends of the scan registers SDFF2 / SDFF3 to the 1 ends of MUX2 / MUX3 through net2 / net3 at the same time. At this time, the input signals In0 / In1 / In2 of the module to be isolated are correspondingly output to the data selection module, so that the data selection module directly outputs the input signals In0 / In1 / In2 of the module to be isolated to the peripheral circuit, realizing the isolation of the module to be isolated.

[0084] Meanwhile, under the control of the scan enable signal, the multiplexer in the scan register will shift the scan signals into the scan chain one by one again and shift out the data cached in the scan chain one by one; since the scan registers in the scan chain are not mixed and chained with the registers of other modules in the circuit design, not only can signals be observed individually, defects in the circuit design can be discovered and repaired in a timely manner, improving the circuit performance; the scan chain of the present application also has a control function, and can realize the control input of the input signal under the control of the scan enable signal, improving the controllability of the circuit.

[0085] As a preferred embodiment of the present invention, the shift input stage of the next cycle is carried out simultaneously with the shift output stage of the previous cycle.

[0086] In this embodiment, multiple input signals of the module to be isolated are sequentially connected to the data input terminals of each scan register in order; the data output terminals of each scan register are correspondingly output to the first input terminal of the data selection module according to the input signals of the module to be isolated received by the scan register.

[0087] Since the input and output of the module to be isolated are in the X state, making it a black box module, in the Shift shift input stage, under the control of the scan enable signal, the N scan registers select the scan signals to the first input terminal of the data selection module, and the scan signals can enter the output circuit through the data selection module. Thus, a signal sequence with 0 / 1 values is provided as a test vector for the registers in the output circuit in the Shift shift input stage. When the Capture capture stage starts after the Shift shift input stage ends, the test vector of the scan signal will be used as the test excitation for the registers in the output circuit, solving the problem that the output of the module to be isolated is unobservable, ensuring that the registers connected to the module to be isolated and the multiplexer can be effectively tested, improving the testability of the registers, and further improving the coverage rate of the peripheral circuit test.

[0088] As a preferred embodiment of the present invention, in this embodiment, the first level is a high level, the second level is a low level, and the signal sequence of the scan signal (01010101010) corresponds to the signal sequence of the scan clock signal.

[0089] The scan chain formed by cascading N scan registers in the present application selects the input signals at the input terminal of the module to be isolated to the data selection module under the control of the scan enable signal. The input signals at the input terminal of the module to be isolated can be directly output to the output circuit through the data selection module, and the output circuit can directly receive the input signals at the input terminal of the module to be isolated, thereby isolating the module to be isolated through the scan register module, shielding the influence of the X-state output signal, and improving the accuracy of the circuit test.

[0090] Some common English nouns or letters used in the present invention for the sake of clear description are only for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0091] It should also be noted that, in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A test circuit, characterized in that: include: Module to be isolated; A scan register module, comprising a scan chain formed by cascading N scan registers; A data selection module comprises a first input terminal and a second input terminal, wherein the N scanning registers select an input signal of the input terminal of the module to be isolated or a scanning signal to the first input terminal of the data selection module under the control of a scanning enable signal; the scanning signal can enter an output circuit in the peripheral circuit through the data selection module; The second input end of the data selection module is connected to the output end of the module to be isolated, and the data selection module selects one of the input data for output under the control of the test mode signal; and a peripheral circuit connected to the input end of the module to be isolated and / or the output end of the data selection module; Wherein, N is a positive integer not less than 1; The multiple input signals of the module to be isolated are sequentially connected to the data input end of each scanning register; The data output end of each scanning register is output to the first input end of the data selection module according to the input signal of the module to be isolated received by the scanning register; The scan register includes a multiplexer controlled by a scan enable signal and a D flip-flop connected to an output terminal of the multiplexer.

2. A test circuit according to claim 1, characterized in that: The input signal of the input end of the module to be isolated is processed by combinational logic and then sequentially input into the data input ends of the N scanning registers.

3. A test circuit according to claim 1, characterized in that: The scanning and registering module also includes: A scan signal input terminal is electrically connected to a scan input terminal of a first-stage scan register to provide a scan signal; A scan enable signal input terminal, electrically connected to the scan enable terminals of the N scan registers, and controlling the scan registers to select the input signal of the module to be isolated or the scan signal for input; A scan clock signal input terminal is electrically connected to the scan clock terminals of the N scan registers to provide a scan clock signal; The scan output terminal is electrically connected to the data output terminal of the last-stage scan register, and shifts and outputs the captured input signal of the module to be isolated.

4. A test circuit according to claim 3, characterized in that: The scan register includes a multiplexer controlled by the scan enable signal, and a D flip-flop connected to an output end of the multiplexer; The scan clock signal is connected to the clock signal interface of the D flip-flop.

5. A test circuit according to claim 4, characterized in that: The working process of the scanning and registering module includes: In the shift input stage, the scan enable signal controls the multiplexer to select the scan signal and shift it into the N scan registers of the scan register module one by one; In the capture phase, the multiplexers in the N scan registers select the input signal of the module to be isolated under the control of the scan enable signal for input and output to the corresponding D flip-flop; In the shift output stage, under the control of the scan clock signal, the input signal of the module to be isolated cached in the D flip-flops in the N scan registers is output to the data selection module through the data output end, and is output to the scan output end bit by bit.

6. A test circuit according to claim 5, characterized in that: The scanning signal is a signal sequence corresponding to the scanning clock signal.

7. A test circuit according to claim 5, characterized in that: The working process of the scanning and registering module also includes: The shift-in phase of the next scan cycle is performed simultaneously with the shift-out phase of the previous scan cycle.

8. A test circuit according to claim 1, characterized in that: The data selection module includes N data selection units, and the data selection unit is a multiplexer; The test mode signal controls the multiplexer to select data of the first input terminal or the second input terminal for output.

9. A test circuit according to claim 1, characterized in that: The peripheral circuit includes an input circuit connected to the input end of the module to be isolated, and / or an output circuit connected to the output end of the data selection module; The input circuit is electrically connected to the input signal interface of the module to be isolated, and different input signals are input to the module to be isolated. The different input signals are transmitted to the data selection module through the scanning register module; the output end of the data selection module is electrically connected to the output circuit, and under the control of the test mode signal, the data of the first input end or the second input end is selected to be output to the output circuit.

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