A multi-channel partition sampling device and method for a fuel cell stack

Abstract

The present invention relates to the field of fuel cell technology, and in particular to a multi-channel partition sampling device and method for a fuel cell stack. The device includes a partition sampling board, a signal gain circuit board, a signal conversion circuit board and a timing control circuit board connected in sequence. The signal gain circuit board includes a signal amplification circuit and a multi-channel multiplexing circuit. The timing control circuit board sends a first clock signal for controlling the time when the multi-channel multiplexing circuit sends an initial analog signal to the multi-channel multiplexing circuit through the signal conversion circuit board, directly sends a second clock signal for controlling the start sequence of data transmission of each signal conversion circuit board to the signal conversion circuit board, and a third clock signal for controlling the sequence of outputting digital signals of the started signal conversion circuit board. Compared with the prior art, the present invention has the advantages of reducing signal bandwidth cost and hardware cost, improving partition sampling accuracy, etc.

Description

Technical Field

[0001] The present invention relates to the technical field of fuel cells, and in particular to a multi-channel partition sampling device and method for a fuel cell stack. Background Art

[0002] During the use of fuel cell stacks, there is a phenomenon that the physical fields such as current, voltage, impedance, and temperature are unevenly distributed along the membrane electrode plane. In the prior art, technicians usually use the partitioned sampling printed circuit board (PCB board) embedded in the fuel cell stack to synchronously transmit the measured signals of each partition to the data acquisition equipment for data processing to obtain relevant physical field spatial distribution information. For example, Chinese patent CN113363539A discloses a high-resolution partition detection system for internal current of a fuel cell stack. The system comprises a high-resolution partitioned current acquisition board, a partitioned hollow current collecting board, a multi-channel signal amplifying device, an analog-to-digital conversion module, a CPU and a host computer. The middle of the high-resolution partitioned current acquisition board and the area corresponding to the active area of ​​the fuel cell stack are the partitioned current acquisition areas. A voltage signal port is provided at one end of the high-resolution partitioned current acquisition board extending out of the fuel cell stack area. The high-resolution partitioned current acquisition board is a multi-layer printed circuit board, which is arranged between any two adjacent fuel cell units. The partitioned current acquisition area is composed of a plurality of acquisition units arranged in an array, each of which comprises a copper-plated and gold-plated partition top layer, a routing layer and a high-precision sampling resistor bottom layer arranged in sequence from top to bottom, and also comprises two current acquisition vias penetrating the copper-plated and gold-plated partition top layer, the routing layer and the high-precision sampling resistor bottom layer and being metallized. The routing layer transmits the voltage signal collected from the positive electrode of the sampling resistor to the multi-channel signal amplifying device through the voltage signal port for amplification processing. After the amplified voltage signal is converted by the analog-to-digital conversion module, the current value of the copper-plated and gold-plated partition top layer in the corresponding acquisition unit is obtained.

[0003] The above system realizes high-resolution detection of partition current at any position in the fuel cell stack through a partition current acquisition board, a multi-channel signal amplifier and an analog-to-digital conversion module. However, when the number of partitions of the partition sampling board is too large, the signal bandwidth and the cost of the data acquisition equipment required by the existing synchronous transmission method will increase significantly, and the frequent switching of the multi-channel signal amplifier will also affect the final current detection accuracy. Summary of the invention

[0004] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and to provide a fuel cell stack multi-channel partition sampling device and method, which can effectively reduce the signal bandwidth cost and hardware cost required for multi-channel partition sampling of the fuel cell stack while ensuring the sampling accuracy.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] According to a first aspect of the present invention, a multi-channel partition sampling device for a fuel cell stack is provided, the device comprising a partition sampling board, a signal gain circuit board, a signal conversion circuit board and a timing control circuit board connected in sequence, the signal gain circuit board comprising a signal amplification circuit and a multi-channel multiplexing circuit, the number of input channels of the multi-channel multiplexing circuit is equal to the number of channels of the signal amplification circuit and is correspondingly connected, and the output end is connected to the signal conversion circuit board; the signal amplification circuit is used to synchronously amplify the multi-channel electrical signal from the partition sampling board, the multi-channel multiplexing circuit is used to send the amplified initial analog signal in sequence, the signal conversion circuit board is used to convert the amplified initial analog signal into a digital signal and output it in sequence, the timing control circuit board is used to send a first clock signal to the multi-channel multiplexing circuit through the signal conversion circuit board, and directly send a second clock signal and a third clock signal to the signal conversion circuit board; the first clock signal is used to control the time when the multi-channel multiplexing circuit sends the amplified initial analog signal, the second clock signal is used to control the startup sequence of each signal conversion circuit board for data transmission, and the third clock signal is used to control the sequence of outputting digital signals by the started signal conversion circuit board.

[0007] As a preferred technical solution, the signal conversion circuit board includes an analog-to-digital conversion circuit, and the output end of the multi-channel multiplexing circuit is connected to the analog-to-digital conversion circuit; the time period of the first clock signal is not less than the product of the time period of the second clock signal and the number of input channels of the multi-channel multiplexing circuit, the time period of the second clock signal is not less than the product of the time required for the analog-to-digital conversion circuit to continuously output data of all channels and the number of input channels of the analog-to-digital conversion circuit, and the time period of the third clock signal is greater than the minimum time period of the clock signal required by the analog-to-digital conversion circuit.

[0008] As a preferred technical solution, the quantitative relationship between the partition sampling boards, the signal gain circuit boards, the signal conversion circuit boards and the timing control circuit boards includes: the product of the number of the partition sampling boards and the number of signal output channels of the partition sampling boards is less than or equal to the product of the number of the timing control circuit boards, the number of control signal output ports of the timing control circuit boards, the number of input channels of the analog-to-digital conversion circuit and the number of input channels of the multi-channel multiplexing circuit; the product of the number of the partition sampling boards and the number of signal output channels of the partition sampling boards is less than or equal to the product of the number of the signal conversion circuit boards, the number of input channels of the analog-to-digital conversion circuit and the number of input channels of the multi-channel multiplexing circuit; and the product of the number of the partition sampling boards and the number of signal output channels of the partition sampling boards is less than or equal to the product of the number of the signal gain circuit boards and the number of input channels of the multi-channel multiplexing circuit.

[0009] As a preferred technical solution, the partitioned sampling plate is placed between the membrane electrodes of the fuel cell to be sampled, or between the membrane electrode and the current collecting plate of the fuel cell to be sampled.

[0010] As a preferred technical solution, the partitioned sampling board includes a partitioned electrical contact structure, a partitioned sampling circuit correspondingly connected to the partitioned electrical contact structure, and a first signal connector, and the first signal connector is located at the edge of the partitioned sampling board.

[0011] As a preferred technical solution, the timing control circuit board includes a timing control circuit, a control signal output port, a digital signal receiving port and a second digital signal output port. The output end of the timing control circuit is connected to the control signal output port, the control signal output port is connected to the signal conversion circuit board, and the digital signal receiving port is respectively connected to the signal conversion circuit board and the digital signal output port.

[0012] As a preferred technical solution, the timing control circuit includes a clock signal generation source, a multi-stage binary counter and a control unit for logic judgment connected in sequence, and the output of the control unit is connected to the control signal output port.

[0013] As a preferred technical solution, the multi-channel multiplexing circuit includes a multi-channel multiplexer chip, a signal output port, a control signal input port and a synchronous binary counter chip. The multi-channel multiplexer chip is connected to the signal amplification circuit and the signal output port, and is connected to the control signal input port through the synchronous binary counter chip. The control signal input port is connected to the signal conversion circuit board.

[0014] As a preferred technical solution, the partition sampling board and the signal gain circuit board are detachably connected.

[0015] According to a second aspect of the present invention, a multi-channel partition sampling method for a fuel cell stack is provided, and the method is implemented based on the device, and includes the following steps: S1, all signal gain circuit boards simultaneously receive a first clock signal, and drive the corresponding multi-channel multiplexing circuit to send amplified initial analog signals in sequence, and the first clock signal is sent by the timing control circuit board to the corresponding signal gain circuit board through the signal conversion circuit board; S2, all signal conversion circuit boards simultaneously receive the corresponding initial analog signals, convert them into digital signals and temporarily store them; S3, all signal conversion circuit boards simultaneously receive a second clock signal from the timing control circuit board, and the signal conversion circuit board corresponding to the second clock signal starts data transmission; S4, the started signal conversion circuit board receives a third clock signal from the timing control circuit board, performs analog-to-digital conversion and outputs the current digital signal in sequence; S5, within the pulse time of one of the first clock signals, repeat S3-S4 to obtain all digital signals; S6, after receiving M complete first clock signals in succession, the electrical signal sampling of all partitions on the partition sampling board is completed, wherein M is the number of input channels of the multi-channel multiplexing circuit.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. On the one hand, the present invention adopts the control logic of synchronous control and parallel sampling between all signal gain circuit boards. All signal amplification circuits synchronously amplify the electrical signals from each partition of the partition sampling board, and synchronously amplify them at the same time to obtain the initial analog signal of multi-channel amplification. After the multi-channel multiplexing circuit, the number of channels of the initial analog signal is consistent with the number of signal gain circuit boards. On the other hand, the time when the multi-channel multiplexing circuit sends the initial analog signal is controlled by the first clock signal, and the order of outputting digital signals of the signal conversion circuit board is controlled by the second clock signal and the third clock signal. At the same time, the synchronously amplified multi-channel initial analog signal can be output in a certain order to obtain the sampling data of each partition. There is no need to frequently convert channels in the case of multi-channel input, which can effectively reduce the channel conversion frequency and signal bandwidth cost, and at the same time reduce the influence of the electrical signal noise generated by the frequent switching of the multi-channel multiplexing circuit on the sampling accuracy, thereby improving the partition sampling accuracy;

[0018] 2. The analog-to-digital conversion circuit of the present invention adopts a control logic of parallel input and serial output of digital signals. The parallel input is realized by controlling the multi-channel multiplexing circuit through the signal amplification circuit and the first clock signal, and the serial output of the digital signal is realized by controlling the signal conversion circuit board through the second clock signal and the third clock signal. The time period of each clock signal can ensure the sampling sequence of the multi-channel multiplexing circuit and the analog-to-digital conversion circuit, improve the efficiency of obtaining the sampling data of each partition in a certain order, and solve the contradiction between the high-frequency sampling requirement of the sampling device and the long sampling time of a single analog signal.

[0019] 3. The present invention adopts a modular design, and the partition sampling board and the signal gain circuit board are detachably connected. According to the relationship between the number of partition sampling boards and the number of signal gain circuit boards, signal conversion circuit boards and timing control circuit boards, the number of signal gain circuit boards and signal conversion circuit boards used can be increased or decreased according to the number of sampling channels of the partition sampling board (i.e., the number of signal output channels of the partition sampling board). When different fuel cell stacks use the sampling device provided by the present invention, they only need to redesign the structural appearance of the partition sampling board without changing other structural components of the device, thereby improving the applicability of the sampling device and effectively reducing the cost of the data acquisition equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of signal transmission of a device provided for the present invention;

[0021] Figure 2 A schematic diagram of a structure of a partition sampling plate in a device is provided for an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of a structure of a signal gain circuit board in a device is provided for an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of a structure of a signal conversion circuit board in a device is provided for an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of a structure of a timing control circuit board in a device is provided for an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of the structure connection of a multi-channel partition sampling device provided in an embodiment of the present invention, wherein the number of signal output channels of the partition sampling board is 128;

[0026] Figure 7 A schematic diagram of a structure of a multi-channel multiplexing circuit in a device is provided for an embodiment of the present invention;

[0027] Figure 8A schematic diagram of a structure of a timing control circuit in a device is provided for an embodiment of the present invention;

[0028] Fig. 9 A schematic diagram of the structure connection of another multi-channel partition sampling device provided by an embodiment of the present invention, wherein the number of signal output channels of the partition sampling board is 2048;

[0029] Fig.10 A schematic diagram of a flow chart of a multi-channel partition sampling method provided by an embodiment of the present invention;

[0030] Wherein: 200, partition sampling board; 300, signal gain circuit board; 400, signal conversion circuit board; 500, timing control circuit board; 201, partition electrical contact structure; 202, first signal connector; 301, signal amplification circuit; 302, multi-channel multiplexing circuit; 303, second signal connector; 3021, 16-channel multiplexer chip; 3022, signal output port; 3023, control signal input port; 3024, 4-bit synchronous binary counter chip; 401, electrical signal receiving port; 402, analog-to-digital conversion circuit; 403, first digital signal output port; 404, third signal connector; 405, fourth signal connector; 501, timing control circuit; 502, control signal output port; 503, digital signal receiving port; 504, second digital signal output port; 5011, clock signal generation source; 5012, multi-stage binary counter; 5013, control unit. DETAILED DESCRIPTION

[0031] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0032] Example:

[0033] When the number of partitions of the partition sampling board is too large, the signal transmission mode of the existing fuel cell stack partition sampling device significantly increases the required signal bandwidth and the cost of the data acquisition equipment, and the detection accuracy is also affected. Therefore, the present invention proposes a fuel cell stack multi-channel partition sampling device. In terms of hardware structure, the device includes a partition sampling board and three circuit boards, namely, a partition sampling board, a signal gain circuit board, a signal conversion circuit board and a timing control circuit board connected in sequence; in terms of specific functions, the device can be divided into five specific circuits, namely, a partition sampling circuit, a signal amplification circuit, a multi-channel multiplexing circuit, an analog-to-digital conversion circuit and a timing control circuit. Among them, the partition sampling circuit is located on the partition sampling board, the signal amplification circuit and the multi-channel multiplexing circuit are located on the signal gain circuit board, the analog-to-digital conversion circuit is located on the signal conversion board, and the timing control circuit is located on the timing control circuit board. Figure 1 The overall signal transmission process of the device provided by the present invention is shown:

[0034] After the signal gain circuit board receives the electrical signals of each partition from the partition sampling board, the signal amplification circuit synchronously amplifies the electrical signals from the partition sampling board, and the multi-channel multiplexing circuit sends the amplified initial analog signals in sequence; the signal conversion circuit board converts the initial analog signals into corresponding digital signals and outputs them in sequence. Optionally, the digital signals obtained by the signal conversion circuit board are transmitted to the host computer or other storage media through the timing control circuit board for storage or analysis.

[0035] In the aforementioned signal transmission process, the timing control circuit board controls the signal transmission sequence inside the signal gain circuit board and the signal conversion circuit board by sending different clock signals. Figure 1 In the figure, the solid double arrow between the timing control circuit board and the signal conversion circuit board indicates that in the hardware structure, the timing control circuit board is directly connected to the signal conversion circuit board to realize the transmission of the clock signal. The dotted double arrow between the timing control circuit board and the signal gain circuit board indicates that the timing control circuit board is not directly connected in the hardware structure, but the timing control circuit board sends the clock signal to the signal gain circuit board through the signal conversion circuit board to realize the transmission of the clock signal.

[0036] The timing control circuit board sends different clock signals to the signal gain circuit board and the signal conversion circuit board respectively, specifically including: the timing control circuit board sends the first clock signal to the multi-channel multiplexing circuit through the signal conversion circuit board, and directly sends the second clock signal and the third clock signal to the signal conversion circuit board. The first clock signal is used to control the time when the multi-channel multiplexing circuit sends the amplified initial analog signal, the second clock signal is used to control the startup sequence of each signal conversion circuit board for data transmission, and the third clock signal is used to control the sequence of the digital signal output by the started signal conversion circuit board. The time periods of the three clock signals are different.

[0037] Figure 2~Figure 5 They are schematic diagrams of one structure of the partition sampling board 200, the signal gain circuit board 300, the signal conversion circuit board 400 and the timing control circuit board 500 in the aforementioned device provided in this embodiment; Figure 6 This is a schematic diagram of the overall structure connection of one of the aforementioned devices provided in this embodiment, wherein the partition sampling board 200 has 128 signal output channels. Specifically:

[0038] The partitioned sampling plate 200 refers to a flat plate device placed between the membrane electrodes of the fuel cell to be sampled or between the membrane electrode and the current collecting plate of the fuel cell to be sampled. Figure 2As shown, there is a partitioned electrical contact structure 201 on the surface of the flat-plate device and a first signal connector 202 on the edge. The partitioned sampling circuit (circuit details are not shown in the figure) is also located on the partitioned sampling board 200 and is correspondingly connected to the partitioned electrical contact structure 201. Optionally, on the partitioned sampling board 200, the sampling element of the partitioned sampling circuit is located above the corresponding partition, and the sampling signal is transmitted to the first signal connector 202 at the edge of the partitioned sampling board 200 through the circuit, and the number of signal output channels is L.

[0039] The signal gain circuit board 300 includes a signal amplification circuit 301, a multi-channel multiplexing circuit 302 and a second signal connector 303. The number of input channels of the multi-channel multiplexing circuit 302 is equal to the number of channels of the signal amplification circuit 301 and is connected correspondingly. The number of channels is M. The output end of the multi-channel multiplexing circuit 302 is connected to the signal conversion circuit board 400. Figure 3 As shown, on a signal gain circuit board 300 , the total number of channels of the signal amplification circuit 301 is 16, and the multi-channel multiplexing circuit 302 is a 16-channel multiplexing circuit, that is, M=16.

[0040] The signal amplifying circuit 301 is a circuit for receiving the electrical signal transmitted from the partition sampling board 200 and performing signal strength gain on the electrical signal. Specifically, the first signal connector 202 is connected to the second signal connector 303 to achieve synchronous transmission of the electrical signal.

[0041] The multi-channel multiplexing circuit 302 refers to a circuit that transmits the output signals of the multiple signal amplification circuits 301 collected synchronously to the signal conversion circuit board 400 one by one in order. Figure 3 The 16-channel multiplexing circuit includes a 16-channel multiplexer chip 3021, a signal output port 3022, a control signal input port 3023 and a 4-bit synchronous binary counter chip 3024. The 16-channel multiplexer chip 3021 is connected to the signal amplification circuit 301 and the signal output port 3022 respectively, and is connected to the control signal input port 3023 through the 4-bit synchronous binary counter chip 3024. The control signal input port 3023 is connected to the signal conversion circuit board 400. Figure 7 As shown, optionally, the 16-channel multiplexing circuit also includes a filtering circuit, and the 16-channel multiplexer chip 3021 is connected to the signal output port 3022 through the filtering circuit, and the signal output port 3022 further outputs the corresponding initial analog signal to the signal conversion circuit board 400.

[0042] The signal conversion circuit board 400 includes an electrical signal receiving port 401, an analog-to-digital conversion circuit 402, a first digital signal output port 403, a third signal connector 404, and a fourth signal connector 405. Exemplarily, Figure 4In the figure, the electrical signal receiving port 401 is connected correspondingly to the signal output port 3022 of the multi-channel multiplexing circuit 302, the analog-to-digital conversion circuit 402 is an 8-channel analog-to-digital conversion circuit, and its input channels are connected correspondingly to the electrical signal receiving port 401. The number of the electrical signal receiving ports 401 is equal to the number of input channels of the analog-to-digital conversion circuit 402, and the number of channels is K. The first digital signal output port 403 is internally connected to the analog-to-digital conversion circuit 402 and is externally connected to the timing control circuit board 500 (specifically connected to the digital signal receiving port 503) for transmitting the digital signal to be stored; the third signal connector 404 is internally connected to the fourth signal connector 405 and is externally connected to the control signal input port 3023 of the signal gain circuit board 300, and is used to provide the digital signal transmitted from the timing control circuit board 500 to the signal gain circuit board 300; the fourth signal connector 405 is externally connected to the timing control circuit board 500 (specifically the control signal output port 502) and is internally connected to the analog-to-digital conversion circuit 402, and is used to provide the digital signal transmitted from the timing control circuit board 500 to the analog-to-digital conversion circuit 402; the analog-to-digital conversion circuit 402 refers to a circuit that can perform analog-to-digital conversion on multiple analog electrical signals and convert them into digital signals, and includes an analog-to-digital conversion chip (ADC chip) with multi-channel input.

[0043] For example, Figure 5 The timing control circuit board 500 includes a timing control circuit 501, a control signal output port 502, a digital signal receiving port 503 and a second digital signal output port 504. The output end of the timing control circuit 501 is connected to the control signal output port 502 in sequence. The control signal output port 502 is connected to the fourth signal connector 405 of the signal conversion circuit board 400 for providing a clock signal. The digital signal receiving port 503 is connected to the first digital signal output port 403 of the signal conversion circuit board 400 for receiving a digital signal to be stored. The digital signal receiving port 503 is connected to the second digital signal output port 504 inside the timing control circuit board 500 so as to transmit a digital signal to a host computer or other storage medium waiting for storage. Among them, the number of control signal output ports 502 and digital signal receiving ports 503 is equal, both of which are 2. N , N is an integer ≥2.

[0044] The timing control circuit 501 refers to a circuit that provides a pulse electrical signal with a certain time sequence to the multi-channel multiplexing circuit 302 and the analog-to-digital conversion circuit 402, thereby controlling the sampling order of the multi-channel multiplexing circuit 302 and the analog-to-digital conversion circuit 402, so as to obtain the sampling partition information of each partition sampling board 200 in a certain order. Optionally, the timing control circuit 501 includes a clock signal generating source 5011, a multi-stage binary counter 5012, and a control unit 5013 for logic judgment, which are connected in sequence. The control unit 5013 is for example a control chip or a circuit structure. The output end of the control unit 5013 is connected to the control signal output port 502 in sequence.

[0045] like Figure 8 As shown, in the timing control circuit 501, the clock signal source 5011 transmits the clock signal to the multi-stage binary counter 5012 to provide a counting signal for it. The multi-stage binary counter 5012 outputs three clock signals CONVST, CSOSC, and RDTIM with different time periods (corresponding to the first clock signal, the second clock signal, and the third clock signal, respectively). After the control chip or circuit performs logical judgment, the control signals are provided to the signal gain circuit board 300 and the signal conversion circuit board 400 as control signals. Figure 6 As shown, the transmission process of the control signal specifically includes:

[0046] The transmission process of providing the clock signal CONVST (first clock signal) to the signal gain circuit board 300 is: control signal output port 502 → fourth signal connector 405 → third signal connector 404 → control signal input port 3023 → 4-bit synchronous binary counter chip 3024 → 16-channel multiplexer chip 3021;

[0047] The transmission process of providing the clock signals CSOSC and RDTIM (the second clock signal and the third clock signal) to the signal conversion circuit board 400 is: control signal output port 502 → fourth signal connector 405 → analog-to-digital conversion circuit 402 .

[0048] Among them, the time period of RDTIM (the third clock signal) is greater than the minimum time period of the required clock signal of the ADC chip on the signal conversion circuit board 400, the time period of CSOSC (the second clock signal) is not less than the time required for the ADC chip to continuously output data of all channels*K (K is the number of input channels of the analog-to-digital conversion circuit 402), and the time period of CONVST (the first clock signal) is not less than the time period of CSOSC*M (M is the number of input channels of the multi-channel multiplexing circuit 302).

[0049] by Figure 6Take the sampling device shown as an example: a 16-channel multi-channel multiplexing circuit 302 (M=16) is used on the signal gain circuit board 300; AD7606 of ADI Company is used as the ADC chip on the signal conversion circuit board 400, which has 8 parallel input signals (K=8). When the operating voltage is greater than 2.7V, the minimum time period of signal transmission is 0.017μs; in the timing control circuit 501, the time period of a clock signal of the selected 8MHz crystal oscillator is 0.125μs, recorded as dT, then the time period of each clock signal can be: the time period of the RDTIM signal is 2*dT, the time period of the CSOSC signal is 16*dT, and the time period of the CONVST signal is 512*dT.

[0050] Optionally, a set of sampling devices includes at least one partition sampling board 200, one signal gain circuit board 300, one signal conversion circuit board 400 and one timing control circuit board 500. The quantitative relationship of the partition sampling board 200, the signal gain circuit board 300, the signal conversion circuit board 400 and the timing control circuit board 500 includes:

[0051] The number of partition sampling boards 200*L≤the number of timing control circuit boards 500*2 N *K*M;

[0052] The number of partition sampling boards 200*L≤the number of signal conversion circuit boards 400*K*M;

[0053] The number of partition sampling boards 200*L≤the number of signal gain circuit boards 300*M;

[0054] Where L is the number of signal output channels of the partition sampling board 200, 2 N is the number of control signal output ports 502 in the timing control circuit board 500 , K is the number of input channels of the analog-to-digital conversion circuit 402 , and M is the number of input channels of the multi-channel multiplexing circuit 302 .

[0055] For example, in the case of M=16, K=8, 2 N =16, Figure 6 and Fig. 9 Two different multi-channel partitioned sampling device structures are shown respectively. Figure 6 The figure shows a multi-channel partition sampling device with a partition sampling board with 128 channels (L=128), which includes a partition sampling board 200, eight signal gain circuit boards 300, a signal conversion circuit board 400 and a timing control circuit board 500. Fig. 9The figure shows a multi-channel partition sampling device having a partition sampling board with 2048 channels (L=2048), which includes 1 partition sampling board 200, 8×16 signal gain circuit boards 300, 1×16 signal conversion circuit boards 400 and 1 timing control circuit board 500. Figure 6 and Fig. 9 The aforementioned quantitative relationships are satisfied between the circuit boards in the device shown.

[0056] Optionally, the partition sampling plate 200 is detachably connected to the signal gain circuit board 300. And according to the aforementioned quantitative relationship, the number of signal gain circuit boards and signal conversion circuit boards used can be increased or decreased according to the number of sampling channels of the partition sampling plate (i.e., the number of signal output channels of the partition sampling plate). Therefore, when different fuel cell stacks use the sampling device provided by the present invention, they only need to redesign the structural appearance of the partition sampling plate without changing other structural components of the device, thereby improving the applicability of the sampling device and effectively reducing the cost of the data acquisition equipment.

[0057] Furthermore, a multi-channel partition sampling method for a fuel cell stack is provided, which is implemented based on the sampling device provided in this embodiment. Fig.10 As shown, the method comprises the following steps:

[0058] Step S1, starting at time t0, all signal gain circuit boards 300 simultaneously receive the clock signal CONVST, i.e., the first clock signal. Each time a pulse of the clock signal is received, the counter on the signal gain circuit board 300 is incremented by 1, and the corresponding multi-channel multiplexing circuit 302 is driven to sequentially send the amplified initial analog signals of the corresponding number of channels. The first clock signal is sent by the timing control circuit board 500 to the corresponding signal gain circuit board 300 through the signal conversion circuit board 400.

[0059] In step S2, all the signal conversion circuit boards 400 simultaneously receive the initial analog signals outputted by the corresponding signal gain circuit boards 300, and perform analog-to-digital conversion, and the converted digital signals are temporarily stored in the ADC chip data buffer.

[0060] In step S3, all signal conversion circuit boards 400 simultaneously receive the counting signal of the cycle counter driven by the clock signal CSOSC, i.e., the second clock signal. The clock signal CSOSC comes from the timing control circuit board 500. The signal conversion circuit board 400 (i.e., the jth signal conversion circuit board) corresponding to the counting value of the cycle counter starts data transmission.

[0061] In step S4, the started signal conversion circuit board 400 receives the RDTIM clock signal, i.e., the third clock signal, from the timing control circuit board 500. Driven by the clock signal RDTIM, the signal conversion circuit board 400 selected to be started in step S3 outputs the current digital signal in sequence (i.e., transmits the digital signals of the 1st to Kth channels in sequence).

[0062] Step S5, within one CONVST pulse time, continuously loop steps S3 to S4 to obtain all converted digital signals and transmit them to a host computer or other storage media.

[0063] Step S6, after receiving M complete clock signals CONVST continuously, the electrical signal sampling of all partitions on the partition sampling board 200 is completed and transmitted to the host computer or other storage media. The corresponding signal sampling time is t0=t+M*DT, where M is the number of input channels of the multi-channel multiplexing circuit 302, and DT is the time period of a clock signal CONVST.

[0064] All the above steps will be repeated under the control of the timing control circuit board 500, so as to obtain the signals of different partitions inside the fuel cell that change with time, and the sampling period is M*DT. Steps S5 and S6 are not marked in the figure. When actually executing the sampling method, it needs to be executed according to the above complete process.

[0065] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A multi-channel partition sampling device for a fuel cell stack, characterized in that: The device comprises a partition sampling board, a signal gain circuit board, a signal conversion circuit board and a timing control circuit board which are connected in sequence, the signal gain circuit board comprises a signal amplification circuit and a multi-channel multiplexing circuit, the number of input channels of the multi-channel multiplexing circuit is equal to the number of channels of the signal amplification circuit and they are connected correspondingly, and the output end is connected to the signal conversion circuit board; The signal amplification circuit is used to synchronously amplify the multi-channel electrical signals from the partition sampling board, the multi-channel multiplexing circuit is used to send the amplified initial analog signals in sequence, the signal conversion circuit board is used to convert the amplified initial analog signals into digital signals and output them in sequence, and the timing control circuit board is used to send a first clock signal to the multi-channel multiplexing circuit through the signal conversion circuit board, and directly send a second clock signal and a third clock signal to the signal conversion circuit board; the first clock signal is used to control the time when the multi-channel multiplexing circuit sends the amplified initial analog signal, the second clock signal is used to control the startup order of each signal conversion circuit board for data transmission, and the third clock signal is used to control the order in which the started signal conversion circuit board outputs digital signals; The signal conversion circuit board includes an analog-to-digital conversion circuit, and the output end of the multi-channel multiplexing circuit is connected to the analog-to-digital conversion circuit; The time period of the first clock signal is not less than the product of the time period of the second clock signal and the number of input channels of the multi-channel multiplexing circuit, the time period of the second clock signal is not less than the product of the time required for the analog-to-digital conversion circuit to continuously output data of all channels and the number of input channels of the analog-to-digital conversion circuit, and the time period of the third clock signal is greater than the minimum time period of the clock signal required by the analog-to-digital conversion circuit.

2. The multi-channel partition sampling device for a fuel cell stack according to claim 1, characterized in that: The quantitative relationship between the partition sampling board, the signal gain circuit board, the signal conversion circuit board and the timing control circuit board includes: The product of the number of the partition sampling boards and the number of signal output channels of the partition sampling boards is less than or equal to the product of the number of the timing control circuit boards, the number of control signal output ports of the timing control circuit boards, the number of input channels of the analog-to-digital conversion circuit and the number of input channels of the multi-channel multiplexing circuit; The product of the number of the partition sampling boards and the number of signal output channels of the partition sampling boards is less than or equal to the product of the number of the signal conversion circuit boards, the number of input channels of the analog-to-digital conversion circuit and the number of input channels of the multi-channel multiplexing circuit; And the product of the number of the partition sampling boards and the number of signal output channels of the partition sampling boards is less than or equal to the product of the number of the signal gain circuit boards and the number of input channels of the multi-channel multiplexing circuit.

3. The multi-channel partition sampling device for a fuel cell stack according to claim 1, characterized in that: The partitioned sampling plate is placed between the membrane electrodes of the fuel cell to be sampled, or between the membrane electrode and the current collecting plate of the fuel cell to be sampled.

4. The multi-channel partition sampling device for a fuel cell stack according to claim 3, characterized in that: The partitioned sampling board includes a partitioned electrical contact structure, a partitioned sampling circuit correspondingly connected to the partitioned electrical contact structure, and a first signal connector, wherein the first signal connector is located at an edge of the partitioned sampling board.

5. The fuel cell stack multi-channel partition sampling device according to claim 1, characterized in that: The timing control circuit board includes a timing control circuit, a control signal output port, a digital signal receiving port and a second digital signal output port. The output end of the timing control circuit is connected to the control signal output port, the control signal output port is connected to the signal conversion circuit board, and the digital signal receiving port is respectively connected to the signal conversion circuit board and the second digital signal output port.

6. The fuel cell stack multi-channel partition sampling device according to claim 5, characterized in that: The timing control circuit comprises a clock signal generating source, a multi-stage binary counter and a control unit for logic judgment which are connected in sequence, and the output of the control unit is connected to the control signal output port.

7. The fuel cell stack multi-channel partition sampling device according to claim 1, characterized in that: The multi-channel multiplexing circuit includes a multi-channel multiplexer chip, a signal output port, a control signal input port and a synchronous binary counter chip. The multi-channel multiplexer chip is connected to the signal amplification circuit and the signal output port, and is connected to the control signal input port through the synchronous binary counter chip. The control signal input port is connected to the signal conversion circuit board.

8. The fuel cell stack multi-channel partition sampling device according to any one of claims 1 to 7, characterized in that: The partition sampling board and the signal gain circuit board are detachably connected.

9. A multi-channel partition sampling method for a fuel cell stack, characterized in that: The method is implemented based on the device according to any one of claims 1 to 7. The following steps are involved: S1, all signal gain circuit boards simultaneously receive a first clock signal and drive corresponding multi-channel multiplexing circuits to sequentially send amplified initial analog signals, wherein the first clock signal is sent by the timing control circuit board to the corresponding signal gain circuit board through the signal conversion circuit board; S2, all signal conversion circuit boards simultaneously receive the corresponding initial analog signals, convert them into digital signals and store them temporarily; S3, all signal conversion circuit boards simultaneously receive the second clock signal from the timing control circuit board, and the signal conversion circuit board corresponding to the second clock signal starts data transmission; S4, the started signal conversion circuit board receives the third clock signal from the timing control circuit board, performs analog-to-digital conversion and outputs the current digital signal in sequence; S5, repeating S3 to S4 within a pulse time of the first clock signal to obtain all digital signals; S6, after receiving M complete first clock signals continuously, the electrical signal sampling of all partitions on the partition sampling board is completed, wherein M is the number of input channels of the multi-channel multiplexing circuit.

Images