Reference signal generation circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a reference signal generation circuit, a chip and an electronic device, the reference signal generation circuit comprises an operational amplifier module, a mirror image module and a reference signal adjustment module, a voltage feedback unit generates a feedback voltage according to an initial current and outputs a corresponding reference voltage, the reference voltage can be independently adjusted, and the reference signal generation efficiency is improved. The current adjusting unit can adjust the initial current to calibrate at least one reference current under the condition that the reference voltage is kept unchanged, so that the reference voltage or the reference current can be independently adjusted.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a reference signal generating circuit, a chip and an electronic device. Background Art

[0002] The bandgap reference circuit (BGR) is a circuit that generates an output voltage that is independent of the power supply voltage and temperature and is widely used in various analog circuits. The bandgap reference circuit adds a voltage that is proportional to the absolute temperature and a voltage that is negatively correlated with the absolute temperature to obtain an output voltage that is independent of temperature.

[0003] The voltage that is negatively correlated with absolute temperature is generally realized by the base-emitter voltage generated by the current flowing through the transistor, and the voltage that is positively correlated with absolute temperature is generally realized by subtracting the base-emitter voltage generated by the current flowing through two transistors. The output voltage of the bandgap reference circuit is clamped by a unity gain buffer to generate a corresponding reference voltage, which is divided by the feedback resistor to obtain the corresponding reference current.

[0004] However, during the adjustment process, the reference voltage and the reference current change synchronously, which makes it impossible to adjust the reference voltage or the reference current separately, thereby reducing the accuracy of the reference voltage or the reference current. Summary of the invention

[0005] In view of the above problems, the embodiments of the present application provide a reference signal generating circuit, a chip and an electronic device to solve the technical problem that the reference voltage or the reference current cannot be adjusted individually.

[0006] In a first aspect, an embodiment of the present application provides a reference signal generating circuit, which includes an operational amplifier module, a mirror module and a reference signal adjustment module. The operational amplifier module is used to output an operational amplifier signal according to a comparison result between a reference voltage and a feedback voltage; the mirror module is used to generate a corresponding initial current under the control of the operational amplifier signal, and to mirror out at least one reference current of a corresponding proportion according to the initial current; the reference signal adjustment module includes a voltage feedback unit and a current adjustment unit, and the voltage feedback unit is used to generate a feedback voltage according to the initial current and output a corresponding reference voltage; the current adjustment unit is used to adjust the initial current to calibrate at least one reference current while the reference voltage remains unchanged.

[0007] In a second aspect, an embodiment of the present application further provides a chip, which includes the above-mentioned reference signal generating circuit.

[0008] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a device body and the above-mentioned reference signal generating circuit or chip provided in the device body.

[0009] The reference signal generating circuit, chip and electronic device provided in the embodiments of the present application can adjust the reference voltage individually by using a voltage feedback unit to generate a feedback voltage according to the initial current and output a corresponding reference voltage. The current adjustment unit can adjust the initial current to calibrate at least one reference current while keeping the reference voltage unchanged, so that the reference voltage or the reference current can be adjusted individually.

[0010] Furthermore, compared to calibrating only one reference current each time, the current adjustment unit of the present application can adjust the initial current to synchronously calibrate all reference currents, thereby improving the calibration efficiency of the reference current.

[0011] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A first principle block diagram of a reference signal generating circuit provided in an embodiment of the present application is shown.

[0014] Figure 2 The principle block diagram of the mirror module is shown.

[0015] Figure 3 A first circuit schematic diagram of the initial current generating branch is shown.

[0016] Figure 4 A second circuit schematic diagram of the initial current generating branch is shown.

[0017] Figure 5 The schematic diagram of the circuit of the mirror current branch is shown.

[0018] Figure 6 A first circuit schematic diagram of a voltage feedback unit is shown.

[0019] Figure 7 A second circuit schematic diagram of the voltage feedback unit is shown.

[0020] Figure 8 The circuit diagram of the current adjustment unit is shown.

[0021] Fig. 9 A first circuit schematic diagram of a reference signal generating circuit provided in an embodiment of the present application is shown.

[0022] Fig.10 A second circuit schematic diagram of a reference signal generating circuit provided in an embodiment of the present application is shown.

[0023] Fig.11 A third circuit schematic diagram of the reference signal generating circuit provided in an embodiment of the present application is shown.

[0024] Fig.12 A fourth circuit schematic diagram of the reference signal generating circuit provided in an embodiment of the present application is shown.

[0025] Fig.13 A schematic diagram of a chip provided in an embodiment of the present application is shown.

[0026] Fig.14 A schematic diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0028] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0029] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0030] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0031] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0032] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0033] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0034] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.

[0035] After the bandgap reference circuit is calibrated, it usually outputs a reference voltage that is independent of the power supply voltage and temperature. When the output reference voltage is required to be greater than or less than the reference voltage, it is usually scaled through a unity gain buffer (operational amplifier) ​​and a resistor divider. Changing the divider ratio can change the output reference voltage, and the current flowing through the divider resistor can be output as a reference current.

[0036] When a high-precision reference current is required to be output, the reference current needs to be calibrated. Usually, the calibration is performed by increasing or decreasing the number of current mirror branches connected in parallel. This method can only calibrate one reference current output at a time. The accuracy of the reference current outputs of other branches is still not high, and the calibration efficiency of the reference current is also low.

[0037] Based on this, the embodiment of the present application provides a reference signal generating circuit 100, such as Figure 1 As shown, the reference signal generating circuit 100 includes an operational amplifier module 10, a mirror module 20 and a reference signal adjusting module 30. The reference signal adjusting module 30 includes a voltage feedback unit 31 and a current adjusting unit 32. The voltage feedback unit 31 generates a feedback voltage VFB according to an initial current and outputs a corresponding reference voltage VREF. The reference voltage VREF can be adjusted separately. The current adjusting unit 32 can adjust the initial current to calibrate at least one reference current IREF while keeping the reference voltage VREF unchanged, so that the reference voltage VREF or the reference current IREF can be adjusted separately.

[0038] Furthermore, compared to calibrating only one reference current IREF each time, the current adjustment unit 32 of the present application can adjust the initial current so as to synchronously calibrate all reference currents IREF, thereby improving the calibration efficiency of the reference current IREF.

[0039] The present application embodiment provides a reference signal generating circuit 100. Figures 1 to 12 ,like Figure 1 As shown, the reference signal generating circuit 100 includes an operational amplifier module 10, a mirror module 20, a reference signal adjusting module 30, a voltage feedback unit 31 and a current adjusting unit 32. The reference signal adjusting module 30 includes a voltage feedback unit 31 and a current adjusting unit 32. The operational amplifier module 10 is used to output an operational amplifier signal according to a comparison result between a reference voltage VBG and a feedback voltage VFB; the mirror module 20 is used to generate a corresponding initial current under the control of the operational amplifier signal, and to mirror out at least one reference current IREF according to the initial current; the voltage feedback unit 31 is used to generate a feedback voltage VFB according to the initial current, and output a corresponding reference voltage VREF; the current adjusting unit 32 is used to adjust the initial current to calibrate at least one reference current IREF when the reference voltage VREF remains unchanged.

[0040] It can be understood that the reference signal generating circuit 100 provided in the embodiment of the present application can generate a feedback voltage VFB according to the initial current and output the corresponding reference voltage VREF through the voltage feedback unit 31, and the reference voltage VREF can be adjusted separately. The current adjustment unit 32 can adjust the initial current to calibrate at least one reference current IREF while keeping the reference voltage VREF unchanged, so that the reference voltage VREF or the reference current IREF can be adjusted separately.

[0041] Furthermore, compared to calibrating only one reference current IREF each time, the current adjustment unit 32 of the present application can adjust the initial current to synchronously calibrate all reference currents IREF, thereby improving the calibration efficiency of the reference current IREF.

[0042] It should be noted that the first input terminal of the operational amplifier module 10 is connected to the reference voltage VBG, the second input terminal of the operational amplifier module 10 is connected to the feedback voltage VFB, and the output terminal of the operational amplifier module 10 outputs the operational amplifier signal. The operational amplifier module 10 is connected to the mirror module 20, the mirror module 20 is connected to the current adjustment unit 32 and the voltage feedback unit 31, and the current adjustment unit 32 is connected in parallel with the voltage feedback unit 31.

[0043] Alternatively, if Figure 2 As shown, the mirror module 20 includes an initial current generating branch 21 and a current mirror branch 22. The initial current generating branch 21 is used to generate an initial current; the current mirror branch 22 is connected to the initial current generating branch 21 and is used to mirror at least one reference current according to the initial current.

[0044] It should be noted that the initial current generating branch 21 can be connected to the operational amplifier module 10 to generate an initial current according to the output signal of the operational amplifier module 10, and the current mirror branch 22 can mirror at least one reference current according to the initial current through a current mirror relationship.

[0045] Alternatively, if Figure 3 As shown, the initial current generating branch 21 includes a first transistor M1, a control electrode of the first transistor M1 is connected to the output end of the operational amplifier OP1, a first electrode of the first transistor M1 is connected to the power supply end VDD, and a second electrode of the first transistor M1 is connected to the voltage feedback unit 31 and the current adjustment unit 32.

[0046] It should be noted that the initial current generating branch 21 can generate the corresponding initial current through the first transistor M1 , which simplifies the circuit structure of the initial current generating branch 21 .

[0047] Alternatively, if Figure 4 As shown, the initial current generating branch 21 includes a first transistor M1 and a second transistor M3, the first electrode of the first transistor M1 is connected to the power supply terminal VDD, and the control electrode of the first transistor M1 is connected to the second electrode of the first transistor M1; the first electrode of the second transistor M3 is connected to the second electrode of the first transistor M1, the second electrode of the second transistor M3 is connected to the voltage feedback unit 31 and the current adjustment unit 32, and the control electrode of the second transistor M3 is connected to the output end of the operational amplifier module 10.

[0048] It should be noted that the initial current generating branch 21 generates a corresponding initial current through the first transistor M1 and the second transistor M3, which is beneficial to improving the accuracy of the initial current.

[0049] Alternatively, if Figure 5 As shown, the current mirror branch 22 includes at least one third transistor M2, the control electrode of the at least one third transistor M2 is connected to the control electrode of the first transistor M1, the first electrode of the at least one third transistor M2 is connected to the power supply terminal VDD, and the second electrode of the at least one third transistor M2 is used to output at least one reference current IREF.

[0050] It should be noted that since the first transistor M1 and at least one third transistor M2 can form a mirror structure, the current flowing through the first transistor M1 is the initial current, and the current flowing through the third transistor M2 is the reference current IREF. As the initial current changes, each reference current IREF will change accordingly to synchronously calibrate each reference current IREF.

[0051] Alternatively, if Figure 6 As shown, the voltage feedback unit 31 includes a first adjustable resistor R1 and a second resistor R2. The first adjustable resistor R1 is used to adjust the reference voltage VREF; the second resistor R2 is connected between the first adjustable resistor R1 and the ground terminal GND.

[0052] It should be noted that the reference voltage VREF can be adjusted by changing the resistance of the first adjustable resistor R1, wherein the reference voltage VREF is smaller than the base voltage VBG.

[0053] Alternatively, if Figure 6 As shown, one end of the first adjustable resistor R1 is connected to the operational amplifier module 10 and the mirror module 20 respectively, and the other end of the first adjustable resistor R1 is used to output the reference voltage VREF.

[0054] It should be noted that the reference voltage VREF outputted by this embodiment may be smaller than the feedback voltage VFB.

[0055] Alternatively, if Figure 7 As shown, one end of the first adjustable resistor R1 is connected to the mirror module 20 and outputs the reference voltage VREF, and the other end of the first adjustable resistor R1 is connected to the operational amplifier module 10 .

[0056] It should be noted that the reference voltage VREF outputted by this embodiment may be greater than the feedback voltage VFB.

[0057] Alternatively, if Figure 8As shown, the current adjustment unit 32 includes a third adjustable resistor R3 , one end of the third adjustable resistor R3 is connected to the mirror module 20 , and the other end of the third adjustable resistor R3 is connected to the ground terminal GND.

[0058] It should be noted that the third adjustable resistor R3 can be a sliding resistor or a resistor array to achieve adjustable resistance. The third adjustable resistor R3 is used to adjust the initial current and at least one reference current IREF when the reference voltage VREF remains unchanged.

[0059] Alternatively, if Fig. 9 , Fig.10 , Fig.11 as well as Fig.12 As shown, the reference signal generating circuit 100 further includes a bandgap reference module 60 , and the bandgap reference module 60 is used to output a reference voltage VBG.

[0060] It should be noted that the bandgap reference module 60 can be a bandgap reference circuit, and can trim the output reference voltage VBG. The bandgap reference module 60 is connected to the operational amplifier OP1 to provide the corresponding reference voltage VBG.

[0061] The operational amplifier module 10 includes an operational amplifier OP1 , a first input terminal of the operational amplifier OP1 is connected to a feedback voltage VFB, a second input terminal of the operational amplifier OP1 is connected to a reference voltage VBG, and an output terminal of the operational amplifier OP1 outputs an operational amplifier signal.

[0062] exist Fig. 9 , Fig.11 In the embodiment, the first input terminal of the operational amplifier OP1 is a non-inverting input terminal, and the second input terminal of the operational amplifier OP1 is an inverting input terminal. Fig.10 , Fig.12 In the embodiment, the first input terminal of the operational amplifier OP1 is an inverting input terminal, and the second input terminal of the operational amplifier OP1 is a non-inverting input terminal.

[0063] like Fig. 9 As shown, the reference voltage VREF output by the reference signal generating circuit 100 is lower than the reference voltage VBG. After the bandgap reference is calibrated, the bandgap reference module 60 of the reference signal generating circuit 100 outputs a reference voltage VBG that is independent of the process, power supply voltage and temperature. The operational amplifier OP1, the second transistor M3, the first adjustable resistor R1, the second resistor R2 and the third adjustable resistor R3 form a negative feedback loop. Under the action of the feedback loop, the positive input terminal and the inverting input terminal of the operational amplifier OP1 are virtually shorted, that is, the potential of the positive input terminal of the operational amplifier OP1 is equal to the potential of its inverting input terminal. Therefore, the magnitude of the reference voltage VREF can be expressed as the following calculation formula:

[0064] VREF=VFB×R2÷(R1+R2)=VBG×R2÷(R1+R2) (1)

[0065] Wherein, VREF represents the voltage value of the reference voltage VREF. VFB represents the potential of the inverting input terminal of the operational amplifier OP1. R1 represents the resistance value of the first adjustable resistor R1. R2 represents the resistance value of the second resistor R2. VBG represents the voltage value of the reference voltage VBG.

[0066] The drain current of the first transistor M1 is equal to the sum of the currents flowing through the first adjustable resistor R1 and the third resistor, and the gate-source voltage, gate length, and gate width of the third transistor M2 are respectively equal to the gate-source voltage, gate length, and gate width of the first transistor M1. This can be achieved by forming the first transistor M1 and the third transistor M2 with a corresponding number of minimum units of the same width-to-length ratio to ensure the mirror accuracy of the current. The reference current IREF (i.e., the drain current of the third transistor M2) is M times the initial current (i.e., the drain current of the first transistor M1), where M is an arbitrary number greater than 0. Therefore, the sum of the currents flowing through the first adjustable resistor R1 and the third adjustable resistor R3, i.e., IM3, can be expressed as the following calculation formula:

[0067] IM3=VFB÷[(R1+R2)∥R3]=VBG÷[(R1+R2)∥R3] (2)

[0068] Wherein, R3 represents the resistance value of the third adjustable resistor R3. (R1+R2)||R3 represents the equivalent resistance of the first adjustable resistor R1 connected in series with the second resistor R2 and then connected in parallel with the third adjustable resistor R3.

[0069] Since the first transistor M1 and the second transistor M3 are both connected in series with the equivalent resistor in the same branch, the current flowing through the equivalent resistor, i.e., IM3, is equal to the current flowing through the first transistor M1 and the current flowing through the second transistor M3. The reference current IREF can be expressed as follows:

[0070] IREF=M×IM3=M×VBG÷[(R1+R2)∥R3] (3)

[0071] Wherein, IREF represents the current value of the reference current IREF, and M is an adjustable coefficient, which is jointly determined by the first transistor M1 and the third transistor M2.

[0072] When the output reference voltage VREF is determined, the reference current IREF can be calibrated by changing the resistance of the third adjustable resistor R3. Fig.10 The calculation formulas for the reference voltage VREF and the reference current IREF can be calculated using the above calculation formulas (1) and (3).

[0073] Fig.11 The reference voltage VREF output by the reference signal generating circuit 100 is higher than the reference voltage VBG. After the bandgap reference is calibrated, a reference voltage VBG that is independent of the process, power supply voltage and temperature is output. The operational amplifier OP1, the second transistor M3, the first adjustable resistor R1, the second resistor R2 and the third adjustable resistor R3 form a negative feedback loop. Under the action of the feedback loop, the positive input terminal and the inverting input terminal of the operational amplifier OP1 are virtually shorted, that is, the potential of the positive input terminal of the operational amplifier OP1 is equal to the potential of its inverting input terminal. Therefore, the size of the reference voltage VREF can be expressed as the following calculation formula:

[0074] VREF=VFB×(1+R1 / R2)=VBG×(1+R1 / R2) (4)

[0075] Wherein, VREF represents the voltage value of the reference voltage VREF. VFB represents the potential of the inverting input terminal of the operational amplifier OP1. R1 represents the resistance value of the first adjustable resistor R1. R2 represents the resistance value of the second resistor R2. VBG represents the voltage value of the reference voltage VBG.

[0076] The drain current of the first transistor M1 is equal to the sum of the currents flowing through the first adjustable resistor R1 and the third resistor, and the gate-source voltage, gate length, and gate width of the third transistor M2 are respectively equal to the gate-source voltage, gate length, and gate width of the first transistor M1. This can be achieved by forming the first transistor M1 and the third transistor M2 with a corresponding number of minimum units of the same width-to-length ratio to ensure the mirror accuracy of the current. The reference current IREF (i.e., the drain current of the third transistor M2) is M times the initial current (i.e., the drain current of the first transistor M1), where M is an arbitrary number greater than 0. Therefore, the sum of the currents flowing through the first adjustable resistor R1 and the third adjustable resistor R3, i.e., IM3, can be expressed as the following calculation formula:

[0077] IM3=VREF÷[(R1+R2)∥R3]=VBG÷[(R1+R2)∥R3]×(1+R1 / R2) (5)

[0078] Wherein, R3 represents the resistance value of the third adjustable resistor R3. (R1+R2)||R3 represents the equivalent resistance of the first adjustable resistor R1 connected in series with the second resistor R2 and then connected in parallel with the third adjustable resistor R3.

[0079] Since the first transistor M1 and the second transistor M3 are both connected in series with the equivalent resistor in the same branch, the current flowing through the equivalent resistor, i.e., IM3, is equal to the current flowing through the first transistor M1 and the current flowing through the second transistor M3. The reference current IREF can be expressed as follows:

[0080] IREF=M×IM3=M×VBG÷[(R1+R2)∥R3]×(1+R1 / R2) (6)

[0081] Wherein, IREF represents the current value of the reference current IREF.

[0082] When the output reference voltage VREF is determined, the reference current IREF can be calibrated by changing the resistance of the third adjustable resistor R3. Fig.12 The calculation formulas for the reference voltage VREF and the reference current IREF can be calculated using the above calculation formulas (4) and (6).

[0083] It can be seen that the present application can be used to adjust the output reference voltage VREF by adjusting the resistance value of the first adjustable resistor R1. When the output reference voltage VREF is determined, the output reference current IREF can be calibrated by adjusting the resistance value of the third adjustable resistor R3 without changing the output reference voltage VREF.

[0084] The present application also provides a chip 200, such as Fig.13 As shown, the chip 200 includes the reference signal generating circuit 100. The chip 200 is also called an integrated circuit (IC), and the chip 200 can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip.

[0085] It can be understood that since the chip 200 provided in the embodiment of the present application includes the above-mentioned reference signal generating circuit 100, it can also generate a feedback voltage VFB according to the initial current through the voltage feedback unit 31 and output the corresponding reference voltage VREF, and the reference voltage VREF can be adjusted separately. The current adjustment unit 32 can adjust the initial current to calibrate at least one reference current IREF while keeping the reference voltage VREF unchanged, so that the reference voltage VREF or the reference current IREF can be adjusted separately.

[0086] Furthermore, compared to calibrating only one reference current IREF each time, the current adjustment unit 32 of the present application can adjust the initial current to synchronously calibrate all reference currents IREF, thereby improving the calibration efficiency of the reference current IREF.

[0087] The present application embodiment also provides an electronic device 300, such as Fig.14As shown, the electronic device 300 includes a device body and the above-mentioned reference signal generating circuit 100 or chip 200 provided in the device body. The electronic device 300 can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0088] It can be understood that since the electronic device 300 provided in the embodiment of the present application includes the above-mentioned reference signal generating circuit 100 or chip 200, it can also generate a feedback voltage VFB according to the initial current through the voltage feedback unit 31 and output the corresponding reference voltage VREF, and the reference voltage VREF can be adjusted separately. The current adjustment unit 32 can adjust the initial current to calibrate at least one reference current IREF while keeping the reference voltage VREF unchanged, so that the reference voltage VREF or the reference current IREF can be adjusted separately.

[0089] Furthermore, compared to calibrating only one reference current IREF each time, the current adjustment unit 32 of the present application can adjust the initial current to synchronously calibrate all reference currents IREF, thereby improving the calibration efficiency of the reference current IREF.

[0090] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as a preferred embodiment as above, it is not intended to limit the present application. Any technical personnel in this field can use the technical contents disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes without departing from the scope of the technical solution of the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A reference signal generating circuit, characterized in that: The reference signal generating circuit comprises: An operational amplifier module, the operational amplifier module is used to output an operational amplifier signal according to a comparison result between a reference voltage and a feedback voltage; A mirror module, the mirror module is used to generate a corresponding initial current under the control of the operational amplifier signal, and to mirror at least one reference current according to the initial current; A reference signal adjustment module, the reference signal adjustment module includes a voltage feedback unit and a current adjustment unit, the voltage feedback unit is used to generate the feedback voltage according to the initial current and output the corresponding reference voltage; the current adjustment unit is used to adjust the initial current to calibrate the at least one reference current when the reference voltage remains unchanged.

2. The reference signal generating circuit according to claim 1, wherein: The mirror module includes: An initial current generating branch, wherein the initial current generating branch is used to generate the initial current; A current mirror branch, the current mirror branch is connected to the initial current generating branch, and is used to mirror at least one reference current according to the initial current.

3. The reference signal generating circuit according to claim 2, wherein: The initial current generating branch includes a first transistor, a control electrode of the first transistor is connected to the output end of the operational amplifier module, a first electrode of the first transistor is connected to the power supply end, and a second electrode of the first transistor is connected to the voltage feedback unit and the current adjustment unit.

4. The reference signal generating circuit according to claim 2, wherein: The initial current generating branch comprises: a first transistor, wherein a first electrode of the first transistor is connected to a power supply terminal, and a control electrode of the first transistor is connected to a second electrode of the first transistor; A second transistor, wherein a first electrode of the second transistor is connected to a second electrode of the first transistor, a second electrode of the second transistor is connected to the voltage feedback unit and the current adjustment unit, and a control electrode of the second transistor is connected to an output end of the operational amplifier module.

5. The reference signal generating circuit according to claim 3 or 4, characterized in that: The current mirror branch includes at least one third transistor, the control electrode of the at least one third transistor is connected to the control electrode of the first transistor, the first electrode of the at least one third transistor is connected to the power supply end, and the second electrode of the at least one third transistor is used to output the at least one reference current.

6. The reference signal generating circuit according to claim 1, wherein: The voltage feedback unit comprises: A first adjustable resistor, used to adjust the reference voltage; A second resistor is connected between the first adjustable resistor and a ground terminal.

7. The reference signal generating circuit according to claim 6, wherein: One end of the first adjustable resistor is connected to the mirror module and the operational amplifier module respectively, and the other end of the first adjustable resistor is used to output the reference voltage.

8. The reference signal generating circuit according to claim 6, wherein: One end of the first adjustable resistor is connected to the mirror module and outputs the reference voltage, and the other end of the first adjustable resistor is connected to the operational amplifier module.

9. The reference signal generating circuit according to claim 1, wherein: The current adjustment unit comprises a third adjustable resistor, one end of the third adjustable resistor is connected to the mirror module, and the other end of the third adjustable resistor is connected to the ground end; The third adjustable resistor is used to adjust the initial current and the at least one reference current when the reference voltage remains unchanged.

10. A chip, characterized in that: The chip comprises the reference signal generating circuit as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: The electronic device comprises a device body and the chip according to claim 10 disposed in the device body.

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