An FEC-based adaptive SerDes architecture and its power consumption adjustment method

Abstract

The application provides an adaptive SerDes architecture and power consumption adjustment method based on FEC, which comprises an analog front end, an analog-to-digital converter, a digital signal processor, a sending side forward error correction encoder, a receiving side forward error correction decoder, a microprogram controller and the like, wherein the sending side forward error correction encoder encodes data by adding an additional error correction code to the transmission data; the receiving side forward error correction decoder decodes the transmission data, identifies and corrects errors occurring in the data transmission process through the added error correction code; the microprogram controller is used for real-time monitoring of the sending side forward error correction encoder and the receiving side forward error correction decoder, and reading back the log information of the sending side forward error correction encoder and the receiving side forward error correction decoder. The technical scheme of the application can adaptively balance the signal quality and power consumption of the SerDes, and has good applicability in different product scenarios and different PVT states of chips.

Description

Technical Field

[0001] This application belongs to the field of communication technology, and specifically relates to an adaptive SerDes architecture based on FEC and its power consumption regulation method. Background Technology

[0002] Power consumption has always been a crucial parameter in chip applications. With technological advancements, chip designs are becoming smaller and more integrated, leading to higher power density. Especially with the advent of FinFET technology, heat dissipation has become a significant factor limiting further increases in chip integration.

[0003] In highly integrated, high-power-density communication and computing chips, the power consumption of SerDes (Serial-Deserial) IP has always been a significant component of total power consumption. This is especially true for high-bandwidth switching and routing chips, where the large signal bandwidth and numerous SerDes ports mean that SerDes power consumption can exceed 50%. Therefore, minimizing SerDes power consumption per unit bandwidth is a crucial and ongoing effort in addressing chip heat dissipation issues.

[0004] In the circuit design process of SerDes, typical circuit modules are designed with different power consumption levels. For example, the current level of the AFE (Analog front end) is adjustable, the bit depth of the ADC (Analog to Digital converter) is adjustable, and the regulator output voltage V... reg With adjustable power levels, different power consumption configuration levels can be used in different application scenarios and with different performance requirements, thereby achieving the goal of minimizing power consumption according to different scenarios.

[0005] However, in the process of productization, the application scenarios of SerDes are often very complex. The same SerDes chip channel may have vastly different link conditions in different applications, making it difficult to clearly define which scenarios use which power consumption levels during chip development. Moreover, due to the different PVT conditions of the chip, the performance of SerDes itself will also fluctuate significantly, making the specific implementation of power consumption level configurations even more difficult.

[0006] Therefore, a higher-performance and more flexible power consumption regulation method is needed. Summary of the Invention

[0007] The purpose of this application is to provide an adaptive SerDes architecture based on FEC (Forward Error Correction) and its power consumption regulation method, which aims to maximize the saving of power consumption used by SerDes in different scenarios.

[0008] According to a first aspect of this application, an adaptive SerDes architecture based on FEC is provided, including an analog front-end, an analog-to-digital converter, a digital signal processor, a transmitting-side forward error correction encoder, a receiving-side forward error correction decoder, a microprogrammed controller, a phase-locked loop, a digital-to-analog converter, and a forward equalizer, wherein...

[0009] The analog front end is used to perform preliminary inter-symbol interference compensation on the input signal;

[0010] The analog-to-digital converter is used to convert the signal after preliminary inter-symbol interference compensation by the analog front end into a digital signal.

[0011] The digital signal processor is used to further compensate for inter-symbol interference in the digital signal digitized by the analog-to-digital converter, and then recover the data in the input signal.

[0012] The transmitting-side forward error correction encoder adds additional error correction codes to the transmitted data to encode the data;

[0013] The forward error correction decoder on the receiving side decodes the transmitted data and uses the added error correction code to identify and correct errors that occur during data transmission.

[0014] The microprogram controller is used to monitor the transmitting-side forward error correction encoder and the receiving-side forward error correction decoder in real time, and to read back the log information of the transmitting-side forward error correction encoder and the receiving-side forward error correction decoder.

[0015] The phase-locked loop is used to generate a high-speed, high-performance local clock;

[0016] The digital-to-analog converter is used for transmitting high-speed signals at this end;

[0017] The forward equalizer is used to pre-compensate the signal quality of the high-speed signal transmitted from this end.

[0018] In an optional implementation, the microprogrammed controller includes a power control algorithm module, which includes a comparator, an accumulator, a threshold comparator, an accumulator, and a lookup table.

[0019] In an optional implementation, the microprogrammed controller includes an FW software module for processing log information.

[0020] In an optional implementation, the microprogrammed controller controls the power consumption of the analog front-end, phase-locked loop, analog-to-digital converter, and digital signal processor.

[0021] In an optional implementation, the microprogrammed controller dynamically adjusts the bias current level of the analog front-end and the phase-locked loop, and the V of the clock path, based on the margin state of the data signal. reg Power consumption control is achieved through voltage levels, bit width levels of analog-to-digital converters, and calculation precision levels of digital signal processors.

[0022] According to a second aspect of this application, an adaptive power regulation method for a SerDes architecture based on FEC is provided, comprising the following steps:

[0023] The transmitting-side forward error correction encoder adds extra error correction codes to the transmitted data to encode the data; after the transmitted data arrives at the receiving side, the receiving-side forward error correction decoder decodes the transmitted data and uses the added error correction codes to identify and correct errors that occur during data transmission.

[0024] The microprogram controller monitors the forward error correction encoder on the transmitting side and the forward error correction decoder on the receiving side, and reads back and analyzes the log information therein to obtain the code data of the maximum symbol error correction of the link.

[0025] The link's margin status is evaluated based on the obtained code data for maximum symbol error correction, and the power consumption levels of the main functional modules in SerDes are dynamically adjusted based on the margin status.

[0026] In an optional implementation, dynamically adjusting the power consumption levels of the main functional modules in SerDes based on the Margin state includes adjusting the Bias current level of modules such as AFE / PLL, the Vreg voltage level of the Clock path, the bit width level of the ADC, and the calculation accuracy level of the DSP.

[0027] In an optional implementation, the microprogram controller uses a built-in FW software processing algorithm to analyze the log information therein.

[0028] In an optional implementation, the FW software processing algorithm includes low-pass filtering.

[0029] In an optional implementation, after obtaining the code data for the maximum symbol error correction of the link, the microprogram controller performs algorithmic processing on the code data. The algorithmic processing includes a comparison algorithm, an accumulation algorithm, a threshold comparison, an accumulator, and a lookup table.

[0030] Compared with related technologies, the technical solution of this application has at least the following advantages:

[0031] The FEC-based adaptive SerDes architecture presented in this application is compatible with typical high-speed SerDes implementation architectures without incurring significant additional costs. This application adaptively balances SerDes signal quality and power consumption, demonstrating excellent applicability across various product scenarios and chip PVT states. Furthermore, due to its software-controlled approach, the optimization and debugging of this application are highly flexible.

[0032] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures and processes shown in the description and the accompanying drawings. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a diagram of an adaptive SerDes architecture based on FEC, according to an exemplary embodiment of this application.

[0035] Figure 2 This is a schematic diagram of an MCU-based power consumption control algorithm according to an exemplary embodiment of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] In order to save as much power consumption as possible in the SerDes PHY (Physical Layer) under normal business environment, this application proposes a technical solution that can adaptively adjust the parameter configuration according to the performance margin of SerDes under the current link scenario and the current chip PVT (Process, Voltage, Temperature) characteristics, so as to maximize the saving of power consumption used by SerDes in different scenarios.

[0038] like Figure 1 As shown, an adaptive SerDes architecture based on FEC is provided, including an AFE (Analog frontend), an ADC (Analog to Digital Converter), a DSP (Digital Signal Processor), a transmitting-side FEC (Forward Error Correction) encoder, a receiving-side FEC decoder, a MCU (Microprogrammed Control Unit), a PLL (Phase Lock Loop), a DAC (Digital to Analog Converter), and an FFE (Feed-Forward Equalizer). The AFE is used to perform preliminary inter-symbol interference compensation on the input signal, the ADC is used to convert the signal after preliminary inter-symbol interference compensation by the analog frontend into a digital signal, and the DSP is used to perform further inter-symbol interference compensation on the digital signal digitized by the analog-to-digital converter, and then recover the data from the input signal.

[0039] The transmitting-side FEC encoder adds additional error correction codes to the transmitted data to encode the data;

[0040] The receiving-side FEC decoder decodes the transmitted data and identifies and corrects errors that occur during data transmission by adding error correction codes. The MCU monitors the transmitting-side FEC encoder and the receiving-side FEC decoder in real time and reads back the log information of the transmitting-side FEC encoder and the receiving-side FEC decoder. LLC is used to generate a high-speed, high-performance local clock, DAC is used for transmitting high-speed signals at this end, and FFE is used to pre-compensate the signal quality of the high-speed signals transmitted at this end.

[0041] Another embodiment of this application provides an adaptive power consumption regulation method based on FEC, comprising the following steps:

[0042] The transmitting-side FEC encoder adds extra error correction codes to the transmitted data to encode the data. This process enhances the error detection and correction capabilities of the data during transmission by adding extra error correction codes. After the transmitted data arrives at the receiving side, the receiving-side FEC decoder decodes the transmitted data and uses the added error correction codes to identify and correct errors that occurred during data transmission, thereby reducing the original bit error rate and improving the reliability and efficiency of data transmission.

[0043] The MCU monitors the transmitting-side FEC encoder and the receiving-side FEC decoder. This process allows the system to gain an immediate understanding of the FEC module's functionality and performance, providing data support for subsequent adjustments and optimizations. It also reads back and analyzes the log information to obtain the code data for maximum symbol correction (MPC) of the link; this log information, containing MPC code data, is crucial for analyzing and optimizing link performance.

[0044] like Figure 2 As shown, after obtaining the code data for the maximum symbol error correction in the link, the microprogram controller performs certain algorithmic processing on the code, including comparison algorithms, accumulation algorithms, threshold comparisons, accumulators, and lookup tables. After the above processing, the power consumption levels of the main functional modules in SerDes can be dynamically adjusted according to the preset margin state, including adjusting the bias current level of modules such as AFE / PLL and the V of the Clock path. reg Voltage level, ADC bit width level, and DSP calculation accuracy level.

[0045] The MCU uses its built-in firmware (FW) software processing algorithm to analyze the log information. FW software refers to software that exists in the form of firmware, which typically resides between the operating system and applications of the hardware device, and is used to control and manage the basic functions of the hardware.

[0046] This application dynamically collects the performance margin of the data signal received by SerDes during normal SerDes operation, and then dynamically adjusts the bias current level of modules such as AFE (Analog front end) / PLL (Phase Locked Loop) and the V value of the clock path based on the performance margin status of the data signal. reg By adjusting voltage levels, ADC bit width levels, and DSP calculation precision levels, the power consumption of SerDes IP is reduced to a certain extent at the cost of lowering the performance margin. This allows SerDes to achieve a dynamic balance between power consumption and performance margin, thereby maximizing power savings.

[0047] In summary, through precise monitoring and dynamic adjustment, high-speed PMA4 (4-Level Pulse Amplitude Modulation) SerDes applications can optimize power consumption while ensuring data transmission performance. This not only improves the system's economy but also enhances its environmental friendliness, making it an indispensable part of modern high-speed communication systems.

[0048] Because the solution proposed in this application can dynamically monitor the link margin status in real time and adaptively control the balance between power consumption and performance, it can be flexibly used in various complex scenarios and under different chip PVT conditions. Furthermore, since the core control components are implemented using software, debugging is also very flexible.

[0049] Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An FEC-based adaptive SerDes architecture, characterized by, The SerDes includes an analog front end, an analog-to-digital converter, a digital signal processor, a transmitting-side forward error correction encoder, a receiving-side forward error correction decoder, a microprogram controller, a phase-locked loop, a digital-to-analog converter and a feed-forward equalizer, wherein the analog front end is configured to perform preliminary inter-symbol interference compensation on an input signal; the analog-to-digital converter is configured to convert the signal after preliminary inter-symbol interference compensation by the analog front end into a digital signal; the digital signal processor is configured to perform further inter-symbol interference compensation on the digital signal after digitization by the analog-to-digital converter, and then recover data in the input signal; the transmitting-side forward error correction encoder encodes the transmission data by adding an additional error correction code to the data; the receiving-side forward error correction decoder decodes the transmission data, and identifies and corrects errors occurring in the data transmission process by using the additional error correction code; the microprogram controller is configured to monitor the transmitting-side forward error correction encoder and the receiving-side forward error correction decoder in real time, and read back log information of the transmitting-side forward error correction encoder and the receiving-side forward error correction decoder; the phase-locked loop is configured to generate a high-speed and high-performance local clock; the digital-to-analog converter is configured to transmit a high-speed signal at the local end; the feed-forward equalizer is configured to pre-compensate the signal quality of the high-speed signal transmitted at the local end, the microprogram controller dynamically adjusts the Bias current level of the analog front end and the phase-locked loop, the Vreg voltage level of the Clock path, the bit width level of the analog-to-digital converter and the calculation precision level of the digital signal processor according to the Margin state of the data signal, to realize power consumption control.

2. The FEC-based adaptive SerDes architecture as in claim 1, wherein, The microprogram controller includes a power consumption control algorithm module, which includes a comparator, an accumulator, a threshold comparator, an accumulator and a lookup table.

3. The FEC-based adaptive SerDes architecture as in claim 1, wherein, The microprogram controller includes an FW software module for processing log information.

4. The FEC-based adaptive SerDes architecture as in claim 1, wherein, The microprogram controller controls the power consumption of the analog front end, the phase-locked loop, the analog-to-digital converter and the digital signal processor.

5. A method of power consumption adjustment for a SerDes architecture employing adaptive FEC as claimed in any one of claims 1 to 4, wherein, The method includes the following steps: the transmitting-side forward error correction encoder encodes the transmission data by adding an additional error correction code to the data; after the transmission data reaches the receiving side, the receiving-side forward error correction decoder decodes the transmission data, and identifies and corrects errors occurring in the data transmission process by using the additional error correction code; the microprogram controller monitors the transmitting-side forward error correction encoder and the receiving-side forward error correction decoder, reads back and analyzes the log information therein, and obtains code data of maximum symbol error correction of the link; According to the obtained code data of maximum symbol error correction of the link, the Margin state of the link is evaluated, and the power consumption level of the main functional modules in the SerDes is dynamically adjusted according to the Margin state.

6. The method of power adjustment for the FEC-based adaptive SerDes architecture of claim 5, wherein, The power consumption level of the main functional modules in the SerDes includes adjusting the Bias current level of the analog front end and the phase-locked loop module, the Vreg voltage level of the Clock path, the bit width level of the analog-to-digital converter and the calculation precision level of the digital signal processor.

7. The method of claim 5, wherein the power consumption of the FEC-based adaptive SerDes architecture is adjusted by, The microprogram controller analyzes the log information therein using a built-in FW software processing algorithm.

8. The method of power adjustment for the FEC-based adaptive SerDes architecture of claim 7, wherein, The FW software processing algorithm includes low pass filtering processing.

9. The method of power adjustment for the FEC-based adaptive SerDes architecture of claim 5, wherein, The microprogram controller, after obtaining code data of maximum symbol error correction of a link, processes the code data using an algorithm, which includes a comparison algorithm, an accumulation algorithm, threshold comparison, an accumulator, and a lookup table.

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