Transmission method, access method, transmission device and access device

Abstract

The embodiment of the invention provides a sending method, an access method, a sending device and an access device, relates to the field of computers, and solves the problem of how to consider both large bandwidth and small memory capacity when a high-bandwidth memory is used as a cache. According to the specific scheme, an access request of a process is obtained, the access request comprises first indication information and second indication information, the first indication information is used for indicating the priority of the process, and the second indication information is used for indicating the required bandwidth of the process; if the first indication information is the first priority and the second indication information indicates that the required bandwidth of the process is greater than or equal to a preset value, third indication information is generated, and the third indication information is used for indicating that data corresponding to the access request is stored in a high-bandwidth memory; and sending the access request based on the third indication information. The embodiment of the invention is used for the storage process when the high-bandwidth memory is used as the cache.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of computers, and in particular, to a sending method, an access method, a sending device, and an access device. Background Art

[0002] At present, the requirements for memory bandwidth in fields such as high performance computing (HPC), artificial intelligence (AI), machine learning and data analysis are getting higher and higher, thus introducing high bandwidth memory (HBM). High bandwidth memory is a computer memory that uses through silicon vias (TSV) technology to achieve three-dimensional (3D) stacking of synchronous dynamic random-access memory (SDRAM). Compared with SDRAM, it has the characteristics of higher density, larger bandwidth and lower latency. When high bandwidth memory is used as cache mode, it can provide large bandwidth, but the memory capacity of high bandwidth memory is small. Therefore, how to reasonably and effectively use high bandwidth memory has become an urgent problem to be solved. Summary of the invention

[0003] The embodiments of the present application provide a sending method, an access method, a sending device, and an access device, which solve the problem of how to balance high bandwidth and small memory capacity when a high-bandwidth memory is used as a cache.

[0004] In order to achieve the above-mentioned purpose, the embodiment of the present application adopts the following technical solution.

[0005] In a first aspect, an embodiment of the present application provides a sending method, the method comprising: obtaining an access request of a process, the access request comprising first indication information and second indication information, the first indication information being used to indicate a priority of the process, and the second indication information being used to indicate a required bandwidth of the process; if the first indication information is a first priority, and the second indication information indicates that the required bandwidth of the process is greater than or equal to a preset value, generating third indication information, the third indication information being used to indicate that data corresponding to the access request is stored in a high-bandwidth memory; and sending the access request based on the third indication information.

[0006] Therefore, in the sending method provided in the embodiment of the present application, each process is configured with a priority, wherein the first priority can be understood as an important priority. In addition, the required bandwidth of a process being greater than or equal to a preset value can be understood as the process having a large demand for bandwidth. Therefore, the data corresponding to the process having an important priority and a large demand for bandwidth can be selectively stored in the high-bandwidth memory, which can reasonably and effectively utilize the large bandwidth characteristics of the high-bandwidth memory while taking into account the small memory capacity characteristics of the high-bandwidth memory.

[0007] In one possible design, the method also includes: if the first indication information is the second priority, or the second indication information indicates that the required bandwidth of the process is less than a preset value, generating fourth indication information, the first priority is higher than the second priority, and the fourth indication information is used to indicate that the data corresponding to the access request is stored in the memory; and sending an access request based on the fourth indication information.

[0008] In this design, the first priority is higher than the second priority, that is, the process of the second priority is a non-important process. In addition, the required bandwidth of the process is less than the preset value, which can be understood as the process has a small demand for bandwidth. Therefore, the data corresponding to the process of non-important priority or small bandwidth demand can be selectively stored in the memory instead of the high-bandwidth memory, which can alleviate the storage pressure of the high-bandwidth memory.

[0009] In one possible design, the third indication information is a first state of a page table entry control bit, and the fourth indication information is a second state of the page table entry control bit, and the first state is opposite to the second state.

[0010] In this design, the embodiments of the present application can provide a fine-grained control method based on page granularity to control the storage of access requested data in a high-bandwidth memory or memory, and can enable the processor core to execute a program to control the caching and elimination of memory data.

[0011] In a possible design, the operating state of the processor core includes a user state and a kernel state. When the processor core is in the user state, the page table entry control bit is a process page table entry control bit; when the processor core is in the kernel state, the page table entry control bit is a kernel page table entry control bit.

[0012] In this design, the processor core can configure the process page table entry control bit through the process page table, and can configure the kernel page table entry control bit through the kernel page table. In different operating states of the processor core, the processor core can execute programs to control the caching and elimination of memory data.

[0013] In a possible design, the third indication information is a first address range, which corresponds to an address of the high bandwidth memory; the fourth indication information is a second address range, which corresponds to an address of the memory.

[0014] In this design, the embodiment of the present application can provide a coarse-grained control method based on the address range to control the storage of the data of the access request to the high-bandwidth storage or memory, and can enable the processor core to execute a program to control the caching and elimination of memory data.

[0015] In a second aspect, an embodiment of the present application provides an access method, the method comprising: receiving an access request from a process; if the access request includes third indication information, storing data corresponding to the access request in a high-bandwidth memory, the third indication information being used to indicate that the data corresponding to the access request should be stored in the high-bandwidth memory.

[0016] Therefore, in the access method provided in the embodiment of the present application, the hardware circuit receives the access request of the processor core, and if the access request includes the third indication information, the processor core indicates that the data corresponding to the access request is stored in the high bandwidth memory. Thus, the processor core can execute the program to control the caching and elimination of memory data.

[0017] In one possible design, the method further includes: if the access request includes fourth indication information, storing the data corresponding to the access request in the memory, and the fourth indication information is used to indicate that the data corresponding to the access request is stored in the memory.

[0018] In this design, if the access request includes the fourth indication information, that is, the processor core instructs to store the data corresponding to the access request into the memory, thereby enabling the processor core to execute a program to control the caching and elimination of memory data.

[0019] In one possible design, the third indication information is a first state of a page table entry control bit, and the fourth indication information is a second state of the page table entry control bit, and the first state is opposite to the second state.

[0020] In a possible design, the operating state of the processor core includes a user state and a kernel state. When the processor core is in the user state, the page table entry control bit is a process page table entry control bit; when the processor core is in the kernel state, the page table entry control bit is a kernel page table entry control bit.

[0021] In a possible design, the third indication information is a first address range, which corresponds to an address of the high bandwidth memory; the fourth indication information is a second address range, which corresponds to an address of the memory.

[0022] In a third aspect, an embodiment of the present application provides a sending method, the method comprising: obtaining an access request of a process, the access request comprising a process identifier; generating third indication information based on the process identifier, the third indication information being a proportion of data corresponding to the process identifier in the storage space of the high-bandwidth memory; and sending the access request based on the third indication information.

[0023] Therefore, in the sending method provided in the embodiment of the present application, each process is configured with the third indication information, that is, the proportion of data allocated to the process in the storage space of the high-bandwidth memory is allocated to each process. Therefore, the embodiment of the present application can control the storage of the data of the access request to the high-bandwidth memory or memory based on the process granularity control method, and can realize the processor core execution program to control the caching and elimination of memory data.

[0024] In a possible design, the access request also includes first indication information and second indication information, the first indication information is used to indicate the priority of the process, and the second indication information is used to indicate the required bandwidth of the process; the process identifier corresponds to the proportion of processes whose first priority is the first indication information and the required bandwidth of the process indicated by the second indication information is greater than or equal to a preset value, which is greater than the proportion of processes whose process identifier corresponds to the first indication information as the second priority or the required bandwidth of the process indicated by the second indication information is less than a preset value.

[0025] In this design, by setting different proportions for each process, the data of important processes with large bandwidth requirements can be stored in the high-bandwidth memory as much as possible, which can reasonably and effectively utilize the large bandwidth characteristics of the high-bandwidth memory while taking into account the small memory capacity characteristics of the high-bandwidth memory.

[0026] In a fourth aspect, an embodiment of the present application provides an access method, the method comprising: receiving an access request from a process, the access request comprising third indication information, the third indication information being a proportion of data corresponding to a process identifier in a storage space of a high-bandwidth memory; if the data corresponding to the access request does not exceed the proportion corresponding to the third indication information, storing the data corresponding to the access request in the high-bandwidth memory.

[0027] Therefore, in the access method provided in the embodiment of the present application, the hardware circuit receives an access request from the processor core. If the data in the access request does not exceed the proportion corresponding to the third indication information, the data corresponding to the access request can be stored in the high-bandwidth memory, and the processor core can execute a program to control the caching and elimination of memory data.

[0028] In one possible design, the method further includes: if the data corresponding to the process exceeds the proportion corresponding to the indication information, storing the data corresponding to the access request in the memory.

[0029] In this design, if the data in the access request exceeds the proportion corresponding to the third indication information, part of the data corresponding to the access request can be first stored in the high-bandwidth memory. When the storage space allocated to the process in the high-bandwidth memory is full, the excess data in the access request can be stored in the memory.

[0030] In a fifth aspect, an embodiment of the present application provides a sending device, the sending device comprising: an acquisition unit, used to acquire an access request of a process, the access request comprising first indication information and second indication information, the first indication information being used to indicate a priority of the process, and the second indication information being used to indicate a required bandwidth of the process; a generation unit, used to generate third indication information if the first indication information is a first priority and the second indication information indicates that the required bandwidth of the process is greater than or equal to a preset value, the third indication information being used to indicate that the data corresponding to the access request is stored in a high-bandwidth memory; a sending unit, used to send the access request based on the third indication information.

[0031] The beneficial effects of the fifth aspect can refer to the description of the first aspect.

[0032] In one possible design, the generating unit is also used to: if the first indication information is the second priority, or the second indication information indicates that the required bandwidth of the process is less than a preset value, generate fourth indication information, the first priority is higher than the second priority, and the fourth indication information is used to indicate that the data corresponding to the access request is stored in the memory; the sending unit is also used to: send an access request based on the fourth indication information.

[0033] In one possible design, the third indication information is a first state of a page table entry control bit, and the fourth indication information is a second state of the page table entry control bit, and the first state is opposite to the second state.

[0034] In a possible design, the operating state of the processor core includes a user state and a kernel state. When the processor core is in the user state, the page table entry control bit is a process page table entry control bit; when the processor core is in the kernel state, the page table entry control bit is a kernel page table entry control bit.

[0035] In a possible design, the third indication information is a first address range, and the first address range corresponds to the address of the high bandwidth memory. The fourth indication information is a second address range, and the second address range corresponds to the address of the memory.

[0036] In a sixth aspect, an embodiment of the present application provides an access device, the access device comprising: a receiving unit, used to receive an access request of a process; a sending unit, used to store the data corresponding to the access request in a high-bandwidth memory if the access request includes third indication information, the third indication information being used to indicate that the data corresponding to the access request should be stored in the high-bandwidth memory.

[0037] The beneficial effects of the sixth aspect can be found in the description of the second aspect.

[0038] In one possible design, the sending unit is further used to: if the access request includes fourth indication information, store the data corresponding to the access request in the memory, and the fourth indication information is used to indicate that the data corresponding to the access request is stored in the memory.

[0039] In one possible design, the third indication information is a first state of a page table entry control bit, and the fourth indication information is a second state of the page table entry control bit, and the first state is opposite to the second state.

[0040] In a possible design, the operating state of the processor core includes a user state and a kernel state. When the processor core is in the user state, the page table entry control bit is a process page table entry control bit; when the processor core is in the kernel state, the page table entry control bit is a kernel page table entry control bit.

[0041] In a possible design, the third indication information is a first address range, which corresponds to an address of the high bandwidth memory; the fourth indication information is a second address range, which corresponds to an address of the memory.

[0042] In the seventh aspect, an embodiment of the present application provides a sending device, the sending device comprising: an acquisition unit, used to obtain an access request of a process, the access request comprising a process identifier; a generation unit, used to generate third indication information based on the process identifier, the third indication information being the proportion of data allocated to the process identifier in the storage space of the high-bandwidth memory; a sending unit, used to send the access request based on the third indication information.

[0043] The beneficial effects of the seventh aspect can be found in the description of the third aspect.

[0044] In a possible design, the access request also includes first indication information and second indication information, the first indication information is used to indicate the priority of the process, and the second indication information is used to indicate the required bandwidth of the process; the process identifier corresponds to the proportion of processes whose first priority is the first indication information and the required bandwidth of the process indicated by the second indication information is greater than or equal to a preset value, which is greater than the proportion of processes whose process identifier corresponds to the first indication information as the second priority or the required bandwidth of the process indicated by the second indication information is less than a preset value.

[0045] In an eighth aspect, an embodiment of the present application provides an access device, the access device comprising: a receiving unit, used to receive an access request from a process, the access request comprising third indication information, the third indication information being the proportion of data corresponding to a process identifier in a storage space of a high-bandwidth memory; a sending unit, used to store the data corresponding to the access request in the high-bandwidth memory if the data corresponding to the access request does not exceed the proportion corresponding to the third indication information.

[0046] The beneficial effects of the eighth aspect can refer to the description of the fourth aspect.

[0047] In a possible design, the sending unit is also used to: if the data corresponding to the process exceeds the proportion corresponding to the indication information, store the data corresponding to the access request in the memory.

[0048] In a ninth aspect, the present application provides a chip, comprising: a processor and a power supply circuit; wherein the power supply circuit is used to supply power to the processor; and the processor is used to implement the method of any aspect.

[0049] In a tenth aspect, the present application provides a computer device, comprising a processor and a memory, wherein the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, it is used to execute the method of any aspect.

[0050] In an eleventh aspect, the present application provides a computer-readable storage medium, comprising computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the sending method and access method in any of the above aspects and any possible implementation methods.

[0051] In a twelfth aspect, the present application provides a computer program product. When the computer program product runs on a computer or a processor, it enables the computer or the processor to execute the sending method and the access method in any of the above aspects and any possible implementation methods.

[0052] It can be understood that any of the sending devices, access devices, chips, computer devices, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0053] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A hardware block diagram of an application resource indicator technology provided in an embodiment of the present application;

[0055] Figure 2A hardware block diagram of a memory system resource partitioning and monitoring technology provided in an embodiment of the present application;

[0056] Figure 3 A schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0057] Figure 4 A system structure diagram of a sending method and an access method application provided in an embodiment of the present application;

[0058] Figure 5 A flow chart of a sending method and an access method provided in an embodiment of the present application;

[0059] Figure 6 A flowchart of another sending method and access method provided in an embodiment of the present application;

[0060] Figure 7 A flow chart based on page table entry control bits provided in an embodiment of the present application;

[0061] Figure 8 A flowchart based on address range is provided for an embodiment of the present application;

[0062] Fig. 9 A flow chart of a sending method and an access method provided in an embodiment of the present application;

[0063] Fig.10 A process granularity-based flowchart provided for an embodiment of the present application;

[0064] Fig.11 A method flow chart of a computer system provided in an embodiment of the present application;

[0065] Fig.12 A schematic diagram of the composition of a sending device provided in an embodiment of the present application;

[0066] Fig.13 A schematic diagram of the composition of an access device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] For ease of understanding, some examples of concepts related to the embodiments of the present application are provided for reference, as shown below:

[0068] User state is the environment in which the application runs. The processor core can access local memory space and limited system resources. The processor core can execute non-privileged instructions in user state, such as MOV instructions, ADD instructions, and SUB instructions.

[0069] Kernel state is the environment in which the operating system runs. The processor core can access all resources and can execute all instructions (privileged instructions and non-privileged instructions), where privileged instructions can include IN instructions and OUT instructions.

[0070] Process (process / job / task), the basic unit of resource allocation of the operating system, contains information such as program code, data, and execution status. Generally, when a program is started, the operating system will create a process for the program.

[0071] Threads are independently executable units within a process. They share the address space of the process but each saves the state (i.e., context) required for runtime.

[0072] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0073] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0074] In order to improve the utilization of memory bandwidth in the server, a resource director technology (RDT) is proposed. Figure 1 As shown, Figure 1 A hardware block diagram of an application resource indicator technology provided in an embodiment of the present application. Figure 1The user mode, kernel mode and hardware circuit are shown in the figure, wherein multiple threads in the user mode call the user interface, and the kernel mode includes: RDT module, configuration module, context switch module and event counter. The RDT module communicates with the configuration module, the morning and afternoon switch module and the event counter by calling the Microsoft reserved partition (MSR) interface. In this technology, the L2 Cache, L3 Cache and memory bandwidth of each CPU core are monitored and allocated through a series of central processing unit (CPU) instructions. This technology is conducive to noise detection, helps to reduce performance interference, and can ensure the performance of key workloads in complex environments.

[0075] In addition, a memory system resource partitioning and monitoring (MPAM) technology is also provided. Figure 2 As shown, Figure 2 A hardware block diagram of an application memory system resource partitioning and monitoring technology provided in an embodiment of the present application. Figure 2A processing element (PE), a memory system (memory system) and a dynamic random access memory (DRAM) are shown. The memory system includes a cache controller (cache controller) and a memory controller (memory controller). Different processes can be identified in a software execution environment (software execution environment), and process identifiers can be obtained. Then, the memory system can be configured for processes with different process identifiers. Specifically, the cache controller can configure the share in DRAM for different process identifiers, for example, a 50% share for a process with a process identifier of 0, a 10% share for a process with a process identifier of 1, and a 40% share for a process with a process identifier of 2. In the memory controller, the maximum bandwidth and the minimum bandwidth can be configured for different process IDs. For example, the maximum bandwidth of 4800 megabits per second (Mbps) and the minimum bandwidth of 0 are configured for the process with process ID 0, the maximum bandwidth of 1200Mbps and the minimum bandwidth of 1000Mbps are configured for the process with process ID 1, and the maximum bandwidth of 600Mbps and the minimum bandwidth of 600Mbps are configured for the process with process ID 2.

[0076] Among them, resource indicator technology and memory system resource partitioning and monitoring technology can both monitor and control the allocation quota of the second-level cache and the third-level cache, and can alleviate the problem of key business performance degradation or overall system performance degradation caused by shared resource competition during CPU memory access. However, resource indicator technology and memory system resource partitioning and monitoring technology still have some shortcomings, including: (1) It is impossible to control the users of the cache and the quota of the cache. (2) The software cannot control data caching and elimination. (3) These two technologies are applied to the second-level cache and the third-level cache, and cannot be applied to high-bandwidth memory.

[0077] However, when HBM is used as a cache, some problems still occur, including: (1) The software cannot control the caching and elimination of HBM. (2) Non-essential / unimportant memory data is cached in HBM, occupying the limited HBM capacity and wasting the bandwidth of HBM. (3) Important data of the process cannot be cached in HBM or is frequently replaced, which makes it impossible to exert the performance of HBM and improve application performance. (4) When data from HBM is written back to the main memory (such as double data rate SDRAM (DDR SDRAM), the size of the cache line of HBM and DDR is inconsistent, which will lead to write amplification and waste the bandwidth of DDR.

[0078] Therefore, the embodiments of the present application provide a sending method and an access method, in which each process is configured with a priority, and the first priority can be understood as an important priority. In addition, the required bandwidth of the process is greater than or equal to the preset value, which can be understood as the process having a large demand for bandwidth. Therefore, the data corresponding to the process with an important priority and a large demand for bandwidth is selectively stored in the high-bandwidth memory, which can reasonably and effectively utilize the large bandwidth characteristics of the high-bandwidth memory while taking into account the problem of the small memory capacity of the high-bandwidth memory. In addition, in the access method, it can be determined based on the indication information that the data of the access request is stored in the high-bandwidth memory or the memory, thereby, the processor core can execute the program to control the caching and elimination of the memory data.

[0079] For ease of understanding, the sending device applied by the sending method and the access device applied by the access method are first introduced below. The sending device can be a terminal device, such as a mobile phone terminal, a tablet computer, a laptop computer, an augmented reality device (AR), a virtual reality device (VR), and a vehicle-mounted terminal, etc., and can also be a server, etc. The sending device can be configured with an input / output (I / O) interface for data interaction with an external device. For example, a user can submit a task request to the input / output interface through an external device. The task request in the embodiment of the present application may include: reading data in the terminal device or writing data to the terminal device, etc. In addition, the access device can also be the same terminal device as the sending device, and reference can be made to the introduction based on the sending device.

[0080] In some embodiments, the sending device and access device provided in the embodiments of the present application may be a computer system. Figure 3 As shown, Figure 3A schematic diagram of the structure of a computer system provided in an embodiment of the present application. The computer system 30 includes a processor 31, an input / output interface 32 and a memory 33. Among them, the processor 31 may include multiple processor cores, and the processor core may be a central processing unit (CPU) core or a graphic processing unit (GPU) core, which is not specifically limited in this application. The processor core can be used to perform calculation operations, configuration operations, and modify configuration operations. The input / output interface 32 can exchange data with external devices. The memory 33 can be a synchronous dynamic random access memory or a double rate synchronous dynamic random access memory, which is not specifically limited in this embodiment of the present application. Among them, the memory 33 can store and retrieve information according to the instructions of the processor core.

[0081] The operating state of the processor core may include user state and kernel state. Figure 4 As shown, Figure 4 A system structure diagram of a sending method and an access method application provided by an embodiment of the present application. Wherein, the user state includes a business process module 401 and a management configuration service module 402, and the business process module 401 and the management configuration service module 402 are used to call the kernel state interface based on the process identification of the process and the bandwidth required to provide fine-grained and coarse-grained control methods. The kernel state includes a kernel page table attribute configuration module 403 and a process page table attribute configuration module 404, and the kernel page table attribute configuration module 403 and the process page table attribute configuration module 404 can provide a fine-grained control method based on a page table entry (page table entry, PTE). The kernel state also includes an address range configuration / modification module 405 and a process quota configuration / modification module 406, and the address range configuration / modification module 405 can provide a coarse-grained control method based on the address range, and the process quota configuration / modification module 406 can provide a coarse-grained control method based on the process quota. The memory management unit (MMU) of the hardware circuit includes a page table attribute recognition module 407, an address range recognition module 408, and a process identification quota distinction module 409. The page table attribute recognition module 407 can process a fine-grained control method, and the address range recognition module 408 and the process identification quota distinction module 409 can process a coarse-grained control method.

[0082] Applied to the above-mentioned terminal device, the following describes a sending method and an access method provided by an embodiment of the present application. Figure 5 As shown, Figure 5 The present invention provides a flow chart of a sending method and an access method. The sending method and the access method include the following process.

[0083] S501: The processor core obtains an access request of a process, wherein the access request includes first indication information and second indication information, the first indication information is used to indicate a priority of the process, and the second indication information is used to indicate a required bandwidth of the process.

[0084] Understandable, Figure 4 The business process module 401 shown in FIG. 4 executes step S501 .

[0085] Exemplarily, a process may include a business process and a service process. A user may configure a priority for a process by analyzing the process. For example, a higher priority may be configured for an important business process, and a lower priority may be configured for an unimportant service process. The priority of a process may include a first priority and a second priority, wherein the first priority is higher than the second priority. In an example, the first indication information may be a flag. For example, if flag=1, the first indication information indicates that the priority of the process is the first priority. If flag=0, the first indication information indicates that the priority of the process is the second priority. Alternatively, if flag=0, the first indication information indicates that the priority of the process is the first priority. If flag=1, the first indication information indicates that the priority of the process is the second priority.

[0086] Exemplarily, the user can identify memory access features through some analysis methods. The memory access features may include latency and bandwidth, and obtain the required bandwidth of the process. The required bandwidth of the process can also be understood as bandwidth sensitivity. Among them, the process with a large bandwidth demand is a process that is sensitive to bandwidth, and the process with a small bandwidth demand is a process that is not sensitive to bandwidth. The analysis method may include compilation static analysis, operation dynamic analysis, and manual code analysis. Thus, the processor core obtains the access request of the process issued by the application, and the access request includes the first indication information and the second indication information.

[0087] S502: If the first indication information is of the first priority, and the second indication information indicates that the required bandwidth of the process is greater than or equal to a preset value, generate third indication information, wherein the third indication information is used to indicate that the data corresponding to the access request is stored in the high bandwidth memory.

[0088] Understandable, Figure 4 The management configuration service module 402 shown in FIG. 4 executes step S502 .

[0089] Exemplarily, the preset value may be a bandwidth value, and the specific value of the preset value may be set by the user. If the bandwidth required by a process is greater than or equal to the preset value, it can be understood that the process has a large bandwidth demand, and if the bandwidth required by a process is less than the preset value, it can be understood that the process has a small bandwidth demand. In one example, processes may be divided into: important processes with large bandwidth demand, important processes with small bandwidth demand, unimportant processes with large bandwidth demand, and unimportant processes with small bandwidth demand. Among them, generating the third indication information for important processes with large bandwidth demand, that is, storing important processes with large bandwidth demand in the high-bandwidth memory, can take into account the characteristics of large bandwidth and small memory capacity of the high-bandwidth memory.

[0090] S503: The processor core sends an access request based on the third indication information.

[0091] Exemplarily, the access request may include: third indication information, virtual address, address space length and operation type. The processor core obtains a work queue element (WQE) based on the access request, and the WQE is stored in a work queue (WQ). A pair of WQs can be understood as a queue pair (QP), and the QP may include a send queue (SQ) and a receive queue (RQ), the send queue is used to store send access requests, and the receive queue is used to store receive access requests.

[0092] S504: The hardware circuit receives an access request from the process.

[0093] Exemplarily, the hardware circuit may include an address management unit, a high bandwidth memory and a memory. The memory may include SDRAM and DDR SDRAM. The high bandwidth memory is used as a cache mode. When the processor core reads data, it will first search in the high bandwidth memory, then search from the memory, and finally search from the external memory. Therefore, important data should be stored in the high bandwidth memory, for example, data that is frequently accessed should be stored in the high bandwidth memory.

[0094] Exemplarily, the hardware circuit receives an access request of a process sent by the processor core, and the access request may be an access request by the processor core to a high-bandwidth memory of the hardware circuit, or an access request by the processor core to a memory of the hardware circuit.

[0095] S505: If the access request includes third indication information, the hardware circuit stores the data corresponding to the access request in the high bandwidth memory.

[0096] Among them, the third indication information is used to indicate that the data corresponding to the access request is stored in the high-bandwidth memory. If the access request includes the third indication information, that is, the priority of the process is the first priority, and the required bandwidth of the process is greater than or equal to the preset value, that is, the process is important and has a large bandwidth demand. The address management unit of the hardware circuit will convert the virtual address in the access request into a physical address, read the data of the memory space corresponding to the physical address, and then store the data in the high-bandwidth memory. Therefore, when the high-bandwidth memory is used as a cache, the characteristics of the high-bandwidth memory with large bandwidth and small memory capacity can be taken into account at the same time.

[0097] Optional, such as Figure 6 As shown, Figure 6 A flowchart of another sending method and access method provided by an embodiment of the present application: After S501, S506 to S507 may be included, and after S504, S508 may be included.

[0098] S506: If the first indication information is of the second priority, or the second indication information indicates that the required bandwidth of the process is less than a preset value, the processor core generates fourth indication information, wherein the first priority is higher than the second priority, and the fourth indication information is used to indicate that the data corresponding to the access request is stored in the high bandwidth memory.

[0099] Understandable, Figure 4 The management configuration service module 402 shown in FIG. 4 executes step S506 .

[0100] Exemplarily, the priority of the process is the second priority, that is, the process is a non-important process, and the second indication information indicates that the required bandwidth of the process is less than the preset value, that is, the process is a process insensitive to bandwidth. Therefore, for non-important processes or processes insensitive to bandwidth, the fourth indication information is generated, that is, important processes with small bandwidth requirements, non-important processes with large bandwidth requirements, or non-important processes with small bandwidth requirements are stored in the memory instead of the high-bandwidth memory, which can reduce the storage pressure of the high-bandwidth memory.

[0101] S507: The processor core sends an access request based on the fourth indication information.

[0102] Exemplarily, the access request may include: fourth indication information, virtual address, address space length and operation type. The processor core obtains a work queue element (WQE) based on the access request, and the WQE is stored in a work queue (WQ). A pair of WQs can be understood as a queue pair (QP), and the QP may include a send queue (SQ) and a receive queue (RQ), the send queue is used to store send access requests, and the receive queue is used to store receive access requests.

[0103] S508: If the access request includes fourth indication information, the hardware circuit stores the data corresponding to the access request in the memory, wherein the fourth indication information is used to instruct to store the data corresponding to the access request in the memory.

[0104] Exemplarily, if the access request includes the fourth indication information, that is, the priority of the process is the second priority, or the required bandwidth of the process is less than the preset value, that is, the process is unimportant or has a small bandwidth requirement. The data of the access request of the process is stored in the memory instead of the high bandwidth memory, so that the storage pressure of the high bandwidth memory can be reduced.

[0105] Optionally, the third indication information is the first state of the page table entry control bit, and the fourth indication information is the second state of the page table entry control bit, and the first state is opposite to the second state. In one example, if the first state is 1, the second state is 0. In another example, if the first state is 0, the second state is 1.

[0106] It is understandable that Figure 4 The kernel page table attribute configuration module 403 and the process page table attribute configuration module 404 shown in generate the third indication information or the fourth indication information.

[0107] In one implementation, the present application embodiment can provide a fine-grained control method based on a page table entry. For example, the size of a page table entry is 4k, which can achieve fine control over the storage location of process data.

[0108] Exemplarily, page table entries can implement address translation (converting virtual addresses into physical addresses), permission management (such as read, write and execute permissions), and address space isolation (such as isolating the address spaces of various processes so that they do not affect each other), etc.

[0109] The operating state of the processor core includes user state and kernel state. When the processor core is in user state, the page table entry control bit is the process page table entry control bit. When the processor core is in kernel state, the page table entry control bit is the kernel page table entry control bit.

[0110] Exemplarily, the page table entry may include a process page table and a kernel page table, the process page table is "user space", and the kernel page table is "system space". In one example, two parts of space may be allocated to each process, the first part of the space is (0x00000000-0xBFFFFFFF), i.e., a 3G-byte virtual address, and the second part of the space is (0xC0000000-0xFFFFFFFF), i.e., a 1G-byte virtual address. Among them, the kernel page table of the second part of the space is the same for each process. From the perspective of the process, each process has 4G bytes of virtual space, of which the lower 3G bytes are user space, and the highest 1G byte is the system space shared by all processes and the kernel.

[0111] like Figure 7 As shown, Figure 7 A flow chart based on page table item control bits is provided for an embodiment of the present application. Wherein, when the processor core is in user mode, the processor core may include a memory application configuration interface and a user mode modification interface, the memory application configuration interface is used for memory allocation, and the process page table item control bits are configured after entering the kernel. The user mode modification interface is used to dynamically modify the process page table item control bits, and the process page table item control bits are configured after entering the kernel. Specifically, the user mode modification interface can modify the process page table item control bits through page table traversal. Wherein, when a process accesses a page in a virtual address space, if the page is not currently in memory, the hardware circuit will trigger a page fault exception (pagefault) to allocate a physical address space, and establish a mapping between the virtual address space and the physical address space.

[0112] When the processor core is in kernel state, the processor core includes a kernel state modification interface, and the kernel state modification interface is used to modify the kernel page table entry control bit. The processor core first initializes the kernel page table to configure the state of the kernel page table entry control bit, and then the processor core can modify the kernel page table entry control bit through the kernel state modification interface. Thus, the processor core sends an access request to the hardware circuit, and the access request includes the page table entry control bit.

[0113] After the hardware circuit receives the access request, the page table attribute recognition module identifies the page table item control bit and identifies whether the page table has a corresponding bit. Specifically, when the processor core is in the user state, the page table attribute recognition module identifies the state of the process page table item control bit. If the process page table item control bit is in the first state, the data corresponding to the access request is stored in the high-bandwidth memory. If the process page table item control bit is in the second state, the data corresponding to the access request is stored in the memory. When the processor core is in the kernel state, the page table attribute recognition module identifies the state of the kernel page table item control bit. If the kernel page table item control bit is in the first state, the data corresponding to the access request is stored in the high-bandwidth memory. If the kernel page table item control bit is in the second state, the data corresponding to the access request is stored in the memory. In addition, in order to improve the efficiency of the high-bandwidth memory, for unimportant data or expired data, the high-bandwidth memory will eliminate / write back the data to the memory.

[0114] Optionally, the third indication information is a first address range, and the first address range corresponds to an address of the high bandwidth memory. The fourth indication information is a second address range, and the second address range corresponds to an address of the memory.

[0115] It is understandable that Figure 4 The address range configuration / modification module 405 shown in generates the third indication information or the fourth indication information.

[0116] In one implementation, the present application embodiment may provide a coarse-grained control method based on an address range. For example, the address range is larger than the page table entry, and a rough control of the storage location of the process data may be implemented.

[0117] like Figure 8 As shown, Figure 8 A flowchart based on address range is provided for an embodiment of the present application. Wherein, when the processor core is in user mode, the processor core can configure one or more physical address ranges through the kernel configuration address range interface. That is, the first address range and the second address range of the embodiment of the present application, the processor core sends the first address range and the second address range to the address range recording module of the hardware circuit. When the processor core initiates access to the virtual address, an access request is sent to the hardware circuit.

[0118] After the hardware circuit receives the access request, the address management unit converts the virtual address into a physical address, and then determines whether the physical address corresponds to the first address range or the second address range through the address range identification module. If the physical address corresponds to the first address range, the data corresponding to the access request is stored in the high-bandwidth memory; if the physical address corresponds to the second address range, the data corresponding to the access request is stored in the memory. In addition, in order to improve the efficiency of the high-bandwidth memory, the high-bandwidth memory will eliminate / write back the unimportant data or expired data to the memory.

[0119] Applied to the above-mentioned terminal device, the following describes another sending method and access method provided by the embodiment of the present application. Fig. 9 As shown, Fig. 9 A flowchart of another sending method and access method provided in an embodiment of the present application. The sending method and access method include the following process.

[0120] S901: The processor core obtains an access request of a process, wherein the access request includes a process identifier.

[0121] Exemplarily, a user can identify different processes by analyzing the processes. For example, a process can correspond to an identification (ID). The process ID corresponds to the process one by one, and the process ID is unique. In one example, the process ID is 1, 2, ..., n, where n is a positive integer.

[0122] S902: The processor core generates third indication information based on the process identifier, wherein the third indication information is the proportion of the storage space of the high bandwidth memory allocated to the data corresponding to the process identifier.

[0123] It is understandable that Figure 4 The process quota configuration / modification module 406 shown in generates the third indication information.

[0124] In one example, the storage space of the high bandwidth memory can be regarded as 100%. Assuming that there are three processes with process IDs 1, 2, and 3, 50% of the storage space can be allocated to the process with process ID 1, 50% is the maximum cache limit of the process with process ID 1, 30% of the storage space can be allocated to the process with process ID 2, and 20% of the storage space can be allocated to the process with process ID 3.

[0125] S903: The processor core sends an access request based on the third indication information.

[0126] Exemplarily, the access request may include: third indication information, a virtual address, an address space length, and an operation type.

[0127] Optionally, the access request further includes first indication information and second indication information, the first indication information is used to indicate the priority of the process, and the second indication information is used to indicate the required bandwidth of the process. The process identifier corresponds to the proportion of processes whose first indication information is the first priority and whose required bandwidth indicated by the second indication information is greater than or equal to a preset value, and is greater than the proportion of processes whose process identifier corresponds to the proportion of processes whose first indication information is the second priority or whose required bandwidth indicated by the second indication information is less than a preset value.

[0128] Exemplarily, a process whose first indication information is of the first priority and whose required bandwidth of the process indicated by the second indication information is greater than or equal to a preset value is an important process with a large bandwidth demand, and a process whose first indication information is of the second priority or whose required bandwidth of the process indicated by the second indication information is less than a preset value is an unimportant process or a process with a small bandwidth demand. Thus, a larger proportion is allocated to important processes with a large bandwidth demand, and a smaller proportion is allocated to unimportant processes with a small bandwidth demand, so that the large bandwidth characteristics of the high-bandwidth memory can be reasonably and effectively utilized, while taking into account the small memory capacity characteristics of the high-bandwidth memory.

[0129] S904: The hardware circuit receives an access request from the process.

[0130] S905: If the data corresponding to the access request does not exceed the proportion corresponding to the third indication information, the hardware circuit stores the data corresponding to the access request in the high bandwidth memory.

[0131] In an example, assuming that the third indication information of the process with process ID 1 corresponds to a proportion of 50%, if the size of the data corresponding to the access request does not exceed 50% of the storage space of the high bandwidth memory, it indicates that all the data can be stored in the high bandwidth memory.

[0132] Optionally, the access method may further include: if the data corresponding to the process exceeds the proportion corresponding to the third indication information, storing the data corresponding to the access request in the memory.

[0133] In an example, assuming that the third indication information of the process with process ID 1 corresponds to a proportion of 50%, if the size of the data corresponding to the access request exceeds 50% of the storage space of the high bandwidth memory, the data corresponding to the access request is stored in the memory.

[0134] In one implementation, the present application embodiment may provide a coarse-grained control method based on process granularity. Fig.10 As shown, Fig.10A flowchart based on process granularity is provided for an embodiment of the present application. Wherein, when the processor core is in user mode, the processor core configures the process quota upper limit through an application programming interface (API), that is, the third indication information of the embodiment of the present application. The processor core sends the third indication information to the hardware circuit, and when the processor core initiates access to the virtual address, it sends an access request to the hardware circuit.

[0135] After receiving the access request, the hardware circuit determines whether the amount of data corresponding to the access request exceeds the proportion corresponding to the third indication information through the process identification quota differentiation module. If the amount of data corresponding to the access request does not exceed the proportion corresponding to the third indication information, the data corresponding to the access request is stored in the high bandwidth memory. If the amount of data corresponding to the access request exceeds the proportion corresponding to the third indication information, the data corresponding to the access request is stored in the memory.

[0136] In summary, if Fig.11 As shown, Fig.11 A method flow chart of a computer system provided for an embodiment of the present application. Among them, process identification and memory feature recognition are performed on critical / important processes and non-critical / non-important processes in user mode. Control methods of different granularities are provided in kernel mode, wherein the control method can be based on fine-grained control methods, that is, control based on page table entries, or can be based on coarse-grained control methods, that is, process control based on address ranges and process quotas. The fine-grained control method includes a kernel page table attribute configuration module and a process page table attribute configuration module, the kernel page table attribute configuration module can be used to configure the kernel page table item control bits, and the process page table attribute configuration module can be used to configure the process page table item control bits. The coarse-grained control method includes an address range configuration / modification module and a process quota configuration / modification module, the address range configuration / modification module can be used to configure / modify the address range, and the process quota configuration / modification module can be used to configure / modify the process quota. The processor core can initiate memory access and send a process access request in either user mode or kernel mode. The hardware circuit includes a page table attribute identification module, an address range identification module and a process identification quota differentiation module, wherein the page table attribute identification module can be used to identify the page table control item bit. If the page table item control bit indicates that the process data is stored in HBM, the process data is stored in HBM, otherwise the process data is stored in memory. The address range identification module can be used to identify the address range. If the address range indicates that the process data is stored in HBM, the process data is stored in HBM, otherwise the process data is stored in memory. The process identification quota differentiation module can be used to identify the process quota. If the proportion of HBM occupied by the process does not reach the upper limit, the process data is stored in HBM, otherwise the process data is stored in memory.

[0137] In addition, for the pre-fetch instructions of the process, the hardware circuit will determine whether the pre-fetch instructions are stored in the HBM. In addition, the data eliminated / written back in the HBM is stored in the memory.

[0138] Therefore, in the sending method and access method provided by the embodiment of the present application, each process in the sending method is configured with a priority, and the first priority can be understood as an important priority. In addition, the required bandwidth of the process is greater than or equal to the preset value, which can be understood as the process has a large demand for bandwidth. Therefore, the data corresponding to the process with important priority and large demand for bandwidth is selectively stored in the high-bandwidth memory, which can reasonably and effectively utilize the large bandwidth characteristics of the high-bandwidth memory, while taking into account the problem of small memory capacity of the high-bandwidth memory. In addition, in the access method, it can be determined based on the indication information that the data of the access request is stored in the high-bandwidth memory or memory, thereby, the program can be executed by the processor core to control the caching and elimination of memory data. In addition, the embodiment of the present application provides fine-grained and coarse-grained control methods, which can flexibly select the appropriate control granularity according to different scenarios, make full use of resources, and improve the performance of the processor core.

[0139] The present application also provides a chip, which includes a processor and a power supply circuit, wherein the power supply circuit is used to supply power to the processor, and the processor is used to implement a sending method or an access method.

[0140] The present application also provides a computer device, which includes a processor and a memory, wherein the memory is used to store instructions, and the processor obtains instructions to execute the sending method or the access method.

[0141] It is understandable that in order to implement the above functions, the electronic device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.

[0142] In this embodiment, the electronic device can be divided into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0143] In the case of dividing each functional module into corresponding functional modules, Fig.12 A possible schematic diagram of the composition of the sending device 1200 involved in the above embodiment is shown. Fig.12 As shown, the sending device 1200 may include: an acquiring unit 1201 , a generating unit 1202 and a sending unit 1203 .

[0144] The acquisition unit 1201 may be used to support the sending device 1200 to execute the above-mentioned step S501, etc., and / or other processes of the technology described in this document.

[0145] The generating unit 1202 may be used to support the sending device 1200 to execute the above-mentioned steps S502 and S506, etc., and / or other processes of the technology described herein.

[0146] The sending unit 1203 may be used to support the sending device 1200 to execute the above-mentioned steps S503 and S507, etc., and / or other processes of the technology described herein.

[0147] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0148] The sending device 1200 provided in this embodiment is used to execute the above sending method, and thus can achieve the same effect as the above implementation method.

[0149] In the case of using integrated units, the sending device 1200 may include a processing module, a storage module and a communication module. Among them, the processing module can be used to control and manage the actions of the sending device 1200, for example, it can be used to support the sending device 1200 to perform the steps performed by the above-mentioned acquisition unit 1201, generation unit 1202 and sending unit 1203. The storage module can be used to support the sending device 1200 to store program codes and data. The communication module can be used to support the communication between the sending device 1200 and other devices, such as communication with wireless access devices.

[0150] Among them, the processing module can be a processor or a controller. It can implement or execute various exemplary logic boxes, modules and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module can be a memory. The communication module can specifically be a device that interacts with other electronic devices, such as a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, etc.

[0151] In the case of dividing each functional module into corresponding functional modules, Fig.13A possible schematic diagram of the composition of the access device 1300 involved in the above embodiment is shown. Fig.13 As shown, the access device 1300 may include: a receiving unit 1301 and a sending unit 1302 .

[0152] The receiving unit 1301 may be used to support the access device 1300 to execute the above step S504 and / or other processes of the technology described herein.

[0153] The sending unit 1302 may be used to support the access device 1300 to execute the above-mentioned steps S505 and S508, etc., and / or other processes of the technology described herein.

[0154] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0155] The access device 1300 provided in this embodiment is used to execute the above sending method, and thus can achieve the same effect as the above implementation method.

[0156] In the case of using integrated units, the access device 1300 may include a processing module, a storage module and a communication module. The processing module may be used to control and manage the actions of the access device 1300, for example, it may be used to support the access device 1300 to perform the steps performed by the above-mentioned receiving unit 1301 and the sending unit 1302. The storage module may be used to support the access device 1300 to store program codes and data, etc. The communication module may be used to support the communication between the access device 1300 and other devices, such as communication with wireless access devices.

[0157] The embodiment of the present application also provides an electronic device, including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program codes, and the computer program codes include computer instructions. When the one or more processors execute the computer instructions, the electronic device executes the above-mentioned related method steps to implement the sending method or access method in the above-mentioned embodiment.

[0158] An embodiment of the present application also provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the sending method or access method in the above-mentioned embodiment.

[0159] The embodiments of the present application also provide a computer program product. When the computer program product is run on a computer, the computer executes the above-mentioned related steps to implement the sending method or access method executed by the electronic device in the above-mentioned embodiments.

[0160] In addition, an embodiment of the present application also provides a device, which may specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer execution instructions, and when the device is running, the processor may execute the computer execution instructions stored in the memory so that the chip executes the sending method or access method executed by the electronic device in the above-mentioned method embodiments.

[0161] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here.

[0162] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0163] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0164] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0165] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0166] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The software product is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage media include: USB flash drives, mobile hard drives, read-only memories (ROM),

[0167] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A sending method, characterized in that: The method comprises: Obtaining an access request of a process, the access request comprising first indication information and second indication information, the first indication information being used to indicate a priority of the process, and the second indication information being used to indicate a required bandwidth of the process; If the first indication information is of the first priority, and the second indication information indicates that the required bandwidth of the process is greater than or equal to a preset value, generating third indication information, wherein the third indication information is used to instruct to store the data corresponding to the access request in a high bandwidth memory; The access request is sent based on the third indication information.

2. The method according to claim 1, characterized in that The method further comprises: If the first indication information is of the second priority, or the second indication information indicates that the required bandwidth of the process is less than the preset value, fourth indication information is generated, the first priority is higher than the second priority, and the fourth indication information is used to instruct to store the data corresponding to the access request into the memory; The access request is sent based on the fourth indication information.

3. The method according to claim 2, characterized in that The third indication information is a first state of a page table entry control bit, and the fourth indication information is a second state of the page table entry control bit, and the first state is opposite to the second state.

4. The method according to claim 3, characterized in that The running state of the processor core includes a user state and a kernel state. When the processor core is in the user state, the page table entry control bit is a process page table entry control bit; When the processor core is in the kernel state, the page table entry control bit is a kernel page table entry control bit.

5. The method according to claim 2, characterized in that: The third indication information is a first address range, and the first address range corresponds to the address of the high bandwidth memory; the fourth indication information is a second address range, and the second address range corresponds to the address of the memory.

6. An access method, characterized in that: The method comprises: Receive access requests from processes; If the access request includes third indication information, the data corresponding to the access request is stored in the high bandwidth memory, and the third indication information is used to instruct to store the data corresponding to the access request in the high bandwidth memory.

7. The method according to claim 6, characterized in that The method further comprises: If the access request includes fourth indication information, the data corresponding to the access request is stored in the memory, and the fourth indication information is used to instruct to store the data corresponding to the access request in the memory.

8. The method according to claim 7, characterized in that The third indication information is a first state of a page table entry control bit, and the fourth indication information is a second state of the page table entry control bit, and the first state is opposite to the second state.

9. The method according to claim 8, characterized in that The running state of the processor core includes a user state and a kernel state. When the processor core is in the user state, the page table entry control bit is a process page table entry control bit; When the processor core is in the kernel state, the page table entry control bit is a kernel page table entry control bit.

10. The method according to claim 7, characterized in that The third indication information is a first address range, and the first address range corresponds to the address of the high bandwidth memory; the fourth indication information is a second address range, and the second address range corresponds to the address of the memory.

11. A sending method, characterized in that: The method comprises: Obtaining an access request of a process, wherein the access request includes a process identifier; generating third indication information based on the process identifier, wherein the third indication information is a proportion of the storage space of the high bandwidth memory allocated to the data corresponding to the process identifier; The access request is sent based on the third indication information.

12. The method according to claim 11, characterized in that The access request further includes first indication information and second indication information, wherein the first indication information is used to indicate the priority of the process, and the second indication information is used to indicate the required bandwidth of the process; The process identifier corresponds to the proportion of processes whose first indication information is the first priority and whose required bandwidth indicated by the second indication information is greater than or equal to a preset value, and is greater than the proportion of processes whose process identifier corresponds to the first indication information being the second priority or whose required bandwidth indicated by the second indication information is less than the preset value.

13. An access method, characterized in that: The method comprises: receiving an access request of a process, the access request comprising third indication information, the third indication information being a proportion of the storage space of the high bandwidth memory allocated to data corresponding to the process identifier; If the data corresponding to the access request does not exceed the proportion corresponding to the third indication information, the data corresponding to the access request is stored in the high bandwidth memory.

14. The method according to claim 13, characterized in that The method further comprises: If the data corresponding to the process exceeds the proportion corresponding to the indication information, the data corresponding to the access request is stored in the memory.

15. A sending device, characterized in that: The sending device comprises: an acquiring unit, configured to acquire an access request of a process, wherein the access request includes first indication information and second indication information, wherein the first indication information is used to indicate a priority of the process, and the second indication information is used to indicate a required bandwidth of the process; a generating unit, configured to generate third indication information if the first indication information is of a first priority and the second indication information indicates that the required bandwidth of the process is greater than or equal to a preset value, wherein the third indication information is used to instruct to store the data corresponding to the access request in a high bandwidth memory; A sending unit is used to send the access request based on the third indication information.

16. The device according to claim 15, characterized in that The generating unit is further configured to: If the first indication information is of the second priority, or the second indication information indicates that the required bandwidth of the process is less than the preset value, fourth indication information is generated, the first priority is higher than the second priority, and the fourth indication information is used to instruct to store the data corresponding to the access request into the memory; The sending unit is also used for: The access request is sent based on the fourth indication information.

17. The device according to claim 16, characterized in that The third indication information is a first state of a page table entry control bit, and the fourth indication information is a second state of the page table entry control bit, and the first state is opposite to the second state.

18. The device according to claim 17, characterized in that The running state of the processor core includes a user state and a kernel state. When the processor core is in the user state, the page table entry control bit is a process page table entry control bit; When the processor core is in the kernel state, the page table entry control bit is a kernel page table entry control bit.

19. The device according to claim 17, characterized in that The third indication information is a first address range, and the first address range corresponds to the address of the high bandwidth memory; the fourth indication information is a second address range, and the second address range corresponds to the address of the memory.

20. An access device, characterized in that: The access device comprises: A receiving unit, used for receiving an access request of a process; The sending unit is configured to store the data corresponding to the access request in the high bandwidth memory if the access request includes third indication information, wherein the third indication information is used to instruct to store the data corresponding to the access request in the high bandwidth memory.

21. The device according to claim 20, characterized in that The sending unit is also used for: If the access request includes fourth indication information, the data corresponding to the access request is stored in the memory, and the fourth indication information is used to instruct to store the data corresponding to the access request in the memory.

22. A sending device, characterized in that: The sending device comprises: An acquisition unit, configured to acquire an access request of a process, wherein the access request includes a process identifier; a generating unit, configured to generate third indication information based on the process identifier, wherein the third indication information is a proportion of the storage space of the high bandwidth memory allocated to the data corresponding to the process identifier; A sending unit is used to send the access request based on the third indication information.

23. The device according to claim 22, characterized in that The access request further includes first indication information and second indication information, wherein the first indication information is used to indicate the priority of the process, and the second indication information is used to indicate the required bandwidth of the process; The process identifier corresponds to the proportion of processes whose first indication information is the first priority and whose required bandwidth indicated by the second indication information is greater than or equal to a preset value, and is greater than the proportion of processes whose process identifier corresponds to the first indication information being the second priority or whose required bandwidth indicated by the second indication information is less than the preset value.

24. An access device, characterized in that: The access device comprises: A receiving unit, configured to receive an access request of a process, wherein the access request includes third indication information, and the third indication information is a proportion of the storage space of the high bandwidth memory allocated to the data corresponding to the process identifier; The sending unit is configured to store the data corresponding to the access request in a high bandwidth memory if the data corresponding to the access request does not exceed the proportion corresponding to the third indication information.

25. The device according to claim 24, characterized in that The sending unit is further used for: if the data corresponding to the process exceeds the proportion corresponding to the indication information, storing the data corresponding to the access request in the memory.

26. A chip, characterized in that: The chip comprises: a processor and a power supply circuit; wherein the power supply circuit is used to supply power to the processor; and the processor is used to implement the method described in any one of claims 1 to 14.

27. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, it is used to execute the method described in any one of claims 1 to 14.

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