Method and device for determining low-delay circuit structure, electronic equipment and storage medium

Abstract

The invention relates to a method and device for determining a low-delay circuit structure, electronic equipment and a storage medium. The method comprises the following steps: acquiring a logic gate in a first logic library; a plurality of groups of quadtrees are constructed based on the logic gates, a single node of each quadtree is a logic gate, nodes in the same layer are the same logic gates, nodes of the quadtrees in the same group except the first layer are the same logic gates, the quadtrees among the groups are different, the first layer of each quadtree is composed of an inverter and a buffer, and the second layer of each quadtree is composed of an inverter and a buffer. Nodes of a single quadtree can form a circuit structure of a plurality of Boolean functions; using the quadtree to determine the time delay of the circuit structure to be tested, and constructing a time delay table which represents the corresponding relation between the circuit structure to be tested and the time delay; and determining a low-delay circuit structure based on the delay table. According to the method disclosed by the invention, the possibility of determining a circuit structure with lower time delay is improved, and the method is more universal.

Description

Technical Field

[0001] The present disclosure relates to the field of information security technology, and in particular to a method and device for determining a low-latency circuit structure, an electronic device, and a storage medium. Background Art

[0002] One of the indicators for hardware performance evaluation is latency. Researching cryptographic primitives with minimum latency in hardware is a hot topic in the field of cryptographic research. Knezevic, Nikov, and Rombouts conducted a comprehensive analysis of the latency properties of various lightweight block ciphers in 2012. Subsequently, several low-latency algorithms such as PRINCE, Midori, QARMA, Mantis, and SPEEDY were proposed, and the low-latency pseudo-random function (PRF) Orthros also received attention. For the above cryptographic algorithms, the S-box is the only nonlinear component, and the performance of these algorithms depends on the choice of the S-box.

[0003] The evaluation criteria for low latency are mainly based on gate depth complexity. Calculation based on gate depth complexity is currently the most commonly used low latency evaluation method, but the delay evaluation methods in related technologies are not practical enough, so the determined delay is not accurate. Therefore, there are circuit structures with lower delay that have not been discovered. Summary of the invention

[0004] In view of this, the present disclosure proposes a solution for determining a low-latency circuit structure.

[0005] According to one aspect of the present disclosure, a method for determining a low-latency circuit structure is provided, comprising: obtaining logic gates in a first logic library; constructing multiple groups of quadtrees based on the logic gates, wherein a single node of the quadtree is a logic gate, nodes at the same layer are the same logic gates, quadtrees in the same group are the same except for the first layer, and quadtrees between groups are different, the first layer of each quadtree is composed of an inverter and a buffer, and a single node of the quadtree can form a circuit structure of multiple Boolean functions; using the quadtree, determining the delay of the circuit structure to be tested, and constructing a delay table, wherein the delay table represents the correspondence between the circuit structure to be tested and the delay; and determining the low-latency circuit structure based on the delay table.

[0006] In one possible implementation, the use of the quadtree to determine the delay of the circuit structure to be tested includes: traversing from the leaf nodes to the root nodes of the multiple groups of quadtrees to obtain multiple first circuit structures; measuring and recording the time from the input of data to the output of the first circuit structure, and using the time as the delay corresponding to the first circuit structure.

[0007] In a possible implementation, the number of quadtrees in the same group is the number of quadtree input lines in the group; except for the first layer, the nodes in the same layer of the quadtrees in the same group are the same, and the probability that the nodes in the first layer are inverters or buffers is the same.

[0008] In a possible implementation manner, the quadtree also includes: the quadtree has no more than four layers.

[0009] In one possible implementation, determining a low-latency circuit structure based on the delay table includes: obtaining an expected delay; based on the expected delay, determining a circuit structure in the delay table whose delay is less than or equal to the expected delay as the low-latency circuit structure, and the low-latency circuit structure is used to construct an S-box.

[0010] In one possible implementation, each of the low-latency circuits corresponds to a first truth table, and the method further includes: determining a second truth table of an existing S-box based on a lookup table and a Boolean function of an existing S-box, wherein the circuit structure of the existing S-box is unknown; determining a target first truth table that is the same as the second truth table, and taking the low-latency circuit structure corresponding to the target first truth table as the selected circuit structure; and constructing an S-box having the same delay effect as the existing S-box based on the selected circuit structure.

[0011] In a possible implementation, the first logic library is an ASIC library, and the logic gates include: an inverter (INV), a buffer (BUF), a two-input NAND gate (NAND2), a two-input NOR gate (NOR2), a two-input AND gate (AND2), a two-input OR gate (OR2), a two-input XOR gate (XOR2), a two-input XNOR gate (XNOR2), a three-input NAND gate (NAND3), a three-input NAND gate (OAI21), a three-input NAND gate (AOI21), a three-input NOT gate (NOR3), a three-input AND gate (AND3), a three-input OR gate (OR3), a two-input selector (MUX2), a four-input NAND gate (OAI22), a four-input NAND gate (AOI22), a four-input NAND gate (NAND4), a four-input NOR gate (NOR4), a four-input AND gate (AND4), and a four-input OR gate (OR4).

[0012] According to another aspect of the present disclosure, there is provided a device for determining a low-latency circuit structure, comprising:

[0013] A logic gate acquisition unit, used to acquire logic gates in a first logic library;

[0014] A quadtree construction unit, used to construct multiple groups of quadtrees based on the logic gates, wherein a single node of the quadtree is a logic gate, nodes in the same layer are the same logic gates, quadtrees in the same group are the same except for the first layer, and quadtrees in different groups are different, the first layer of each quadtree is composed of an inverter and a buffer, and a single node of the quadtree can form a circuit structure of multiple Boolean functions;

[0015] A delay table construction unit, used to use the quadtree to determine the delay of the circuit structure to be tested and to construct a delay table, wherein the delay table represents the corresponding relationship between the circuit structure to be tested and the delay;

[0016] A low-latency circuit structure determining unit is used to determine the low-latency circuit structure based on the delay table.

[0017] In a possible implementation, the delay table construction unit includes:

[0018] A first circuit structure determining unit, configured to traverse from leaf nodes to root nodes of the plurality of groups of quadtrees to obtain a plurality of first circuit structures;

[0019] The delay determination unit is used to measure and record the time from when data is input into the first circuit structure to when data is output, and use the time as the delay corresponding to the first circuit structure.

[0020] In a possible implementation, the number of quadtrees in the same group is the number of quadtree input lines in the group; except for the first layer, the nodes in the same layer of the quadtrees in the same group are the same, and the probability that the nodes in the first layer are inverters or buffers is the same.

[0021] In a possible implementation manner, the quadtree also includes: the quadtree has no more than four layers.

[0022] In a possible implementation manner, the low-latency circuit structure determining unit is further used to:

[0023] Get expected delay;

[0024] Based on the expected delay, a circuit structure with a delay less than or equal to the expected delay is determined in the delay table as the low-delay circuit structure, and the low-delay circuit structure is used to construct an S-box.

[0025] In a possible implementation manner, each of the low-latency circuits corresponds to a first truth table, and the device further includes:

[0026] A second truth table determination unit, configured to determine a second truth table of an existing S-box based on a lookup table and a Boolean function of the existing S-box, wherein the circuit structure of the existing S-box is unknown;

[0027] A selected circuit structure determination unit is used to determine a target first truth table that is the same as the second truth table, and use the low-latency circuit structure corresponding to the target first truth table as the selected circuit structure;

[0028] The S-box construction unit is used to construct an S-box with the same delay effect as the existing S-box based on the selected circuit structure.

[0029] In a possible implementation, the first logic library is an ASIC library, and the logic gates include: an inverter (INV), a buffer (BUF), a two-input NAND gate (NAND2), a two-input NOR gate (NOR2), a two-input AND gate (AND2), a two-input OR gate (OR2), a two-input XOR gate (XOR2), a two-input XNOR gate (XNOR2), a three-input NAND gate (NAND3), a three-input NAND gate (OAI21), a three-input NAND gate (AOI21), a three-input NOT gate (NOR3), a three-input AND gate (AND3), a three-input OR gate (OR3), a two-input selector (MUX2), a four-input NAND gate (OAI22), a four-input NAND gate (AOI22), a four-input NAND gate (NAND4), a four-input NOR gate (NOR4), a four-input AND gate (AND4), and a four-input OR gate (OR4).

[0030] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0031] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0032] According to another aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0033] In the disclosed embodiment, each group of quadtrees can simulate the actual operating environment of a single circuit structure, so that the measured delay is more realistic and more accurate. By constructing the quadtree in the disclosed embodiment, as many combinations of logic gates in the first logic library as possible can be determined to expand the selection range of low-latency circuits, thereby increasing the possibility of determining a circuit structure with lower latency. In addition, the method in the disclosed embodiment can be applied to various logic libraries, thereby improving universality.

[0034] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0036] Figure 1 A flowchart of a method for determining a low-latency circuit structure provided in an embodiment of the present disclosure.

[0037] Figure 2 A schematic diagram of a local structure of a quadtree provided in an embodiment of the present disclosure.

[0038] Figure 3 A schematic diagram of another local structure of a quadtree provided in an embodiment of the present disclosure.

[0039] Figure 4 A schematic diagram of a quadtree of a Boolean function provided in an embodiment of the present disclosure.

[0040] Figure 5 A schematic diagram of a flow chart of an apparatus for determining a low-latency circuit structure provided in an embodiment of the present disclosure.

[0041] Figure 6 A schematic diagram of the structure of an electronic device for determining a low-latency circuit structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0043] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0044] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present disclosure.

[0045] One indicator for evaluating hardware performance is delay. Researching cryptographic primitives that achieve minimum delay in hardware is a hot topic in the field of cryptographic research. The delay of existing low-latency circuit structures is not the lowest for three reasons: First, the types and numbers of logic gates used in the circuit structures in the related art are limited and cannot cover the logic gates in the logic library. In other words, the low-latency circuits determined in the related art do not fully utilize the various logic gates in the logic library. Second, there are many factors that affect circuit delay in practice, which are strongly related to the application environment of the circuit structure, including power, voltage, temperature, fan-in, fan-out and other factors. It is not enough to determine the delay based solely on the gate depth. Third, the delays of logic gates in different libraries are not the same. It is inaccurate to simply determine the delay of the circuit structure by accumulating the delays corresponding to each logic gate in the circuit structure to be tested.

[0046] In view of this, the present disclosure proposes a method for determining a low-latency circuit structure, which can be applied to determine a low-latency circuit for constructing an S-box from various logic libraries. Among them, in cryptography, the S-box (Substitution-box) is a basic component for a symmetric cryptographic algorithm to perform nonlinear operations. This method can reduce the difficulty of determining a low-latency circuit structure; thereby, as many logic gates as possible in the logic library can be used to determine the low-latency circuit structure, providing an effective way to determine a circuit structure with a lower delay.

[0047] Figure 1 A flow chart of a method for determining a low-latency circuit structure provided by an embodiment of the present disclosure. Figure 1 As shown, the method includes:

[0048] S11, obtaining logic gates in a first logic library.

[0049] The first logic library may be an existing common logic library, such as an ASIC logic library, an FPGA logic library, etc. The first logic library may be an uncommon logic library developed according to actual needs. Classified according to functional characteristics, logic gates may include basic logic gates, compound logic gates, and special compound logic gates. Classified according to the number of input variables, logic gates may include single-input logic gates, two-input logic gates, and multi-input logic gates. The disclosed embodiments do not limit the types of logic gates.

[0050] In the disclosed embodiment, all or most of the logic gates in the first logic library can be obtained to increase the number of determined circuit structure categories as much as possible, thereby expanding the selection range to select a low-latency circuit structure with lower latency.

[0051] S12, construct multiple groups of quadtrees based on the logic gates, a single node of the quadtree is a logic gate, nodes in the same layer are the same logic gates, quadtrees in the same group are the same except for the first layer, and the quadtrees between groups are different, the first layer of each quadtree is composed of an inverter and a buffer, and a single node of the quadtree can form a circuit structure of multiple Boolean functions.

[0052] Since the number of input variables of a logic gate usually does not exceed four, the number of branches of the tree is determined to be 4. In this way, the quadtree can satisfy the operation of each logic gate. In order to traverse the logic gates in the first logic library to complete the circuit structure of the logic gate with itself or with other logic gates; in the embodiment of the present disclosure, the nodes in the same layer of the quadtree except the first layer are set to the same logic gate. The layers in the quadtree can be the same logic gate or different logic gates. One or more branches of the quadtree in the present disclosure may not contain nodes. Thus, the quadtree may include: one branch containing a node, two branches containing nodes, three branches containing nodes, or four branches containing nodes. In this way, the quadtree of the present disclosure is compatible with linear structures (containing only one branch containing a node), binary trees, ternary trees, etc.

[0053] In the disclosed embodiment, in order to simulate the fan-in and fan-out of the circuit structure in the actual application environment, multiple quadtrees that are completely identical except for the first layer can be set, and these quadtrees that are completely identical except for the first layer can be grouped into a quadtree group. All quadtree groups can cover all possible circuit structures and can cover various combinations of logic gates in the first logic library.

[0054] The first layer of the quadtree can be composed of inverters and buffers. Signal data enters the first layer after being input into the quadtree. The first layer can invert the signal data or perform buffer processing (enhancement, delay, etc.). In the disclosed embodiment, the probability of each node in the first layer selecting an inverter or a buffer as a node is equal. Therefore, the inverters and buffers in the first layer of the quadtree are randomly and evenly distributed.

[0055] A single quadtree may include multiple circuit structures, and a branch of a single quadtree may include multiple circuit structures at different levels.

[0056] Figure 2 A schematic diagram of a local structure of a quadtree provided in an embodiment of the present disclosure. Figure 2 As shown in FIG. 1 , the quadtree has three layers. Data X0, X1, and X3 are input to the quadtree through the first layer. In this example, the first layer is a buffer (BUF) and an inverter (INV). Figure 2 The buffer is shown in triangles. Figure 2Not shown. The second layer is a two-input NAND gate (NAND2), and the third layer is a three-input NAND gate (NAND3). Parts of the quadtree can form multiple circuit structures. For ease of understanding, the following method is used to represent each circuit structure. Among them, BUF is omitted. The circuit structure includes: NAND3(NAND2(x0,x1),x2,NAND2(x3,INV(x0))), NAND2(x3,INV(x0), NAND2(x0,x1). Among them, the elements in () are the input variables of the circuit structure.

[0057] Figure 3 FIG. 1 is another schematic diagram of a local structure of a quadtree provided in an embodiment of the present disclosure. Figure 3 As shown, the quadtree has two layers. Data X0, X1, and X2 are input to the quadtree through the first layer. In this example, the first layer is a buffer (BUF) and an inverter (INV), and the second layer is a three-input NAND gate (NAND3), where BUF is omitted. The circuit structure that can be formed by the local part of the quadtree includes: NAND3 (x0, x1, INV (x2))

[0058] The above only uses two examples to illustrate the circuit structures included in the quadtree. The quadtree in the embodiments of the present disclosure is not limited to the above two structures.

[0059] In this way, each group of quadtrees in the embodiment of the present disclosure can simulate various combinations of logic gates in the first logic library, and can also simulate the operating status of each circuit structure in the actual application environment, so as to facilitate the subsequent measurement of the delay of different circuit structures to be tested.

[0060] S13, using the quadtree to determine the delay of the circuit structure to be tested, and construct a delay table, wherein the delay table represents the corresponding relationship between the circuit structure to be tested and the delay.

[0061] In the disclosed embodiment, the delay of the circuit structure to be tested can be measured, and a delay table is constructed using each circuit structure to be tested and the corresponding delay, the delay table including the correspondence between the circuit structure to be tested and the delay.

[0062] In the disclosed embodiment, the circuit structure to be tested can be disassembled to obtain at least one sub-circuit structure to be tested; a first quadtree representing the sub-circuit structure to be tested is selected; the number of input lines of the sub-circuit structure to be tested is used as the number of first quadtrees in the same group; each group of first quadtrees is used to measure the delay of the at least one sub-circuit structure to be tested; and the maximum value of each of the delays is used as the delay of the circuit to be tested.

[0063] Figure 4A schematic diagram of a Boolean function quadtree provided by an embodiment of the present disclosure. The first layer of the quadtree includes an inverter and a buffer, the second layer is a two-input NAND gate (NAND2), and the third layer is a three-input NAND gate (NAND3).

[0064] Therefore, the circuit structure to be tested is NAND3(NAND2(x0,x1),x2,NAND2(x3,INV(x0))). The input variables x0, x1, x2, and x3 correspond to five input lines respectively. The input lines can be a combination of logic gates that the input variables pass through in the quadtree (excluding inverters and buffers). Among them, starting from the left, the input lines corresponding to the first x0, x1, x3, and the second x0 are the same, and x2 corresponds to a single input line. In order to estimate the delay of the circuit structure to be tested, the circuit structure to be tested can be disassembled according to the input lines to obtain two sub-circuit structures to be tested, namely: the first sub-circuit structure to be tested NAND3(NAND2(x,x), NAND2(x,x)) and the second sub-circuit structure to be tested NAND3(x,x,x,x). A quadtree representing the first sub-circuit structure to be tested and a quadtree representing the second sub-circuit structure to be tested can be selected. The number of input lines of the first sub-circuit structure to be tested is 4, so the 4 quadtrees representing the first sub-circuit structure to be tested can constitute a first group of quadtrees; the number of input lines of the second sub-circuit structure to be tested is 4, so the 4 quadtrees representing the second sub-circuit structure to be tested can constitute a second group of quadtrees.

[0065] The time length of the input variable from input to output of the first group of quadtrees is measured, and the maximum value of these time lengths is taken as the delay of the first subcircuit structure to be tested; the time length of the input variable from input to output of the second group of quadtrees is measured, and the maximum value of these time lengths is taken as the delay of the second subcircuit structure to be tested. Finally, the maximum value of the delay of the first subcircuit structure to be tested and the delay of the second subcircuit structure to be tested is taken as the delay of the circuit structure to be tested.

[0066] S14, determining a low-delay circuit structure based on the delay table.

[0067] The delay table can record the logic gates included in each circuit structure, the delay of each circuit structure, the number of input lines, and the level of the circuit structure. When determining a low-latency circuit structure, based on given circuit structure, delay, level, number of input lines and other conditions, a circuit structure that meets the conditions and has the lowest delay can be determined as a low-latency circuit, or multiple circuit structures that meet the conditions and have a delay lower than a given delay can be determined as a low-latency circuit.

[0068] In the disclosed embodiment, each group of quadtrees can simulate the actual operating environment of a single circuit structure, so that the measured delay is more realistic and more accurate. By constructing the quadtree in the disclosed embodiment, the delays of various combinations of logic gates in the first logic library can be determined as much as possible to expand the selection range of low-latency circuits, thereby increasing the possibility of determining a circuit structure with lower delay. In addition, the method in the disclosed embodiment can be applied to various logic libraries, improving universality.

[0069] In one possible implementation, the use of the quadtree to determine the delay of the circuit structure to be tested includes: traversing from the leaf nodes to the root nodes of the multiple groups of quadtrees to obtain multiple first circuit structures; measuring and recording the time from the input of data to the output of the first circuit structure, and using the time as the delay corresponding to the first circuit structure.

[0070] For the quadtrees in the same group, multiple circuit structures are determined by traversing from the leaf node to the root node. For the convenience of the following description, the circuit structure determined by the traversal is named the first circuit structure, that is, the sub-circuit structure to be tested mentioned above. As mentioned above, the quadtrees in the same group are the same. A single first circuit structure can appear in each quadtree in the same group. The same first circuit structures in the quadtrees in the same group can be run together to measure the time from the input of the first circuit structure to the output of the first circuit structure. The earliest time point when the data enters the first circuit structure is taken as the input time point, and the latest time point when the data is output from the first circuit structure is taken as the output time point; the difference between the output time point and the input time point is taken as the delay of the first circuit structure.

[0071] In the embodiments of the present disclosure, multiple factors such as power, voltage, temperature, fan-in and fan-out of the first circuit structure in an actual operating environment are fully considered, so that the measured delay of the first circuit structure is more practical and more accurate.

[0072] In a possible implementation, the number of quadtrees in the same group is the number of quadtree input lines in the group; except for the first layer, the nodes in the same layer of the quadtrees in the same group are the same, and the probability that the nodes in the first layer are inverters or buffers is the same.

[0073] In an n-bit S-box, suppose the k-th Boolean function has m k (m k ≥n) input lines, where n represents the number of input variables. For n input variables, the average fan-out number of each input variable is and To approximate the delay of the real Boolean function in the S-box, we repeat m k Boolean function structure, and this Boolean function structure has mk input lines.

[0074] In order to simulate the number of fan-in and fan-out in the actual environment, a single circuit structure can be repeated m times. k That is, for m k The circuit structure of each input line should be repeated m k times, the simulation requirements for the number of fan-in and fan-out can be met. Therefore, the number of quadtrees in the same group can be equal to the number of quadtree input lines. In this way, the circuit structure with the largest number of input lines in the same group of quadtrees can obtain an operating state similar to that in the actual environment. Then other circuit structures (circuit structures in which the number of input lines in the same group of quadtrees is less than the number of input lines of the quadtree) can naturally obtain an operating state similar to that in the actual environment. The number of fan-in and fan-out in the actual environment is simulated more accurately, so that the fan-out number of the input variable is close to the fan-out number of the real Boolean function.

[0075] In a possible implementation manner, the quadtree also includes: the quadtree has no more than four layers.

[0076] The number of layers of the quadtree determines the maximum number of layers of the circuit structure constructed by the quadtree.

[0077] By studying the existing low-latency circuits, it can be found that the critical path of the existing low-latency circuits does not exceed four layers. Therefore, in the disclosed embodiment, the quadtree can be directly limited to a four-layer quadtree. In this way, the probability that the circuit structure determined by the quadtree is a non-low-latency circuit is reduced. Moreover, the quadtree structure can be simplified, and the number of determined circuit structures can be reduced when possible low-latency circuit structures are included. Moreover, since the level of the quadtree is limited, the number of repetitions of the same group of quadtrees can be limited. When the actual operating environment of the circuit structure can be accurately simulated, redundancy can be reduced, the complexity of determining the low-latency circuit can be reduced, and the feasibility of the method can be improved.

[0078] In one possible implementation, determining a low-latency circuit structure based on the delay table includes: obtaining an expected delay; based on the expected delay, determining a circuit structure in the delay table whose delay is less than or equal to the expected delay as the low-latency circuit structure, and the low-latency circuit structure is used to construct an S-box.

[0079] The expected delay can be a delay given by the user according to the needs of the application scenario. The expected delay can be the delay of an existing S-box with the same number of bits as the S-box to be built. For example: if a 4-bit S-box needs to be built, the expected delay can be the delay of an existing 4-bit S-box.

[0080] In one example, according to the expected delay, a circuit structure with a delay less than or equal to the expected delay can be determined in the delay table as a low-delay circuit structure. As mentioned above, the number of input lines of each circuit structure can be recorded in the delay table. Therefore, in another example, according to the expected delay, a second circuit structure with a number of input lines that meets the number of bits required for the S-box to be constructed can be determined in the delay table; and then a circuit structure with a delay less than or equal to the expected delay can be determined from the second circuit structure as a low-delay circuit structure.

[0081] In the embodiment of the present disclosure, one or more low-latency circuits can be determined based on the delay table according to the needs of the scene to be applied to the same scene. Not only can the circuit structure with lower latency be accurately determined, but also the adaptability of these low-latency circuit structures to the scene is improved.

[0082] In one possible implementation, each of the low-latency circuits corresponds to a first truth table, and the method further includes: determining a second truth table of an existing S-box based on a lookup table and a Boolean function of an existing S-box, wherein the circuit structure of the existing S-box is unknown; determining a target first truth table that is the same as the second truth table, and taking the low-latency circuit structure corresponding to the target first truth table as the selected circuit structure; and constructing an S-box having the same delay effect as the existing S-box based on the selected circuit structure.

[0083] In a scenario where an existing S-box is known and it is desired to construct a delay that is the same as that of the existing S-box, the lookup table and Boolean function of the existing S-box can be obtained, and the second truth table of the existing S-box can be determined based on the lookup table and the Boolean function. For different circuit structures, if the truth tables of the two circuit structures are the same, it means that the two circuit structures can achieve the same delay. A single low-latency circuit structure can correspond to the first truth table, and the existing S-box can correspond to the second truth table. Then, the first truth table that is the same as the second truth table can be determined as the target first truth table, and the S-box can be constructed using the low-latency circuit structure corresponding to the target first truth table. In this way, the delay of the constructed S-box is the same as the delay of the existing S-box. Using the method of the embodiment of the present disclosure, S-boxes with more circuit structures can be constructed on the premise of achieving a given S-box delay, providing more possibilities for selection.

[0084] After testing, the S-box constructed using the method in the embodiment of the present disclosure has a lower delay than the existing S-boxes with the same number of bits (including 4-bit, 5-bit, and 6-bit S-boxes), and the delay can be reduced by 5%-10%.

[0085] In a possible implementation, the first logic library is an ASIC library, and the logic gates include: an inverter (INV), a buffer (BUF), a two-input NAND gate (NAND2), a two-input NOR gate (NOR2), a two-input AND gate (AND2), a two-input OR gate (OR2), a two-input XOR gate (XOR2), a two-input XNOR gate (XNOR2), a three-input NAND gate (NAND3), a three-input NAND gate (OAI21), a three-input NAND gate (AOI21), a three-input NOT gate (NOR3), a three-input AND gate (AND3), a three-input OR gate (OR3), a two-input selector (MUX2), a four-input NAND gate (OAI22), a four-input NAND gate (AOI22), a four-input NAND gate (NAND4), a four-input NOR gate (NOR4), a four-input AND gate (AND4), and a four-input OR gate (OR4).

[0086] The first logic library may include all or part of the logic gates and combinations of logic gates in the ASIC library. In the related art, the difficulty of determining a low-latency circuit is related to the number of logic gates. Therefore, low-latency circuits have always been determined only within the range of a few logic gates. Since the method disclosed in the present invention reduces the complexity of the method for determining a low-latency circuit, a quadtree can be constructed using most or all of the logic gates in the first logic library. In this way, the constructed quadtree can measure the delay of circuit structures within a larger range, thereby expanding the candidate range of low-latency circuit structures and increasing the possibility of selecting a circuit with a lower delay.

[0087] Figure 5 A schematic diagram of a flow chart of a device for determining a low-latency circuit structure provided by an embodiment of the present disclosure. Figure 5 As shown, the device 20 comprises:

[0088] A logic gate acquisition unit 21, used to acquire logic gates in a first logic library;

[0089] A quadtree construction unit 22, configured to construct multiple groups of quadtrees based on the logic gates, wherein a single node of the quadtree is a logic gate, nodes at the same layer are the same logic gates, quadtrees in the same group are the same except for the first layer, and quadtrees between groups are different, the first layer of each quadtree is composed of an inverter and a buffer, and a node of a single quadtree can form a circuit structure of multiple Boolean functions;

[0090] A delay table construction unit 23, configured to use the quadtree to determine the delay of the circuit structure to be tested and to construct a delay table, wherein the delay table represents the correspondence between the circuit structure to be tested and the delay;

[0091] The low-latency circuit structure determining unit 24 is used to determine the low-latency circuit structure based on the delay table.

[0092] In a possible implementation, the delay table construction unit 23 includes:

[0093] A first circuit structure determining unit, configured to traverse from leaf nodes to root nodes of the plurality of groups of quadtrees to obtain a plurality of first circuit structures;

[0094] The delay determination unit is used to measure and record the time from when data is input into the first circuit structure to when data is output, and use the time as the delay corresponding to the first circuit structure.

[0095] In a possible implementation, the number of quadtrees in the same group is the number of quadtree input lines in the group; except for the first layer, the nodes in the same layer of the quadtrees in the same group are the same, and the probability that the nodes in the first layer are inverters or buffers is the same.

[0096] In a possible implementation manner, the quadtree also includes: the quadtree has no more than four layers.

[0097] In a possible implementation, the low-latency circuit structure determining unit 24 is further configured to:

[0098] Get expected delay;

[0099] Based on the expected delay, a circuit structure with a delay less than or equal to the expected delay is determined in the delay table as the low-delay circuit structure, and the low-delay circuit structure is used to construct an S-box.

[0100] In a possible implementation manner, each of the low-latency circuits corresponds to a first truth table, and the device 20 further includes:

[0101] A second truth table determination unit, configured to determine a second truth table of an existing S-box based on a lookup table and a Boolean function of the existing S-box, wherein the circuit structure of the existing S-box is unknown;

[0102] A selected circuit structure determination unit is used to determine a target first truth table that is the same as the second truth table, and use the low-latency circuit structure corresponding to the target first truth table as the selected circuit structure;

[0103] The S-box construction unit is used to construct an S-box with the same delay effect as the existing S-box based on the selected circuit structure.

[0104] In a possible implementation, the first logic library is an ASIC library, and the logic gates include: an inverter (INV), a buffer (BUF), a two-input NAND gate (NAND2), a two-input NOR gate (NOR2), a two-input AND gate (AND2), a two-input OR gate (OR2), a two-input XOR gate (XOR2), a two-input XNOR gate (XNOR2), a three-input NAND gate (NAND3), a three-input NAND gate (OAI21), a three-input NAND gate (AOI21), a three-input NOT gate (NOR3), a three-input AND gate (AND3), a three-input OR gate (OR3), a two-input selector (MUX2), a four-input NAND gate (OAI22), a four-input NAND gate (AOI22), a four-input NAND gate (NAND4), a four-input NOR gate (NOR4), a four-input AND gate (AND4), and a four-input OR gate (OR4).

[0105] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0106] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0107] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0108] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0109] Figure 6 A schematic diagram of a structure of an electronic device for determining a low-latency circuit structure provided by an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Figure 6, the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0110] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2003. TM , Mac OS X TM , Unix TM ,Linux TM , FreeBSD TM or similar.

[0111] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0112] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0113] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0114] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0115] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0116] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0117] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0118] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0119] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0120] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for determining a low-latency circuit structure, characterized in that: include: Obtaining logic gates in a first logic library; Constructing multiple groups of quadtrees based on the logic gates, wherein a single node of the quadtree is a logic gate, nodes in the same layer are the same logic gates, quadtrees in the same group are the same except for the first layer, and quadtrees in different groups are different, the first layer of each quadtree is composed of an inverter and a buffer, and a single node of the quadtree can form a circuit structure of multiple Boolean functions; Using the quadtree, determining the delay of the circuit structure to be tested, and constructing a delay table, wherein the delay table represents the corresponding relationship between the circuit structure to be tested and the delay; Based on the delay table, a low-delay circuit structure is determined.

2. The method according to claim 1, characterized in that The method of using the quadtree to determine the delay of the circuit structure to be tested includes: Traversing from the leaf nodes of the multiple groups of quadtrees to the root nodes to obtain multiple first circuit structures; The time from when data is input into the first circuit structure to when data is output is measured and recorded, and the time is used as the delay corresponding to the first circuit structure.

3. The method according to claim 1, characterized in that Also includes: The number of quadtrees in the same group is the number of quadtree input lines in the group; except for the first layer, the nodes in the same layer of the quadtrees in the same group are the same, and the probability that the nodes in the first layer are inverters or buffers is the same.

4. The method according to claim 1, characterized in that: Also includes: The quadtree has no more than four layers.

5. The method according to claim 1, characterized in that The step of determining a low-delay circuit structure based on the delay table includes: Get expected delay; Based on the expected delay, a circuit structure with a delay less than or equal to the expected delay is determined in the delay table as the low-delay circuit structure, and the low-delay circuit structure is used to construct an S-box.

6. The method according to claim 1, characterized in that Each of the low-latency circuits corresponds to a first truth table, and the method further includes: Determine a second truth table of an existing S-box based on a lookup table and a Boolean function of the existing S-box, wherein the circuit structure of the existing S-box is unknown; Determine a target first truth table that is the same as the second truth table, and use the low-latency circuit structure corresponding to the target first truth table as the selected circuit structure; Based on the selected circuit structure, an S-box having the same delay effect as the existing S-box is constructed.

7. The method according to claim 1, characterized in that The first logic library is an ASIC library, and the logic gates include: inverter, buffer, two-input NAND gate, two-input NOR gate, two-input AND gate, two-input OR gate, two-input XOR gate, two-input XNOR gate, three-input NAND gate, three-input OR NAND gate, three-input AND NOR gate, three-input NOT gate, three-input AND gate, three-input OR gate, two-input selector, four-input OR NAND gate, four-input AND NOR gate, four-input NAND gate, four-input NOR gate, four-input NOR gate, four-input AND gate, and four-input OR gate.

8. A device for determining a low-latency circuit structure, characterized in that: include: A logic gate acquisition unit, used to acquire logic gates in a first logic library; A quadtree construction unit, used to construct multiple groups of quadtrees based on the logic gates, wherein a single node of the quadtree is a logic gate, nodes in the same layer are the same logic gates, quadtrees in the same group are the same except for the first layer, and quadtrees in different groups are different, the first layer of each quadtree is composed of an inverter and a buffer, and a single node of the quadtree can form a circuit structure of multiple Boolean functions; A delay table construction unit, used to use the quadtree to determine the delay of the circuit structure to be tested and to construct a delay table, wherein the delay table represents the corresponding relationship between the circuit structure to be tested and the delay; A low-latency circuit structure determining unit is used to determine the low-latency circuit structure based on the delay table.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to implement the method described in any one of claims 1 to 7 when executing the instructions stored in the memory.

10. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

Images