Method and apparatus for determining low latency circuit structure, electronic device and storage medium

Abstract

This disclosure relates to a method, apparatus, electronic device, and storage medium for determining low-latency circuit structures. The method includes: obtaining logic gates from a first logic library; constructing multiple sets of quadtrees based on the logic gates, where each node of the quadtree is a logic gate, nodes at the same level are the same logic gates, and nodes in the same group are the same logic gates except for the first level; the quadtrees in different groups are different, the first level of each quadtree consists of inverters and buffers, and the nodes of a single quadtree can form multiple Boolean function circuit structures; using the quadtrees, determining the delay of the circuit structure under test, constructing a delay table, the delay table representing the correspondence between the circuit structure under test and the delay; and determining the low-latency circuit structure based on the delay table. The method of this disclosure improves the possibility of determining circuit structures with even lower delays and is more universal.

Description

Technical Field

[0001] This disclosure relates to the field of information security technology, and in particular to a method and apparatus for determining low-latency circuit structures, electronic devices, and storage media. Background Technology

[0002] One metric for hardware performance evaluation is latency. Researching hardware implementations of cryptographic primitives with minimal latency is a hot topic in cryptography research. Knezevic, Nikov, and Rombouts conducted a comprehensive analysis of the latency properties of various lightweight block ciphers in 2012. Subsequently, several low-latency algorithms, including PRINCE, Midori, QARMA, Mantis, and SPEEDY, were proposed, and the low-latency pseudo-random function (PRF) Orthros also gained attention. For these cryptographic algorithms, the S-box is the only non-linear component, and the performance of these algorithms depends on the choice of the S-box.

[0003] The evaluation criteria for low latency mainly focus on gate depth complexity. Gate depth complexity-based calculation is currently the most commonly used method for low latency evaluation. However, the latency evaluation methods in related technologies are not realistic enough, so the determined latency is not accurate. Therefore, there are circuit structures with even lower latency that have not yet been discovered. Summary of the Invention

[0004] In view of this, this disclosure proposes a scheme for determining the structure of a low-delay circuit.

[0005] According to one aspect of this disclosure, a method for determining a low-latency circuit structure is provided, comprising: obtaining logic gates in a first logic library; constructing multiple sets of quadtrees based on the logic gates, wherein a single node of the quadtree is a logic gate, nodes at the same level are the same logic gates, quadtrees in the same group are identical except for the first level, and quadtrees between groups are different, the first level of each quadtree consists of inverters and buffers, and nodes of a single quadtree can form a circuit structure of multiple Boolean functions; using the quadtrees, determining the delay of the circuit structure under test, constructing a delay table, the delay table representing the correspondence between the circuit structure under test and the delay; and determining a low-latency circuit structure based on the delay table.

[0006] In one possible implementation, determining the delay of the circuit structure under test using the quadtree includes: traversing from the leaf nodes to the root node of the multiple sets of quadtrees to obtain multiple first circuit structures; measuring and recording the time from the input of the first circuit structure to its output, and using this time as the delay corresponding to the first circuit structure.

[0007] One possible implementation also includes: the number of quadtrees in the same group is equal to the number of quadtree input lines in the group; the nodes in the same quadtree in the same group are the same except for the first level, and the nodes in the first level have the same probability of being inverters or buffers.

[0008] In one possible implementation, the quadtree is further defined as having no more than four levels.

[0009] In one possible implementation, determining the low-delay circuit structure based on the delay table includes: obtaining the desired delay; and, based on the desired delay, determining a circuit structure in the delay table whose delay is less than or equal to the desired delay as the low-delay circuit structure, wherein the low-delay circuit structure is used to construct an S-box.

[0010] In one possible implementation, each of the low-delay circuits corresponds to a first truth table, and the method further includes: determining a second truth table of an existing S-box based on a lookup table and a Boolean function, wherein the circuit structure of the existing S-box is unknown; determining a target first truth table that is the same as the second truth table, and using the low-delay circuit structure corresponding to the target first truth table as the selected circuit structure; and constructing an S-box with the same delay effect as the existing S-box based on the selected circuit structure.

[0011] In one possible implementation, the first logic library is an ASIC library, and the logic gates include: inverters (INV), buffers (BUF), two-input NAND gates (NAND2), two-input NOR gates (NOR2), two-input AND gates (AND2), two-input OR gates (OR2), two-input XOR gates (XOR2), two-input XNOR gates (XNOR2), three-input NAND gates (NAND3), three-input NAND gates (OAI21), three-input AND-OR-NOT gates (AOI21), three-input NOT gates (NOR3), three-input AND gates (AND3), three-input OR gates (OR3), two-input selectors (MUX2), four-input NAND gates (OAI22), four-input AND-OR-NOT gates (AOI22), four-input NAND gates (NAND4), four-input NOR gates (NOR4), four-input AND gates (AND4), and four-input OR gates (OR4).

[0012] According to another aspect of this disclosure, an apparatus for determining a low-delay circuit structure is provided, comprising:

[0013] The logic gate acquisition unit is used to acquire logic gates from the first logic library;

[0014] The quadtree construction unit is used to construct multiple quadtrees based on the logic gates. Each node of the quadtree is a logic gate, and nodes at the same level are the same logic gates. The quadtrees in the same group are the same except for the first level. The quadtrees between different groups are different. The first level of each quadtree is composed of inverters and buffers. The nodes of a single quadtree can form the circuit structure of multiple Boolean functions.

[0015] The delay table construction unit is used to determine the delay of the circuit structure under test using the quadtree and construct a delay table, wherein the delay table represents the correspondence between the circuit structure under test and the delay.

[0016] A low-delay circuit structure determination unit is used to determine the low-delay circuit structure based on the delay table.

[0017] In one possible implementation, the delay table construction unit includes:

[0018] The first circuit structure determination unit is used to traverse from the leaf nodes to the root node of the multiple sets of quadtrees to obtain multiple first circuit structures.

[0019] The delay determination unit is used to measure and record the time from the input of data to the output of the first circuit structure, and use the time as the delay corresponding to the first circuit structure.

[0020] One possible implementation also includes: the number of quadtrees in the same group is equal to the number of quadtree input lines in the group; the nodes in the same quadtree in the same group are the same except for the first level, and the nodes in the first level have the same probability of being inverters or buffers.

[0021] In one possible implementation, the quadtree is further defined as having no more than four levels.

[0022] In one possible implementation, the low-delay circuit structure determination unit is further configured to:

[0023] Obtain the desired delay;

[0024] Based on the expected delay, circuit structures with delays less than or equal to the expected delay are determined in the delay table as the low-delay circuit structures, which are used to construct the S-box.

[0025] In one possible implementation, each of the low-delay circuits corresponds to a first truth table, and the device further includes:

[0026] The second truth table determination unit is used to determine the second truth table of the existing S-box based on the lookup table and Boolean function of the existing S-box, wherein the circuit structure of the existing S-box is unknown.

[0027] A circuit structure determination unit is selected to determine a target first truth table that is the same as the second truth table, and to select the low-delay circuit structure corresponding to the target first truth table as the selected circuit structure.

[0028] The S-box construction unit is used to construct an S-box with the same delay effect as the existing S-box based on the selected circuit structure.

[0029] In one possible implementation, the first logic library is an ASIC library, and the logic gates include: inverters (INV), buffers (BUF), two-input NAND gates (NAND2), two-input NOR gates (NOR2), two-input AND gates (AND2), two-input OR gates (OR2), two-input XOR gates (XOR2), two-input XNOR gates (XNOR2), three-input NAND gates (NAND3), three-input NAND gates (OAI21), three-input AND-OR-NOT gates (AOI21), three-input NOT gates (NOR3), three-input AND gates (AND3), three-input OR gates (OR3), two-input selectors (MUX2), four-input NAND gates (OAI22), four-input AND-OR-NOT gates (AOI22), four-input NAND gates (NAND4), four-input NOR gates (NOR4), four-input AND gates (AND4), and four-input OR gates (OR4).

[0030] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing instructions stored in the memory.

[0031] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided that stores computer program instructions thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.

[0032] According to another aspect of this disclosure, a computer program product is provided, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0033] In this embodiment, each quadtree can simulate the actual operating environment of a single circuit structure, making the measured delay more realistic and accurate. By constructing the quadtrees in this embodiment, as many combinations of logic gates in the first logic library as possible can be determined, thereby expanding the selection range of low-latency circuits and increasing the likelihood of determining circuit structures with even lower delays. Furthermore, the method in this embodiment is applicable to various logic libraries, improving its universality.

[0034] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0035] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0036] Figure 1 This is a flowchart illustrating a method for determining a low-delay circuit structure, provided as an embodiment of the present disclosure.

[0037] Figure 2 This is a schematic diagram of a partial quadtree structure provided in an embodiment of this disclosure.

[0038] Figure 3 This is a schematic diagram of a partial quadtree structure provided in an embodiment of this disclosure.

[0039] Figure 4 This is a schematic diagram of a quadtree for a Boolean function provided in an embodiment of this disclosure.

[0040] Figure 5 This is a flowchart illustrating an apparatus for determining a low-delay circuit structure, provided as an embodiment of the present disclosure.

[0041] Figure 6 This is a schematic diagram of an electronic device for determining a low-delay circuit structure, provided as an embodiment of the present disclosure. Detailed Implementation

[0042] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0043] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0044] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0045] One metric for evaluating hardware performance is latency. Researching cryptographic primitives that achieve minimum latency in hardware implementation is a hot topic in cryptography research. Existing low-latency circuit structures do not achieve the lowest possible latency for three reasons: First, the types and number of logic gates used in the circuit structures of related technologies are limited and cannot cover all the logic gates in the logic library. In other words, the low-latency circuits identified in related technologies do not fully utilize the various logic gates in the logic library. Second, many factors affect circuit latency in practice, and it is strongly related to the application environment of the circuit structure, including power, voltage, temperature, and fan-in / fan-out factors. Determining latency solely based on gate depth is insufficient. Third, the latency of logic gates in different libraries is not the same. Simply summing the latency of each logic gate in the circuit structure under test to determine the overall latency is inaccurate.

[0046] In view of this, this disclosure proposes a method for determining low-latency circuit structures, applicable to identifying low-latency circuits for constructing S-boxes from various logic libraries. In cryptography, the S-box (Substitution-box) is a fundamental component for performing nonlinear operations in symmetric cryptographic algorithms. This method reduces the difficulty of determining low-latency circuit structures; thus, it allows the application of as many logic gates as possible from logic libraries to determine low-latency circuit structures, providing an effective approach to determining even lower latency circuit structures.

[0047] Figure 1 This is a flowchart illustrating a method for determining a low-delay circuit structure according to an embodiment of the present disclosure. Figure 1 As shown, the method includes:

[0048] S11, retrieve the logic gates from the first logic library.

[0049] The first logic library can be an existing, commonly used logic library, such as an ASIC logic library or an FPGA logic library. The first logic library can also be a less common logic library developed according to specific needs. Classified by functional characteristics, logic gates can include basic logic gates, composite logic gates, and special composite logic gates. Classified by the number of input variables, logic gates can include single-input logic gates, two-input logic gates, and multi-input logic gates. This disclosure does not limit the type of logic gates used in its embodiments.

[0050] In this embodiment of the disclosure, all or most of the logic gates in the first logic library can be obtained to maximize the number of identified circuit structure categories. This expands the selection range to identify low-latency circuit structures with lower latency.

[0051] S12, construct multiple sets of quadtrees based on the logic gates. Each node of the quadtree is a logic gate, and nodes at the same level are the same logic gates. The quadtrees in the same group are the same except for the first level. The quadtrees between different groups are different. The first level of each quadtree is composed of inverters and buffers. The nodes of a single quadtree can form the circuit structure of multiple Boolean functions.

[0052] Since the number of input variables for a logic gate typically does not exceed four, the number of branches in the tree is determined to be four. This quadtree ensures that each logic gate can operate. To traverse the logic gates in the first logic library and construct a circuit structure with that gate and itself or other logic gates, in this embodiment, nodes in the same level of the quadtree (excluding the first level) are set to the same logic gate. Levels in the quadtree can contain the same logic gate or different logic gates. One or more branches of the quadtree in this disclosure may not contain nodes. Therefore, the quadtree can include: one branch containing a node, two branches containing nodes, three branches containing nodes, or four branches containing nodes. This makes the quadtree of this disclosure compatible with linear structures (containing only one branch containing a node), binary trees, ternary trees, etc.

[0053] In this embodiment of the disclosure, in order to simulate the fan-in and fan-out of the circuit structure in a real-world application environment, multiple identical quadtrees (excluding the first layer) can be set up, and these identical quadtrees (excluding the first layer) can be grouped into a quadtree group. All quadtree groups can cover all possible circuit structures and various combinations of logic gates in the first logic library.

[0054] The first level of a quadtree can consist of inverters and buffers. Signal data is input into the quadtree and then enters the first level. The first level can perform inversion or buffering (amplification, delay, etc.) on the signal data. In this embodiment, each node in the first level has an equal probability of choosing either an inverter or a buffer. Therefore, the inverters and buffers in the first level of the quadtree are randomly and uniformly distributed.

[0055] A single quadtree can contain multiple circuit structures, and the branches of a single quadtree can include multiple circuit structures at different levels.

[0056] Figure 2 This is a schematic diagram of a partial quadtree structure provided in an embodiment of this disclosure. Figure 2 As shown, the quadtree has three levels. Data X0, X1, and X3 are input into the quadtree through the first level. In this example, the first level consists of a buffer (BUF) and an inverter (INV). The inverter... Figure 2 The buffer is represented by a triangle. Figure 2The second layer is a two-input NAND gate (NAND2), and the third layer is a three-input NAND gate (NAND3). This quadtree can be used to construct multiple circuit structures. For ease of understanding, each circuit structure is represented as follows. BUF is omitted. The circuit structures include: NAND3(NAND2(x0,x1),x2,NAND2(x3,INV(x0))), NAND2(x3,INV(x0), NAND2(x0,x1). The elements in parentheses are the input variables of the circuit structure.

[0057] Figure 3 This is a schematic diagram of a partial quadtree structure provided in an embodiment of this disclosure. (See diagram below.) Figure 3 As shown, the quadtree has two levels. Data X0, X1, and X2 are input to the quadtree through the first level. In this example, the first level consists of a buffer (BUF) and an inverter (INV), and the second level consists of a three-input NAND gate (NAND3), where BUF is omitted. A partial circuit structure that can be formed from this quadtree includes: NAND3(x0, x1, INV(x2))

[0058] The above are just two examples illustrating the circuit structures contained in a quadtree. The quadtrees in this disclosure are not limited to these two structures.

[0059] In this way, each set of quadtrees in the embodiments of this disclosure can simulate various combinations of logic gates in the first logic library, and can also simulate the operating state of each circuit structure in the actual application environment, so as to facilitate subsequent measurement of the delay of different circuit structures under test.

[0060] S13, using the quadtree, determine the delay of the circuit structure under test, and construct a delay table, which represents the correspondence between the circuit structure under test and the delay.

[0061] In this embodiment of the disclosure, the delay of the circuit structure under test can be measured, and a delay table can be constructed using each circuit structure under test and its corresponding delay. The delay table contains the correspondence between the circuit structure under test and the delay.

[0062] In this embodiment of the disclosure, the circuit under test can be disassembled to obtain at least one sub-circuit structure under test; a first quadtree representing the sub-circuit structure under test is selected; the number of input lines of the sub-circuit structure under test is taken as the number of first quadtrees in the same group; the delay of each of the at least one sub-circuit structure under test is measured using each group of first quadtrees; and the maximum value of each delay is taken as the delay of the circuit under test.

[0063] Figure 4This is a schematic diagram of a quadtree for a Boolean function provided in an embodiment of this disclosure. The first layer of the quadtree includes an inverter and a buffer, the second layer is a two-input NAND gate (NAND2), and the third layer is a three-input NAND gate (NAND3).

[0064] Therefore, the circuit under test (DUT) structure is NAND3(NAND2(x0,x1),x2,NAND2(x3,INV(x0))). Input variables x0, x1, x2, and x3 each correspond to five input lines, which can be combinations of logic gates (excluding inverters and buffers) through which the input variables pass in the quadtree. Specifically, the first x0, x1, x3, and the second x0 from the left correspond to the same input line, while x2 corresponds to a separate input line. To estimate the delay of the DUT structure, it can be decomposed according to the input lines, resulting in two sub-circuit structures: the first sub-circuit structure NAND3(NAND2(x,x),NAND2(x,x)) and the second sub-circuit structure NAND3(x,x,x,x). Quadtrees representing the first and second sub-circuit structures can be selected. The first sub-circuit under test has 4 input lines, so the 4 quadtrees representing the first sub-circuit under test can be used to form the first set of quadtrees; the second sub-circuit under test has 4 input lines, so the 4 quadtrees representing the second sub-circuit under test can be used to form the second set of quadtrees.

[0065] The time taken for each quadtree in the first group of input variables to travel from input to output is measured, and the maximum value of these times is taken as the delay of the first sub-circuit structure under test. The time taken for the second group of quadtrees to travel from input to output is also measured, and the maximum value of these times is taken as the delay of the second sub-circuit structure under test. Finally, the maximum value of the delays of the first and second sub-circuit structures under test is taken as the delay of the circuit structure under test.

[0066] S14, Based on the delay table, determine the low-delay circuit structure.

[0067] The delay table can record the logic gates contained in each circuit structure, the delay of each circuit structure, the number of input lines, and the hierarchy of the circuit structure. When determining the low-delay circuit structure, based on the given circuit structure, delay, hierarchy, number of input lines, and other conditions, the circuit structure with the lowest delay that meets the conditions can be identified as the low-delay circuit, or multiple circuit structures that meet the conditions and have a delay lower than the given delay can be identified as the low-delay circuit.

[0068] In this embodiment, each quadtree can simulate the actual operating environment of a single circuit structure, making the measured delay more realistic and accurate. By constructing the quadtrees in this embodiment, the delays of various combinations of logic gates in the first logic library can be determined as much as possible, thereby expanding the selection range of low-latency circuits and increasing the likelihood of determining circuit structures with even lower delays. Furthermore, the method in this embodiment is applicable to various logic libraries, improving its universality.

[0069] In one possible implementation, determining the delay of the circuit structure under test using the quadtree includes: traversing from the leaf nodes to the root node of the multiple sets of quadtrees to obtain multiple first circuit structures; measuring and recording the time from the input of the first circuit structure to its output, and using this time as the delay corresponding to the first circuit structure.

[0070] For the quadtrees in the same group, multiple circuit structures are determined by traversing from the leaf nodes to the root node. For ease of description below, the circuit structure determined by traversal is named the first circuit structure, i.e., the sub-circuit structure to be tested mentioned earlier. As mentioned before, the quadtrees in the same group are identical. A single first circuit structure can appear in each quadtree in the same group. Identical first circuit structures in the quadtrees of the same group can be run together, and the time from input to output of the first circuit structure is measured. The earliest time point when the data enters the first circuit structure is taken as the input time point, and the latest time point when the data is output to the first circuit structure is taken as the output time point; the difference between the output time point and the input time point is taken as the delay of the first circuit structure.

[0071] In this embodiment, the power, voltage, temperature, fan-in and fan-out of the first circuit structure in the actual operating environment are fully considered, so that the measured delay of the first circuit structure is more realistic and more accurate.

[0072] One possible implementation also includes: the number of quadtrees in the same group is equal to the number of quadtree input lines in the group; the nodes in the same quadtree in the same group are the same except for the first level, and the nodes in the first level have the same probability of being inverters or buffers.

[0073] In an n-bit S-box, suppose the k-th Boolean function has m... k (m k There are ≥n) input lines, where n represents the number of input variables. For n input variables, the average fan-out of each input variable is... and To approximate the delay of the real Boolean function in the S-box, we repeat m... k A Boolean function structure with m substructures.k One input line.

[0074] To simulate the number of fan-in and fan-out cycles in a real-world environment, a single circuit structure can be repeated m times. k That is to say, for m... k The circuit structure for each input line should be repeated m k This satisfies the simulation requirements for fan-in and fan-out counts. Therefore, the number of quadtrees in the same group can be equal to the number of quadtree input lines. Thus, the circuit structure with the largest number of input lines in the same group of quadtrees can achieve an operating state similar to that in a real-world environment. Similarly, other circuit structures (those with fewer input lines in the same group of quadtrees than the total number of quadtree input lines) can also achieve a similar operating state to a real-world environment. This more accurately simulates the fan-in and fan-out counts in a real-world environment, making the fan-out count of the input variables close to the fan-out count of a real Boolean function.

[0075] In one possible implementation, the quadtree is further defined as having no more than four levels.

[0076] The number of levels in a quadtree determines the maximum number of levels in the circuit structure that can be constructed from it.

[0077] By studying existing low-latency circuits, it can be found that the critical path of existing low-latency circuits does not exceed four levels. Therefore, in this embodiment, the quadtree can be directly limited to a four-level quadtree. This reduces the probability that the circuit structure determined by the quadtree is not a low-latency circuit. Moreover, the quadtree structure can be simplified, reducing the number of determined circuit structures while including possible low-latency circuit structures. Furthermore, by limiting the level of the quadtree, the number of repetitions of the same group of quadtrees can be limited. This reduces redundancy while accurately simulating the actual operating environment of the circuit structure, lowering the complexity of determining the low-latency circuit and improving the feasibility of the method.

[0078] In one possible implementation, determining the low-delay circuit structure based on the delay table includes: obtaining the desired delay; and, based on the desired delay, determining a circuit structure in the delay table whose delay is less than or equal to the desired delay as the low-delay circuit structure, wherein the low-delay circuit structure is used to construct an S-box.

[0079] The expected latency can be a latency specified by the user based on the application scenario. The expected latency can be the latency of an existing S-box with the same number of bits as the S-box to be constructed. For example, if a 4-bit S-box needs to be constructed, the expected latency can be the latency of an existing 4-bit S-box.

[0080] In one example, based on the expected delay, circuit structures with delays less than or equal to the expected delay can be identified from the delay table as low-delay circuit structures. As mentioned earlier, the delay table can record the number of input lines for each circuit structure. Therefore, in another example, based on the expected delay, a second circuit structure whose number of input lines meets the bit requirement of the S-box to be constructed can be identified from the delay table; then, circuit structures with delays less than or equal to the expected delay can be identified from the second circuit structure as low-delay circuit structures.

[0081] In this embodiment of the disclosure, one or more low-latency circuits can be determined based on a delay table according to the needs of the scenario, for application in the same scenario. This not only accurately determines the circuit structure with lower latency, but also improves the adaptability of these low-latency circuit structures to the scenario.

[0082] In one possible implementation, each of the low-delay circuits corresponds to a first truth table, and the method further includes: determining a second truth table of an existing S-box based on a lookup table and a Boolean function, wherein the circuit structure of the existing S-box is unknown; determining a target first truth table that is the same as the second truth table, and using the low-delay circuit structure corresponding to the target first truth table as the selected circuit structure; and constructing an S-box with the same delay effect as the existing S-box based on the selected circuit structure.

[0083] In a scenario where an existing S-box is known and the desired delay is to construct one with the same delay as the existing S-box, the lookup table and Boolean function of the existing S-box can be obtained, and the second truth table of the existing S-box can be determined based on the lookup table and Boolean function. If two different circuit structures have the same truth table, it means that these two circuit structures can achieve the same delay. A single low-delay circuit structure can correspond to a first truth table, and an existing S-box can correspond to a second truth table. Therefore, a first truth table identical to the second truth table can be determined as the target first truth table, and the S-box is constructed using the low-delay circuit structure corresponding to the target first truth table. In this way, the delay of the constructed S-box is the same as the delay of the existing S-box. Using the method of this disclosure embodiment, more circuit structures of S-boxes can be constructed while achieving a given S-box delay, providing more selection possibilities.

[0084] Experiments have shown that S-boxes constructed using the methods described in this disclosure have lower latency compared to existing S-boxes of the same bit length (including 4-bit, 5-bit, and 6-bit S-boxes), with latency reductions of 5%-10%.

[0085] In one possible implementation, the first logic library is an ASIC library, and the logic gates include: inverters (INV), buffers (BUF), two-input NAND gates (NAND2), two-input NOR gates (NOR2), two-input AND gates (AND2), two-input OR gates (OR2), two-input XOR gates (XOR2), two-input XNOR gates (XNOR2), three-input NAND gates (NAND3), three-input NAND gates (OAI21), three-input AND-OR-NOT gates (AOI21), three-input NOT gates (NOR3), three-input AND gates (AND3), three-input OR gates (OR3), two-input selectors (MUX2), four-input NAND gates (OAI22), four-input AND-OR-NOT gates (AOI22), four-input NAND gates (NAND4), four-input NOR gates (NOR4), four-input AND gates (AND4), and four-input OR gates (OR4).

[0086] The first logic library can contain all or part of the logic gates or combinations of logic gates from the ASIC library. In related technologies, the difficulty in identifying low-latency circuits is related to the number of logic gates. Therefore, traditionally, low-latency circuits have only been identified within a range consisting of a few logic gates. By using the method of this disclosure, the complexity of identifying low-latency circuits is reduced. A quadtree can be constructed using most or all of the logic gates in the first logic library. This constructed quadtree can measure the delay of a wider range of circuit structures, thus expanding the candidate range of low-latency circuit structures and increasing the likelihood of selecting circuits with even lower delays.

[0087] Figure 5 This is a flowchart illustrating an apparatus for determining a low-delay circuit structure, provided as an embodiment of this disclosure. Figure 5 As shown, the device 20 includes:

[0088] The logic gate acquisition unit 21 is used to acquire logic gates in the first logic library;

[0089] Quadtree construction unit 22 is used to construct multiple groups of quadtrees based on the logic gates. Each node of the quadtree is a logic gate, and nodes at the same level are the same logic gates. The quadtrees in the same group are the same except for the first level. The quadtrees between different groups are different. The first level of each quadtree is composed of an inverter and a buffer. The nodes of a single quadtree can form the circuit structure of multiple Boolean functions.

[0090] The delay table construction unit 23 is used to determine the delay of the circuit structure under test using the quadtree and construct a delay table, wherein the delay table represents the correspondence between the circuit structure under test and the delay.

[0091] The low-delay circuit structure determination unit 24 is used to determine the low-delay circuit structure based on the delay table.

[0092] In one possible implementation, the delay table construction unit 23 includes:

[0093] The first circuit structure determination unit is used to traverse from the leaf nodes to the root node of the multiple sets of quadtrees to obtain multiple first circuit structures.

[0094] The delay determination unit is used to measure and record the time from the input of data to the output of the first circuit structure, and use the time as the delay corresponding to the first circuit structure.

[0095] One possible implementation also includes: the number of quadtrees in the same group is equal to the number of quadtree input lines in the group; the nodes in the same quadtree in the same group are the same except for the first level, and the nodes in the first level have the same probability of being inverters or buffers.

[0096] In one possible implementation, the quadtree is further defined as having no more than four levels.

[0097] In one possible implementation, the low-delay circuit structure determination unit 24 is further configured to:

[0098] Obtain the desired delay;

[0099] Based on the expected delay, circuit structures with delays less than or equal to the expected delay are determined in the delay table as the low-delay circuit structures, which are used to construct the S-box.

[0100] In one possible implementation, each of the low-delay circuits corresponds to a first truth table, and the device 20 further includes:

[0101] The second truth table determination unit is used to determine the second truth table of the existing S-box based on the lookup table and Boolean function of the existing S-box, wherein the circuit structure of the existing S-box is unknown.

[0102] A circuit structure determination unit is selected to determine a target first truth table that is the same as the second truth table, and to select the low-delay circuit structure corresponding to the target first truth table as the selected circuit structure.

[0103] The S-box construction unit is used to construct an S-box with the same delay effect as the existing S-box based on the selected circuit structure.

[0104] In one possible implementation, the first logic library is an ASIC library, and the logic gates include: inverters (INV), buffers (BUF), two-input NAND gates (NAND2), two-input NOR gates (NOR2), two-input AND gates (AND2), two-input OR gates (OR2), two-input XOR gates (XOR2), two-input XNOR gates (XNOR2), three-input NAND gates (NAND3), three-input NAND gates (OAI21), three-input AND-OR-NOT gates (AOI21), three-input NOT gates (NOR3), three-input AND gates (AND3), three-input OR gates (OR3), two-input selectors (MUX2), four-input NAND gates (OAI22), four-input AND-OR-NOT gates (AOI22), four-input NAND gates (NAND4), four-input NOR gates (NOR4), four-input AND gates (AND4), and four-input OR gates (OR4).

[0105] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0106] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium can be volatile or non-volatile.

[0107] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0108] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0109] Figure 6 This is a schematic diagram of an electronic device for determining a low-latency circuit structure, provided as an embodiment of the present disclosure. For example, the electronic device 1900 can be provided as a server or terminal device. (Refer to...) Figure 6The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0110] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). Electronic device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM Mac OS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0111] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0112] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0113] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0114] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0115] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0116] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0117] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0118] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0119] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0120] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for determining a low-delay circuit structure, characterized in that, include: Retrieve the logic gates from the first logic library; Multiple quadtrees are constructed based on the logic gates. Each node of the quadtree is a logic gate, and nodes at the same level are the same logic gates. The quadtrees in the same group are the same except for the first level. The quadtrees between different groups are different. The first level of each quadtree is composed of inverters and buffers. The nodes of a single quadtree can form the circuit structure of multiple Boolean functions. Using the quadtree, the delay of the circuit structure under test is determined, and a delay table is constructed, which represents the correspondence between the circuit structure under test and the delay. Based on the delay table, determine the low-delay circuit structure; The delay for determining the structure of the circuit under test includes: The circuit under test is disassembled to obtain at least one sub-circuit structure under test; a first quadtree representing the sub-circuit structure under test is selected; the number of input lines of the sub-circuit structure under test is taken as the number of first quadtrees in the same group; the delay of each of the at least one sub-circuit structure under test is measured using each group of first quadtrees; the maximum value of each delay is taken as the delay of the circuit under test.

2. The method according to claim 1, characterized in that, The process of using the quadtree to determine the delay of the circuit structure under test includes: By traversing from the leaf nodes to the root node of the multiple sets of quadtrees, multiple first circuit structures are obtained; Measure and record the time from the input of the data to the output of the first circuit structure, and use this time as the delay corresponding to the first circuit structure.

3. The method according to claim 1, characterized in that, Also includes: The number of quadtrees in the same group is equal to the number of quadtree input lines in that group; in the same group, except for the first level, the nodes of the same level are the same, and the nodes of the first level have the same probability of being inverters or buffers.

4. The method according to claim 1, characterized in that, Also includes: The quadtree has no more than four levels.

5. The method according to claim 1, characterized in that, The step of determining the low-delay circuit structure based on the delay table includes: Obtain the desired delay; Based on the expected delay, circuit structures with delays less than or equal to the expected delay are determined in the delay table as the low-delay circuit structures, which are used to construct the S-box.

6. The method according to claim 1, characterized in that, Each of the aforementioned low-delay circuits corresponds to a first truth table, and the method further includes: Based on the lookup table and Boolean function of the existing S-box, determine the second truth table of the existing S-box, wherein the circuit structure of the existing S-box is unknown; A target first truth table that is identical to the second truth table is determined, and the low-delay circuit structure corresponding to the target first truth table is selected as the circuit structure. Based on the selected circuit structure, an S-box with the same delay effect as the existing S-box is constructed.

7. The method according to claim 1, characterized in that, The first logic library is an ASIC library, and the logic gates include: inverters, buffers, two-input NAND gates, two-input NOR gates, two-input AND gates, two-input OR gates, two-input XOR gates, two-input XNOR gates, three-input NAND gates, three-input AND-OR-NOT gates, three-input NOT gates, three-input AND gates, three-input OR gates, two-input selectors, four-input NAND gates, four-input AND-OR-NOT gates, four-input NAND gates, four-input NOR gates, four-input AND gates, and four-input OR gates.

8. An apparatus for determining a low-delay circuit structure, characterized in that, include: The logic gate acquisition unit is used to acquire logic gates from the first logic library; The quadtree construction unit is used to construct multiple quadtrees based on the logic gates. Each node of the quadtree is a logic gate, and nodes at the same level are the same logic gates. The quadtrees in the same group are the same except for the first level. The quadtrees between different groups are different. The first level of each quadtree is composed of inverters and buffers. The nodes of a single quadtree can form the circuit structure of multiple Boolean functions. The delay table construction unit is used to determine the delay of the circuit structure under test using the quadtree and construct a delay table, wherein the delay table represents the correspondence between the circuit structure under test and the delay. A low-delay circuit structure determination unit is used to determine the low-delay circuit structure based on the delay table; The delay table construction unit is further used for: The circuit structure under test is disassembled to obtain at least one sub-circuit structure under test; a first quadtree representing the sub-circuit structure under test is selected. The number of input lines of the sub-circuit under test is taken as the number of first quadtrees in the same group; the delay of each of the first quadtrees is measured using each group of at least one sub-circuit under test; the maximum value of each delay is taken as the delay of the circuit under test.

9. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to implement the method of any one of claims 1 to 7 when executing instructions stored in the memory.

10. A non-volatile computer-readable storage medium storing computer program instructions thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 7.

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