Offset voltage determination method and device, storage medium and electronic equipment

Abstract

The invention provides an offset voltage determination method and device, a storage medium and electronic equipment, and relates to the field of semiconductor storage. The method comprises the following steps: the electronic equipment obtains a first test voltage and a second test voltage corresponding to each optimal threshold voltage according to at least one current optimal threshold voltage of a target memory; reading the target memory through a first test voltage obtained by the at least one optimal threshold voltage to obtain a first number of memory units which are overturned in the target memory; reading the target memory through a second test voltage obtained by the at least one optimal threshold voltage to obtain a second number of memory units which are overturned in the target memory; and obtaining the optimal offset voltage of each optimal threshold voltage according to the first number and the second number. Therefore, the optimal offset voltage for adjusting the current optimal voltage threshold value can be quickly found by utilizing the relationship between the number of the memory units which are overturned and the optimal offset voltage.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage, and in particular, to a method, device, storage medium and electronic device for determining an offset voltage. Background Art

[0002] NAND flash memory includes three storage modes: SLC (Single-Level Cell), MLC (Multi-Level Cell), and TLC (Triple-Level Cell). The difference lies in the number of data bits that each storage cell (also known as Cell) can store. Among them, SLC stores 1 bit per storage cell, MLC stores 2 bits per storage cell, and TLC can store 3 bits per cell. This means that with the evolution of storage modes, storage density has been improved, but it also brings differences in reliability and performance. Regardless of the storage mode, the storage principle is based on charge storage, that is, data is represented by charging or releasing charges in floating gate transistors. When reading data, these three storage modes need to be implemented through threshold voltage, that is, the controller will apply a series of voltages to the storage cell and compare it with the threshold voltage of the storage cell. SLC needs to distinguish between two different voltage states, MLC needs to distinguish between four, and TLC needs to distinguish between eight different voltage states to determine the specific data stored in the storage cell.

[0003] Therefore, the threshold voltage is a key parameter used to determine the state of the storage cell in NAND flash memory. The precise setting of the threshold voltage is crucial to ensure the correctness of data reading. Any slight deviation may cause reading errors, thus affecting the data integrity of the entire storage system. However, with the passage of time and frequent use, NAND flash memory faces a variety of changes in physical and electrical properties. These changes are mainly reflected in charge leakage, accumulation of program / erase cycles, ambient temperature fluctuations, subtle differences in manufacturing processes, and degradation of the oxide layer of floating gate transistors. These factors work together to cause the threshold voltage of the storage cell to drift, thus affecting the correct reading of data.

[0004] The existing firmware algorithm will recover the erroneous data. The Nand manufacturer will provide RRT (Read Retry Table) as a reference to adjust the current optimal reference voltage to reduce bit flipping, thereby achieving data recovery. However, in practice, it is found that there are too many RRTs provided by the manufacturer. If you don’t know which RRT is the most suitable, you can only traverse the RRT, which will cause a serious decline in read performance and slow response speed, which will eventually affect the user experience. Summary of the invention

[0005] In order to overcome at least one of the deficiencies in the prior art, the present application provides a method, device, storage medium and electronic device for determining an offset voltage, specifically including:

[0006] In a first aspect, the present application provides a method for determining an offset voltage, the method comprising:

[0007] According to at least one current optimal threshold voltage of the target memory, obtaining a first test voltage and a second test voltage corresponding to each of the optimal threshold voltages, wherein each of the optimal threshold voltages is between the corresponding first test voltage and the second test voltage, and the corresponding first test voltage is greater than the second test voltage;

[0008] Reading the target memory with a first test voltage obtained by the at least one optimal threshold voltage to obtain a first number of flipped memory cells in the target memory;

[0009] Reading the target memory with a second test voltage obtained by the at least one optimal threshold voltage to obtain a second number of flipped memory cells in the target memory;

[0010] An optimal offset voltage for each of the optimal threshold voltages is obtained according to the first number and the second number.

[0011] In combination with the optional implementation manner of the first aspect, obtaining the optimal offset voltage of each optimal threshold voltage according to the first quantity and the second quantity includes:

[0012] obtaining a difference between the first quantity and the second quantity;

[0013] The difference is mapped to an optimal offset voltage for each of the optimal threshold voltages according to a first mapping relationship pre-fitted for each of the optimal threshold voltages.

[0014] In combination with the optional implementation manner of the first aspect, obtaining the optimal offset voltage of each optimal threshold voltage according to the first quantity and the second quantity includes:

[0015] obtaining a ratio between the first quantity and the second quantity;

[0016] The ratio is mapped to an optimal offset voltage for each of the optimal threshold voltages according to a second mapping relationship pre-fitted for each of the optimal threshold voltages.

[0017] In combination with the optional implementation manner of the first aspect, obtaining the optimal offset voltage of each optimal threshold voltage according to the first quantity and the second quantity includes:

[0018] Obtaining a cumulative value between the first quantity and the second quantity;

[0019] The accumulated value is mapped to an optimal offset voltage for each of the optimal threshold voltages according to a third mapping relationship pre-fitted for each of the optimal threshold voltages.

[0020] In combination with the optional implementation manner of the first aspect, the method further includes:

[0021] Get the offset voltage reference table;

[0022] The best offset voltage closest to each of the best threshold voltages in the voltage reference table is used as the best offset optimization voltage for each of the best threshold voltages.

[0023] In combination with the optional implementation manner of the first aspect, the obtaining of the offset voltage reference table includes:

[0024] Acquire current operating condition information of the target storage;

[0025] According to the operating condition information, an offset voltage reference table matching the operating condition information is determined from a complete offset voltage reference table of the target memory.

[0026] In combination with the optional implementation manner of the first aspect, obtaining a first test voltage and a second test voltage corresponding to each of the optimal threshold voltages according to at least one current optimal threshold voltage of the target memory includes:

[0027] For each of the optimal threshold voltages, increasing the optimal threshold voltage by a preset offset to obtain the first test voltage;

[0028] The optimal threshold voltage is reduced by the preset offset to obtain the second test voltage.

[0029] In a second aspect, the present application provides an offset voltage determination device, the device comprising:

[0030] A test voltage module, which obtains a first test voltage and a second test voltage corresponding to each optimal threshold voltage according to at least one current optimal threshold voltage of the target memory, wherein each optimal threshold voltage is between the corresponding first test voltage and the second test voltage, and the corresponding first test voltage is greater than the second test voltage;

[0031] A flip statistics module, configured to read the target memory through a first test voltage obtained by the at least one optimal threshold voltage, and obtain a first number of flipped storage cells in the target memory;

[0032] The flip statistics module is used to read the target memory through a second test voltage obtained by the at least one optimal threshold voltage to obtain a second number of memory cells flipped in the target memory;

[0033] An offset voltage module is used to obtain an optimal offset voltage for each of the optimal threshold voltages according to the first quantity and the second quantity.

[0034] In combination with the optional implementation manner of the second aspect, the offset voltage module is further specifically used for:

[0035] obtaining a difference between the first quantity and the second quantity;

[0036] The difference is mapped to an optimal offset voltage for each of the optimal threshold voltages according to a first mapping relationship pre-fitted for each of the optimal threshold voltages.

[0037] In combination with the optional implementation manner of the second aspect, the offset voltage module is further specifically used for:

[0038] obtaining a ratio between the first quantity and the second quantity;

[0039] The ratio is mapped to an optimal offset voltage for each of the optimal threshold voltages according to a second mapping relationship pre-fitted for each of the optimal threshold voltages.

[0040] In combination with the optional implementation manner of the second aspect, the offset voltage module is further specifically used for:

[0041] Obtaining a cumulative value between the first quantity and the second quantity;

[0042] The accumulated value is mapped to an optimal offset voltage for each of the optimal threshold voltages according to a third mapping relationship pre-fitted for each of the optimal threshold voltages.

[0043] In combination with the optional implementation manner of the second aspect, the offset voltage module is further used for:

[0044] Get the offset voltage reference table;

[0045] The best offset voltage closest to each of the best threshold voltages in the voltage reference table is used as the best offset optimization voltage for each of the best threshold voltages.

[0046] In conjunction with the optional implementation manner of the second aspect, the offset voltage module is further used to:

[0047] Acquire current operating condition information of the target storage;

[0048] According to the operating condition information, an offset voltage reference table matching the operating condition information is determined from a complete offset voltage reference table of the target memory.

[0049] In conjunction with the optional implementation manner of the second aspect, the test voltage module is further specifically used for:

[0050] For each of the optimal threshold voltages, increasing the optimal threshold voltage by a preset offset to obtain the first test voltage;

[0051] The optimal threshold voltage is reduced by the preset offset to obtain the second test voltage.

[0052] In a third aspect, the present application further provides a storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the offset voltage determination method is implemented.

[0053] In a fourth aspect, the present application further provides an electronic device, comprising a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the offset voltage determination method is implemented.

[0054] Compared with the prior art, this application has the following beneficial effects:

[0055] In the offset voltage determination method, device, storage medium and electronic device provided by the present application, the electronic device obtains a first test voltage and a second test voltage corresponding to each optimal threshold voltage according to at least one optimal threshold voltage currently of the target memory, wherein each optimal threshold voltage is between the corresponding first test voltage and the second test voltage, and the corresponding first test voltage is greater than the second test voltage; the target memory is read by the first test voltage obtained by at least one optimal threshold voltage to obtain a first number of storage cells flipped in the target memory; the target memory is read by the second test voltage obtained by at least one optimal threshold voltage to obtain a second number of storage cells flipped in the target memory; the optimal offset voltage for each optimal threshold voltage is obtained according to the first number and the second number. In this way, by using the relationship between the number of storage cells flipped and the optimal offset voltage, the optimal offset voltage for adjusting the current optimal voltage threshold can be quickly found. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0057] Figure 1 A schematic diagram of the structure of a storage unit in a NAND flash memory provided in an embodiment of the present application;

[0058] Figure 2 A schematic diagram of the storage principle in the TLC mode provided in an embodiment of the present application;

[0059] Figure 3 A schematic diagram of a flow chart of a method for determining an offset voltage provided in an embodiment of the present application;

[0060] Figure 4 A schematic diagram of a mapping table provided in an embodiment of the present application;

[0061] Figure 5 A schematic diagram of the structure of an offset voltage determination device provided in an embodiment of the present application;

[0062] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0063] Icons: 11 - control gate; 12 - drain; 13 - source; 14 - floating gate; 15 - silicon dioxide layer; 21 - test voltage module; 22 - flip statistics module; 23 - offset voltage module; 31 - memory; 32 - processor. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0065] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0066] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0067] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the invented product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0068] In addition, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0069] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0070] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0071] Based on the above statement, as introduced in the background technology, when the threshold voltage in the Nand flash memory is adjusted through the RRT provided by the original manufacturer, there are many RRTs provided by the original manufacturer. When it is unknown which RRT is the most suitable, the RRT can only be traversed. Therefore, the number of search steps is relatively large and time-consuming, which seriously affects the performance of read error correction.

[0072] Based on the discovery of the above technical problems, the inventors have proposed the following technical solutions to solve or improve the above problems through creative work. It should be noted that the defects in the solutions in the above prior art are the results obtained by the inventors after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of the present application for the above problems below should all be the contributions made by the inventors to the present application in the process of invention and creation, and should not be understood as technical contents known to those skilled in the art.

[0073] Since this embodiment involves NAND flash memory, in order to make the subsequent embodiments easier to understand, the storage principle of NAND flash memory is first explained in conjunction with the corresponding schematic diagram. First of all, it should be understood that in NAND flash memory, when data needs to be written, Figure 1 The control gate 11 shown applies a high voltage, and then allows electrons to flow into the N-channel between the source 13 and the drain 12. When the current reaches a certain intensity, the electrons gain enough energy and will cross the silicon dioxide layer 15 (SiO2) under the floating gate 14 and be captured by the unit. This process is called the tunneling effect.

[0074] Continue to see Figure 1 Once the electrons enter the floating gate 14, even if the power is removed, as long as there is not enough energy, the electrons cannot escape from the silicon dioxide layer 15 below, and the state of capturing electrons will continue, which can be as long as ten years, depending on the wear of the silicon dioxide layer 15 used for insulation. When reading data, a voltage is also applied to the control gate 11 to attract the electrons in the floating gate 14, but it does not need to be as high as when the electrons are injected through tunneling. At the same time, the N channel is allowed to flow with current, and the current is used to sense the amount of electrons captured in the floating gate 14, so as to convert it into binary 0 and 1 according to the induction strength, and finally output the read data.

[0075] like Figure 2As shown, each storage cell stores 1 bit in SLC mode, 2 bits in MLC mode, and 3 bits in TLC mode. Since one memory storage cell of TLC can store 3 bits of data, different threshold voltages must be used to distinguish them. In other words, in addition to being able to achieve 000 (TLC) = 0 (SLC) and 111 (TLC) = 1 (SLC) like SLC, there are six other data formats that must be distinguished by other different threshold voltages, allowing different numbers of electrons to enter the storage cell to achieve different data expressions. In this way, TLC achieves the purpose of storing more data in a single storage cell than SLC and MLC.

[0076] Based on the introduction of the storage principle of NAND flash memory in the above embodiment, this embodiment provides a method for determining an offset voltage. In this method, the electronic device obtains a first test voltage and a second test voltage corresponding to each optimal threshold voltage according to at least one optimal threshold voltage of the target memory at present, wherein each optimal threshold voltage is between the corresponding first test voltage and the second test voltage, and the corresponding first test voltage is greater than the second test voltage; the target memory is read by the first test voltage obtained by at least one optimal threshold voltage to obtain the first number of storage cells flipped in the target memory; the target memory is read by the second test voltage obtained by at least one optimal threshold voltage to obtain the second number of storage cells flipped in the target memory; the optimal offset voltage for each optimal threshold voltage is obtained according to the first number and the second number. In this way, by using the relationship between the number of flipped storage cells and the optimal offset voltage, the optimal offset voltage for adjusting the current optimal voltage threshold can be quickly found.

[0077] It should be noted that the electronic device implementing the above method may be, but is not limited to, a storage controller of a Nand flash memory or a core processor for reading and writing data in the Nand flash memory.

[0078] To make the solution provided by this embodiment clearer, the following takes the storage controller as an example and combines Figure 3 Each step of the method is described in detail. However, it should be understood that the operations of the flowchart may not be implemented in order, and steps without logical contextual relationships may be reversed in order or implemented simultaneously. In addition, those skilled in the art may add one or more other operations to the flowchart, or remove one or more operations from the flowchart under the guidance of the content of this application. Figure 3 As shown, the method includes:

[0079] S1, obtaining a first test voltage and a second test voltage corresponding to each optimal threshold voltage according to at least one current optimal threshold voltage of a target memory.

[0080] Wherein, each optimal threshold voltage is between the corresponding first test voltage and the second test voltage, and the corresponding first test voltage is greater than the second test voltage. In a specific implementation, for each optimal threshold voltage, the storage controller may increase the optimal threshold voltage by a preset offset to obtain a first test voltage; and reduce the optimal threshold voltage by a preset offset to obtain a second test voltage. Wherein, this embodiment selects 80mV as the preset offset, but 80mV cannot be regarded as a limitation of this application. When implementing this solution, those skilled in the art may adjust the preset offset according to actual needs.

[0081] In addition, it should be noted that the target memory in this embodiment can be a Nand flash memory based on storage principles such as SLC, MLC and TLC. Regarding the number of optimal threshold voltages, it should also be noted that when the target memory is a NAND flash memory based on TLC, RL1, RL2, RL3, RL4, RL5, RL6, and RL7 are used to represent different read levels (ReadLevels) of the read operation, and these read levels correspond to different optimal threshold voltages used by the storage controller to determine the charge state in the storage unit. However, due to the limitation of the hardware circuit, some target memories cannot be read sequentially according to the read levels, but are read in groups. For example, RL3 and RL7 are a group, RL1 and RL5 are a group, and RL2, RL4 and RL7 are a group; this means that it is necessary to use the optimal threshold voltages corresponding to RL3 and RL7 for simultaneous reading; or use the optimal threshold voltages corresponding to RL1 and RL5 for simultaneous reading. Therefore, each time the target memory is tested, the optimal threshold voltage of at least one read level will be used.

[0082] Based on the introduction of each optimal threshold voltage and its corresponding first test voltage and second test voltage in the above embodiment, continue to refer to Figure 3 , the offset voltage determination method provided in this embodiment further includes:

[0083] S2, reading a target memory using a first test voltage obtained through at least one optimal threshold voltage to obtain a first number of flipped memory cells in the target memory.

[0084] S3, reading the target memory using a second test voltage obtained through at least one optimal threshold voltage to obtain a second number of flipped memory cells in the target memory.

[0085] It should be understood that reading the target memory at a voltage different from the current optimal threshold voltage will inevitably cause some memory cells to flip. For example, for some memory cells, when reading at the current optimal threshold voltage, the read bit value is 1, and when reading at the first test voltage or the second test voltage, the read bit value is 0, which is a flip. The target memory includes multiple memory cells. Therefore, each memory cell is read at the first test voltage, and the first number of memory cells that flip is counted; similarly, each memory cell is read at the second test voltage, and the second number of memory cells that flip is counted. It is worth noting that both the first number and the second number are counted relative to the data read using the current optimal threshold voltage.

[0086] S4, obtaining an optimal offset voltage for each optimal threshold voltage according to the first quantity and the second quantity.

[0087] It should be noted that, in practice, it is found that the difference, ratio and cumulative value between the first number and the second number respectively present a specific mapping relationship with the official optimal offset voltage, specifically a very strong linear relationship. This embodiment is based on this finding, and obtains the optimal offset voltage for each optimal threshold voltage according to the first number and the second number.

[0088] In an optional implementation manner provided by this embodiment, the storage controller may obtain the difference between the first quantity and the second quantity; and map the difference to an optimal offset voltage for each optimal threshold voltage according to a first mapping relationship pre-fitted for each optimal threshold voltage.

[0089] In other optional implementations provided by this embodiment, the storage controller may also obtain a ratio between the first quantity and the second quantity; and map the ratio to an optimal offset voltage for each optimal threshold voltage according to a second mapping relationship pre-fitted for each optimal threshold voltage.

[0090] In another optional implementation manner provided by this embodiment, the memory may also obtain a cumulative value between the first quantity and the second quantity; and map the cumulative value to an optimal offset voltage for each optimal threshold voltage according to a third mapping relationship pre-fitted for each optimal threshold voltage, wherein the cumulative value between the first quantity and the second quantity is the sum of the two.

[0091] It should be understood that the above-mentioned mapping relationship may be a fitted mapping function in some embodiments; while in some other embodiments, the mapping relationship may be a fitted mapping table, which records the mapping relationship between the difference range, ratio range or cumulative value range and the optimal offset voltage.

[0092] In addition, it is found in practice that for different models, different manufacturers or different read levels of the same memory, the difference, ratio and cumulative value between the first quantity and the second quantity can respectively obtain the optimal offset voltage with different precision; therefore, those skilled in the art can make adaptive choices when implementing this solution. For example, it is found in practice that for some memories, the optimal offset voltage mapped by the cumulative value of RL5-RL7 is closest to the reference offset voltage provided by the official.

[0093] Therefore, if it is found after experimental comparison that the mapped optimal offset voltage is very close to the reference offset voltage obtained by traversing the RRT, the mapped optimal offset voltage may not be corrected by using the RRT, and the current optimal threshold voltage of the target memory may be adjusted directly with the mapped optimal offset voltage. On the contrary, if it is found after experimental comparison that there is a large error between the mapped optimal offset voltage and the reference offset voltage obtained by traversing the RRT, the offset voltage determination method provided in this embodiment further includes:

[0094] S5, obtaining an offset voltage reference table.

[0095] S6, taking the best offset voltage closest to each best threshold voltage in the voltage reference table as the best offset optimization voltage for each best threshold voltage.

[0096] In this embodiment, in order to improve the matching efficiency, the official RRT table is used as a complete offset voltage reference table, and the offset voltage reference table can be a part of the complete offset voltage reference table. In a specific implementation, the storage controller can obtain the current working condition information of the target memory; according to the working condition information, determine the offset voltage reference table that matches the working condition information from the complete offset voltage reference table of the target memory.

[0097] Exemplarily, the storage controller obtains the temperature of the target memory during writing and reading to determine whether the reading environment is a cross-temperature environment, a long-term storage environment, or other environment, and determines a matching smaller-range RRT table from the official complete RRT table based on this information. After determining the smaller range, the mapped optimal offset voltage is compared with the RRT table of the smaller range, and the offset voltage with the closest Euclidean distance is selected as the optimal offset optimization voltage, which is used to adjust the current optimal threshold voltage of the target memory.

[0098] The above embodiment is further described in detail below in conjunction with a specific example. For the three read levels RL2, RL4 and RL6 in the target memory. First, the current optimal threshold voltages of the three read levels RL2, RL4 and RL6 are simultaneously shifted to the left by an interval of 80mV, and the first number of memory cells that are flipped is counted. Then, the current optimal threshold voltages of the three read levels RL2, RL4 and RL6 are simultaneously shifted to the right by an interval of 80mV, and the second number of memory cells that are flipped is counted. Assuming that the difference between the first number and the second number is 2330, 2330 is multiplied by 1. Figure 4 The mapping table shown in the figure records the corresponding relationship between the difference range and the optimal offset voltage of each read level. Through the mapping table, it can be obtained that the optimal offset voltage required for the optimal threshold voltage of RL2 is -6mV, the optimal offset voltage required for the optimal threshold voltage of RL4 is -14mV, and the optimal offset voltage required for the optimal threshold voltage of RL6 is -18mV. It can be understood that after the optimal threshold voltage of each read level changes, if it is impossible to count the specific number of memory cells that have flipped, then the total number of all memory cells that have flipped after the optimal threshold voltage changes under multiple read levels is counted, and then, based on the total number, the optimal offset voltage corresponding to the optimal threshold voltage of each read level is mapped out respectively.

[0099] Based on the same inventive concept as the offset voltage determination method provided in this embodiment, this embodiment also provides an offset voltage determination device, which includes at least one software function module that can be stored in a memory or fixed in an electronic device in the form of software. The processor in the electronic device is used to execute the executable module stored in the memory. For example, the software function module and computer program included in the device. Please refer to Figure 5 , functionally speaking, the device may include:

[0100] The test voltage module 21 obtains a first test voltage and a second test voltage corresponding to each optimal threshold voltage according to at least one current optimal threshold voltage of the target memory, wherein each optimal threshold voltage is between the corresponding first test voltage and the second test voltage, and the corresponding first test voltage is greater than the second test voltage.

[0101] The flip statistics module 22 is used to read the target memory through a first test voltage obtained by at least one optimal threshold voltage to obtain a first number of flipped memory cells in the target memory.

[0102] The flip statistics module 22 is further configured to read the target memory through a second test voltage obtained by at least one optimal threshold voltage to obtain a second number of flipped memory cells in the target memory.

[0103] The offset voltage module 23 is used to obtain an optimal offset voltage for each optimal threshold voltage according to the first quantity and the second quantity.

[0104] In this embodiment, the test voltage module 21 is used to implement Figure 3 In step S1, the flip statistics module 22 is used to implement Figure 3 In steps S2 and S3, the offset voltage module 23 is used to implement Figure 3 Therefore, for the detailed description of each of the above modules, please refer to the specific implementation of the corresponding step. Of course, in view of the same inventive concept as the method provided in this embodiment, the above modules can also be used to implement other steps or sub-steps of the method, which will not be described in detail in this embodiment.

[0105] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0106] It should also be understood that if the above implementation is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application.

[0107] Therefore, this embodiment further provides a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by the processor, the offset voltage determination method provided in this embodiment is implemented. Among them, the storage medium can be a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc., which can store program codes.

[0108] This embodiment provides an electronic device for implementing a method for determining an offset voltage. Figure 6 As shown, the electronic device may include a processor 32 and a memory 31. In addition, the memory 31 stores a computer program, and the processor implements the offset voltage determination method provided in this embodiment by reading and executing the computer program corresponding to the above implementation in the memory 31.

[0109] The memory 31 may be an information recording device based on any electronic, magnetic, optical or other physical principle, used to record execution instructions, data, etc. In some embodiments, the memory 31 may be, but is not limited to, a volatile memory, a non-volatile memory, a storage drive, etc.

[0110] In some embodiments, the volatile memory may be a random access memory (RAM); in some embodiments, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), a flash memory, etc.; in some embodiments, the storage drive may be a disk drive, a solid-state drive, any type of storage disk (such as a CD, a DVD, etc.), or a similar storage medium, or a combination thereof, etc.

[0111] The processor 32 may be an integrated circuit chip having a signal processing capability, and the processor may include one or more processing cores (e.g., a single-core processor or a multi-core processor). By way of example only, the processor may include a central processing unit (CPU), an application specific integrated circuit (ASIC), an application specific instruction set processor (ASIP), a graphics processing unit (GPU), a physical processing unit (PPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC), or a microprocessor, or any combination thereof.

[0112] Understandably, Figure 6 The structure shown is for illustration only. The electronic device may also have Figure 6 More or fewer components than shown, or with Figure 6 Different configurations shown. Figure 6 The components shown may be implemented in hardware, software or a combination thereof.

[0113] It should be understood that the apparatus and method disclosed in the above-mentioned embodiments can also be implemented in other ways. The apparatus embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0114] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for determining an offset voltage, characterized in that: The method comprises: According to at least one current optimal threshold voltage of the target memory, obtaining a first test voltage and a second test voltage corresponding to each of the optimal threshold voltages, wherein each of the optimal threshold voltages is between the corresponding first test voltage and the second test voltage, and the corresponding first test voltage is greater than the second test voltage; Reading the target memory with a first test voltage obtained by the at least one optimal threshold voltage to obtain a first number of flipped memory cells in the target memory; Reading the target memory with a second test voltage obtained by the at least one optimal threshold voltage to obtain a second number of flipped memory cells in the target memory; An optimal offset voltage for each of the optimal threshold voltages is obtained according to the first number and the second number.

2. The offset voltage determination method according to claim 1, characterized in that: The step of obtaining an optimal offset voltage for each optimal threshold voltage according to the first quantity and the second quantity includes: obtaining a difference between the first quantity and the second quantity; The difference is mapped to an optimal offset voltage for each of the optimal threshold voltages according to a first mapping relationship pre-fitted for each of the optimal threshold voltages.

3. The offset voltage determination method according to claim 1, characterized in that: The step of obtaining an optimal offset voltage for each optimal threshold voltage according to the first quantity and the second quantity includes: obtaining a ratio between the first quantity and the second quantity; The ratio is mapped to an optimal offset voltage for each of the optimal threshold voltages according to a second mapping relationship pre-fitted for each of the optimal threshold voltages.

4. The offset voltage determination method according to claim 1, characterized in that: The step of obtaining an optimal offset voltage for each optimal threshold voltage according to the first quantity and the second quantity includes: Obtaining a cumulative value between the first quantity and the second quantity; The accumulated value is mapped to an optimal offset voltage for each of the optimal threshold voltages according to a third mapping relationship pre-fitted for each of the optimal threshold voltages.

5. The offset voltage determination method according to claim 1, characterized in that: The method further comprises: Get the offset voltage reference table; The best offset voltage closest to each of the best threshold voltages in the voltage reference table is used as the best offset optimization voltage for each of the best threshold voltages.

6. The offset voltage determination method according to claim 5, characterized in that: The step of obtaining the offset voltage reference table includes: Acquire current operating condition information of the target storage; According to the operating condition information, an offset voltage reference table matching the operating condition information is determined from a complete offset voltage reference table of the target memory.

7. The offset voltage determination method according to claim 1, characterized in that: The step of obtaining a first test voltage and a second test voltage corresponding to each of the optimal threshold voltages according to at least one current optimal threshold voltage of the target memory includes: For each of the optimal threshold voltages, increasing the optimal threshold voltage by a preset offset to obtain the first test voltage; The optimal threshold voltage is reduced by the preset offset to obtain the second test voltage.

8. An offset voltage determination device, characterized in that: The device comprises: A test voltage module, which obtains a first test voltage and a second test voltage corresponding to each optimal threshold voltage according to at least one current optimal threshold voltage of the target memory, wherein each optimal threshold voltage is between the corresponding first test voltage and the second test voltage, and the corresponding first test voltage is greater than the second test voltage; A flip statistics module, configured to read the target memory through a first test voltage obtained by the at least one optimal threshold voltage, and obtain a first number of flipped storage cells in the target memory; The flip statistics module is used to read the target memory through a second test voltage obtained by the at least one optimal threshold voltage to obtain a second number of memory cells flipped in the target memory; An offset voltage module is used to obtain an optimal offset voltage for each of the optimal threshold voltages according to the first quantity and the second quantity.

9. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the offset voltage determination method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the offset voltage determination method according to any one of claims 1 to 7 is implemented.

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