Testing device and testing method for memory module

Abstract

The invention provides a test device and a test method for a memory module, and the test device comprises an interface adapter plate which comprises a memory interface module and is used for being connected with different types of memory modules; the main control board comprises an interface module, a DC test function module and an AC test function module, the DC test function module and the AC test function module are selectively connected with the interface module, and the interface module is connected with the interface adapter board; the upper computer is used for outputting working information and acquiring test result information; the core control board comprises a communication module and a processor module which are connected with each other, the communication module is in communication connection with the upper computer, obtains work information and returns test result information after the test is completed, and the processor module is connected with the DC test function module and the AC test function module. And the interface module is configured to be connected with the DC test function module or the AC test function module according to the working information, and test result information is obtained after the test is completed. Therefore, in the technical scheme, the testing device can support both AC testing and DC testing, the testing platform does not need to be replaced in the testing process, the testing time is shortened, and the cost is low.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory module testing device and a testing method thereof. Background Art

[0002] The memory module is composed of DRAM (Dynamic Random Access Memory) particles, PCB (Printed Circuit Board) and SPD (Serial Presence Detect). After the production of the memory module is completed, the SPD information needs to be burned, and there may be many problems, such as: DRAM particle welding problems, PCB gold finger damage, DRAM particle defects, etc. In the prior art, the AC (Alternating Current) test method is usually used for SPD burning, DRAM function and performance testing, and HPPR (Hard Post Package Repair) maintenance; or the DC (Direct Current) test method is used for Contact (connectivity) testing to detect DRAM particle welding and PCB gold finger damage.

[0003] Therefore, there are two types of memory testing technologies at present: one is to use the motherboard for AC testing, and the other is to use special equipment to perform AC testing and DC testing. In memory module testing, the DC test must pass before the AC test, otherwise there is a risk of damaging the motherboard. When the DC test fails, it is usually necessary to replace the hardware for repair. When the AC test fails, HPPR technology can be used for software repair.

[0004] However, in the prior art, the motherboard only supports AC testing of the memory module, but does not support DC testing. Therefore, the testing of the memory module requires replacing the testing platform, resulting in a long testing time and high cost.

[0005] In view of this, it is necessary to design an improved memory module testing device to solve the above problems. Summary of the invention

[0006] The object of the present invention is to provide a memory module testing device and a testing method thereof which can fully detect the memory module without replacing the platform.

[0007] To achieve the above-mentioned object of the invention, the present invention provides a memory module testing device, the testing device comprising:

[0008] An interface adapter board, including a memory interface module, for connecting with different types of memory modules;

[0009] A main control board, comprising an interface module, a DC test function module and an AC test function module selectively connected to the interface module, wherein the interface module is connected to the interface adapter board;

[0010] Host computer, used to output work information and obtain test result information;

[0011] The core control board includes a communication module and a processor module connected to each other. The communication module is connected to the host computer for communication and obtains working information and returns test result information after the test is completed. The processor module is connected to the DC test function module and the AC test function module, and the interface module is configured to be connected to the DC test function module or the AC test function module according to the working information, and obtains the test result information after the test is completed.

[0012] As a further improvement of the present invention, the DC test function module includes a driving source circuit, an I / O control circuit and a signal processing circuit connected in sequence, and the I / O control circuit includes a switch switching circuit; the switch switching circuit includes a plurality of switching units, and the output end of each switching unit is respectively connected to a pin of the memory module.

[0013] As a further improvement of the present invention, the I / O control circuit further includes an I / O expansion circuit, and the selection control terminal of each of the switching units is connected to the I / O expansion circuit.

[0014] As a further improvement of the present invention, the driving source circuit includes a positive voltage source, a negative voltage source, a positive current source, and a negative current source, and all are connected to the input of each switching unit.

[0015] As a further improvement of the present invention, the AC test function module includes:

[0016] High-speed performance test circuit, used to test DRAM function and performance under high-speed conditions;

[0017] Sideband line function circuit, used to burn or read the SPD information of the memory module and read or configure the register information;

[0018] During the AC test, the interface module is connected to a high-speed performance test circuit.

[0019] As a further improvement of the present invention, the AC test function module also includes a low-speed function test circuit for HPPR repair. When the memory module is subjected to HPPR repair, the interface module is connected to the low-speed function test circuit and the sideband line function circuit.

[0020] As a further improvement of the present invention, the working information includes configuration information and instruction information, and the processor module receives the configuration information and enables and configures the corresponding circuit in the DC test function module or the AC test function module; and receives the instruction information and controls the DC test function module or the AC test function module to perform the corresponding test task;

[0021] The host computer includes a system configuration loading module and a system business function module; the system configuration loading module is used to send configuration information to the core control board, and the system business function module is used to send instruction information to the core control board, and receive and display test result information.

[0022] To achieve the above-mentioned object of the invention, the present invention provides a method for testing a memory module, the method comprising:

[0023] The core control board receives work information;

[0024] When the core control board determines to perform a DC test on the memory module according to the working information, the interface module of the main control board is connected to the DC test function module;

[0025] When the core control board determines to perform an AC test on the memory module according to the working information, the interface module of the main control board is connected to the AC test function module;

[0026] The core control board tests the memory module through the main control board.

[0027] As a further improvement of the present invention, when the core control board determines to perform a DC test on the memory module according to the working information, after connecting the interface module of the main control board with the DC test function module, it also includes:

[0028] The I / O expansion circuit in the DC test function module controls the output end of each switching unit and the pin of the memory module to be connected in sequence at different times, and enables the driving source circuit to perform DC testing on the memory module through each pin of the memory module.

[0029] As a further improvement of the present invention, the AC test function module includes a sideband line function circuit, and before the step of "core control board receiving working information", it also includes:

[0030] Insert the memory module into the interface adapter board, and the host computer obtains the model information of the tested memory module;

[0031] The host computer sends the burning command and burning information to the core control board;

[0032] After the core control board obtains the burning command and burning information, it configures and enables the sideband line function circuit;

[0033] Connecting the interface module to the sideband line functional circuit;

[0034] The sideband line function circuit burns the burning information into the memory module;

[0035] The burning is completed and the burning result is fed back to the host computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of the structure of a test device for a memory module in the present disclosure;

[0037] Figure 2 Schematic diagram of the circuit structure of the DC test function module of the test device in the present disclosure;

[0038] Figure 3 Schematic diagram of the circuit structure of the AC test function module of the test device in the present disclosure;

[0039] Figure 4 Schematic diagram of the test method in the present disclosure. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] It should also be noted here that in order to avoid obscuring the present disclosure due to unnecessary details, only structures and / or processing steps closely related to the scheme of the present disclosure are shown in the accompanying drawings, while other details that are not very relevant to the present disclosure are omitted.

[0042] In addition, it should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0043] In order to make the purpose, technical scheme and advantages of the present disclosure clearer, the present disclosure is further described in detail below in conjunction with the accompanying drawings. It is hereby declared that the following embodiments are only special cases of the method proposed in the present disclosure, not all embodiments, and all other embodiments obtained by making detailed adjustments without creative labor based on the embodiments in the present disclosure are within the scope of protection of the present disclosure.

[0044] like Figures 1 to 3As shown, the present disclosure provides a test device for a memory module M, the test device comprising:

[0045] The interface adapter board 1 includes a memory interface module 11 for connecting with different types of memory modules M;

[0046] The main control board 2 includes an interface module 20, a DC test function module 21 and an AC test function module 25 selectively connected to the interface module 20, and the interface module 20 is connected to the interface adapter board 1;

[0047] Host computer 4, used to output work information and obtain test result information;

[0048] The core control board 3 includes a communication module 31 and a processor module 32 connected to each other. The communication module 31 is connected to the host computer 4 for communication and acquisition of working information and returns test result information after the test is completed. The processor module 32 is connected to the DC test function module 21 and the AC test function module 25, and the interface module is configured to be connected to the DC test function module or the AC test function module according to the working information, and obtains the test result information after the test is completed.

[0049] Therefore, in the above technical solution of the present disclosure, the test device can support both AC testing and DC testing of the memory module M. There is no need to replace the test platform during the test, which shortens the test time and reduces the cost.

[0050] The tested memory module M needs to be connected to the interface adapter board 1 through the corresponding module Socket. The memory interface module 11 of the interface adapter board 1 supports the interface signal conversion of DDR3 UDIMM (Double Data Rate Unbuffered Dual In-line Memory Module), RDIMM (Registered Dual In-line Memory Module), SODIMM (Small Outline Dual In-line Memory Module), DDR4 UDIMM / RDIMM / SODIMM and DDR5UDIMM / RDIMM / SODIMM.

[0051] The interface adapter board 1 further comprises a hot-swap protection module 12, which can support the plugging and unplugging of the memory module M under test without powering off the test system, thereby improving the safety and effectiveness of the test device.

[0052] The main control board 2 is a test service execution unit of the test device. The main control board 2 can receive the work information sent by the core control board 3, and execute the corresponding test service according to the work information. After completing the test, the test result information is fed back to the core control board 3. The interface module 20 is an interface MUX (Multiplexer) module. The interface module 20 can realize the multiplexing of the DC test function module 21 and the AC test function module 25. Before executing the corresponding test, the interface module 20 needs to be connected with the corresponding DC test function module 21 or AC test function module 25.

[0053] The DC test function module 21 supports the contact test of DDR3 UDIMM / RDIMM / SODIMM, DDR4 UDIMM / RDIMM / SODIMM, DDR5 UDIMM / RDIMM / SODIMM, i.e., DC test. The AC test function module 25 supports SPD burning and DRAM function performance detection of DDR3, DDR4, and DDR5 memory modules M, and also supports HPPR repair of DDR4 and DDR5 memory modules M.

[0054] Specifically, Figure 2 As shown, the DC test function module 21 includes a driving source circuit 22, an I / O control circuit 23 and a signal processing circuit 24 connected in sequence, the I / O control circuit 23 includes a switch switching circuit 231; the switch switching circuit 231 includes a plurality of switching units 2311, and the output end O of each switching unit 2311 is respectively connected to a pin of the memory module M. The driving source circuit 22 is used to provide driving power to the I / O control circuit 23, the I / O control circuit 23 is used to switch the pin of the memory module M under test in the DC test, and the signal processing circuit 24 can amplify and process the test signal returned by the I / O control circuit 23 to facilitate the core control board 3 to receive it.

[0055] In this specific implementation, the driving source circuit 22 includes a positive voltage source 221, a negative voltage source 222, a positive current source 223, and a negative current source 224, and all are connected to the input end of each switching unit 2311. Specifically, the driving source circuit 22 includes a FVMI (Force Voltage Measure Ampere) circuit driven by the positive voltage source 221 or the negative voltage source 222, and a FIMV (Force Ampere Measure Voltage) circuit driven by the positive current source 223 or the negative current source 224.

[0056] The switch switching circuit 231 is implemented by an analog switch device equipped with a peripheral circuit to control the selection of each pin of the memory module M and the switching of the driving source circuit 22 in the DC test. Each switching unit 2311 of the switch switching circuit 231 includes 6 input terminals I, 1 output terminal O and a selection control terminal S. Among them, the 6 input terminals are connected to 4 types of driving sources, ground and common I / O. As mentioned above, the output terminal O of each switching unit 2311 is respectively connected to a pin of the memory module M, so that each pin of the memory module M can be Contact tested.

[0057] The I / O control circuit 23 also includes an I / O expansion circuit 232, and the selection control terminal S of each of the switching units 2311 is connected to the I / O expansion circuit 232, so that during the DC test process, the I / O expansion circuit 232 can control and enable any switching unit 2311, flexibly control the input drive of each switching unit 2311, and then perform contact tests on each pin of the memory module M. The I / O expansion circuit 232 is connected to each switching unit 2311 in the switch switching circuit 231 and performs time-sharing control, so that the I / O control circuit 23 can be simplified and optimized, and the area of ​​the I / O control circuit 23 and the number of discrete devices can be reduced.

[0058] Of course, in another embodiment, the Contact test can also be implemented through a relay circuit, but there are the following problems:

[0059] 1. If a relay with fewer channels is selected, the topology of the circuit used to implement the Contact test will be more complex, thereby increasing the complexity of the hardware design;

[0060] 2. If a relay with more channels is selected, the circuit cost of implementing the contact test will be higher and the power consumption will be higher;

[0061] 3. The relay's pull-in time and release time are long, and the memory module M has many pins, so the test is time-consuming.

[0062] The signal processing circuit 24 includes a signal amplifying circuit 241 and a signal conversion circuit 242. Since the current response of the positive voltage source 221, the negative voltage source 222, the positive current source 223, and the negative current source 224 on the pins of the memory module M is extremely small, usually less than 500uA, it is not conducive to the signal sampling circuit to obtain the test result. The cost of the high-precision signal sampling circuit is relatively high, so in this embodiment, the signal amplifying circuit 241 is used to amplify the test signal, and the hierarchical amplification technology can be used to be compatible with a wider sampling range. The signal conversion circuit 242 can convert the amplified test signal from an analog quantity to a digital quantity, so that the core control board 3 can receive it conveniently.

[0063] like Figure 3 As shown, the AC test function module 25 includes:

[0064] High-speed performance test circuit 251, used to test DRAM function and performance under high-speed conditions;

[0065] The sideband line function circuit 253 is used to burn or read the SPD information of the memory module M and read or configure the register information;

[0066] During the AC test, the interface module 20 is connected to the high-speed performance test circuit 251 .

[0067] The high-speed performance test circuit 251 has a high-speed MC (Memory Controller) unit of the memory module M, which is used to detect the function and performance of DRAM under high-speed conditions. When there is a defect in the function or performance of the memory module M under test, the high-speed performance test circuit 251 will send the defect information to the core control board 3.

[0068] The sideband line function circuit 253 has an IIC (Inter-Integrated Circuit) main control unit for burning or reading the SPD information of the tested memory module M. For the DDR5 memory module M, the sideband line function circuit 253 can also read and configure the register information of the PMIC (Power Management Integrated Circuit), such as temperature, voltage, etc.

[0069] Therefore, the sideband line function circuit 253 can be used to burn the SPD information of the tested memory module M before testing. If the tested memory module M has functional or performance defects, the sideband line function circuit 253 can read the SPD information of the tested memory module M, thereby performing HPPR repair on the tested memory module M.

[0070] Specifically, the AC test function module 25 also includes a low-speed function test circuit 252 for HPPR repair. When the tested memory module is subjected to HPPR repair, the interface module 20 is connected to the low-speed function test circuit 252 and the sideband line function circuit 253 .

[0071] The low-speed function test circuit 252 has a memory control unit, which can be used for HPPR repair or other low-speed control functions. When performing HPPR repair of the tested memory module M, the low-speed function test circuit 252 receives the defect information sent by the core control board 3 and performs corresponding HPPR operations according to the defect information.

[0072] like Figure 1 As shown, the core control board 3 is the control and communication unit of the test module. As mentioned above, the core control board 3 includes a communication module 31 and a processor module 32. Specifically, the communication module 31 can be used to receive the working information sent by the host computer 4, and the processor module 32 can enable and configure the corresponding functional circuit according to the working information, or perform the corresponding test business. After completing the test, the communication module 31 can return the test result information to the host computer 4. In this embodiment, the communication module 31 can communicate with the host computer 4 through an Ethernet interface, a USB (Universal Serial Bus) interface or a UART (Universal Asynchronous Receiver / Transmitter) interface.

[0073] Specifically, in this embodiment, the working information includes configuration information and instruction information. The processor module 32 of the core control board 3 receives the configuration information and enables and configures the corresponding circuits in the DC test function module 21 or the AC test function module 25; and receives instruction information and controls the DC test function module 21 or the AC test function module 25 to perform corresponding test tasks.

[0074] The host computer 4 includes a system configuration loading module 41 and a system business function module 42. The system configuration loading module 41 is used to send configuration information to the core control board 3, and the system business function module 42 is used to send instruction information to the core control board 3, and receive and display test result information. Specifically, in this embodiment, the host computer 4 is the information interaction and synchronization unit of the test device, and the host computer 4 can obtain the target business automatically or manually. Furthermore, the system business function module 42 of the host computer 4 can also be used to process and display Bin status and Fail information.

[0075] The testing device also includes a server 5 connected to the host computer 4 , and the server 5 is deployed with a memory information database for storing test result information and model information of the corresponding memory module M; accordingly, the host computer 4 also includes a system automatic synchronization module 43 that communicates with the server 5 .

[0076] The server 5 is a memory information database storage platform. The host computer 4 automatically synchronizes the test result information of the tested memory module M to the server 5. Specifically, the host computer 4 synchronizes the test result information of the DC test and AC test and the PN and SN information of the tested memory module M, i.e., the model information, to the database of the server 5 for management, so as to facilitate the subsequent information tracing. When repairing the HPPR, the server 5 can send the repair information of the defective memory module to the host computer 4.

[0077] Therefore, compared with the prior art, the motherboard in the prior art usually only supports DRAM function and performance testing in AC testing. If the motherboard is used for other AC tests such as SPD burning or HPPR repair, an SPD or HPPR interface is required, and the interface is not public and requires the CPU manufacturer to open the above interface. Alternatively, the dedicated equipment used for DC testing of memory module M usually only supports SPD burning in AC testing, and it is still necessary to replace the test platform when performing other AC tests such as DRAM function, performance testing or HPPR, resulting in a long test time and high test cost; and the dedicated equipment can only test one generation of memory module M. Therefore, the test device of memory module M in the present disclosure can perform AC testing and DC testing on memory module M, and can perform SPD burning, DRAM function performance testing, and HPPR repair in AC testing, and can also perform Contact testing in DC testing, so that there is no need to replace the test platform, and the test cost is low.

[0078] In addition, when the memory module M is subjected to a DC test, an O / S (OPEN / SHORT) situation of any pin may occur; in an AC test, memory particle defects and situations requiring HPPR repair may also occur. In these situations, it is necessary to record the PN (Part Number), SN (Serial Number) and test result information of the memory module M. . However, the automatic upload and synchronization of the test result information cannot be achieved in the prior art. In the technical solution disclosed in the present invention, a network communication is performed between the host computer 4 and the server 5, so that the acquired test result information and the PN / SN information of the tested memory module M are synchronized to the server 5 for management for information tracing, thereby facilitating the user to manage and save the data after the test, and in the event of an AC test error, it is also easier to find the repair information corresponding to the defective memory module.

[0079] The present disclosure also provides a method for testing a memory module M, the method comprising:

[0080] The core control board receives work information;

[0081] When the core control board determines to perform a DC test on the memory module according to the working information, the interface module of the main control board is connected to the DC test function module;

[0082] When the core control board determines to perform an AC test on the memory module according to the working information, the interface module of the main control board is connected to the AC test function module;

[0083] The core control board tests the memory module through the main control board.

[0084] During the test process of the test module of the memory module M, the DC test must be completed before the AC test. If the DC test of the memory module M is not performed or fails, there is a risk of damaging the motherboard. When the DC test fails, it can be repaired by replacing the hardware. When the AC test fails, the software can be repaired by HPPR technology. Therefore, the test method disclosed in the present invention must first perform a DC test, i.e., a Contact test. After the DC test passes, the AC test is performed. If the DC test fails, the hardware of the tested memory module M is replaced for repair. After the AC test is completed, the host computer 4 obtains the test result information of the AC test.

[0085] Furthermore, when the core control board determines to perform a DC test on the memory module based on the working information, after connecting the interface module of the main control board and the DC test function module, it also includes: the I / O expansion circuit in the DC test function module controls the output end of each switching unit and the pin of the memory module to be connected in sequence at different times, and enables the driving source circuit to perform a DC test on the memory module through each pin of the memory module.

[0086] Specifically, they include:

[0087] Connect the output terminal O of each switching unit 2311 to the pin of the memory module M under test in a one-to-one correspondence;

[0088] The input end of one switching unit 2311 is controlled to be connected to the forward voltage source 221 through the I / O expansion circuit 232, and the input ends of other switching units 2311 are grounded;

[0089] Test and obtain the test signal of the corresponding pin;

[0090] The signal processing circuit 24 amplifies and converts the test signal to form test result information, and feeds it back to the host computer 4;

[0091] Repeat the above steps to traverse all pins of memory module M in turn;

[0092] The input end of the switching unit 2311 is connected to the negative voltage source 222, the positive current source 223, and the negative current source 224 in sequence through the I / O expansion circuit 232, and the above steps S32 to S35 are repeated to perform DC tests on the pins of the memory module M respectively, and form test result information for each pin under different driving source circuits 22.

[0093] The DC test control module 21 of the test device in the present disclosure includes the signal processing circuit 24, which can amplify and perform analog-to-digital conversion on the test signal returned by the I / O control circuit 23 in the above-mentioned step of feeding back to the host computer 4, so as to facilitate the core control board 3 and the host computer 4 to receive it.

[0094] After the host computer 4 receives the test result of a pin of the tested memory module M, it compares the test result with the pin threshold of the corresponding model. If the test result is greater than or equal to the SHORT threshold, it is a short circuit; if the test result is less than or equal to the OPEN threshold, it is an open circuit; the test results in other cases are correct.

[0095] Furthermore, since the AC test function module 25 further includes a sideband line function circuit 253, the step of "core control board receiving working information" further includes:

[0096] Insert the memory module M into the interface adapter board 1, and the host computer 4 obtains the model information of the tested memory module M;

[0097] The host computer 4 sends a burning command and burning information to the core control board 3;

[0098] After the core control board 3 obtains the burning command and burning information, it configures and enables the sideband line function circuit 253;

[0099] Connecting the interface module 20 and the sideband line functional circuit 253;

[0100] The sideband line function circuit 253 burns the burning information into the memory module M;

[0101] The burning is completed, and the burning result is fed back to the host computer 4.

[0102] Specifically, the model information of the tested memory module M is the PN and SN information of the tested memory module M. After the burning is completed, the host computer 4 obtains the burning completion result and starts to perform a DC test, namely a Contact test.

[0103] Furthermore, during the AC test, the following steps are specifically included:

[0104] Connecting the interface module 20 of the main control board 2 to the high-speed performance test circuit 251;

[0105] The high-speed performance test circuit 251 performs a high-speed performance test on the memory module M under test;

[0106] Acquire the test result information of the AC test and send it to the host computer 4.

[0107] Furthermore, the test result information of the AC test has two situations: detection passed and detection error. Specifically, if the test result information of the AC test is detection passed, the test of the tested memory module M is completed;

[0108] If the test result information of the AC test is a detection error, HPPR repair is performed. Specifically, the steps of the HPPR repair include:

[0109] The host computer 4 sends a HPPR repair command to the core control board 3;

[0110] The core control board 3 configures and enables the low-speed function test circuit 252 and the sideband line function circuit 253 of the main control board 2;

[0111] Connecting the interface module 20 to the low-speed functional test circuit 252 and the sideband line functional circuit 253;

[0112] The sideband line function circuit 253 obtains the model information of the memory module M and sends it to the host computer 4;

[0113] The host computer 4 searches the database in the server 5 to obtain the repair information of the corresponding memory module M, and sends it to the low-speed function test circuit 252;

[0114] The low-speed functional test circuit 252 performs HPPR repair on the target memory module M;

[0115] The repair is completed and the repair result is fed back to the host computer 4.

[0116] It should be noted that DDR3 memory module M does not support HPPR repair, so when testing DDR3 memory module M, even if the AC test fails, HPPR repair cannot be performed, so the above steps are not included. If the memory module M is DDR4 or DDR5, the above steps can be performed.

[0117] In addition, the testing device further includes a server 5, and the testing method further includes, after the step S8:

[0118] S9: The host computer 4 synchronizes the test result information of the DC test and the AC test and the model information of the tested memory module M to the server 5. Of course, if the tested memory module is repaired by HPPR, the host computer 4 will also upload the repair record to the server 5 after the repair is completed.

[0119] The following describes the test process in detail by taking the DDR5 memory module M as an example.

[0120] 1. Insert the DDR5 memory module M into the socket on the interface adapter board 1, and the host computer 4 obtains the model information of the tested memory module M, such as PN, SN, etc., and prepares for SPD burning;

[0121] 2. The host computer 4 sends the SPD burning command and burning information to the core control board 3. After the core control board 3 obtains the burning command, it configures and enables the sideband line function circuit 253 in the AC test function module 25 of the main control board 2, and connects the interface module 20 to the sideband line function circuit 253. Then, the SPD information is burned into the memory module M through the IIC main control unit in the sideband line function circuit 253. After the burning is completed, the burning completion result information is fed back to the host computer 4;

[0122] 3. After collecting the SPD burning completion result information, the host computer 4 starts the DC test, namely the Contact test;

[0123] 4. The host computer 4 sends a DC test, i.e., a Contact test command, to the core control board 3. After the core control board 3 obtains the working information, it connects the interface module 20 of the main control board 2 with the DC test function module 21, and enables the forward voltage source 221 circuit in the driving source circuit 22 to perform the Contact test;

[0124] 5. The switching unit 2311 corresponding to one pin of the memory module M is controlled by the I / O expansion circuit 232 to switch, and the input end of the switching unit 2311 is connected to the forward voltage source 221, and the switching units 2311 corresponding to the remaining pins of the tested memory module M are all switched and connected to the ground;

[0125] 6. The signal processing circuit 24 amplifies the test signal of the pin, and then feeds it back to the host computer 4 after analog-to-digital conversion;

[0126] 7. The host computer 4 compares the test value of the pin with the threshold of the general pin M of the DDR5 memory module. If it is greater than or equal to the SHORT threshold, it is a short circuit, and if it is less than or equal to the OPEN threshold, it is an open circuit. The rest of the test results are correct;

[0127] 8. Repeat steps 5 to 7, traverse all pins of the memory module M in turn, and all are switched by the I / O expansion circuit 232, and the host computer 4 determines the test result of each pin, so that the contact test of the forward voltage source 221, that is, the DC test, can be completed;

[0128] 9. Then, the core control board 3 sequentially enables the negative voltage source 222, the positive current source 223, and the negative current source 224 in the driving source circuit 22, and performs contact tests according to steps 5 to 8 respectively;

[0129] 10. The host computer 4 counts the test results according to the Contact test conditions of the above four different driving source circuits 22. If an error occurs, the test of the memory module M is terminated, and the PN, SN, Pin information and Contact error information of the memory module M are transmitted to the server 5; if the test passes, the AC test is continued;

[0130] 11. The host computer 4 sends a high-speed performance test command to the core control board 3. After receiving the command, the core control board 3 configures and enables the DDR5 high-speed performance test circuit 251 in the AC test function module 25 of the main control board 2, and connects the interface module 20 to the high-speed performance test circuit 251. The high-speed MC unit in the high-speed performance test circuit 251 performs a high-speed performance test on the memory module M under test, and feeds back the result to the host computer 4 after the test is completed;

[0131] 12. The host computer 4 obtains the function and performance test results of the tested memory module M. If the test passes, the test of the memory module M is completed; if an error occurs during the test, the PN, SN, Bank Group, Bank, Row and DQ information of the memory module M is transmitted to the server 5, and HPPR repair is started;

[0132] 13. The host computer 4 sends the HPPR repair command to the core control board 3. After the core control board 3 obtains the command, it configures and enables the DDR5 low-speed function test circuit 252 and the DDR5 sideband line function circuit 253 in the AC test function module 25 of the main control board 2, and connects the interface module 20 with the low-speed function test circuit 252 and the sideband line function circuit 253; reads the SPD information of the Socket memory module M inserted into the interface adapter board 1 through the IIC main control unit in the sideband line function circuit 253, and feeds back the PN and SN information therein to the host computer 4;

[0133] 14. The host computer 4 retrieves the PN and SN information from the database in the server 5, collects and obtains the Bank Group, Bank, Row and DQ information of the corresponding module, and sends the repair information to the main control board 2; then the memory control unit in the low-speed functional test circuit 252 performs HPPR repair on the target module, and after the repair is completed, the repair result is fed back to the host computer 4;

[0134] 15. The host computer 4 uploads the repair record to the server 5 via the network, thus completing the test of the memory module M.

[0135] Therefore, in summary, firstly, in the present invention, the test device of the memory module M can support both AC test and DC test of the memory module M, and there is no need to replace the test platform during the test process, so the test time is shortened and the cost is low. Secondly, the test device of the memory module M in the present disclosure can perform AC test and DC test on the memory module M, and can perform SPD burning, DRAM functional performance detection, HPPR maintenance in AC test, and can also perform Contact test in DC test, so that the test is more convenient and comprehensive, and a set of test devices can be used to complete the comprehensive detection of the tested memory module M. Finally, in the technical solution of the present disclosure, the host computer 4 and the server 5 are used for network communication, so that the acquired test result information and the PN / SN information of the tested memory module M are synchronized to the server 5 for management, so as to be used for information tracing, so as to facilitate the user to manage and save the data after the test, and when the AC test fails, it is also easier to find the repair information corresponding to the defective memory module.

[0136] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0137] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0138] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

[0139] The above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A memory module testing device, characterized in that: The testing device comprises: An interface adapter board, including a memory interface module, for connecting with different types of memory modules; A main control board, comprising an interface module, a DC test function module and an AC test function module selectively connected to the interface module, wherein the interface module is connected to the interface adapter board; Host computer, used to output work information and obtain test result information; The core control board includes a communication module and a processor module connected to each other. The communication module is connected to the host computer for communication and obtains working information and returns test result information after the test is completed. The processor module is connected to the DC test function module and the AC test function module, and the interface module is configured to be connected to the DC test function module or the AC test function module according to the working information, and obtains the test result information after the test is completed.

2. The testing device according to claim 1, characterized in that: The DC test function module includes a driving source circuit, an I / O control circuit and a signal processing circuit connected in sequence, and the I / O control circuit includes a switch switching circuit; the switch switching circuit includes a plurality of switching units, and the output end of each switching unit is respectively connected to a pin of the memory module.

3. The testing device according to claim 2, characterized in that: The I / O control circuit also includes an I / O expansion circuit, and the selection control end of each of the switching units is connected to the I / O expansion circuit.

4. The testing device according to claim 2, characterized in that: The driving source circuit includes a positive voltage source, a negative voltage source, a positive current source, and a negative current source, and all are connected to the input of each switching unit.

5. The testing device according to claim 1, characterized in that: The AC test function module includes: a high-speed performance test circuit for testing DRAM functions and performance under high-speed conditions; Sideband line function circuit, used to burn or read the SPD information of the memory module and read or configure the register information; During the AC test, the interface module is connected to a high-speed performance test circuit.

6. The testing device according to claim 5, characterized in that: The AC test function module also includes a low-speed function test circuit for HPPR repair. When the memory module is subjected to HPPR repair, the interface module is connected to the low-speed function test circuit and the sideband line function circuit.

7. The testing device according to claim 6, characterized in that: The working information includes configuration information and instruction information, and the processor module receives the configuration information and enables and configures the corresponding circuit in the DC test function module or the AC test function module; and receives the instruction information and controls the DC test function module or the AC test function module to perform the corresponding test task; The host computer includes a system configuration loading module and a system business function module; the system configuration loading module is used to send configuration information to the core control board, and the system business function module is used to send instruction information to the core control board, and receive and display test result information.

8. A method for testing a memory module, characterized in that: The test method includes: The core control board receives work information; When the core control board determines to perform a DC test on the memory module according to the working information, the interface module of the main control board is connected to the DC test function module; When the core control board determines to perform an AC test on the memory module according to the working information, the interface module of the main control board is connected to the AC test function module; The core control board tests the memory module through the main control board.

9. The testing method according to claim 8, characterized in that: When the core control board determines to perform a DC test on the memory module according to the working information, after connecting the interface module of the main control board with the DC test function module, the method further includes: The I / O expansion circuit in the DC test function module controls the output end of each switching unit and the pin of the memory module to be connected in sequence at different times, and enables the driving source circuit to perform DC testing on the memory module through each pin of the memory module.

10. The testing method according to claim 8, characterized in that: The AC test function module includes a sideband line function circuit, and before the step of "core control board receiving working information" further includes: Insert the memory module into the interface adapter board, and the host computer obtains the model information of the tested memory module; The host computer sends the burning command and burning information to the core control board; After the core control board obtains the burning command and burning information, it configures and enables the sideband line function circuit; Connecting the interface module to the sideband line functional circuit; The sideband line function circuit burns the burning information into the memory module; The burning is completed and the burning result is fed back to the host computer.

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