Integrated assembly comprising capacitor and discrete varistor

Abstract

An integrated component may include a multilayer capacitor including a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal. The integrated component may include a discrete varistor including a first external varistor terminal connected to a first active terminal of the multilayer capacitor and a second external varistor terminal connected to a second active terminal of the multilayer capacitor.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the application date of April 17, 2020, application number 202080031059.0, and invention name “Integrated component including a capacitor and a discrete varistor”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 838,410, filed April 25, 2019, which is hereby incorporated by reference in its entirety. Background Art

[0004] For some time, the design of various electronic components has been driven by a general industry trend toward miniaturization and increased functionality. In this regard, there is a need for smaller electronic components with improved operating characteristics. Certain applications would benefit from the equivalence of multiple components, but are severely limited in the amount of space such electronic components may occupy (e.g., on a circuit board).

[0005] Multilayer ceramic devices, such as multilayer ceramic capacitors or varistor, are sometimes composed of multiple dielectric-electrode layers arranged in a stack. During manufacturing, these layers can be pressed and formed into a monolithic stack structure.

[0006] It would therefore be advantageous if devices and corresponding methods could be provided that resulted in improved miniaturization, as well as increased functionality and / or operating characteristics. Summary of the invention

[0007] According to one embodiment of the present invention, an integrated component having capacitor and varistor functions may include a multilayer capacitor including a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal. The integrated component may include a discrete varistor including: a first external varistor terminal connected to the first active terminal of the multilayer capacitor; and a second external varistor terminal connected to the second active terminal of the multilayer capacitor.

[0008] According to another embodiment of the present invention, a method for forming an integrated component having capacitor and varistor functions may include: providing a multilayer capacitor body, the multilayer capacitor body including electrodes forming a pair of capacitors; forming a first active terminal, a second active terminal and at least one ground terminal outside the multilayer capacitor body, so that the pair of capacitors is connected in series between the first active terminal and the second active terminal; and stacking a discrete varistor with the multilayer capacitor body, so that the first varistor terminal of the discrete varistor is connected to the first active terminal, and the second varistor terminal is connected to the second active terminal.

[0009] Other features and aspects of the invention are discussed in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A complete and enabling disclosure of the presently disclosed subject matter, including the best mode of the presently disclosed subject matter, to one of ordinary skill in the art is set forth in the specification with reference to the accompanying drawings, in which:

[0011] Figure 1A shows an external perspective view of an exemplary embodiment of a multi-terminal multilayer device according to the presently disclosed subject matter for use in, for example, an SMD configuration;

[0012] Figure 1B Shows Figure 1A a first electrode layer of a device;

[0013] Figure 1C Shows Figure 1A a second electrode layer of a device;

[0014] Figure 1D Shows Figure 1A A stack-up of alternating first and second electrode layers of a device;

[0015] Figure 1E The device further includes leads connected to corresponding external terminals. Figure 1A Devices;

[0016] Figure 1F yes Figure 1A A schematic diagram of a device;

[0017] Figure 2A and Figure 2B Shown for Figure 1A a device comprising alternating first and second electrode layers, wherein the second electrode layer comprises a T-electrode;

[0018] Figure 2C It shows that Figure 2A and Figure 2B A stack of alternating first and second electrode layers as shown;

[0019] Figure 3A An integrated assembly including a multilayer capacitor and a discrete varistor in a stacked configuration according to the presently disclosed subject matter is shown;

[0020] Figure 3B yes Figure 3A A schematic diagram of a device;

[0021] Figure 3C An external perspective view of another embodiment of an integrated assembly in accordance with the presently disclosed subject matter is shown.

[0022] Figure 4 is a flow chart of a method 400 for forming an integrated component having capacitor and varistor functionality according to aspects of the present disclosure.

[0023] Throughout the present specification and drawings, repeated use of reference numerals is intended to represent the same or analogous features, elements or steps thereof. DETAILED DESCRIPTION

[0024] Now will refer to various embodiments of the present invention in detail, one or more embodiments of the present invention are set forth below. Each embodiment is provided in a manner to explain the present invention rather than to limit the present invention. In fact, it will be apparent to those skilled in the art that various modifications and variations may be made to the present invention without departing from the scope or spirit of the present invention. For example, the features shown or described as a part of one embodiment may be used in another embodiment to produce another embodiment. Therefore, the present invention is intended to encompass such modifications and variations within the scope of the appended claims and their equivalents.

[0025] In general, the present invention relates to an integrated device including a multilayer capacitor and a discrete varistor. Without being limited by theory, a capacitor is an electrical component that stores electrical energy in an electric field. Without being limited by theory, a varistor is an electrical component whose resistance can change with an applied voltage, making it a voltage-dependent resistor.

[0026] The capacitor and varistor combined can provide filtering and EMI and / or EMI / ESD circuit protection in a single package, which may be particularly useful when space is limited. The present invention may be particularly suitable for automotive applications, such as motor start-stop applications.

[0027] The multilayer capacitor of the integrated component may have a split feedthrough type construction and include a first active terminal, a second active terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal. The capacitor may be formed by internal electrodes separated by a dielectric layer.

[0028] The discrete varistor may include: a first external varistor terminal connected to a first active terminal of the multilayer capacitor; and a second external varistor terminal connected to a second active terminal of the multilayer capacitor. For example, the discrete varistor and the multilayer capacitor may be stacked to form a single monolithic integrated component. In some embodiments, leads may be connected to the external terminals and / or the integrated component may be over-molded. Thus, the over-molded layer may encapsulate the discrete varistor and the multilayer capacitor.

[0029] The multilayer capacitor may include at least one ground terminal located outside the ceramic body. A first plurality of electrode layers may be disposed within the body and connected to a first active terminal. A second plurality of electrode layers may be disposed within the body and connected to a second active terminal. A third plurality of electrode layers may be connected to the ground terminal and capacitively coupled to each of the first plurality of electrode layers and the second plurality of electrode layers to form a split feed-through configuration. A first capacitor may be formed at a first overlapping region between the first plurality of electrode layers and the third plurality of electrode layers. A second capacitor may be formed at a second overlapping region between the second plurality of electrode layers and the third plurality of electrode layers.

[0030] In one embodiment, the first capacitor may have a first capacitance, and the second capacitor may have a second capacitance. In some embodiments, the first overlapping area and the second overlapping area may be approximately equal, so that the second capacitance may be approximately equal to the first capacitance. However, in other embodiments, the first overlapping area and the second overlapping area may be different, so that the first capacitance may be greater than or less than the second capacitance.

[0031] For example, at least one of the first capacitance and the second capacitance can be in the range of from about 10 nF to about 3 μF, in some embodiments in the range of from about 200 nF to about 2 μF, and in some embodiments in the range of from about 400 nF to about 1.5 μF. The second capacitance can be in the range of from about 5% to about 500% of the first capacitance, in some embodiments in the range of from about 10% to about 300%, in some embodiments in the range of from about 25% to about 200%, and in some embodiments in the range of from about 50% to about 150%.

[0032] In some embodiments, the third plurality of electrode layers may be generally cross-shaped and may be connected to paired relative ground terminals. For example, the third plurality of electrode layers may each include paired relative edges. One of the relative edges may be connected to a first ground terminal, and another of the relative edges may be connected to a second ground terminal.

[0033] The monolithic body may be free of any additional capacitors formed within the monolithic body. For example, the first plurality of electrodes, the second plurality of electrodes, and the third plurality of electrodes may be arranged in an electrode stack that extends through a majority of the thickness of the monolithic body. For example, the ratio of the thickness of the electrode stack to the thickness of the monolithic body may be in the range of from about 0.5 to about 0.97, in some embodiments in the range of from about 0.6 to about 0.95, and in some embodiments in the range of from about 0.7 to about 0.9.

[0034] In some embodiments, the component can include one or more leads connected to external terminals. For example, the first lead and the second lead can be coupled to the first active terminal and the second active terminal, respectively. The third lead and / or the fourth lead can be coupled to the ground terminal. The component can be overmolded so that the leads protrude from the overmolded package for connecting the component.

[0035] In other embodiments, at least one of the first active terminal, the second active terminal, or the at least one ground terminal can be exposed along the bottom surface of the integrated component for surface mounting the component, such as as a surface mount device (SMD) or using a grid array type mounting (e.g., land grid array (LGA), ball grid array (BGA), etc.).

[0036] Aspects of the present disclosure can simplify the assembly and / or installation of leaded or SMD components by replacing multiple discrete capacitors with a single integrated capacitor device. For example, in an SMD configuration, multiple discrete components are avoided on the PCB, which saves space on the PCB and, in some cases, reduces inductance and / or equivalent series resistance (ESR). In addition, the number of solder joints can be reduced, thereby increasing reliability.

[0037] Generally, the dielectric layer of the multilayer capacitor can be made of any material commonly used in the art. For example, the dielectric layer can be made of a ceramic material including titanate as a main component. Titanate can include but is not limited to barium titanate (BaTiO3). The ceramic material can also contain oxides of rare earth metals and / or compounds of acceptor type elements such as Mn, V, Cr, Mo, Fe, Ni, Cu or Co. Titanate can also contain MgO, CaO, Mn3O4, Y2O3, V2O5, ZnO, ZrO2, Nb2O5, Cr2O3, Fe2O3, P2O5, SrO, Na2O, K2O, Li2O, SiO2 or WO3, etc. In addition to ceramic powder, the ceramic material can also include other additives, organic solvents, plasticizers, adhesives or dispersants, etc.

[0038] Generally, the internal electrodes of multilayer capacitors can be made of any material commonly used in the art. For example, the internal electrodes can be formed by sintering a conductive paste, the main component of which is a precious metal material. These materials may include, but are not limited to, palladium, palladium-silver alloy, nickel and copper. For example, in one embodiment, the electrode can be made of nickel or a nickel alloy. The alloy may contain one or more of Mn, Cr, Co, Al and W, and the Ni content in the alloy is preferably 95% by weight or more. Ni or a Ni alloy may contain various trace components of 0.1% by weight or less, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F and S, etc.

[0039] The ceramic body of the multilayer capacitor may be formed using any method known in the art. For example, the ceramic body may be formed by forming a laminated body having alternately stacked ceramic sheets and patterned internal electrodes; removing a binder from the laminated body; sintering the laminated body from which the binder has been removed in a non-oxidizing atmosphere at a high temperature in the range of 1200° C. to 1300° C.; and re-oxidizing the sintered laminated body in an oxidizing atmosphere.

[0040] Typically, the varistor can be configured to divert the surge to ground. For example, the varistor can have a clamping voltage in the range of from about 3 volts to about 150 volts, in some embodiments in the range of from about 5 volts to about 100 volts, in some embodiments in the range of from about 10 volts to about 50 volts, and in some embodiments in the range of from about 15 volts to about 30 volts.

[0041] The varistor may include a ceramic body having external electrodes. The ceramic body is manufactured by sintering a layered body formed of alternately stacked ceramic layers and internal electrodes. Each pair of adjacent internal electrodes faces each other with a ceramic layer therebetween, and may be electrically coupled to different external electrodes, respectively.

[0042] Typically, the dielectric layer may include any suitable dielectric material, such as barium titanate, zinc oxide, or any other suitable dielectric material. Various additives may be included in the dielectric material, for example, a dielectric material that produces or enhances the varistor of the dielectric material. For example, in some embodiments, the additive may include an oxide of cobalt, bismuth, manganese, or a combination thereof. In some embodiments, the additive may include an oxide of gallium, aluminum, antimony, chromium, boron, titanium, lead, barium, nickel, vanadium, tin, or a combination thereof. The dielectric material may be doped with an additive in the range of from about 0.5 mole percent to about 3 mole percent, and in some embodiments, with an additive in the range of from about 1 mole percent to about 2 mole percent. The average particle size of the dielectric material may contribute to the nonlinear characteristics of the dielectric material. In some embodiments, the average particle size may be in the range of from about 10 microns to 100 microns, and in some embodiments, in the range of from about 20 microns to 80 microns. The varistor may also include two terminals, and each electrode may be connected to a corresponding terminal. The electrode may be provided with a resistor along the length of the electrode and / or at the connection between the electrode and the terminal.

[0043] Generally, the internal electrode can be made of any material commonly used in the art. For example, the internal electrode can be formed by sintering a conductive paste, the main component of which is a precious metal material. These materials may include, but are not limited to, palladium, palladium-silver alloy, silver, nickel and copper. For example, in one embodiment, the electrode can be made of nickel or a nickel alloy. The alloy may contain one or more of Mn, Cr, Co, Al and W, and the Ni content in the alloy is preferably 95% by weight or more. Ni or a Ni alloy may contain various trace components of 0.1% by weight or less, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F and S, etc.

[0044] The integrated assembly can have a variety of sizes. For example, the housing size of the integrated assembly can range from EIA 0504 or smaller to EIA 2920 or larger. Exemplary housing sizes include 0805, 1206, 1806, 2020, etc.

[0045] As described above, in some embodiments, the integrated components may be overmolded using a variety of suitable methods. Examples include silicone rubber, thermoplastic elastomers, or other similar polymers.

[0046] Exemplary embodiments will now be discussed with reference to the drawings. Figure 1AAn external perspective view of an exemplary embodiment of a multi-terminal multilayer device 100 according to the presently disclosed subject matter is shown. As shown, the device 100 may include a body 102, such as a hexagonal body. The device 100 may include a first end terminal 104, a second end terminal 106, a first side terminal 108, and a second side terminal 110. All such external terminals are typically present on a designated bottom side 112 of the device 100 for use, for example, in a surface mount device (SMD) configuration.

[0047] The device 100 may include two formed capacitors connected in series between two of the first terminal 104 and the second terminal 106. As will be understood by one of ordinary skill in the art with respect to all embodiments described herein, the cooperating layers in the subject multilayer constructions include electrode layers that in turn form an integrated capacitive structure.

[0048] Figure 1B Shows Figure 1A The first electrode layer 120 of the device 100. The electrode arrangement 120 may include a cross-shaped electrode 122 having a first side terminal 108 and a second side terminal 110 ( Figure 1A ) are connected to a pair of opposing edges 124, 126. Figure 1C A second electrode layer 128 is shown and includes a first electrode 130 connected to the first end terminal 104 and a second electrode 132 connected to the second end terminal 106 . Figure 1D An electrode stack 133 is shown of alternating first electrode layers 120 and second electrode layers 128. It will be appreciated that the electrode stack 133 may include any suitable number of electrode layers 120, 128.

[0049] Refer again Figure 1B The cross-shaped electrode 122 may overlap the first electrode 130 along a first overlapping region 134 to form a first capacitor, and may overlap the second electrode 132 along a second overlapping region 136 to form a second capacitor.

[0050] In some embodiments, the monolithic body 102 ( Figure 1A ) in the monolithic body 102 ( Figure 1A ) may not have any additional capacitors (except the first capacitor and the second capacitor). Figure 1D The electrode stack 133 depicted may extend through the monolithic body 102 in a Z direction 140 perpendicular to the electrodes 122, 130, 132 ( Figure 1A) of the majority thickness 138. For example, a ratio of a thickness 142 of the electrode stack 133 in the Z direction 140 to a thickness 138 of the monolithic body 102 can be in a range from about 0.4 to about 0.97.

[0051] Figure 1E A perspective view of another embodiment of a device 100 according to aspects of the present application is shown. Figure 1A , a lead configuration is added. More specifically, leads 148, 150, and 152 are attached to external terminals 104, 108, and 106, respectively. Leads 148 and 152 may constitute first and second leads attached to the first pair of terminals 104 and 106, respectively, while lead 150 may constitute a third lead attached to at least one of the second pair of terminals 108 and 110. One of ordinary skill in the art will also appreciate that both terminals 108 and 110 are connected to layer 122, such that lead 150 may be connected to such terminals 108 or 110 with the same circuit result. Application Figure 1C The final configuration is an overmolded three-lead assembly.

[0052] Figure 1F Shows the application Figure 1A Schematic diagram of a device 100 in its connected / mounted configuration (as indicated by an application Figure 1C More specifically, leads 148, 150, and 152 are shown as being in contact with the series capacitor and the parallel capacitor, respectively. The indicated capacitance values ​​are intended to be exemplary only and not limiting.

[0053] As shown, device 100 provides a single device solution for containing a series capacitor and a parallel capacitor. A first capacitor 154 can be formed between a cross-shaped electrode 122 and a first electrode 130 at a first overlapping region 134. A second capacitor 156 can be formed between a cross-shaped electrode 122 and a second electrode 132 at a second overlapping region 136. The first overlapping region 134 can be approximately equal to the second overlapping region 136, so that the first capacitor and the second capacitor present an approximate capacitance. However, in other embodiments, the first overlapping region 134 can be greater than or less than the second overlapping region 136, so that the first capacitance can be greater than or less than the second capacitance. One or both of the first capacitance and the second capacitance can be in the range from about 10nF to about 3μF.

[0054] Figure 2A and Figure 2B 2 shows an electrode configuration according to another embodiment of the present disclosure. The first electrode layer 220 may include a cross-shaped electrode 222 having a first side terminal 108 and a second side terminal 110 ( Figure 1A ) are connected to a pair of opposite edges 224, 226. Figure 1C106. A second electrode layer 228 is shown, which includes a first electrode 230 connected to the first end terminal 104 and a second electrode 232 connected to the second end terminal 106. The first electrode 230 and / or the second electrode 232 may be T-electrodes, such that the electrodes 230, 232 extend to side edges 235, 237 of the electrode layer 227 and are connected to the respective end terminals 104, 106 ( Figure 1A )connect.

[0055] Figure 2C An electrode stack 233 is shown of alternating first electrode layers 220 and second electrode layers 228. The electrode stack 233 may have a thickness 242 in the Z-direction 140.

[0056] The thickness 242 of the electrode stack 233 in the Z direction 140 is equal to that of the monolithic body 102 ( Figure 1A )'s thickness 138 may be in the range of about 0.4 to about 0.97.

[0057] Refer again Figure 2A The cross-shaped electrode 222 may overlap the first electrode 230 along a first overlapping region 234 , and may overlap the second electrode 232 along a second overlapping region 236 .

[0058] Figure 3A An external perspective view of an exemplary embodiment of a multi-terminal multilayer device 600, generally in accordance with the presently disclosed subject matter, is shown for use in a stacked configuration with a varistor device 660 having corresponding additional leads 648, 650, and 652, as shown. As further discussed herein, Figure 3B Shows the application Figure 3A Schematic diagram of an exemplary embodiment 600 of .

[0059] The varistor 660 may have external varistor terminals 662, 664. A lead configuration arrangement may be used to place the device 600 and the varistor 660 in parallel relative to each other. More specifically, the leads 648, 650, and 652 may be attached to the external (capacitor device) terminals 604, 608, and 606 of the device 600, respectively, while the leads 648 and 652 are connected to the external (varistor) terminals 662 and 664 of the varistor 660, respectively, as shown. Applications Figure 3A The final configuration can be overmolded.

[0060] Figure 3B The application is generally shown Figure 3A Schematic diagram of an exemplary embodiment 600 of the present invention, which is in its connected / installed configuration (as shown by the application Figure 3A648, 650, and 652 are shown as being in contact with a series capacitor and a parallel capacitor, respectively. The indicated capacitance values ​​are intended to be exemplary only and not limiting. A varistor 660 is also in contact with leads 648 and 652 as shown so as to be in parallel relation with the device 600. The indicated varistor characteristics are intended to be exemplary only and not limiting.

[0061] Figure 3C A perspective view of an integrated component having capacitor and varistor functionality according to aspects of the present disclosure is shown. In general, Figure 3C Shown in another perspective Figure 3A For example, Figure 3C The embodiment of the present invention provides the device 600 (e.g., a multilayer ceramic device) on the bottom and the varistor 660 on the top. Such a configuration can allow the device 600 and the varistor 660 to be used as a surface mount device after being combined together, for example, by welding. In addition, as Figure 3C The embodiment shown does not Figure 3A However, it should be understood that when in this configuration, wire leads may also be employed.

[0062] As shown, device 600 provides a single device solution for containing both series capacitors and shunt capacitors. Device 600 shows two representative capacitors 654 and 656, such as may be formed by a split feed-through configuration of multiple layers in an isolated region of device 600.

[0063] Although various sizes can be practiced for any of the exemplary embodiments disclosed herein, device 600 and varistor 660 can be considered representative of standard MLC case sizes, such as 1206 case size. Of course, various sizes can be practiced in various embodiments as needed or desired for a particular application. All such variations and changes in exemplary capacitance values ​​are intended to be consistent with the spirit and scope of the presently disclosed subject matter.

[0064] As shown in the present disclosure, for some embodiments used in SMD arrangements, the presently disclosed subject matter can result in the replacement of multiple discrete components on a printed circuit board (PCB), thereby saving space and, in some cases, reducing inductance. All of these presently disclosed exemplary embodiments can be used in some of their uses by being packaged in an overmolded three-lead assembly. According to the presently disclosed subject matter, a significant reduction in device size is obtained, which results in a reduction in the number of solder joints, which correspondingly increases reliability.

[0065] Figure 4 is a flow chart of a method 400 for forming an integrated component having capacitor and varistor functionality according to aspects of the present disclosure. Figures 1A to 3CThe method 400 is described with reference to the integrated components 100, 200 described herein. However, it should be understood that the disclosed method 400 may be implemented with any suitable integrated components. In addition, although for purposes of illustration and discussion, Figure 4 The steps performed in a particular order are depicted, but the methods discussed herein are not limited to any particular order or arrangement. Using the disclosure provided herein, those skilled in the art will appreciate that the various steps of the methods disclosed herein may be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of the present disclosure.

[0066] The method 400 may include, at (402), providing a multilayer capacitor body of a split feed-through configuration, the multilayer capacitor body including electrodes forming a pair of capacitors, such as described above with reference to Figures 1A to 3C As described.

[0067] The method may include: at (404), forming a first active terminal and a second active terminal outside the multilayer capacitor body such that the paired capacitors are connected in series between the first active terminal and the second active terminal, for example as described above with reference to Figures 1A to 3C As described.

[0068] The method may include, at (406), stacking a discrete varistor with the multilayer capacitor body such that a first varistor terminal of the discrete varistor is connected to the first active terminal and a second varistor terminal is connected to the second active terminal.

[0069] It should be understood that the various steps for implementing the disclosed configurations are intended only as a representation of the present disclosure and do not represent the desired use of other aspects beyond the general nature of the present disclosure, otherwise indicated in other ways. For example, one of ordinary skill in the art will recognize that the selected steps can be practiced to produce a specific design selected for a given application of the presently disclosed subject matter.

[0070] Example

[0071] According to an exemplary embodiment of the present disclosure, the integrated assembly has a first capacitor and a second capacitor, each capacitor exhibiting approximately 475 nF. The integrated assembly includes a discrete varistor having a clamping voltage of approximately 22 volts.

[0072] According to an exemplary embodiment of the present disclosure, an integrated assembly has a first capacitor and a second capacitor, each of which exhibits approximately 685 nF. The integrated assembly includes a discrete varistor having a clamping voltage of approximately 22 volts.

[0073] According to another exemplary embodiment of the present disclosure, an integrated assembly has a first capacitor and a second capacitor, each of which exhibits approximately 1 μF. The integrated assembly includes a discrete varistor having a clamping voltage of approximately 22 volts.

[0074] Test Method

[0075] The following sections provide example methods for testing varistors to determine various characteristics of multilayer ceramic capacitors, discrete capacitors, and / or integrated components.

[0076] The clamping voltage of a rheostat may be measured using a Keithley 2400 Series Source Measure Unit (SMU), such as a Keithley 2410-C SMU. The rheostat may be subjected to an 8 / 20 μs current wave, such as in accordance with ANSI Standard C62.1. The current wave may have a peak current value of 1 mA. The peak current value may be selected so that the peak current causes the rheostat to "clamp" the voltage. The current may increase to the peak current value and then decay. The "rise" time period may be from the start of the current pulse to when the current reaches 90% of the peak current value. The "rise" time may be 8 μs. The "decay time" may be from the start of the current pulse to 50% of the peak current value. The "decay time" may be 20 μs. The clamping voltage is measured as the maximum voltage across the rheostat during the current wave.

[0077] The capacitance of the multilayer capacitor can be measured using a Keithley 2400 Series Source Measure Unit (SMU), such as a Keithley 2410-C SMU. For example, a first capacitance of a first capacitor can be measured between ground and a first external terminal of the multilayer capacitor. A second capacitance of a second capacitor can be measured between ground and a second external terminal of the multilayer capacitor.

[0078] Although the present disclosed subject matter has been described in detail with reference to the specific embodiments of the present disclosed subject matter, it should be understood that those skilled in the art can easily make changes, variations and equivalences to these embodiments after understanding the above content. Therefore, the scope of the present disclosure is to be taken as an example rather than as a limitation, and the present subject disclosure does not exclude such modifications, variations and / or additions to the present disclosed subject matter, which are obvious to those of ordinary skill in the art.

Claims

1. An integrated component, comprising: A multilayer capacitor comprising a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal, the multilayer capacitor further comprising: a body comprising a plurality of dielectric layers; a first plurality of electrode layers disposed within the body and connected to the first active terminal; a second plurality of electrode layers disposed within the body and connected to the second active terminal; and a third plurality of electrode layers connected to the at least one ground terminal and capacitively coupled to each of the first plurality of electrode layers and the second plurality of electrode layers to form a first capacitor of the pair of capacitors between the first plurality of electrode layers and the third plurality of electrode layers and a second capacitor of the pair of capacitors between the second plurality of electrode layers and the third plurality of electrode layers; and a discrete varistor comprising a first external varistor terminal connected to the first active terminal of the multilayer capacitor and a second external varistor terminal connected to the second active terminal of the multilayer capacitor; wherein the first plurality of electrode layers and the second plurality of electrode layers are T-electrodes, such that side edges of the first plurality of electrode layers are connected to the first active terminal, and side edges of the second plurality of electrode layers are connected to the second active terminal; wherein the third plurality of electrode layers overlap with the first plurality of electrode layers along a first overlapping region; wherein the third plurality of electrode layers overlaps the second plurality of electrode layers along a second overlapping region different from the first overlapping region, such that the first capacitor of the pair of capacitors has a first capacitance and the second capacitor of the pair of capacitors has a second capacitance different from the first capacitance; and The second capacitance is in a range from 5% to 500% of the first capacitance except 100%.

2. The integrated assembly according to claim 1, wherein: The third plurality of electrode layers is generally cross-shaped.

3. The integrated assembly according to claim 1, wherein: The at least one ground terminal includes a first ground terminal and a second ground terminal.

4. The integrated assembly according to claim 3, wherein: Each of the third plurality of electrode layers includes a pair of opposing edges, one of the opposing edges being connected to the first ground terminal, and the other of the opposing edges being connected to the second ground terminal.

5. The integrated assembly according to claim 3, wherein: The first ground terminal is opposite to the second ground terminal.

6. The integrated assembly according to claim 1, wherein: At least one of the first capacitance or the second capacitance is in a range from 10 nF to 3 μF.

7. The integrated assembly according to claim 1, wherein: The second capacitance is in a range from 50% to 150% of the first capacitance except 100%.

8. The integrated assembly according to claim 1, wherein: The discrete varistor has a clamping voltage in the range of 15 volts to 30 volts.

9. The integrated assembly according to claim 1, wherein: The plurality of dielectric layers, the first plurality of electrode layers, and the second plurality of electrode layers are stacked to form an electrode stack, and a ratio of a thickness of the electrode stack to a thickness of the body is greater than 0.

4.

10. A method for forming an integrated assembly, the method comprising: providing a multilayer capacitor body including electrodes forming a first capacitor and a second capacitor; forming a first active terminal, a second active terminal, and at least one ground terminal on the exterior of the multilayer capacitor body; stacking a discrete varistor with the multilayer capacitor body, the discrete varistor comprising a first varistor terminal and a second varistor terminal; and coupling a first lead to the first active terminal and the first varistor terminal, coupling a second lead to the second active terminal and the second varistor terminal, and coupling a third lead to the at least one ground terminal, Wherein, the multilayer capacitor body comprises: a first plurality of electrode layers disposed within the multilayer capacitor body and connected to the first active terminal; a second plurality of electrode layers disposed within the multilayer capacitor body and connected to the second active terminal; and a third plurality of electrode layers connected to the at least one ground terminal and capacitively coupled to each of the first plurality of electrode layers and the second plurality of electrode layers to form the first capacitor between the first plurality of electrode layers and the third plurality of electrode layers and to form the second capacitor between the second plurality of electrode layers and the third plurality of electrode layers; wherein the first plurality of electrode layers and the second plurality of electrode layers are T-electrodes, such that side edges of the first plurality of electrode layers are connected to the first active terminal, and side edges of the second plurality of electrode layers are connected to the second active terminal; wherein the third plurality of electrode layers overlap with the first plurality of electrode layers along a first overlapping region; wherein the third plurality of electrode layers overlaps the second plurality of electrode layers along a second overlapping region different from the first overlapping region, such that the first capacitor has a first capacitance and the second capacitor has a second capacitance different from the first capacitance; and The second capacitance is in a range from 5% to 500% of the first capacitance except 100%.

11. The method according to claim 10, wherein: Forming the at least one ground terminal includes forming a first ground terminal and a second ground terminal.

12. The method according to claim 11, wherein: The first ground terminal is opposite to the second ground terminal.

13. The method according to claim 10, wherein: The third plurality of electrode layers is generally cross-shaped.

14. The method according to claim 11, wherein: Each of the third plurality of electrode layers includes a pair of opposing edges, one of the opposing edges is connected to the first ground terminal, and the other of the opposing edges is connected to the second ground terminal.

15. The method according to claim 10, wherein: At least one of the first capacitance or the second capacitance is in a range from 10 nF to 3 μF.

16. The method according to claim 10, wherein: The second capacitance is in a range from 50% to 150% of the first capacitance except 100%.

17. The method according to claim 10, wherein: A plurality of dielectric layers, the first plurality of electrode layers, and the second plurality of electrode layers are stacked to form an electrode stack, and a ratio of a thickness of the electrode stack to a thickness of the body is in a range of 0.95 to 0.97.

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