Semiconductor integrated circuit wafer test optimization method and system

Abstract

The invention discloses a semiconductor integrated circuit wafer test optimization method and system, and relates to the technical field of semiconductor device testing, and the method comprises the steps: employing a multi-point probe array to make contact with a plurality of test points on a wafer to be tested, so as to collect initial electrical performance data in parallel; analyzing the collected initial electrical performance data so as to evaluate the performance of the integrated circuit of each area on the wafer to be tested; scanning the surface of the wafer to be detected by using a resolution imaging system; extracting a test feature matrix of the image of the integrated circuit of each area on the wafer to be tested; adjusting the number and layout of the probes of the multi-point probe array; based on the test characteristic matrix, the fitting value of the integrated circuit of each area on the to-be-tested wafer and the reference electrical performance data, obtaining the deviation of the to-be-tested wafer; and when the deviation meets the first threshold range, determining that the wafer to be detected is qualified, otherwise, determining that the wafer to be detected is unqualified.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device testing technology, and in particular to a semiconductor integrated circuit wafer testing optimization method and system. Background Art

[0002] In the manufacturing process of semiconductor integrated circuits, wafer testing is a crucial link. Wafer testing refers to the electrical performance test of each bare chip on the semiconductor wafer before the wafer is cut. Its purpose is to detect defective chips and ensure that bad chips are picked out before packaging to improve the yield rate. Wafer testing ensures that the electrical performance of each chip can be accurately evaluated before the chip is packaged. Wafer testing can detect bad chips in the early production stage, prevent unqualified chips from entering subsequent processes, reduce packaging costs and testing time, and maximize economic benefits and efficiency. In addition, wafer testing can also improve product quality, which is crucial to improving the reliability and performance of end products.

[0003] However, in the prior art, due to the limitations of the wafer testing method and the structure of the wafer testing device itself, the accuracy of the wafer testing results is low.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor integrated circuit wafer testing optimization method and system to solve the above-mentioned technical problems.

[0006] The present application provides a semiconductor integrated circuit wafer test optimization method, comprising: A multi-point probe array is used to contact multiple test points on the wafer to be tested to collect preliminary electrical performance data in parallel; Wherein, the probes of the multi-point probe array have an adjustable loading force; Analyzing the collected preliminary electrical performance data to evaluate the performance of the integrated circuits in various regions on the wafer to be tested, and obtaining preliminary electrical performance evaluation data; Scanning the surface of the wafer to be tested using a high-resolution imaging system to identify images of integrated circuits in various regions on the wafer to be tested; Extracting a test feature matrix of an image of an integrated circuit in each area on the wafer to be tested; Adjusting the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested, and the test feature matrix; Using the adjusted multi-point probe array to contact multiple test points on the wafer to be tested to collect reference electrical performance data in parallel; Calculating fitting values ​​of integrated circuits in various regions on the wafer to be tested based on the reference electrical performance data and a test feature matrix of images of integrated circuits in various regions on the wafer to be tested; Obtaining a deviation of the wafer to be tested based on the test characteristic matrix, the fitting values ​​of the integrated circuits in each area on the wafer to be tested and the reference electrical performance data; When the deviation satisfies a first threshold range, the wafer to be tested is qualified; otherwise, the wafer to be tested is unqualified.

[0007] Further, adjusting the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix includes: Based on a two-dimensional reference coordinate system, the coordinates of the grains corresponding to the integrated circuits in each area on the wafer to be tested are determined; wherein the grains corresponding to the integrated circuits in each area on the wafer to be tested are one or more grains on which the integrated circuits are distributed; the two-dimensional reference coordinate system uses a preset position on the outer edge of the wafer to be tested as a coordinate origin; Determine the pixel points corresponding to the coordinates of the crystal grains corresponding to the integrated circuits in each area on the wafer to be tested according to the coordinates of the crystal grains corresponding to the integrated circuits in each area on the wafer to be tested, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix; Determine a test correlation matrix according to the pixel points corresponding to the coordinates of the dies corresponding to the integrated circuits in each area on the wafer to be tested; wherein the test correlation matrix reflects the test correlation between each pixel point; The number and layout of the probes of the multi-point probe array are adjusted according to the test correlation matrix, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test characteristic matrix.

[0008] Furthermore, the values ​​of the pixel points corresponding to the coordinates of the crystal grains corresponding to the integrated circuits in each region on the wafer to be tested are the test feature vectors of the crystal grains corresponding to the integrated circuits in each region.

[0009] Further, adjusting the number and layout of the probes of the multi-point probe array according to the test correlation matrix, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test characteristic matrix includes: Encode the number and layout of probes into chromosomes ; A set of possible probe layouts is randomly generated as the initial population; A fitness function is defined; wherein the fitness function is used to determine the score of each probe layout; Design constraint conditions; wherein the constraint conditions are used to limit the generated probe layout to not exceed the size limit of the wafer to be tested; Selection operation: Use the tournament selection algorithm to select chromosomes with scores greater than the screening score threshold according to the scores determined by the fitness function. Participate in the generation of the next generation; Mutation operation: using the test feature matrix to guide the process of the mutation operation; Iterate the selection operation, the crossover operation and the mutation operation until a maximum number of iterations is reached, and output the optimal probe layout solution at this time; The number and layout of the probes of the multi-point probe array are adjusted according to the test correlation matrix and the optimal probe layout scheme.

[0010] Furthermore, the resolution imaging system includes: an optical microscope lens for magnifying the surface image of the wafer to be tested; an image processing unit for analyzing the surface image of the wafer to be tested and identifying the images of integrated circuits in various regions on the wafer to be tested; Wherein, the imaging resolution of the resolution imaging system is between 60 nanometers and 200 nanometers.

[0011] Furthermore, when the wafer to be tested is qualified, a thermal simulation test is performed on the chip on the wafer to be tested using three-dimensional modeling and simulation technology to predict and optimize the performance of the chip under actual working conditions; wherein the chip is composed of multiple integrated circuits.

[0012] The present application provides a semiconductor integrated circuit wafer test optimization system, including a preliminary test unit, a preliminary electrical performance evaluation unit, an integrated circuit image acquisition unit, a multi-point probe array optimization unit, a reference electrical performance data acquisition unit, an integrated circuit fitting value calculation unit, and a wafer qualification judgment unit; The preliminary test unit is used to contact multiple test points on the wafer to be tested using a multi-point probe array to collect preliminary electrical performance data in parallel; wherein the probes of the multi-point probe array have an adjustable loading force; The preliminary electrical performance evaluation unit is used to analyze the collected preliminary electrical performance data to evaluate the performance of the integrated circuits in various regions on the wafer to be tested, and obtain preliminary electrical performance evaluation data; The integrated circuit image acquisition unit is used to scan the surface of the wafer to be tested using a high-resolution imaging system to identify images of integrated circuits in various regions on the wafer to be tested; and extract a test feature matrix of the images of integrated circuits in various regions on the wafer to be tested; The multi-point probe array optimization unit is used to adjust the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix; The reference electrical performance data acquisition unit uses an adjusted multi-point probe array to contact multiple test points on the wafer to be tested to collect reference electrical performance data in parallel; The integrated circuit fitting value calculation unit is used to calculate the fitting value of the integrated circuit in each area on the wafer to be tested based on the reference electrical performance data and the test feature matrix of the image of the integrated circuit in each area on the wafer to be tested; The wafer qualification judgment unit is used to obtain the deviation of the wafer to be tested based on the test feature matrix, the fitting values ​​of the integrated circuits in each area on the wafer to be tested and the reference electrical performance data; when the deviation meets the first threshold range, the wafer to be tested is qualified, otherwise, the wafer to be tested is unqualified.

[0013] Further, the multi-point probe array optimization unit adjusts the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix, and is configured as follows: Based on a two-dimensional reference coordinate system, the coordinates of the grains corresponding to the integrated circuits in each area on the wafer to be tested are determined; wherein the grains corresponding to the integrated circuits in each area on the wafer to be tested are one or more grains on which the integrated circuits are distributed; the two-dimensional reference coordinate system uses a preset position on the outer edge of the wafer to be tested as a coordinate origin; Determine the pixel points corresponding to the coordinates of the crystal grains corresponding to the integrated circuits in each area on the wafer to be tested according to the coordinates of the crystal grains corresponding to the integrated circuits in each area on the wafer to be tested, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix; Determine a test correlation matrix according to the pixel points corresponding to the coordinates of the dies corresponding to the integrated circuits in each area on the wafer to be tested; wherein the test correlation matrix reflects the test correlation between each pixel point; The number and layout of the probes of the multi-point probe array are adjusted according to the test correlation matrix, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test characteristic matrix.

[0014] Furthermore, the semiconductor integrated circuit wafer test optimization system also includes: The thermal simulation test unit is used to perform a thermal simulation test on the chip on the wafer to be tested using three-dimensional modeling and simulation technology when the wafer to be tested is qualified, so as to predict and optimize the performance of the chip under actual working conditions; wherein the chip is composed of multiple integrated circuits.

[0015] Based on the embodiments provided by the present application, a multi-point probe array is used to contact multiple test points on a wafer to be tested to collect preliminary electrical performance data in parallel; wherein the probes of the multi-point probe array have an adjustable loading force; the collected preliminary electrical performance data are analyzed to evaluate the performance of the integrated circuits in various regions on the wafer to be tested to obtain preliminary electrical performance evaluation data; a high-resolution imaging system is used to scan the surface of the wafer to be tested to identify images of the integrated circuits in various regions on the wafer to be tested; a test feature matrix of the images of the integrated circuits in various regions on the wafer to be tested is extracted; and based on the preliminary electrical performance evaluation data, the wafer to be tested, the test feature matrix of the integrated circuits in various regions on the wafer to be tested is extracted; and the test feature matrix of the integrated circuits in various regions on the wafer to be tested is extracted. The number and layout of the probes of the multi-point probe array are adjusted according to the size of the circle and the test feature matrix; the adjusted multi-point probe array is used to contact multiple test points on the wafer to be tested to collect reference electrical performance data in parallel; based on the reference electrical performance data and the test feature matrix of the image of the integrated circuits in each area of ​​the wafer to be tested, the fitting values ​​of the integrated circuits in each area of ​​the wafer to be tested are calculated; based on the test feature matrix, the fitting values ​​of the integrated circuits in each area of ​​the wafer to be tested and the reference electrical performance data, the deviation of the wafer to be tested is obtained; when the deviation meets the first threshold range, the wafer to be tested is qualified, otherwise, the wafer to be tested is unqualified. Thereby, the efficiency of wafer testing and the accuracy of wafer test results are improved to improve the quality of semiconductor integrated circuits and wafer products; the test efficiency can be improved while ensuring the detection quality, providing the semiconductor manufacturing industry with a more powerful and flexible detection method to cope with increasingly complex detection challenges.

[0016] Specifically, it has the following beneficial effects: a multi-point probe array is used to contact multiple test points on the wafer to be tested. This method can collect preliminary electrical performance data in parallel, thereby improving test efficiency and comprehensiveness of data. The probes of the multi-point probe array have adjustable loading forces, which means that the strength of the probes can be adjusted according to the characteristics of the test points, so as to obtain more accurate test results; the collected preliminary electrical performance data is analyzed to evaluate the performance of the integrated circuits in various regions on the wafer to be tested, and preliminary electrical performance evaluation data is obtained; this analysis can identify performance problems of the circuit and provide a basis for subsequent optimization; the surface of the wafer to be tested is scanned using a resolution imaging system to identify the images of the integrated circuits in various regions on the wafer to be tested; this high-resolution imaging technology can provide clear images, which is helpful for subsequent feature extraction and analysis; based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix, the number and layout of the probes of the multi-point probe array are adjusted; this adjustment can optimize the probe layout according to the actual characteristics of the wafer and the test requirements, and further improve the accuracy and efficiency of the test; the adjusted multi-point probe array is used to contact multiple test points on the wafer to be tested to collect reference electrical performance evaluation data in parallel; this re-testing can verify the effect of the probe layout adjustment and provide more accurate data; based on the reference electrical performance evaluation data and the test feature matrix of the images of the integrated circuits in various regions on the wafer to be tested, the fitting values ​​of the integrated circuits in various regions on the wafer to be tested are calculated. Fitted values ​​are the predicted values ​​of the regression calculated by applying the regression coefficients to the explanatory variables. This step helps to assess the accuracy of the test data. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the embodiments of the present invention and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A flowchart of an optional semiconductor integrated circuit wafer test optimization method according to an embodiment of the present application; Figure 2 A structural diagram of an optional semiconductor integrated circuit wafer test optimization system according to an embodiment of the present application.

[0018] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0020] Alternatively, if Figure 1As shown, the present application provides a semiconductor integrated circuit wafer test optimization method, comprising: S101, using a multi-point probe array to contact multiple test points on the wafer to be tested to collect preliminary electrical performance data in parallel; wherein the probes of the multi-point probe array have an adjustable loading force; S102, analyzing the collected preliminary electrical performance data to evaluate the performance of the integrated circuits in various regions on the wafer to be tested, and obtaining preliminary electrical performance evaluation data; S103, scanning the surface of the wafer to be tested using a resolution imaging system to identify images of integrated circuits in various regions on the wafer to be tested; S104, extracting a test feature matrix of the image of the integrated circuit in each area on the wafer to be tested; S105, adjusting the number and layout of probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested, and the test feature matrix; S106, using the adjusted multi-point probe array to contact multiple test points on the wafer to be tested to collect reference electrical performance data in parallel; S107, calculating fitting values ​​of integrated circuits in various regions on the wafer to be tested based on the reference electrical performance data and the test feature matrix of the images of the integrated circuits in various regions on the wafer to be tested; S108, obtaining a deviation of the wafer to be tested based on the test characteristic matrix, the fitting values ​​of the integrated circuits in each area on the wafer to be tested, and the reference electrical performance data; S109, when the deviation meets the first threshold range, the wafer to be tested is qualified, otherwise, the wafer to be tested is unqualified.

[0021] Based on the embodiments provided by the present application, a multi-point probe array is used to contact multiple test points on a wafer to be tested to collect preliminary electrical performance data in parallel; wherein the probes of the multi-point probe array have an adjustable loading force; the collected preliminary electrical performance data are analyzed to evaluate the performance of the integrated circuits in various regions on the wafer to be tested to obtain preliminary electrical performance evaluation data; a high-resolution imaging system is used to scan the surface of the wafer to be tested to identify images of the integrated circuits in various regions on the wafer to be tested; a test feature matrix of the images of the integrated circuits in various regions on the wafer to be tested is extracted; and based on the preliminary electrical performance evaluation data, the wafer to be tested, the test feature matrix of the integrated circuits in various regions on the wafer to be tested is extracted; and the test feature matrix of the integrated circuits in various regions on the wafer to be tested is extracted. The number and layout of the probes of the multi-point probe array are adjusted according to the size of the circle and the test feature matrix; the adjusted multi-point probe array is used to contact multiple test points on the wafer to be tested to collect reference electrical performance data in parallel; based on the reference electrical performance data and the test feature matrix of the image of the integrated circuits in each area of ​​the wafer to be tested, the fitting values ​​of the integrated circuits in each area of ​​the wafer to be tested are calculated; based on the test feature matrix, the fitting values ​​of the integrated circuits in each area of ​​the wafer to be tested and the reference electrical performance data, the deviation of the wafer to be tested is obtained; when the deviation meets the first threshold range, the wafer to be tested is qualified, otherwise, the wafer to be tested is unqualified. Thereby, the efficiency of wafer testing and the accuracy of wafer test results are improved to improve the quality of semiconductor integrated circuits and wafer products; the test efficiency can be improved while ensuring the detection quality, providing the semiconductor manufacturing industry with a more powerful and flexible detection method to cope with increasingly complex detection challenges.

[0022] Specifically, it has the following beneficial effects: a multi-point probe array is used to contact multiple test points on the wafer to be tested. This method can collect preliminary electrical performance data in parallel, which improves test efficiency and data comprehensiveness. The probes of the multi-point probe array have adjustable loading force, which means that the strength of the probes can be adjusted according to the characteristics of the test points to obtain more accurate test results; the collected preliminary electrical performance data is analyzed to evaluate the performance of the integrated circuits in various areas on the wafer to be tested, and preliminary electrical performance evaluation data is obtained; this analysis can identify performance problems of the circuit and provide a basis for subsequent optimization; a high-resolution imaging system is used to scan the surface of the wafer to be tested to identify the images of the integrated circuits in various areas on the wafer to be tested; this high-resolution imaging technology can provide clear images, which is helpful for subsequent feature extraction and analysis; and a test feature matrix of the images of the integrated circuits in various areas on the wafer to be tested is extracted. The test feature matrix contains key parameters and features, which are crucial for subsequent data analysis and fitting value calculation; based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix, the number and layout of the probes of the multi-point probe array are adjusted; this adjustment can optimize the probe layout according to the actual characteristics of the wafer and the test requirements, and further improve the accuracy and efficiency of the test; the adjusted multi-point probe array is used to contact multiple test points on the wafer to be tested to collect reference electrical performance evaluation data in parallel; this re-test can verify the effect of the probe layout adjustment and provide more accurate data; based on the reference electrical performance evaluation data and the test feature matrix of the image of the integrated circuits in each area on the wafer to be tested, the fitting values ​​of the integrated circuits in each area on the wafer to be tested are calculated. The fitting value refers to the predicted value of the regression calculated by applying the regression coefficient to the explanatory variable. This step helps to evaluate the accuracy of the test data.

[0023] Further, based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix, the number and layout of the probes of the multi-point probe array are adjusted, including: Based on a two-dimensional reference coordinate system, the coordinates of the grains corresponding to the integrated circuits in each area on the wafer to be tested are determined; wherein the grains corresponding to the integrated circuits in each area on the wafer to be tested are one or more grains on which the integrated circuits are distributed; and the two-dimensional reference coordinate system uses a preset position at the outer edge of the wafer to be tested as a coordinate origin; Determine the pixel points corresponding to the coordinates of the dies corresponding to the integrated circuits in each region on the wafer to be tested according to the coordinates of the dies corresponding to the integrated circuits in each region on the wafer to be tested, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix; Determine a test correlation matrix according to the pixel points corresponding to the coordinates of the dies corresponding to the integrated circuits in each area on the wafer to be tested; wherein the test correlation matrix reflects the test correlation between each pixel point; Adjust the number and layout of the probes of the multi-point probe array according to the test correlation matrix, the preliminary electrical performance evaluation data, the size of the wafer to be tested, and the test feature matrix.

[0024] Further, the value of the pixel corresponding to the coordinate of the die corresponding to the integrated circuit in each area on the wafer to be tested is the test feature vector of the die corresponding to the integrated circuit in each area; ; wherein, is the test feature vector of the die corresponding to the integrated circuit in each area; are the coordinates of the die corresponding to the integrated circuit in each area on the wafer to be tested; is the number of test features, and the test features include electrical performance features; is the th function of the electrical performance feature, based on the characteristic definition of the th electrical performance feature, represents the evaluation value of the th electrical performance feature on .

[0025] Further, adjust the number and layout of the probes of the multi-point probe array according to the test correlation matrix, the preliminary electrical performance evaluation data, the size of the wafer to be tested, and the test feature matrix, including: Encode the number and layout of the probes into a chromosome ; Randomly generate a set of possible probe layouts as the initial population; Define the fitness function; wherein, the fitness function is used to determine the score of each probe layout; Design the constraint conditions; wherein, the constraint conditions are used to limit that the generated probe layout does not exceed the size limit of the wafer to be tested; Selection operation: Use the tournament selection algorithm to select the chromosomes with scores greater than the screening score threshold according to the scores determined by the fitness function to participate in the generation of the next generation; Crossover operation: Use the single-point crossover method to generate the probe layout; wherein, in the single-point crossover method, the parental chromosomes are the encoded representations of the probe layout; let the two parental chromosomes be and ; is the gene value of at the nth position; is the gene value of at the nth position; Select a crossover point c according to the test correlation matrix and the test feature matrix, 1 < c < n; obtain the offspring chromosomes through the following formula and : ; ; Wherein, during the crossover operation, if two parent probe layouts show a correlation greater than a correlation threshold in the test correlation matrix, the two parent probe layouts are retained; Mutation operation: The process of using the test feature matrix to guide the mutation operation; The selection operation, crossover operation and mutation operation are iterated and repeated until the maximum number of iterations is reached, and the optimal probe layout scheme at this time is output; According to the test correlation matrix and the optimal probe layout plan, the number and layout of the probes of the multi-point probe array are adjusted.

[0026] Further, ; in, Chromosome The fitness function of Test coverage is used to characterize the coverage of the probe layout for electrical performance feature testing; is the threshold value of the number of probes; It is the preliminary electrical performance evaluation data; To test the escape rate; is the parameter volatility; is spatial correlation; is the corresponding weight coefficient, which is used to balance the importance of different factors.

[0027] Further, the resolution imaging system includes: an optical microscope lens for magnifying the surface image of the wafer to be tested; an image processing unit for analyzing the surface image of the wafer to be tested and identifying the images of the integrated circuits in various regions on the wafer to be tested; Among them, the imaging resolution of the resolution imaging system is between 60 nanometers and 200 nanometers.

[0028] Furthermore, when the wafer to be tested is qualified, a thermal simulation test is performed on the chip on the wafer to be tested using three-dimensional modeling and simulation technology to predict and optimize the performance of the chip under actual working conditions; wherein the chip is composed of multiple integrated circuits.

[0029] Alternatively, if Figure 2 As shown, the present application provides a semiconductor integrated circuit wafer test optimization system, including a preliminary test unit 201, a preliminary electrical performance evaluation unit 202, an integrated circuit image acquisition unit 203, a multi-point probe array optimization unit 204, a reference electrical performance data acquisition unit 205, an integrated circuit fitting value calculation unit 206 and a wafer qualified judgment unit 207; The preliminary test unit 201 is used to contact multiple test points on the wafer to be tested using a multi-point probe array to collect preliminary electrical performance data in parallel; wherein the probes of the multi-point probe array have an adjustable loading force; A preliminary electrical performance evaluation unit 202 is used to analyze the collected preliminary electrical performance data to evaluate the performance of the integrated circuits in various regions on the wafer to be tested, and obtain preliminary electrical performance evaluation data; The integrated circuit image acquisition unit 203 is used to scan the surface of the wafer to be tested using a resolution imaging system to identify the image of the integrated circuits in each area on the wafer to be tested; and extract the test feature matrix of the image of the integrated circuits in each area on the wafer to be tested; The multi-point probe array optimization unit 204 is used to adjust the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test characteristic matrix; The reference electrical performance data acquisition unit 205 uses the adjusted multi-point probe array to contact multiple test points on the wafer to be tested to collect reference electrical performance data in parallel; The integrated circuit fitting value calculation unit 206 is used to calculate the fitting value of the integrated circuit of each area on the wafer to be tested based on the reference electrical performance data and the test feature matrix of the image of the integrated circuit of each area on the wafer to be tested; The wafer qualification judgment unit 207 is used to obtain the deviation of the wafer to be tested based on the test feature matrix, the fitting values ​​of the integrated circuits in each area on the wafer to be tested and the reference electrical performance data; when the deviation meets the first threshold range, the wafer to be tested is qualified, otherwise, the wafer to be tested is unqualified.

[0030] Furthermore, the multi-point probe array optimization unit adjusts the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test characteristic matrix, and is configured as follows: Based on a two-dimensional reference coordinate system, the coordinates of the grains corresponding to the integrated circuits in each area on the wafer to be tested are determined; wherein the grains corresponding to the integrated circuits in each area on the wafer to be tested are one or more grains on which the integrated circuits are distributed; and the two-dimensional reference coordinate system uses a preset position at the outer edge of the wafer to be tested as a coordinate origin; Determine the pixel points corresponding to the coordinates of the dies corresponding to the integrated circuits in each region on the wafer to be tested according to the coordinates of the dies corresponding to the integrated circuits in each region on the wafer to be tested, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix; Determine a test correlation matrix according to the pixel points corresponding to the coordinates of the dies corresponding to the integrated circuits in each area on the wafer to be tested; wherein the test correlation matrix reflects the test correlation between each pixel point; The number and layout of the probes of the multi-point probe array are adjusted according to the test correlation matrix, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test characteristic matrix.

[0031] Furthermore, the semiconductor integrated circuit wafer test optimization system also includes: The thermal simulation test unit is used to perform thermal simulation testing on the chip on the wafer to be tested using three-dimensional modeling and simulation technology when the wafer to be tested is qualified, so as to predict and optimize the performance of the chip under actual working conditions; wherein the chip is composed of multiple integrated circuits.

[0032] It should be noted that in the present application, the embodiments implemented on the semiconductor integrated circuit wafer test optimization system side can be cross-referenced with the embodiments implemented on the semiconductor integrated circuit wafer test optimization method side, and the present application will not describe them one by one.

[0033] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A semiconductor integrated circuit wafer test optimization method, characterized in that: include: A multi-point probe array is used to contact multiple test points on the wafer to be tested to collect preliminary electrical performance data in parallel; wherein the probes of the multi-point probe array have an adjustable loading force; Analyzing the collected preliminary electrical performance data to evaluate the performance of the integrated circuits in various regions on the wafer to be tested, and obtaining preliminary electrical performance evaluation data; Scanning the surface of the wafer to be tested using a high-resolution imaging system to identify images of integrated circuits in various regions on the wafer to be tested; Extracting a test feature matrix of an image of an integrated circuit in each area on the wafer to be tested; Adjusting the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested, and the test feature matrix; Using the adjusted multi-point probe array to contact multiple test points on the wafer to be tested to collect reference electrical performance data in parallel; Calculating fitting values ​​of integrated circuits in various regions on the wafer to be tested based on the reference electrical performance data and a test feature matrix of images of integrated circuits in various regions on the wafer to be tested; Obtaining a deviation of the wafer to be tested based on the test characteristic matrix, the fitting values ​​of the integrated circuits in each area on the wafer to be tested and the reference electrical performance data; When the deviation satisfies a first threshold range, the wafer to be tested is qualified; otherwise, the wafer to be tested is unqualified.

2. The semiconductor integrated circuit wafer test optimization method according to claim 1, characterized in that: The adjusting the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix includes: Based on a two-dimensional reference coordinate system, the coordinates of the grains corresponding to the integrated circuits in each area on the wafer to be tested are determined; wherein the grains corresponding to the integrated circuits in each area on the wafer to be tested are one or more grains on which the integrated circuits are distributed; the two-dimensional reference coordinate system uses a preset position on the outer edge of the wafer to be tested as a coordinate origin; Determine the pixel points corresponding to the coordinates of the crystal grains corresponding to the integrated circuits in each area on the wafer to be tested according to the coordinates of the crystal grains corresponding to the integrated circuits in each area on the wafer to be tested, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix; Determine a test correlation matrix according to the pixel points corresponding to the coordinates of the dies corresponding to the integrated circuits in each area on the wafer to be tested; wherein the test correlation matrix reflects the test correlation between each pixel point; The number and layout of the probes of the multi-point probe array are adjusted according to the test correlation matrix, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test characteristic matrix.

3. The semiconductor integrated circuit wafer test optimization method according to claim 2, characterized in that: The values ​​of the pixel points corresponding to the coordinates of the crystal grains corresponding to the integrated circuits in each area on the wafer to be tested are the test feature vectors of the crystal grains corresponding to the integrated circuits in each area.

4. The semiconductor integrated circuit wafer test optimization method according to claim 3, characterized in that: The step of adjusting the number and layout of the probes of the multi-point probe array according to the test correlation matrix, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix comprises: Encode the number and layout of probes into chromosomes ; A set of possible probe layouts is randomly generated as the initial population; A fitness function is defined; wherein the fitness function is used to determine the score of each probe layout; Design constraint conditions; wherein the constraint conditions are used to limit the generated probe layout to not exceed the size limit of the wafer to be tested; Selection operation: Use the tournament selection algorithm to select chromosomes with scores greater than the screening score threshold according to the scores determined by the fitness function. Participate in the creation of the next generation.

5. The semiconductor integrated circuit wafer test optimization method according to claim 4, characterized in that: Mutation operation: using the test feature matrix to guide the process of the mutation operation; Iterate the selection operation, the crossover operation and the mutation operation until a maximum number of iterations is reached, and output the optimal probe layout solution at this time; The number and layout of the probes of the multi-point probe array are adjusted according to the test correlation matrix and the optimal probe layout scheme.

6. The semiconductor integrated circuit wafer test optimization method according to claim 1, characterized in that: The resolution imaging system includes: an optical microscope lens for magnifying the surface image of the wafer to be tested; an image processing unit for analyzing the surface image of the wafer to be tested and identifying the images of integrated circuits in various regions on the wafer to be tested; Wherein, the imaging resolution of the resolution imaging system is between 60 nanometers and 200 nanometers.

7. The semiconductor integrated circuit wafer test optimization method according to claim 1, characterized in that: When the wafer to be tested is qualified, a thermal simulation test is performed on the chip on the wafer to be tested using three-dimensional modeling and simulation technology to predict and optimize the performance of the chip under actual working conditions; wherein the chip is composed of multiple integrated circuits.

8. A semiconductor integrated circuit wafer test optimization system, the system implementing the semiconductor integrated circuit wafer test optimization method according to claim 1, characterized in that: It includes a preliminary test unit, a preliminary electrical performance evaluation unit, an integrated circuit image acquisition unit, a multi-point probe array optimization unit, a reference electrical performance data acquisition unit, an integrated circuit fitting value calculation unit and a wafer qualification judgment unit; wherein, The preliminary test unit is used to use a multi-point probe array to contact multiple test points on the wafer to be tested to collect preliminary electrical performance data in parallel; wherein the probes of the multi-point probe array have an adjustable loading force; The preliminary electrical performance evaluation unit is used to analyze the collected preliminary electrical performance data to evaluate the performance of the integrated circuits in various regions on the wafer to be tested, and obtain preliminary electrical performance evaluation data; The integrated circuit image acquisition unit is used to scan the surface of the wafer to be tested using a high-resolution imaging system to identify images of integrated circuits in various regions on the wafer to be tested; and extract a test feature matrix of the images of integrated circuits in various regions on the wafer to be tested; The multi-point probe array optimization unit is used to adjust the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix; The reference electrical performance data acquisition unit uses an adjusted multi-point probe array to contact multiple test points on the wafer to be tested to collect reference electrical performance data in parallel; The integrated circuit fitting value calculation unit is used to calculate the fitting value of the integrated circuit in each area on the wafer to be tested based on the reference electrical performance data and the test feature matrix of the image of the integrated circuit in each area on the wafer to be tested; The wafer qualification judgment unit is used to obtain the deviation of the wafer to be tested based on the test feature matrix, the fitting values ​​of the integrated circuits in each area on the wafer to be tested and the reference electrical performance data; when the deviation meets the first threshold range, the wafer to be tested is qualified, otherwise, the wafer to be tested is unqualified.

9. The semiconductor integrated circuit wafer test optimization system according to claim 8, characterized in that: The multi-point probe array optimization unit adjusts the number and layout of the probes of the multi-point probe array based on the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix, and is configured as follows: Based on a two-dimensional reference coordinate system, the coordinates of the grains corresponding to the integrated circuits in each area on the wafer to be tested are determined; wherein the grains corresponding to the integrated circuits in each area on the wafer to be tested are one or more grains on which the integrated circuits are distributed; the two-dimensional reference coordinate system uses a preset position on the outer edge of the wafer to be tested as a coordinate origin; Determine the pixel points corresponding to the coordinates of the crystal grains corresponding to the integrated circuits in each area on the wafer to be tested according to the coordinates of the crystal grains corresponding to the integrated circuits in each area on the wafer to be tested, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test feature matrix; Determine a test correlation matrix according to the pixel points corresponding to the coordinates of the dies corresponding to the integrated circuits in each area on the wafer to be tested; wherein the test correlation matrix reflects the test correlation between each pixel point; The number and layout of the probes of the multi-point probe array are adjusted according to the test correlation matrix, the preliminary electrical performance evaluation data, the size of the wafer to be tested and the test characteristic matrix.

10. The semiconductor integrated circuit wafer test optimization system according to claim 8, characterized in that: The semiconductor integrated circuit wafer test optimization system further includes: The thermal simulation test unit is used to perform a thermal simulation test on the chip on the wafer to be tested using three-dimensional modeling and simulation technology when the wafer to be tested is qualified, so as to predict and optimize the performance of the chip under actual working conditions; wherein the chip is composed of multiple integrated circuits.

Images