SOI structure and preparation method thereof

Abstract

The invention provides an SOI structure and a preparation method thereof, and the method comprises the steps: providing a first substrate, and forming a low-resistance layer on a first surface of the first substrate; a second substrate is provided, the second substrate comprises a semiconductor layer located on the surface layer of the second substrate, and an insulating layer is formed on the semiconductor layer; forming an insulating layer on one of the low-resistance layer and the semiconductor layer, and overlapping the first substrate and the second substrate by bonding the other one of the low-resistance layer and the semiconductor layer with the insulating layer; a portion of the second substrate away from the insulating layer is removed to transfer the insulating layer and the semiconductor layer onto the first substrate. According to the preparation method of the SOI structure, after the porous material layer is formed in a wet etching mode, the low-resistance layer of the single-crystal semiconductor material or the polycrystalline semiconductor material is manufactured, the porous material layer has large resistivity, and the low-resistance layer is far away from the substrate layer and is separated from the interface of the porous material layer; the pinning effect of the porous material layer on free carriers can be exerted, and the influence of an electric leakage path is also avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to an SOI structure and a preparation method thereof. Background Art

[0002] Radio Frequency (RF) devices need to maintain high signal transmission efficiency and low signal loss, and the substrate material around the RF devices needs to have good insulation properties. Therefore, a large number of RF devices and systems are made on semiconductor-on-insulator (SOI) substrates.

[0003] In SOI substrates for RF applications, the substrate layer near the device area needs to be kept in a high-resistance state to avoid large energy loss in the substrate caused by RF signals. However, since the insulating layer of the SOI substrate usually contains a certain amount of positive charge, when the insulating layer contacts the substrate layer, it can attract electrons in the substrate layer and make the attracted electrons enriched at the interface where the substrate layer and the insulating layer contact, forming a better conductive path, resulting in large RF signal loss. In some cases, the electromagnetic field of the high-frequency signal may even penetrate the substrate and cause electrical performance problems such as crosstalk and parasitic capacitance. Figure 1 A schematic structural diagram of a typical high-resistivity SOI substrate is provided.

[0004] Figure 1 It is a typical structural diagram of a high resistivity SOI substrate. Figure 1 As shown, the high resistivity SOI substrate includes a trap rich layer (Trap rich layer) inserted between the substrate layer 1 and the buried oxide layer 23, usually a trap rich polysilicon layer 22 is used. There are a large number of grain boundaries in the trap rich polysilicon layer 22, which can pin the free carriers in the parasitic surface conductive layer of the high resistance silicon, thereby reducing the energy loss of the transmission line and the crosstalk of the signal between the devices.

[0005] Nevertheless, when the high resistivity SOI substrate is used for the integration of RFSOI devices and FDSOI devices, Figure 3a and Figure 3b Displayed as based on Figure 1 The cross-sectional structure diagram of the FDSOI device made of the high resistivity SOI substrate shown in the figure has the following shortcomings:

[0006] 1) Poor compatibility: Figure 2 The structure diagram of the system-level chip with integrated RF front-end module based on RFSOI technology is shown as follows: Figure 2As shown, the thickness of the buried oxide layer in the high resistivity SOI substrate is usually greater than 400 nm, while the buried oxide layer in the FDSOI substrate is usually thinner, generally around 20 nm.

[0007] 2) If Figure 3a The SOI substrate shown in the figure is doped on the back plane of the device to form a P-type well region, an N-type well region and other structures in the trap-rich polysilicon layer 22 to apply a back gate bias. However, under a DC bias, there is a leakage path between the trap-rich polysilicon layer 22 where the P-type well region, the N-type well region and other structures are located and the high-resistance silicon substrate. It is found that a buried oxide layer 24 can be additionally inserted between the trap-rich polysilicon layer 22 and the substrate layer 1, as shown in FIG. Figure 3b The SOI substrate shown is used to suppress the leakage current between the FD-SOI back plane and the substrate, but the introduction of the buried oxide layer weakens the pinning effect of the trap-rich polysilicon layer to a certain extent.

[0008] 3) The crystal orientation of polysilicon is difficult to control: the lower uniformity of the back gate may lead to inconsistent device threshold voltage.

[0009] Therefore, there is an urgent need to find a new SOI structure and a preparation method thereof. Summary of the invention

[0010] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an SOI structure and a preparation method thereof, which are used to solve the problems that when the existing high-resistivity SOI substrate is used to integrate RFSOI devices and FDSOI devices, there is a trap-rich layer between the buried oxide layer and the substrate layer, such as a polysilicon layer, and the introduction of the trap-rich polysilicon layer is incompatible with the back gate modulation layer in the FDSOI device, which is manifested in that while improving the isolation of the substrate, a leakage channel will be introduced at the interface of the high-resistance substrate, and there is a significant difference in the thickness of the buried oxide layer required for RF SOI devices and fully depleted SOI devices.

[0011] To achieve the above object and other related objects, the present invention provides a method for preparing an SOI structure, comprising the following steps:

[0012] Providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, wherein the porous material layer is formed to extend inwardly from the first surface of the first substrate, and a low resistance layer is formed on the first surface of the first substrate;

[0013] Providing a second substrate, wherein the second substrate includes a semiconductor layer located on a surface thereof;

[0014] forming an insulating layer on one of the low-resistance layer and the semiconductor layer, and stacking the first substrate and the second substrate by bonding the other of the low-resistance layer and the semiconductor layer to the insulating layer;

[0015] removing a portion of the second substrate away from the insulating layer to transfer the insulating layer and the semiconductor layer onto the first substrate, wherein the semiconductor layer serves as a top functional layer;

[0016] The material of the low resistance layer includes heavily doped polycrystalline semiconductor material or single crystal semiconductor material.

[0017] Optionally, the step of forming the porous material layer based on the first substrate includes:

[0018] The substrate layer is partially or completely transformed into a porous structure by a wet etching method; or,

[0019] A wet etching process or a dry etching process is used to form a gap extending from the surface of the substrate layer to the inside; then, the gap is filled with nanocrystalline particles.

[0020] Optionally, the step of forming the porous material layer based on the first substrate includes: growing a polycrystalline material on the substrate layer, selectively etching the polycrystalline material to form a porous structure; and passivating the porous structure.

[0021] Optionally, the step of forming the low-resistance layer includes: growing an epitaxial material layer on the porous material layer through an epitaxial process; wherein the material of the epitaxial material layer includes a single crystal semiconductor material or a polycrystalline semiconductor material, and the epitaxial material layer is heavily doped while or after forming the epitaxial material layer.

[0022] Optionally, after the step of passivating the porous structure, the following steps are included:

[0023] Thinning the exposed surface of the porous material layer to reveal the semiconductor lattice structure in the porous material layer;

[0024] An insulating layer is formed on the passivated porous material layer, and the insulating layer is manufactured by thin film deposition, thin film bonding, thin film transfer, and oxidation.

[0025] Optionally, the second substrate is selected as a semiconductor substrate, and a preset stripping interface is defined in the semiconductor substrate; by stripping a portion of the semiconductor substrate along the preset stripping interface, the insulating layer and the semiconductor layer are transferred to the first substrate, and the semiconductor layer retained on the insulating layer serves as a top functional layer.

[0026] The present invention also provides a method for preparing an SOI structure, comprising the following steps:

[0027] Providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, wherein the porous material layer is formed to extend inwardly from the first surface of the first substrate, and a low resistance layer is formed on the first surface of the first substrate;

[0028] Providing a second substrate, wherein the second substrate comprises a semiconductor layer located on a surface thereof, and forming an insulating layer on the semiconductor layer;

[0029] forming an amorphous material layer on one of the insulating layer and the low-resistance layer, and stacking the first substrate and the second substrate by bonding the other of the insulating layer and the low-resistance layer to the amorphous material layer;

[0030] removing a portion of the second substrate away from the insulating layer to transfer the insulating layer and the semiconductor layer onto the first substrate, wherein the semiconductor layer serves as a top functional layer;

[0031] Recrystallize the amorphous material layer and transform the amorphous material therein into a polycrystalline material;

[0032] The material of the low resistance layer includes heavily doped polycrystalline semiconductor material or single crystal semiconductor material.

[0033] Optionally, after the step of forming the insulating layer, the step includes: forming an amorphous material layer on the insulating layer, the material of the amorphous material layer is selected to be an amorphous semiconductor material; by bonding the amorphous material layer and the low-resistance layer, the first substrate and the second substrate are stacked; wherein, through a heating annealing process, the amorphous semiconductor material between the insulating layer and the low-resistance layer is recrystallized into a polycrystalline semiconductor material.

[0034] Optionally, after the step of forming the insulating layer, the step includes: forming an amorphous material layer on the low-resistance layer, the material of the amorphous material layer is selected to be an amorphous semiconductor material; by bonding the amorphous material layer and the insulating layer, the first substrate and the second substrate are stacked; wherein, through a heating annealing process, the amorphous semiconductor material between the insulating layer and the low-resistance layer is recrystallized into a polycrystalline semiconductor material.

[0035] Optionally, the step of forming the low-resistance layer includes: growing an epitaxial material layer on the insulating layer through an epitaxial process, wherein the material of the epitaxial material layer is a single crystal semiconductor material or a polycrystalline semiconductor material; and heavily doping the epitaxial material layer while or after forming the epitaxial material layer.

[0036] The present invention also provides a method for preparing an SOI structure, characterized in that it comprises the following steps:

[0037] Providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, wherein the porous material layer is formed to extend inwardly from the first surface of the first substrate, and a low resistance layer is formed on the first surface of the first substrate;

[0038] Providing a second substrate, wherein the second substrate comprises a semiconductor layer located on a surface thereof, and forming an insulating layer and a low-resistance layer on the semiconductor layer;

[0039] forming an amorphous material layer on one of the porous material layer and the low-resistance layer, and stacking the first substrate and the second substrate by bonding the other of the porous material layer and the low-resistance layer to the amorphous material layer;

[0040] removing a portion of the second substrate away from the insulating layer to transfer the insulating layer and the semiconductor layer onto the first substrate, wherein the semiconductor layer serves as a top functional layer;

[0041] Recrystallize the amorphous material layer and transform the amorphous material therein into a polycrystalline material;

[0042] The material of the low resistance layer includes heavily doped polycrystalline semiconductor material or single crystal semiconductor material.

[0043] On the other hand, the present invention provides an SOI structure, comprising a substrate layer, a porous material layer, an insulating layer and a top functional layer stacked from bottom to top, a low-resistance layer is inserted between the porous material layer and the insulating layer, the material of the low-resistance layer comprises a heavily doped single crystal semiconductor material or a polycrystalline semiconductor material, and at least one insulating layer and one top functional layer are arranged on the surface of the low-resistance layer away from the substrate layer.

[0044] Optionally, a first insulating layer is sandwiched between the porous material layer and the low-resistance layer, a second insulating layer is provided on a surface of the low-resistance layer away from the porous material layer, and a thickness of the second insulating layer is 1 nm-300 nm.

[0045] Optionally, the SOI structure further includes a patterned region, in which the low-resistance layer, the insulating layer and the top functional layer located on the porous material layer are removed.

[0046] Optionally, it is used to manufacture an integrated structure of FD-SOI devices and RF-SOI devices.

[0047] As described above, the SOI substrate and the method for preparing the same according to the present invention have the following beneficial effects:

[0048] The preparation method of the SOI structure provided by the present invention forms a porous material layer by a wet etching method, and then manufactures a low-resistance layer of a single crystal semiconductor material or a polycrystalline semiconductor material. The porous material layer has a large resistivity, and the low-resistance layer is far away from the interface between the substrate layer and the porous material layer. The porous material layer can not only exert the pinning effect of the free carriers in the parasitic surface conductive layer of the substrate layer, but also avoid the influence of the leakage path. The above-mentioned preparation method has the advantages of low manufacturing cost, short manufacturing cycle, high process consistency, etc., can realize mass production, can meet the production needs of the production line, and has high industrial utilization value.

[0049] The SOI structure provided by the present invention introduces a low-resistance layer between a porous material layer and an insulating layer. The material of the low-resistance layer includes a heavily doped single crystal semiconductor material or a polycrystalline semiconductor material. The porous material layer has a higher resistance and a stronger carrier pinning ability, thereby reducing the energy loss of the transmission line and the crosstalk of signals between devices. In addition, the SOI structure is applied to the co-integration of RF-SOI and FDSOI. A back gate modulation layer is manufactured based on the low-resistance layer. The low-resistance layer can be made of a heavily doped single crystal semiconductor material to ensure the adjustment ability of the back gate and improve the threshold voltage consistency of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 Shown is a typical structural schematic diagram of a high-resistivity SOI substrate.

[0051] Figure 2 Shown is a schematic diagram of the structure of a system-level chip with an integrated RF front-end module based on RFSOI technology.

[0052] Figure 3a to Figure 3b Based on Figure 1 Schematic diagram of a fully depleted SOI device with a high resistivity SOI substrate is shown.

[0053] Figures 4a to 4e It is a schematic diagram showing the structure obtained at each stage in the preparation process of the SOI structure in the first embodiment of the present invention using SOI as the second substrate.

[0054] Figure 5a to Figure 5e It is a schematic diagram showing the structure obtained at each stage in the preparation process of the SOI structure in the first embodiment of the present invention using a semiconductor substrate as the second base.

[0055] Figures 6a to 6f It is a schematic diagram showing the structure obtained at each stage of another example of the preparation process of the SOI structure in the first embodiment of the present invention using SOI as the second substrate.

[0056] Figures 7a to 7c It is a schematic diagram showing the structure obtained at each stage of the method for preparing the SOI structure in the second embodiment of the present invention.

[0057] Figures 8a to 8e It is a schematic diagram showing the structure obtained at each stage of the method for preparing the SOI structure in the third embodiment of the present invention.

[0058] Figures 9a to 9d It is a schematic diagram showing the structures obtained at each stage of another example of the method for preparing the SOI structure in the third embodiment of the present invention.

[0059] Figures 10a to 10f It is a schematic diagram showing the structure obtained at each stage of the method for preparing the SOI structure in the fourth embodiment of the present invention.

[0060] Fig.11 Shown is a schematic diagram of the SOI structure in Embodiment 4 of the present invention.

[0061] Component number description

[0062] 1. Substrate layer

[0063] 22 Trap-rich polysilicon layer

[0064] 22a Back gate modulation layer

[0065] 23, 24 Oxygen Buried Layer

[0066] 3 Top functional layer

[0067] 41 Source

[0068] 42 Drain

[0069] 21 Back gate lead electrode

[0070] 5. Gate electrode

[0071] 6 Isolation Structure

[0072] 100 First substrate

[0073] 10. Substrate layer

[0074] 210 porous material layer

[0075] 220 First insulation layer

[0076] 230 Low resistance layer

[0077] 300 Insulation

[0078] 40 Semiconductor substrate

[0079] 400 Top functional layer

[0080] 500 Insulation

[0081] 2300 Second insulation layer

[0082] 11 SOI substrate

[0083] 1300, 3300, 4300 Insulation layer

[0084] 1400 Semiconductor layer

[0085] 2410, 3410, 4410, 5410 preset stripping interface

[0086] 2400, 3400, 4400 semiconductor substrate

[0087] 5300 Insulation buried layer

[0088] 5400 Backing

[0089] 230a Amorphous material layer DETAILED DESCRIPTION

[0090] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0091] See also Figures 1 to 11 . It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0092] Embodiment 1

[0093] In order to enhance the isolation effect of the substrate and avoid the introduction of leakage channels at the interface of the high-resistance substrate to meet high-frequency applications, the present invention provides a method for preparing an SOI structure, comprising the following steps:

[0094] S110: providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, the porous material layer being formed to extend inwardly from the first surface of the first substrate, and forming a low-resistance layer on the first surface of the first substrate;

[0095] S120: providing a second substrate, wherein the second substrate includes a semiconductor layer located on a surface thereof, and forming an insulating layer on the semiconductor layer;

[0096] S130: stacking the first substrate and the second substrate by bonding the side of the first substrate on which the low-resistance layer is formed to the insulating layer;

[0097] S140: removing a portion of the second substrate away from the insulating layer to transfer the insulating layer and the semiconductor layer to the first substrate, with the semiconductor layer serving as a top functional layer.

[0098] It should be noted that the above sequence does not strictly represent the execution sequence of the method for preparing the SOI structure protected by the present invention, and those skilled in the art may change the sequence of steps according to the actual process.

[0099] First, step S110 is performed to provide a first substrate, wherein the first substrate has a first surface and a second surface relative to each other, and a low-resistance layer is formed on the first surface of the first substrate. The first substrate includes a first substrate and a porous material layer formed based on the first substrate, and the porous material layer is formed to extend inward from the first surface of the first substrate.

[0100] Specifically, the first base includes a first substrate 100, and a porous material layer 210 is formed based on the first substrate 100. The material of the first substrate 100 can be selected from single crystal semiconductor materials or polycrystalline semiconductor materials. For example, the material of the first substrate 100 is selected from silicon, germanium, Si x Ge 1-x .

[0101] See also Figures 4a to 4e , which is a schematic diagram showing the structures obtained at each stage in the preparation process of the SOI structure using SOI as the second substrate. Figure 4a As shown, a low resistance layer 230 is formed on the first surface of the first substrate.

[0102] At step S110, the step of forming the porous material layer 210 based on the first substrate includes: performing a wet etching process or a dry etching process to form a gap extending from the surface of the first substrate to the inside; filling the gap with nanocrystalline particles. In some cases, some of the gaps are formed to penetrate the substrate layer. Similar to porous materials, nanocrystalline materials have higher resistivity, lower fixed charge density, are less likely to attract electrons in the substrate layer, and have lower loss to radio frequency signals.

[0103] In this embodiment, the steps of forming the nanocrystalline material by a sol-gel method include: filling the gap with a solution containing nanocrystalline particles; then, volatilizing the solvent by a heating annealing process, leaving the nanocrystalline particles, the insulating dielectric material wrapping the nanocrystalline particles, and the pore structure to form the porous material layer.

[0104] Alternatively, the step of forming the porous material layer 210 includes: using a wet etching method, such as an electrochemical etching method, to partially or completely transform the first substrate into a porous structure.

[0105] Furthermore, after the step of partially or completely converting the first substrate into a porous structure, the method further includes: performing a passivation treatment on the porous structure to form a passivation structure coated on the porous structure, so that the obtained porous material has a stable morphology and stable physical and chemical properties. For example, the passivation treatment is performed by one or more of oxidation treatment, nitridation treatment, carbonization treatment, heteroepitaxial process, physical vapor deposition process, chemical vapor deposition process, chemical etching process, and electrochemical etching process.

[0106] In other examples, the step of forming the porous material layer 210 based on the first substrate 100 includes: growing a polycrystalline material on the first substrate by an epitaxial process; transforming the polycrystalline material and forming the porous material layer 210 by the following process includes: selectively etching the polycrystalline material to form a porous structure distributed along the grain boundary; wherein the polycrystalline material is selected from one of the following groups, or a mixture thereof: a semiconductor element or semiconductor compound of the IV main group, such as silicon, germanium, Si x Ge 1-x , SiC; or, semiconductor compounds of the III-V main group, such as binary compounds of the III-V main group, ternary compounds of the II-VI or III-V groups, and quaternary compounds of the II-VI or III-V groups. Since the polycrystalline material contains a crystal structure with irregular crystal orientation, a porous structure is formed by selective etching, and the thickness and pore size of the porous material layer can be flexibly adjusted according to the application scenario of the resulting SOI structure and its required electrical properties, such as different radio frequency properties such as substrate loss, effective resistivity, harmonic distortion, etc.

[0107] Furthermore, after the step of selectively etching the polycrystalline material, the method further includes: performing a passivation treatment on the porous structure to form a passivation structure coated on the porous structure, so that the obtained porous material has a stable morphology and stable physical and chemical properties. For example, the passivation treatment is performed by one or more of oxidation treatment, nitridation treatment, carbonization treatment, heteroepitaxial process, physical vapor deposition process, chemical vapor deposition process, chemical etching process, and electrochemical etching process.

[0108] At step S110, after the step of passivating the porous structure, it also includes: polishing the surface of the porous material layer after the passivation treatment to expose the semiconductor lattice structure in the porous material layer; then, a low-resistance layer 230 can be formed on the porous material layer 210, wherein the low-resistance layer 230 can be prepared by thin film deposition, thin film bonding, thin film transfer, epitaxial growth, etc.; preferably, the material of the low-resistance layer 230 is selected to be a single crystal semiconductor material. Since the interior of the single crystal material has a consistent crystal orientation, the device threshold voltage fluctuation caused by the inconsistent crystal orientation of the polycrystalline material can be avoided.

[0109] like Figure 4a and Figure 5a As shown, after the step of forming the porous material layer 210 , an epitaxial material layer may be grown by an epitaxial process, and the epitaxial material layer may be in-situ doped to form a low resistance layer 230 .

[0110] In some examples, the low-resistance layer 230 may be formed by in-situ doping such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). Since the porous material layer is formed based on the first substrate, the porous material layer has the same crystal orientation inside, and the low-resistance layer is epitaxially grown based on the semiconductor lattice structure exposed by the porous material layer, and the grown low-resistance layer may be a single crystal material.

[0111] Optionally, before forming the low resistance layer 230, a first insulating layer 220 is formed on the surface of the porous material layer to inhibit the possible recrystallization of the porous material or the diffusion of impurity ions into the porous material in the subsequent process. Figures 6a to 6e , which is a schematic diagram of the structure obtained at each stage in another example of the preparation process of the SOI structure using SOI as the second substrate. For the first insulating layer at the interface between the porous material layer and the low-resistance layer, for example, the first insulating layer at the interface between the porous silicon and the low-resistance silicon, such as Figures 6a to 6e As shown, the first insulating layer 220 may be retained. In other examples, the first insulating layer 220 between the porous material layer and the low resistance layer may be removed.

[0112] Next, step S120 is performed to provide a second substrate, wherein the second substrate includes a semiconductor layer on a surface thereof, and an insulating layer is formed on the semiconductor layer.

[0113] Specifically, the second substrate can be selected from one of an SOI substrate and a semiconductor substrate. Figure 4b and Figure 4cAs shown, when an SOI substrate is selected, the top semiconductor layer of the SOI substrate is used as the semiconductor layer, and an insulating layer 1300 is formed on the semiconductor layer 1400; wherein the thickness of the insulating layer 1300 is between 1nm and 300nm.

[0114] like Figure 4b to Figure 4c As shown, the SOI substrate 11 includes a back substrate, an insulating buried layer and a top semiconductor layer 1400 , and an insulating layer 1300 is formed on the top semiconductor layer 1400 .

[0115] See also Figure 5a to Figure 5e , which is a schematic diagram showing the structure obtained at each stage in the preparation process of the SOI structure using a semiconductor substrate as the second substrate. Figure 5c As shown, an insulating layer 1300 is formed on the semiconductor substrate 40 .

[0116] When the second substrate is selected as a semiconductor substrate, that is, a substrate of a single material, a preset stripping interface 2410 is defined in the semiconductor substrate, and the preset stripping interface 2410 can be formed by one or more ion implantations, wherein; the material of the second substrate includes silicon, silicon carbide, silicon germanium or other suitable semiconductor materials, such as a single crystal silicon substrate; the material of the insulating layer 1300 includes insulating dielectric materials, porous semiconductor materials, nanocrystalline materials, porous insulating dielectric materials, semiconductor materials with a wider bandgap or a wide bandgap, or one or more mixtures thereof.

[0117] In a specific example, Figure 5b to Figure 5c As shown, before the step of forming the insulating layer 1300, it also includes: performing an ion implantation to define a preset stripping interface in the second substrate, where hydrogen ion implantation is used; or, the step of performing the ion implantation to define the preset stripping interface 2410 includes: performing a first ion implantation on the second substrate to form an initial stripping layer in the second substrate (not shown in the figure), wherein the implanted particles of the first ion implantation include B-containing impurities; performing a second ion implantation at the position of the initial stripping layer to define the preset stripping interface 2410, wherein the implanted particles of the second ion implantation include at least one of H ions and He ions. In the above manner, in the process of defining the stripping interface, B is implanted in advance at the stripping interface. + , BF2 plasma, so that a clear distribution profile of implanted particles can be defined at a lower dose and the subsequent ion implantation dose can be reduced. The implanted ions of the second ion implantation are enriched at the first implanted particles, thereby accurately defining the peeling interface, reducing peeling damage, and reducing peeling surface roughness.

[0118] Next, step S130 is performed to stack the first substrate and the second substrate by bonding the side of the second substrate on which the insulating layer is formed to the low-resistance layer.

[0119] like Figure 4d and Figure 5e As shown, in some examples, the step of bonding the insulating layer 1300 to the low-resistance layer 230 includes: pre-bonding with the insulating layer and the low-resistance layer as bonding interfaces; then, performing a heating annealing process to enhance the bonding strength of the interface between the low-resistance layer and the insulating layer.

[0120] Optionally, before performing the bonding process, the insulating layer 1300 and / or the low-resistance layer 230 are surface treated, for example, by using a chemical mechanical polishing (CMP) process, a material deposition process, a specific atmosphere annealing, an oxidation corrosion process or a similar process to adjust the surface quality of the above-mentioned material layers, which is beneficial to the subsequent bonding process.

[0121] Next, step S140 is performed to remove a portion of the second substrate away from the insulating layer, so as to transfer the insulating layer and the semiconductor layer to the first substrate, with the semiconductor layer serving as a top functional layer.

[0122] like Figure 5d As shown, a preset stripping interface 2410 is defined in the semiconductor substrate 40. By stripping a portion of the semiconductor substrate along the preset stripping interface 2410 in the semiconductor substrate, the insulating layer 1300 and the semiconductor layer 2400 are transferred to the first base, and the semiconductor layer 2400 serves as a top functional layer.

[0123] Some examples include Figure 6d As shown, after bonding is completed, a back thinning process is used to remove the back substrate in the SOI substrate by grinding or etching, and stop at the insulating buried layer; then, a selective etching process is used to remove the insulating buried layer, and the second insulating layer 2300 and the semiconductor layer 1400 are transferred to the first substrate.

[0124] Embodiment 2

[0125] This embodiment provides a method for preparing an SOI structure, comprising the following steps:

[0126] S210: providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, the porous material layer is formed to extend inward from the first surface of the first substrate, and a low resistance layer and an insulating layer are formed on the first surface of the first substrate;

[0127] S220: providing a second substrate, wherein the second substrate includes a semiconductor layer located on a surface thereof;

[0128] S230: stacking the first substrate and the second substrate by bonding the side of the second substrate on which the semiconductor layer is formed to the insulating layer;

[0129] S240: removing a portion of the second substrate away from the insulating layer to transfer the semiconductor layer onto the first substrate, wherein the semiconductor layer serves as a top functional layer.

[0130] It should be noted that the above sequence does not strictly represent the execution sequence of the method for preparing the SOI structure protected by the present invention, and those skilled in the art may change the sequence of steps according to the actual process.

[0131] First, step S210 is performed to provide a first substrate, wherein the first substrate has a first surface and a second surface relative to each other, and the first substrate includes a first substrate and a porous material layer formed based on the first substrate, wherein the porous material layer is formed to extend inward from the first surface of the first substrate, and a low-resistance layer and an insulating layer are formed on the first surface of the first substrate.

[0132] In step S210, after forming the low resistance layer 230 on the porous material layer 210, an insulating layer 3300 is formed on the low resistance layer 230 instead of on the semiconductor layer. The formation method of the porous material layer 210, the low resistance layer 230 and the insulating layer 3300 in step S210 can refer to the example in the previous embodiment 1, and will not be repeated here.

[0133] See also Figures 7a to 7c , which is a schematic diagram showing the structures obtained at each stage of the preparation method of the SOI structure. Figure 7a As shown, at step S210 , after the step of forming the low resistance layer 230 , an insulating layer 3300 is formed on the low resistance layer 230 .

[0134] As an example, at step S210, after the step of forming the low resistance layer 230, an insulating layer 3300 is formed on the exposed surface of the low resistance layer. The insulating layer 3300 can be formed by thin film deposition, thin film bonding, thin film transfer, epitaxial growth, etc.

[0135] Next, step S220 is performed to provide a second substrate, wherein the second substrate includes a semiconductor layer located on a surface thereof.

[0136] like Figure 7bAs shown, step S220 further includes: defining a preset peeling interface 3410 in the semiconductor substrate. In step S220 of this embodiment, the step of defining the preset peeling interface 3410 in the semiconductor substrate 40 can refer to the example in step S120 of the previous embodiment 1.

[0137] Next, step S230 is performed to stack the first substrate and the second substrate by bonding the side of the second substrate on which the semiconductor layer is formed to the insulating layer. The bonding method of the insulating layer and the semiconductor layer and the surface treatment of the bonding interface can refer to the step of bonding the insulating layer and the low-resistance layer in step S130 of the first embodiment, and the example of surface treatment of the insulating layer and / or the low-resistance layer.

[0138] Next, step S240 is performed to remove a portion of the second substrate away from the insulating layer to transfer the semiconductor layer onto the first substrate, with the semiconductor layer serving as a top functional layer.

[0139] like Figure 7c As shown, the insulating layer 3300 and the semiconductor layer 3400 are transferred to the first base by peeling off a portion of the semiconductor substrate along the preset peeling interface 3410, and the semiconductor layer 3400 serves as a top functional layer. The partial removal of the first base and the processing of the transferred semiconductor layer after removal can refer to the partial removal of the first base and the processing of the transferred insulating layer and the semiconductor layer after removal in Embodiment 1, which will not be repeated here.

[0140] Embodiment 3

[0141] This embodiment provides a method for manufacturing an SOI structure, comprising the following steps:

[0142] S310: providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, the porous material layer being formed to extend inwardly from the first surface of the first substrate, and forming a low-resistance layer on the first surface of the first substrate;

[0143] S320: providing a second substrate, wherein the second substrate includes a semiconductor layer located on a surface thereof, and forming an insulating layer on the semiconductor layer;

[0144] S330: forming an amorphous material layer on one of the insulating layer and the low-resistance layer, and stacking the first substrate and the second substrate by bonding the other of the insulating layer and the low-resistance layer to the amorphous material layer;

[0145] S340: removing a portion of the second substrate away from the insulating layer to transfer the insulating layer and the semiconductor layer to the first substrate, with the semiconductor layer serving as a top functional layer.

[0146] S350: causing the amorphous material layer to recrystallize and converting the amorphous material therein into a polycrystalline material;

[0147] First, step S310 is performed to provide a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, and the first substrate includes a first substrate and a porous material layer formed based on the first substrate, wherein the porous material layer is formed to extend inward from the first surface of the first substrate, and a low-resistance layer is formed on the first surface of the first substrate. In this embodiment, the formation method of the porous material layer 210 and the low-resistance layer 230 in step S310 can refer to the example in the previous embodiment 1.

[0148] Next, S320 is performed to provide a second substrate, wherein the second substrate includes a semiconductor layer on its surface, and an insulating layer is formed on the semiconductor layer. In this embodiment, the method for forming the insulating layer 4300 in step S320 can refer to the example of forming an insulating layer on the semiconductor layer in the previous embodiment 1.

[0149] Then, step S330 is performed to form an amorphous material layer on one of the insulating layer and the low-resistance layer, and the first substrate and the second substrate are stacked by bonding the other of the insulating layer and the low-resistance layer to the amorphous material layer.

[0150] See also Figures 8a to 8e , which is a schematic diagram of the structure obtained at each stage of the preparation method of the SOI structure of this embodiment. Figure 8b As shown, at step S330, an amorphous material layer 230a is formed on the low-resistance layer 230, which can serve as a bonding interface in subsequent processes, thereby reducing the bonding difficulty. Figure 8d As shown, in step S330 , an amorphous material layer 230 a is formed on the low resistance layer 230 , and the first substrate is stacked on the second substrate by bonding the insulating layer 4300 and the amorphous material layer 230 a .

[0151] As an example, the amorphous material layer 230a is formed by chemical vapor deposition, radio frequency chemical vapor deposition or a similar thin film deposition process; wherein the amorphous material layer 230a has the same or different material as the low resistance layer, including but not limited to semiconductor materials, such as silicon, germanium, Si x Ge 1-x; or, an insulating material, such as a diamond film. When the amorphous material layer 230a uses an amorphous semiconductor material layer such as an amorphous silicon layer as a bonding interface, the amorphous semiconductor material layer is easy to polish compared to the low-resistance layer composed of polycrystalline semiconductor materials, and can optimize the surface roughness and flatness, thereby reducing the difficulty of polishing the bonding interface; in addition, since the structure of the amorphous semiconductor material layer itself is relatively loose, its interior can absorb the defects caused by hydrophilic bonding, so when the amorphous semiconductor material layer acts as a bonding interface, it can reduce the thickness requirement for the bonding medium (for example, the insulating layer 4300).

[0152] In another implementation, the amorphous material layer 230a may be formed on the insulating layer. Figures 9a to 9d The schematic diagram of the structure obtained at each stage of another example of the method for preparing the SOI structure of this embodiment is shown. Fig.9c As shown, after step S310, a low resistance layer 230 is formed on the first substrate, an insulating layer 4300 is formed on the second substrate, and at step S330, an amorphous material layer 230a is formed on the insulating layer 4300. In this case, the amorphous material layer 230a and the low resistance layer 230 are used as bonding interfaces, and the first substrate and the second substrate can be stacked by bonding the low resistance layer 230 and the amorphous material layer 230a.

[0153] Next, step S340 is performed to remove a portion of the second substrate away from the insulating layer, and transfer the insulating layer and the semiconductor layer to the first substrate, with the semiconductor layer serving as the top functional layer. Figure 8d As shown, by removing a portion of the glass of the second substrate along the preset peeling interface 3410, a portion of the second substrate away from the insulating layer is removed, and the remaining portion of the second substrate on the insulating layer serves as a top functional layer.

[0154] Preferably, after executing step S340, the first substrate having an insulating layer and a top functional layer thereon is reinforced, and the reinforcement treatment includes: performing a heating annealing process to enhance the bonding strength of the interface between the amorphous material layer 230a and the low resistance layer 230 or the insulating layer 4300, and at the same time allowing the amorphous material at the interface between the low resistance layer and the insulating layer to recrystallize into a polycrystalline material, thereby reducing the interface thermal resistance and improving the thermal conductivity of the SOI structure finally prepared.

[0155] Embodiment 4

[0156] This embodiment provides a method for manufacturing an SOI structure, comprising the following steps:

[0157] S410: providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, the porous material layer being formed to extend inwardly from the first surface of the first substrate;

[0158] S420: providing a second substrate, wherein the second substrate comprises a second substrate, and an insulating layer and a low-resistance layer located on the second substrate, wherein a preset peeling interface is defined in the second substrate;

[0159] S430: forming an amorphous material layer on one of the porous material layer and the low-resistance layer, and stacking the first substrate and the second substrate by bonding the other of the porous material layer and the low-resistance layer to the amorphous material layer;

[0160] S440: peeling off a portion of the second substrate along the preset peeling interface, transferring the insulating layer and the low-resistance layer to the first base, and the portion of the second substrate remaining on the insulating layer serves as a top functional layer;

[0161] S450: Recrystallize the amorphous material layer and transform the amorphous material therein into a polycrystalline material.

[0162] First, step S410 is performed to provide a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, and the first substrate includes a first substrate and a porous material layer formed based on the first substrate, wherein the porous material layer is formed to extend inward from the first surface of the first substrate. In some examples, such as Fig.10a As shown, in step S410, a porous material layer 210 is formed based on the first substrate 100. The method of forming the porous material layer 210 in step S410 can refer to the example of forming the porous material layer based on the first substrate in the previous embodiment 1.

[0163] Then, step S420 is performed to provide a second substrate, wherein the second substrate includes a second substrate, and an insulating layer and a low-resistance layer located on the second substrate, wherein a preset peeling interface is defined in the second substrate.

[0164] In this embodiment, the second substrate is selected as an SOI substrate, and the SOI substrate includes a back substrate 5400, an insulating buried layer 5300 and a top semiconductor layer, and a low resistance layer 230 is formed based on the top semiconductor layer. Figure 10c to Figure 10d As shown, in step S420 , the SOI substrate is used as the second base, the back substrate 5400 is used as the second substrate, and a preset peeling interface 5410 is defined in the back substrate 5400 .

[0165] Next, step S430 is performed to form an amorphous material layer on one of the insulating layer and the low-resistance layer, and the first substrate and the second substrate are stacked by bonding the other of the insulating layer and the low-resistance layer to the amorphous material layer. Fig.10b and Fig.10e As shown, in some examples, an amorphous material layer 220 is formed on the porous material layer 210; then, the amorphous material layer 220 and the low resistance layer 230 are pre-bonded with each other as bonding interfaces. The bonding method of the low resistance layer 230 and the amorphous material layer 220 and the surface treatment of the bonding interface can refer to the step S330 of bonding the amorphous material layer to the low resistance layer in the third embodiment and the example of surface treatment of the amorphous material layer and / or the low resistance layer.

[0166] Next, step S440 is performed to peel off a portion of the second substrate along the preset peeling interface, transfer the insulating layer and the low-resistance layer to the first base, and the portion of the second substrate retained on the insulating layer serves as a top functional layer.

[0167] like Fig.10f As shown, at step S440, a portion of the back substrate is peeled off along the preset peeling interface 5410, and the low-resistance layer 230, the buried insulating layer 5300, and a portion of the back substrate are transferred to the first substrate, the buried insulating layer is used as an insulating layer, and the remaining portion of the back substrate on the insulating layer is used as a top functional layer. Step S450 can be performed synchronously with step S440, which includes: strengthening the first substrate having the insulating layer and the top functional layer thereon by a heating annealing process, and at the same time, the amorphous material layer is recrystallized and the amorphous material therein is converted into a polycrystalline material, which can reduce the interface thermal resistance and improve the thermal conductivity of the SOI structure finally prepared.

[0168] Embodiment 5

[0169] The present application provides an SOI structure, and the SOI structure is preferably prepared using the preparation method of the SOI structure in the previously described embodiment.

[0170] The SOI structure provided in the present application includes: a substrate layer 10, a porous material layer 210, an insulating layer and a top functional layer 400 stacked from bottom to top, a low-resistance layer 230 is inserted between the porous material layer 210 and the insulating layer, and the material of the low-resistance layer 230 includes a heavily doped polycrystalline semiconductor material or a single crystal semiconductor material, and at least one insulating layer and one top functional layer are arranged on the surface of the low-resistance layer away from the substrate layer.

[0171] Specifically, the material of the substrate layer 10 includes silicon, silicon carbide, silicon germanium or other suitable semiconductor materials, such as a single crystal silicon substrate; the material of the insulating layer includes but is not limited to insulating dielectric materials, porous semiconductor materials, nanocrystalline materials, porous insulating dielectric materials, and one or more mixtures of semiconductor materials with a wide bandgap width, and the thickness of the insulating layer is 1nm-300nm; in some cases, gaps are formed in the insulating layer or at its interface.

[0172] In some examples, the porous material layer 210 may be made of a material different from that of the substrate layer; or, the porous material layer 210 may be formed based on a portion of the substrate layer. When the substrate layer 10 is a high-resistance substrate, the thickness of the porous material layer 210 is greater than 500 nm.

[0173] When the substrate layer 10 is a low-resistance substrate, the thickness of the porous material layer 210 is greater than 5 μm. The "high-resistance substrate" mentioned here usually has a resistivity of not less than 500 Ω·cm, and the "low-resistance layer" usually has a resistivity of less than 0.01 Ω·cm.

[0174] Some examples include Figure 6f As shown, a first insulating layer 220 is sandwiched between the porous material layer 210 and the low-resistance layer 230 , and a second insulating layer 2300 is disposed on a surface of the low-resistance layer away from the porous material layer.

[0175] In a specific example, the low-resistance layer 230 may be made of heavily doped single-crystal semiconductor material, so that the low-resistance layer has a lower resistivity and effectively conducts voltage signals without causing significant loss of radio frequency signals. By configuring a single-crystal low-resistance layer, the consistency of its internal crystal orientation and electrical properties can be ensured.

[0176] Fig.11 It is a schematic diagram of a SOI structure. Fig.11 As shown, in some examples, the SOI structure further includes a patterned region, in which the low-resistance layer, the insulating layer and the top functional layer located on the porous material layer are removed, and the patterned region corresponds to a formation region of a radio frequency passive device.

[0177] The SOI structure is applied to the co-integration of the RF front-end module and the logic module. The SOI structure can improve the isolation of the substrate layer and reduce the loss and crosstalk of the RF signal.

[0178] For example, the SOI structure can be configured to fabricate an integrated structure of a fully depleted SOI (FD-SOI) device and a radio frequency SOI (RF-SOI) device, such as Fig.11As shown, the patterned area corresponds to the RF-SOI area R, and the RF-SOI area R also includes an insulating layer 500 disposed on the porous material layer, and a radio frequency passive device is disposed on the insulating layer 500, which can be manufactured based on the insulating layer, such as shallow trench isolation (STI); the FD-SOI area F includes a low-resistance layer 230, an insulating layer 300 and a top functional layer 400, and a back-gate modulation layer is manufactured based on the low-resistance layer 230, and the insulating layer 300 is used as a back-gate dielectric layer. By inserting a low-resistance layer between the porous material layer and the insulating layer, a back-gate modulation layer is manufactured based on the low-resistance layer, and the substrate layer and the back-gate modulation layer are separated by at least the porous material layer, and the porous material layer is used to avoid the porous material layer from introducing a leakage path between the back-gate modulation layer and the high-resistivity substrate; preferably, the material of the low-resistance layer is selected from a single crystal semiconductor material, which can improve the threshold voltage consistency of the FD-SOI device.

[0179] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a SOI structure, characterized in that: The following steps are involved: Providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, wherein the porous material layer is formed to extend inwardly from the first surface of the first substrate, and a low resistance layer is formed on the first surface of the first substrate; Providing a second substrate, wherein the second substrate includes a semiconductor layer located on a surface thereof; forming an insulating layer on one of the low-resistance layer and the semiconductor layer, and stacking the first substrate and the second substrate by bonding the other of the low-resistance layer and the semiconductor layer to the insulating layer; removing a portion of the second substrate away from the insulating layer to transfer the insulating layer and the semiconductor layer onto the first substrate, wherein the semiconductor layer serves as a top functional layer; The material of the low resistance layer includes heavily doped polycrystalline semiconductor material or single crystal semiconductor material.

2. The method for preparing the SOI structure according to claim 1, characterized in that: The step of forming the porous material layer based on the first substrate comprises: The substrate layer is partially or completely transformed into a porous structure by a wet etching method; or, A wet etching process or a dry etching process is used to form a gap extending from the surface of the substrate layer to the inside; then, the gap is filled with nanocrystalline particles.

3. The method for preparing the SOI structure according to claim 1, characterized in that: The step of forming the porous material layer based on the first substrate includes: growing polycrystalline material on the substrate layer, selectively etching the polycrystalline material to form a porous structure; and passivating the porous structure.

4. The method for preparing an SOI structure according to claim 2 or 3, characterized in that: The step of forming the low-resistance layer includes: growing an epitaxial material layer on the porous material layer through an epitaxial process; wherein the material of the epitaxial material layer includes a single crystal semiconductor material or a polycrystalline semiconductor material, and the epitaxial material layer is heavily doped while or after forming the epitaxial material layer.

5. The method for preparing the SOI structure according to claim 3, characterized in that: After the step of passivating the porous structure, the method further comprises: Thinning the exposed surface of the porous material layer to reveal the semiconductor lattice structure in the porous material layer; An insulating layer is formed on the passivated porous material layer, and the insulating layer is manufactured by thin film deposition, thin film bonding, thin film transfer, and oxidation.

6. The method for preparing an SOI structure according to claim 1, characterized in that: The second base is selected to be a semiconductor substrate, and a preset peeling interface is defined in the semiconductor substrate; The insulating layer and the semiconductor layer are transferred to the first base by peeling off a portion of the semiconductor substrate along the preset peeling interface, and the semiconductor layer retained on the insulating layer serves as a top functional layer.

7. A method for preparing a SOI structure, characterized in that: The following steps are involved: Providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, wherein the porous material layer is formed to extend inwardly from the first surface of the first substrate, and a low resistance layer is formed on the first surface of the first substrate; Providing a second substrate, wherein the second substrate comprises a semiconductor layer located on a surface thereof, and forming an insulating layer on the semiconductor layer; forming an amorphous material layer on one of the insulating layer and the low-resistance layer, and stacking the first substrate and the second substrate by bonding the other of the insulating layer and the low-resistance layer to the amorphous material layer; removing a portion of the second substrate away from the insulating layer to transfer the insulating layer and the semiconductor layer onto the first substrate, wherein the semiconductor layer serves as a top functional layer; Recrystallize the amorphous material layer and transform the amorphous material therein into a polycrystalline material; The material of the low resistance layer includes heavily doped polycrystalline semiconductor material or single crystal semiconductor material.

8. The method for preparing the SOI structure according to claim 7, characterized in that: After the step of forming the insulating layer, it includes: forming an amorphous material layer on the insulating layer, the material of the amorphous material layer is selected to be an amorphous semiconductor material; by bonding the amorphous material layer and the low-resistance layer, the first substrate and the second substrate are stacked; wherein, through a heating annealing process, the amorphous semiconductor material between the insulating layer and the low-resistance layer is recrystallized into a polycrystalline semiconductor material.

9. The method for preparing an SOI structure according to claim 7, characterized in that: After the step of forming the insulating layer, it includes: forming an amorphous material layer on the low-resistance layer, the material of the amorphous material layer is selected to be an amorphous semiconductor material; by bonding the amorphous material layer and the insulating layer, the first substrate and the second substrate are stacked; wherein, through a heating annealing process, the amorphous semiconductor material between the insulating layer and the low-resistance layer is recrystallized into a polycrystalline semiconductor material.

10. The method for preparing an SOI structure according to claim 7, characterized in that: The step of forming the low resistance layer includes: growing an epitaxial material layer on the insulating layer through an epitaxial process, wherein the epitaxial material layer is made of a single crystal semiconductor material or a polycrystalline semiconductor material; and heavily doping the epitaxial material layer while or after forming the epitaxial material layer.

11. A method for preparing a SOI structure, characterized in that: The following steps are involved: Providing a first substrate, the first substrate having a first surface and a second surface opposite to each other, the first substrate comprising a first substrate and a porous material layer formed based on the first substrate, the porous material layer being formed to extend inwardly from the first surface of the first substrate; Providing a second substrate, wherein the second substrate comprises a semiconductor layer located on a surface thereof, and forming an insulating layer and a low-resistance layer on the semiconductor layer; forming an amorphous material layer on one of the porous material layer and the low-resistance layer, and stacking the first substrate and the second substrate by bonding the other of the porous material layer and the low-resistance layer to the amorphous material layer; removing a portion of the second substrate away from the insulating layer to transfer the insulating layer and the semiconductor layer onto the first substrate, wherein the semiconductor layer serves as a top functional layer; Recrystallize the amorphous material layer and transform the amorphous material therein into a polycrystalline material; The material of the low resistance layer includes heavily doped polycrystalline semiconductor material or single crystal semiconductor material.

12. An SOI structure, characterized in that: It includes: It is characterized in that it includes: a substrate layer, a porous material layer, an insulating layer and a top functional layer stacked from bottom to top, a low-resistance layer is inserted between the porous material layer and the insulating layer, the material of the low-resistance layer includes heavily doped single crystal semiconductor material or polycrystalline semiconductor material, and the surface of the low-resistance layer away from the substrate layer is provided with at least one insulating layer and one top functional layer.

13. The SOI structure according to claim 12, characterized in that: A first insulating layer is sandwiched between the porous material layer and the low-resistance layer, and a second insulating layer is arranged on a surface of the low-resistance layer away from the porous material layer. The thickness of the second insulating layer is 1nm-300nm.

14. The SOI structure according to claim 12, characterized in that: The SOI structure further comprises a patterned region, in which the low resistance layer, the insulating layer and the top functional layer located on the porous material layer are removed.

15. The SOI structure according to claim 12, characterized in that: Used to make integrated structures of FD-SOI devices and RF-SOI devices.

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